WO2016010270A1 - 기판 구조, 그 형성방법, 및 이를 이용한 질화물 반도체 제조방법 - Google Patents
기판 구조, 그 형성방법, 및 이를 이용한 질화물 반도체 제조방법 Download PDFInfo
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- WO2016010270A1 WO2016010270A1 PCT/KR2015/006263 KR2015006263W WO2016010270A1 WO 2016010270 A1 WO2016010270 A1 WO 2016010270A1 KR 2015006263 W KR2015006263 W KR 2015006263W WO 2016010270 A1 WO2016010270 A1 WO 2016010270A1
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- 239000000758 substrate Substances 0.000 title claims abstract description 192
- 239000004065 semiconductor Substances 0.000 title claims abstract description 150
- 150000004767 nitrides Chemical class 0.000 title claims abstract description 135
- 238000000034 method Methods 0.000 title claims abstract description 58
- 238000004519 manufacturing process Methods 0.000 title abstract description 15
- 239000010409 thin film Substances 0.000 claims abstract description 103
- 239000013078 crystal Substances 0.000 claims abstract description 31
- 239000011800 void material Substances 0.000 claims description 15
- 238000010438 heat treatment Methods 0.000 claims description 14
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 7
- 239000001301 oxygen Substances 0.000 claims description 7
- 229910052760 oxygen Inorganic materials 0.000 claims description 7
- 239000003960 organic solvent Substances 0.000 claims description 3
- 238000000926 separation method Methods 0.000 abstract description 5
- 230000035882 stress Effects 0.000 description 20
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical group Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 12
- 230000007547 defect Effects 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- 239000011347 resin Substances 0.000 description 10
- 229920005989 resin Polymers 0.000 description 10
- 239000010408 film Substances 0.000 description 9
- 229910052594 sapphire Inorganic materials 0.000 description 9
- 239000010980 sapphire Substances 0.000 description 9
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 8
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 8
- 238000000231 atomic layer deposition Methods 0.000 description 8
- 229910002601 GaN Inorganic materials 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 239000000463 material Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 238000000605 extraction Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 3
- 230000005693 optoelectronics Effects 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000004528 spin coating Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- VSCWAEJMTAWNJL-UHFFFAOYSA-K aluminium trichloride Chemical compound Cl[Al](Cl)Cl VSCWAEJMTAWNJL-UHFFFAOYSA-K 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000003618 dip coating Methods 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000000704 physical effect Effects 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000000348 solid-phase epitaxy Methods 0.000 description 2
- 238000005507 spraying Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 239000005751 Copper oxide Substances 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- -1 InN Chemical compound 0.000 description 1
- 208000012868 Overgrowth Diseases 0.000 description 1
- CYTYCFOTNPOANT-UHFFFAOYSA-N Perchloroethylene Chemical group ClC(Cl)=C(Cl)Cl CYTYCFOTNPOANT-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910010413 TiO 2 Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 229910000431 copper oxide Inorganic materials 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000010419 fine particle Substances 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 238000000025 interference lithography Methods 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000000197 pyrolysis Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 230000003362 replicative effect Effects 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
- 238000010897 surface acoustic wave method Methods 0.000 description 1
- 238000001308 synthesis method Methods 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
- 229950011008 tetrachloroethylene Drugs 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- RUDFQVOCFDJEEF-UHFFFAOYSA-N yttrium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Y+3].[Y+3] RUDFQVOCFDJEEF-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
- H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/0242—Crystalline insulating materials
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
- H01L21/02458—Nitrides
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02488—Insulating materials
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/0254—Nitrides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
-
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02647—Lateral overgrowth
- H01L21/0265—Pendeoepitaxy
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- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
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- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
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- H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
- H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
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- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
Definitions
- the present invention relates to a semiconductor layer of gallium nitride (GaN) or a mixed nitride of gallium and another metal, and a method of forming the same.
- the invention also relates to an electronic or opto-electronic device, a nitride semiconductor substrate and a method of manufacturing the same comprising such a layer.
- the technical field of the present invention can be broadly defined as a substrate structure and a method for forming the nitride semiconductor layer of high quality with low crystal defects.
- LEDs are typical of nitride semiconductor devices such as gallium nitride.
- the LED market grew based on low-power LEDs used in portable communication devices such as mobile phones, keypads of small home appliances, and back light units of liquid crystal displays (LCDs).
- LCDs liquid crystal displays
- the most frequently used substrates for the growth of nitride semiconductor layers are "heterogeneous" substrates such as sapphire, silicon carbide (SiC) and silicon.
- substrates such as sapphire, silicon carbide (SiC) and silicon.
- SiC silicon carbide
- the nitride semiconductor layer grown on the dissimilar substrate contains a large amount of crystal defects such as dislocations. These defects are the major cause of poor LED performance.
- the nitride semiconductor layer is subjected to compressive stress when the nitride semiconductor layer is grown at a high temperature and then cooled. Since the silicon substrate has a smaller coefficient of thermal expansion than the nitride semiconductor layer, when the nitride semiconductor layer is grown at a high temperature and cooled, a tensile stress is applied to the nitride semiconductor layer. For this reason, there exists a problem that the board
- the stress itself of the thin film can be reduced, it is advantageous to be able to use a thin substrate.
- the LED substrate is manufactured to be removed after leaving the substrate about 100 ⁇ m for chip separation, it is possible to use a thin substrate to obtain a big gain in terms of LED production.
- the nitride semiconductor layer formed on the dissimilar substrate may need to be separated from the dissimilar substrate.
- Laser lift off has been proposed in the prior art. However, even when the laser lift-off method is used, the substrate may be warped or the semiconductor layer may be damaged due to a difference in coefficient of thermal expansion between the sapphire substrate and the nitride semiconductor. In addition, defects such as cracks are likely to occur in the epi layer due to the impact of the laser beam, and furthermore, the epi layer is fragile and the process is unstable. Laser lift-off methods involve thermal and mechanical deformation and decomposition of nitride semiconductors. Therefore, it is not efficient in terms of energy as well as loss of the thin film already grown.
- the biggest problem with LEDs is low luminous efficiency.
- the luminous efficiency is determined by the light generation efficiency (internal quantum efficiency), the efficiency emitted out of the device (external light extraction efficiency), and the efficiency in which light is amplified by the phosphor.
- the efficiency in which light is amplified by the phosphor In order to increase the output power of the LED, it is important to improve the active layer characteristics in terms of internal quantum efficiency, and to increase the external light extraction efficiency of light actually generated.
- the patterned sapphire substrate (PSS) patterned on the sapphire substrate is known to reduce the defects generated during the growth of the nitride semiconductor layer to increase the internal quantum efficiency, and to reduce the total internal reflection to increase the external light extraction efficiency.
- 1 is a view for explaining a case of growing a nitride semiconductor layer using the existing PSS.
- the nitride semiconductor layer 20 is started on the bottom surface of the substrate, and the upper portion of the PSS lens 15 is formed by epitaxial lateral overgrowth (ELO). It grows in the form of covering.
- ELO epitaxial lateral overgrowth
- the growth of GaN is 1100 ° C or lower. At this temperature, GaN growth mainly occurs only at the bottom surface according to the strong anisotropy growth mode as shown in FIG. 1A, and the dislocation density is reduced in the region where ELO occurs as shown in (b), thereby improving crystal quality. .
- the nitride semiconductor layer is AlN.
- the growth of AlN is at least 1300 ° C., higher than GaN. At this temperature, it has a growth mode with strong isotropy. Accordingly, referring to FIG. 1C, the AlN 30 is actively grown not only on the bottom surface of the PSS 10 but also on the surface of the lens 15. Accordingly, the probability that the AlN epilayer is merged before filling the bottom surface is very high, so that voids 40 and void are generated inside the AlN epilayer 35 as shown in FIG. . These voids 40 degrade the crystal quality.
- the problem to be solved by the present invention is a substrate structure and a method for forming a high-quality nitride semiconductor layer to reduce the stress received by the nitride semiconductor layer during growth of the nitride semiconductor layer and easy separation from the substrate, and the same It is to provide a semiconductor laminate structure, a method of forming the same, and a nitride semiconductor manufacturing method using the same.
- the substrate structure according to the present invention is a single crystal substrate heterogeneous with the nitride semiconductor; And an inorganic material crystallized in the same crystal structure as the substrate and including a leg portion contacting the substrate and an upper surface portion parallel to the substrate so as to define an integrated cavity between the substrate and the leg portion contacting the substrate. It includes a thin film.
- the leg may have a hollow pipe shape.
- the leg portion is plural and the upper surface portion is formed continuously extending from the plurality of leg portions. It is preferable that the area occupied by the empty space is larger than the area occupied by the leg portion.
- the semiconductor laminate structure according to the present invention further includes a nitride semiconductor layer formed on the inorganic thin film using the substrate structure.
- the nitride semiconductor layer may be two or more layers. Even if the thermal expansion coefficients of the substrate and the nitride semiconductor layer are different, the integrated void space can be compressed or stretched by the nitride semiconductor layer, so that the stress applied to the nitride semiconductor layer is reduced.
- a hole type sacrificial layer pattern is formed on a nitride semiconductor and a heterocrystalline single substrate, and then an inorganic thin film is formed on the sacrificial layer pattern.
- the sacrificial layer pattern is removed from the substrate on which the inorganic thin film is formed so that an integrated empty space defined by the substrate and the inorganic thin film is formed. Thereafter, the inorganic thin film is crystallized in the same crystal structure as the substrate.
- the sacrificial layer pattern may be formed by various methods. After coating the photoresist on the substrate may be formed by a photolithography method, or by applying a nanoimprint resin on the substrate may be formed by a nanoimprint method.
- the forming of the inorganic thin film may be performed within a temperature limit at which the sacrificial layer pattern is not deformed. Forming the inorganic thin film may be by ALD.
- the removing of the sacrificial layer pattern may be a heat treatment in an oxygen atmosphere or a wet removal using an organic solvent. The empty space is a position where the sacrificial layer pattern is removed.
- the step of forming a nitride semiconductor layer on the crystallized inorganic thin film is performed.
- nitride semiconductors such as vertical or horizontal LEDs, LEDs transferred or transferred to any substrate, or free-standing nitride semiconductor substrates may be produced.
- an ultraviolet light detector By using the substrate structure, the method of forming the same, the semiconductor laminate and the method of manufacturing the nitride semiconductor according to the present invention, an ultraviolet light detector, a surface acoustic wave device, an LED, an LD, a microwave electronic device, and the like can be manufactured. Can be extended to modules, systems, etc. In addition, a free standing nitride semiconductor substrate can be produced. Specific details of other embodiments are included in the detailed description and drawings.
- the substrate structure includes an inorganic thin film that defines an integrated void space, which may be included while minimizing a contact surface with the substrate.
- the nitride semiconductor layer is formed in such a substrate structure, the total stress of the nitride semiconductor layer is reduced due to the presence of the empty space. Therefore, even if a stress is generated in the nitride semiconductor layer due to a difference in thermal expansion coefficient between the substrate and the nitride semiconductor layer, local stress relaxation may occur, and thus the substrate warpage may be reduced. This makes it possible to use a relatively thin substrate even in a large area substrate.
- the nitride semiconductor layer is formed on the crystallized inorganic thin film on the integrated void space.
- the crystallized inorganic thin film can be resolved by dividing the stress with the nitride semiconductor layer growing thereon.
- the nitride semiconductor layer is grown at high quality with a small defect density. Therefore, a high quality nitride semiconductor layer having a small defect density can be formed and the internal quantum efficiency can be increased by reducing the density of nitride semiconductor crystal defects. Even in the case of AlN in which the isotropic growth mode is dominant, it is possible to form high quality without irregular void generation.
- the hole type sacrificial layer pattern is formed by a controlled method such as photolithography or nanoimprint, the integrated void space is irregularly or randomly formed. Rather, it is formed in a controlled manner, so the reproducibility is good and the device uniformity is excellent.
- the nitride semiconductor epitaxial layer having excellent physical properties can be grown, an optoelectronic device having high efficiency and high reliability can be realized.
- the substrate structure and the semiconductor laminate structure according to the present invention include an integrated void space, there is little contact between the substrate and the nitride semiconductor layer and there is some physical separation therebetween. Accordingly, the nitride semiconductor layer can be separated from the nitride semiconductor layer and the substrate by a small physical force or impact naturally in the cooling process after growth of the nitride semiconductor layer or without applying a large energy such as a laser. Therefore, it is easy to separate the nitride semiconductor layer from the substrate even without using the laser lift-off, making it easy to manufacture vertical or horizontal LEDs, LEDs transferred or transferred to any substrate, or free standing nitride semiconductor substrates. Nitride semiconductor can be manufactured.
- 1 is a view for explaining a case of growing a nitride semiconductor layer using the existing PSS.
- FIG. 2 is a process perspective view illustrating a substrate structure, a semiconductor stack structure, methods for forming the same, and a method of manufacturing a nitride semiconductor according to the present invention.
- FIG. 3 shows a section III-III ′ of each step in FIG. 2.
- FIGS. 4 and 5 are views for explaining various methods for forming a hole type sacrificial layer pattern in the method according to the present invention.
- Figure 6 is a view showing to better see the crystallized inorganic thin film according to the present invention.
- FIG. 7 is a view showing that the nitride semiconductor layer and the substrate can be separated with a smaller force in accordance with the present invention.
- FIG. 2 is a perspective view illustrating processes of a substrate structure, a semiconductor stack structure, a method of forming the same, and a method of manufacturing a nitride semiconductor according to the present invention
- FIG. 3 is a cross-sectional view taken along the line III-III ′ of FIG. 2. do.
- a hole type sacrificial layer pattern 110 is formed on a single crystal substrate 100 heterogeneous with a nitride semiconductor.
- the sacrificial layer pattern 110 is formed to have a hole (H).
- the hole H is an opening that exposes the bottom surface of the substrate 100.
- the sacrificial layer pattern 110 may be formed according to various methods, and FIGS. 4 and 5 are views for explaining various methods of forming the hole type sacrificial layer pattern in the methods according to the present invention.
- the photoresist film PR is coated on the substrate 100 as shown in FIG. 4A.
- the photoresist film PR may be applied to the substrate 100 by selecting among spin coating, dip coating, spray coating, solution dropping, and dispensing. For uniformity of coating, spin coating is recommended.
- the photoresist film PR is exposed using the photomask 112 having the appropriate light shielding pattern 111.
- Light transmitted through a region other than the light shielding pattern 111 exposes a part of the photosensitive film PR, and an exposed portion EA is formed.
- the photoresist pattern PR ′ having the hole H may be left as shown in FIG. 4C.
- the photoresist film PR is an example of a positive type in which the exposed part is removed, but a negative photosensitive film in which the exposed part is not removed may be used, in which case, the position of the light shielding pattern of the photomask is changed.
- the hole of the photoresist pattern PR ′ that can be formed therefrom may also have the shape, size, The two-dimensional arrangement may be adjusted, and the photoresist pattern PR ′ may be used as the hole type sacrificial layer pattern 110. If necessary, additional processes such as reflow for modifying the shape of the photoresist pattern PR ′ may be further performed.
- the hole type sacrificial layer pattern 110 may be formed by a nano-imprint method.
- a nanoimprint resin R is coated on the substrate 100.
- the nanoimprint resin R may also be applied to the substrate 100 by selecting from spin coating, dip coating, spray coating, solution dropping, and dispensing.
- the nanoimprint stamp 114 may be a master mold made of silicon or quartz manufactured by a conventional manufacturing method, or may be an organic mold obtained by replicating the master mold.
- the nanoimprint stamp 114 is pressed onto the resin for nanoimprint R as in FIG. 5 (b).
- the nanoimprint resin R is filled between the patterns 113 of the nanoimprint stamp 114.
- the nanoimprint resin (R) is cured by heating at the same time as pressurization or by irradiating ultraviolet rays or by irradiating ultraviolet rays at the same time.
- the nanoimprint stamp 114 is separated, the cured nanoimprint resin R 'remains on the substrate 100 as shown in FIG. 5 (c), which is then transferred to the hole type sacrificial layer pattern 110. It becomes available.
- the concave-convex pattern 113 is formed to have a columnar shape to form a hole, and can be formed by controlling the shape, size, spacing, etc. according to the design of the nanoimprint method.
- the hole shape, size, and two-dimensional arrangement of the nanoimprint resin (R ') can also be adjusted. If necessary, the shape of the cured nanoimprint resin (R ′) may be modified by additional heating or ultraviolet irradiation.
- the pattern of the concave-convex structure may be manufactured by laser interference lithography or the like.
- Laser interference exposure process is a method of forming a periodic pattern using a two-dimensional or three-dimensional interference phenomenon generated by two or more laser light sources, it is an advantage that it can easily implement a fine pattern of less than 1 ⁇ m.
- a method of forming the hole type sacrificial layer pattern 110 is relatively simple, and the degree of damage to the substrate is relatively small compared to the case of etching the substrate in a technique such as PSS, and the process may be simplified. Can be.
- the substrate 100 on which the various hole type sacrificial layer patterns 110 are formed all hetero-monocrystalline substrates used for heterogeneous epitaxial growth of nitride semiconductor layers such as sapphire, silicon, SiC, and GaAs substrates may be used.
- nitride semiconductor layers such as sapphire, silicon, SiC, and GaAs substrates
- sapphire substrate the case of a sapphire substrate is demonstrated as an example.
- the sacrificial layer pattern 110 is formed as shown in FIGS. 2A and 3A, the sacrificial layer pattern 110 is described with reference to FIGS. 2B and 3B.
- An inorganic thin film 130 is formed on the top.
- the inorganic thin film 130 subsequently defines an empty space integrated with the substrate 100.
- the inorganic thin film 130 is performed within a temperature limit at which the sacrificial layer pattern 110 is not deformed. It is desirable to.
- the inorganic thin film 130 has a thickness such that the original shape can be stably maintained.
- Processes for forming the inorganic thin film 130 may be various methods such as atomic layer deposition (ALD), wet synthesis, metal deposition and oxidation, sputtering, etc. It is also possible to form metal nitride by supplying nitrogen in a gas or plasma state in the process of depositing the metal thin film.
- ALD atomic layer deposition
- wet synthesis metal deposition and oxidation
- sputtering etc.
- metal nitride by supplying nitrogen in a gas or plasma state in the process of depositing the metal thin film.
- the inorganic thin film 130 includes silica (SiO 2 ), alumina (Al 2 O 3 ), titania (TiO 2 ), zirconia (ZrO 2 ), yttria (Y 2 O 3 ) -zirconia, copper oxide (CuO, Cu 2 O) and tantalum oxide (Ta 2 O 5 ), aluminum nitride (AlN), silicon nitride (Si 3 N 4 ), or at least one of an oxide or a nitride, in the preferred embodiment using a sapphire substrate, the inorganic thin film is alumina Is preferably. In an embodiment using a silicon substrate, the inorganic thin film is preferably AlN.
- the inorganic thin film 130 By adjusting at least one of the composition, strength, and thickness of the inorganic thin film 130, it is possible to control the stress applied to the nitride semiconductor layer formed on the substrate structure using the same. As illustrated, the inorganic thin film 130 is formed on the entire surface of the substrate 100 while covering the sacrificial layer pattern 110.
- the inorganic thin film 130 when the inorganic thin film 130 is formed of ALD, a thin film can be deposited with a very uniform thickness.
- the inorganic thin film 130 has a hole ( H)
- the inner wall and the bottom of the hole H are coated without filling the inside, and the upper surface of the sacrificial layer pattern 110 is covered.
- Part of the inorganic thin film which is shaped like a pipe. If the diameter of the hole H is very small even by the method other than ALD or ALD, the inside of the hole H may be filled with the inorganic thin film 130. In such a case, the leg becomes columnar.
- the diameter of the hole H is preferably 2 ⁇ m or less. This is to fill the upper portion of the hole H when the nitride semiconductor layer is formed using ELO.
- the pitch between the holes H is preferably 2 ⁇ m or more. Maximizing the pitch is desirable to minimize the density of bridges such as pipes and columns.
- the alumina may be formed in a uniform thickness along the shape of the substrate 100 and the sacrificial layer pattern 110 by a deposition method such as ALD.
- a wet synthesis method using a wet solution is also possible.
- the wet solution may be uniformly coated along the shape of the substrate 100 and the hole type sacrificial layer pattern 110, and then alumina may be synthesized by heating, drying, or chemical reaction.
- an aluminum precursor powder such as aluminum chloride (AlCl 3 ) is mixed with a solvent such as tetrachloroethylene (C 2 Cl 4 ), and then coated on a substrate 100 on which the hole type sacrificial layer pattern 110 is formed.
- alumina thin film When heated and reacted in an oxygen atmosphere, an alumina thin film may be coated.
- alumina may be formed by depositing a metal Al thin film by sputtering or the like and then performing an oxidation process. Such alumina is formed in a state consisting of polycrystals of amorphous or fine particles.
- the sacrificial layer pattern 110 may be selectively removed from the substrate 100 as shown in FIGS. 2C and 3C. Since the sacrificial layer pattern 110 is a polymer such as a photoresist film or a nanoimprint resin as described with reference to FIGS. 4 and 5, a method of easily removing the sacrificial layer pattern 110 is heating. Photoresist films with spontaneous flash points usually around 600 ° C can be easily removed by heat. And in order to burn more easily by the oxidation method, a chemical reaction with a gas containing oxygen may be added. Heating to a high temperature in an oxygen atmosphere makes it easy to remove polymer components by a pyrolysis process, commonly called ashing. When the heat treatment of the oxygen atmosphere is not appropriate, for example, when the substrate 100 is a silicon substrate and an oxide is concerned, wet removal using an organic solvent may be used.
- the integrated empty space C defined by the substrate 100 and the inorganic thin film 130 is formed. Can be formed.
- the empty space C defined by the inorganic thin film 130 has a shape in which the sacrificial layer pattern 110 is inverted. That is, when the sacrificial layer pattern 110 is formed to have a plurality of holes H spaced apart from each other, the inorganic thin film 130 is connected to the substrate 100 through the plurality of holes H.
- the empty space C is the remaining portion except for the portion where the inorganic thin film 130 is connected to the substrate 100 and the holes H are spaced apart from each other so that the empty space C is integrated into one in which each other is in communication with each other.
- the volume is larger when the empty space C is a continuous continuous space compared to a plurality of discrete spaces separated from each other.
- the substrate 100 and the structure formed thereon may have a minimum contact area.
- As-deposited inorganic thin film 130 usually has an amorphous or very small polycrystalline crystals.
- the heat treatment is preferably performed to raise the temperature to a high temperature so that the amorphous or polycrystalline inorganic thin film 130 can be densified and crystallized.
- the inorganic thin film 130 is made of the same composition as the substrate 100 or the substrate 100 is a silicon substrate and the inorganic thin film 130, such as the substrate 100 is a sapphire substrate and the inorganic thin film 130 is alumina. Even when the inorganic thin film 130 is of a material different from that of the substrate 100 as in the case of AlN, for example, when the heating is performed at about 1000 ° C., the inorganic thin film 130 is heat treated by heat treatment. As shown in FIG. 3 (d), the inorganic thin film 130 ′ crystallized in the same crystal structure as the substrate 100 is formed.
- the interface between the crystallized inorganic thin film 130 ′ and the substrate 100 disappears. This is because direct contact with the substrate 100 during the high temperature heat treatment and solid phase epitaxy occurs in the inorganic thin film 130 to cause crystallization along the crystal direction of the substrate 100.
- the solid phase epitaxy starts from the interface between the substrate 100 and the inorganic thin film 130, and when the inorganic thin film 130 is amorphous, the finally crystallized inorganic thin film 130 ′ becomes polycrystalline or fine polycrystalline. If the size is larger or most desirable, it will turn into a single crystal, such as the substrate 100.
- This crystallization is preferably to occur throughout the inorganic thin film 130, in particular formed in the portion of the crystallized inorganic thin film 130 ', ie, the substrate 100 and subsequent processing over the integrated void space (C)
- FIG. 6 is a view illustrating the crystallized inorganic thin film 130 ′ according to the present invention for better viewing.
- the crystallized inorganic thin film 130 ′ includes a leg portion 130a contacting the substrate 100 and an upper surface portion 130b extending from the leg portion 130a and parallel to the substrate 100. have.
- An empty space C integrated between the substrate 100 and the substrate 100 is defined by the crystallized inorganic thin film 130 ′.
- There are a plurality of leg portions 130a and the upper surface portion 130b extends from the plurality of leg portions 130a and is formed continuously.
- the area occupied by the empty space C is larger than the area occupied by the leg portion 130a.
- the inorganic thin film 130 ′ is very important in the present invention because it defines the void space C integrated with the substrate 100 and serves as a seed layer and a support of the nitride semiconductor layer subsequently grown thereon. to be.
- the substrate structure according to the present invention has a leg 130a and a leg in contact with the substrate 100 so that an empty space C integrated between the substrate 100 and the substrate 100 is defined.
- An inorganic thin film 130 ′ including an upper surface portion 130b extending from the portion 130a and parallel to the substrate 100 and crystallized in the same crystal structure as the substrate 100 is included.
- a substrate structure according to the present invention will be defined as CES (Cavity Engineered Substrate).
- CES Chemical Engineered Substrate
- the present invention relates to a semiconductor laminated structure using such a CES, a method of forming the same, and a method of manufacturing a nitride semiconductor.
- the nitride semiconductor layer 150 is further formed on the crystallized inorganic thin film 130 ′.
- the nitride semiconductor layer 150 may be formed in a multilayer structure including an appropriate buffer layer.
- the nitride semiconductor layer 150 includes all nitride semiconductor materials such as Ga x Al y In z N (0 ⁇ x, y, z ⁇ 1), which is GaN, InN, AlN, or a combination thereof.
- the band gap may be adjusted according to the material of the nitride semiconductor layer 150 to emit light in the ultraviolet, visible and infrared regions.
- the nitride semiconductor layer 150 is not grown on the substrate 100, but the seeds are formed from the portion of the crystallized inorganic thin film 130 ′, particularly the upper surface 130b, above the integrated void C.
- the parts grown therefrom are coalesced according to the growth conditions to finally form the nitride semiconductor layer 155 in the form of a thin film connected as shown in FIGS. 2F and 3F.
- the nitride semiconductor layer 155 is grown not from the substrate 100 but from the portion of the crystallized inorganic thin film 130 'on the integrated empty space C, the nitride semiconductor layer 155 is grown in a completely different manner from the ELO method.
- the semiconductor layer 155 is formed.
- the nitride semiconductor is formed on the upper flat surface of the inorganic thin film 130 ', that is, the upper surface portion 130b.
- the growth of the layer 150 starts to grow in the form of covering the leg portion 130a, that is, the upper portion of the hole shape.
- the nitride semiconductor layer 150 started to grow in the upper surface portion 130b is formed in the nitride semiconductor layer 155 which is connected laterally and has fewer crystal defects.
- the inorganic thin film 130 ′ crystallized according to the present invention can solve the stress by dividing the stress with the nitride semiconductor layer 155 growing thereon, thereby acting as a compliant layer, and the stress which can generate dislocations is eliminated. As it grows, it grows with high quality with small defect density.
- the stress due to the physical difference between the substrate and the thin film becomes a driving force that is converted into elastic energy at the interface to generate dislocations.
- the deformation is difficult. Instead, the stress is released as the dislocation is generated in the thin film.
- the elastic energy at the interface becomes larger than the generated energy of the dislocation so that dislocations start to occur.
- the inorganic thin film 130 ′ when the inorganic thin film 130 ′ is thinner than the nitride semiconductor layer 155, the potential thickness of the nitride semiconductor layer 155 is lowered because the critical thickness is larger.
- the inorganic thin film 130 ′ when the inorganic thin film 130 ′ is thinner than the nitride semiconductor layer 155, it can be regarded that the roles of the substrate and the thin film are changed in a normal case, and the nitride semiconductor layer 155 grows in a state in which dislocations are generated less. Done. Therefore, since the nitride semiconductor layer 155 of high quality having a small defect density can be formed and the nitride semiconductor crystal defect density is reduced, the internal quantum efficiency can be increased when manufacturing the LED.
- the semiconductor stack structure according to the present invention formed as described above has a single crystal substrate 100 heterogeneous with a nitride semiconductor and a crystallized inorganic thin film 130 ′. It includes. An integrated empty space C is defined between the substrate 100 and the inorganic thin film 130 ′.
- the substrate structure also includes a nitride semiconductor layer 155 that is grown and coalesced from the crystallized inorganic thin film 130 'above the integrated void space C.
- the integrated empty space C is a position where the hole type sacrificial layer pattern 110 is removed during the formation method. Since there is an integrated void space C, if there is a difference in coefficient of thermal expansion between the substrate 100 and the nitride semiconductor layer 155 formed thereon, the integrated void space C is locally stretched or compressed in the plane direction. Phosphorus deformation may occur and stress energy may be consumed. Accordingly, the thermal stress applied to the nitride semiconductor layer 155 may be reduced, and thus the warpage phenomenon of the substrate 100 may be reduced. This makes it possible to use a relatively thin thickness even if the substrate 100 has a large area.
- the integrated empty space C may be controlled by adjusting the shape, size, and two-dimensional arrangement of the hole type sacrificial layer pattern, such as photolithography or nanoimprint when forming the hole type sacrificial layer pattern 110. Since it is formed in a controlled manner, the integrated void space C is not formed irregularly or randomly, but is formed in a controlled manner, and thus the reproducibility is good and the device uniformity is excellent.
- nitride semiconductor layer 155 having excellent physical properties can be epitaxially grown, an optoelectronic device having high efficiency and high reliability can be realized.
- high-output LD and LED may be implemented according to an increase in light extraction efficiency.
- the integrated empty space C enables a structure in which the connection between the substrate 100 and the nitride semiconductor layer 155 is minimized. Since the substrate 100 and the nitride semiconductor layer 155 are physically separated to some extent, the stress generation is further suppressed, and naturally, during the cooling after the growth of the nitride semiconductor layer 155, or a large energy such as a laser is applied. It is possible to separate between the nitride semiconductor layer 155 and the substrate 100 as shown in Fig. 2 (g) and 3 (g) by a small physical force or impact without applying.
- the area occupied by the empty space C is larger than the area occupied by the leg portion 130a. Therefore, it is easy to separate the nitride semiconductor layer 155 from the substrate 100 even without using laser lift-off. Since it is naturally separated or separated by a small force, the nitride semiconductor layer 155 can be separated without bending, cracking or breaking. Accordingly, the substrate 100 and the nitride semiconductor layer 155 are highly advantageous for the manufacture of applications requiring the separation of the substrate 100 such as a vertical LED or a horizontal LED, an LED transferred to any substrate, and the substrate 100 is easy to recycle.
- the nitride semiconductor layer 155 is formed into a thick film to be separated from the substrate 100 or may be used as a free standing nitride semiconductor substrate, it is easy to manufacture a nitride semiconductor substrate as a homogeneous substrate for excellent nitride semiconductor growth.
- the substrate 100 and the nitride semiconductor layer 155 are connected to each other by a non-linear point.
- the part connected by dots is the leg part 130a of the inorganic thin film 130 ', Preferably it is a hollow pipe shape.
- the preferred embodiment of the present invention uses the hole type sacrificial layer pattern 120 and the formation of the inorganic thin film 130 by ALD.
- the final structure obtained by removing such a sacrificial layer pattern 120 has an integrated empty space C connected in series.
- This integrated empty space C facilitates physical lift-off without using a laser.
- FIG. 7 illustrates the bridge portion 130a connecting the nitride semiconductor layer 155 and the substrate 100, that is, the area of the pillar becomes smaller from (a) to (d) and with the nitride semiconductor layer 155 with a smaller force.
- the figure shows that the substrate 100 can be separated.
- the most preferred embodiment is to minimize the direct connection between the nitride semiconductor layer 155 and the substrate 100 such that the pillar structure is hollow, that is, a pipe shape such as (d).
- a structure for supporting the nitride semiconductor layer 155 using the inorganic thin film 130 'having the pipe-shaped leg portion 130a having an empty inside is used.
- the present invention it is possible to induce dislocations to be generated only in the upper portion of the leg 130a, that is, the hole, and unlike the PSS, it is possible to improve the crystal quality even when growing AlN.
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Abstract
Description
Claims (12)
- 질화물 반도체와 이종인 단결정 기판; 및상기 기판과의 사이에 일체화된 빈 공간(cavity)이 정의되도록 상기 기판과 접촉하는 다리부 및 상기 다리부로부터 연장되어 상기 기판과 평행한 상면부를 포함하고 상기 기판과 같은 결정 구조로 결정화된 무기물 박막을 포함하는 기판 구조.
- 제1항에 있어서, 상기 다리부는 속이 빈 파이프 모양인 것을 특징으로 하는 기판 구조.
- 제1항에 있어서, 상기 다리부는 복수개이고 상기 상면부는 복수개의 다리부로부터 연장되어 연속적으로 형성되어 있는 것을 특징으로 하는 기판 구조.
- 제3항에 있어서, 상기 다리부가 차지하는 면적보다 상기 빈 공간이 차지하는 면적이 더 큰 것을 특징으로 하는 기판 구조.
- 질화물 반도체와 이종인 단결정 기판;상기 기판과의 사이에 일체화된 빈 공간(cavity)이 정의되도록 상기 기판과 접촉하는 다리부 및 상기 다리부로부터 연장되어 상기 기판과 평행한 상면부를 포함하고 상기 기판과 같은 결정 구조로 결정화된 무기물 박막; 및상기 무기물 박막 상에 형성된 질화물 반도체층을 포함하는 반도체 적층 구조.
- 제5항에 있어서, 상기 질화물 반도체층은 상기 일체화된 빈 공간 위의 결정화된 무기물 박막 상에서부터 성장하여 합체된 것임을 특징으로 하는 반도체 적층 구조.
- 질화물 반도체와 이종인 단결정 기판 상에 홀 타입 희생층 패턴을 형성하는 단계;상기 희생층 패턴 상에 무기물 박막을 형성하는 단계;상기 기판과 무기물 박막으로 정의되는 일체화된 빈 공간(cavity)이 형성되도록, 상기 무기물 박막이 형성된 상기 기판으로부터 상기 희생층 패턴을 제거하는 단계; 및상기 기판과 같은 결정 구조로 상기 무기물 박막을 결정화시키는 단계를 포함하는 기판 구조 형성방법.
- 제7항에 있어서, 상기 무기물 박막을 형성하는 단계는 ALD에 의하는 것을 특징으로 하는 기판 구조 형성방법.
- 제7항에 있어서, 상기 희생층 패턴을 제거하는 단계는 산소 분위기에서의 열처리 또는 유기 용매를 이용한 습식 제거인 것을 특징으로 하는 기판 구조 형성방법.
- 제7항에 있어서, 상기 희생층 패턴을 제거하는 단계는 산소 분위기에서의 열처리로 수행하고, 상기 무기물 박막을 결정화시키는 단계는 그보다 온도가 높은 열처리로 수행하는 것을 특징으로 하는 기판 구조 형성방법.
- 질화물 반도체와 이종인 단결정 기판 상에 홀 타입 희생층 패턴을 형성하는 단계;상기 희생층 패턴 상에 무기물 박막을 형성하는 단계;상기 기판과 무기물 박막으로 정의되는 일체화된 빈 공간(cavity)이 형성되도록, 상기 무기물 박막이 형성된 상기 기판으로부터 상기 희생층 패턴을 제거하는 단계;상기 기판과 같은 결정 구조로 상기 무기물 박막을 결정화시키는 단계; 및상기 빈 공간 위의 상기 결정화된 무기물 박막 상에 질화물 반도체층을 성장시키는 단계를 포함하는 반도체 적층 구조 형성방법.
- 질화물 반도체와 이종인 단결정 기판 상에 홀 타입 희생층 패턴을 형성하는 단계;상기 희생층 패턴 상에 무기물 박막을 형성하는 단계;상기 기판과 무기물 박막으로 정의되는 일체화된 빈 공간(cavity)이 형성되도록, 상기 무기물 박막이 형성된 상기 기판으로부터 상기 희생층 패턴을 제거하는 단계;상기 기판과 같은 결정 구조로 상기 무기물 박막을 결정화시키는 단계;상기 빈 공간 위의 상기 결정화된 무기물 박막 상에 질화물 반도체층을 성장시키는 단계; 및상기 기판과 상기 질화물 반도체층 사이를 분리시키는 단계를 더 포함하는 질화물 반도체 제조방법.
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DE112015003258.4T DE112015003258T5 (de) | 2014-07-14 | 2015-06-19 | Substratstruktur, Verfahren zum Bilden derselben und Verfahren zur Herstellung eines Nitridhalbleiters unter Verwendung derselben |
CN201580048455.3A CN106688112B (zh) | 2014-07-14 | 2015-06-19 | 衬底结构、其形成方法以及使用其制造氮化物半导体的方法 |
US15/326,256 US10355169B2 (en) | 2014-07-14 | 2015-06-19 | Substrate structure, method for forming same, and method for manufacturing nitride semiconductor using same |
JP2017523745A JP6745799B2 (ja) | 2014-07-14 | 2015-06-19 | 基板構造及びその形成方法、並びにこれを用いた窒化物半導体の製造方法 |
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CN106688112A (zh) | 2017-05-17 |
KR102232265B1 (ko) | 2021-03-25 |
JP2017521878A (ja) | 2017-08-03 |
JP6745799B2 (ja) | 2020-08-26 |
CN106688112B (zh) | 2019-10-22 |
US20170213938A1 (en) | 2017-07-27 |
DE112015003258T5 (de) | 2017-04-13 |
US10355169B2 (en) | 2019-07-16 |
KR20160008339A (ko) | 2016-01-22 |
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