WO2012120930A1 - Structure de montage de dispositif de dispositif semi-conducteur - Google Patents

Structure de montage de dispositif de dispositif semi-conducteur Download PDF

Info

Publication number
WO2012120930A1
WO2012120930A1 PCT/JP2012/051405 JP2012051405W WO2012120930A1 WO 2012120930 A1 WO2012120930 A1 WO 2012120930A1 JP 2012051405 W JP2012051405 W JP 2012051405W WO 2012120930 A1 WO2012120930 A1 WO 2012120930A1
Authority
WO
WIPO (PCT)
Prior art keywords
lead
source
gate
drain
terminal
Prior art date
Application number
PCT/JP2012/051405
Other languages
English (en)
Japanese (ja)
Inventor
井尻　良
明照 頼
Original Assignee
シャープ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by シャープ株式会社 filed Critical シャープ株式会社
Priority to CN2012800122915A priority Critical patent/CN103415924A/zh
Publication of WO2012120930A1 publication Critical patent/WO2012120930A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49177—Combinations of different arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13064—High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Definitions

  • the present invention relates to a semiconductor device, and more particularly to a device mounting structure when a power device chip using GaN is mounted on a frame.
  • the breakdown voltage of a device is expressed by the product of the length of the drift layer (WD) and the breakdown electric field (Ec). Therefore, when the breakdown voltage is the same, the length of the drift layer can be shortened when the breakdown electric field is large.
  • the dielectric breakdown electric field is about 10 times higher than that of Si, so that the length of the drift layer can be reduced to about 1/10.
  • the impurity concentration is proportional to the square of the dielectric breakdown electric field, it can be made 100 times higher than Si.
  • Ron on-resistance of the device using the wide gap semiconductor can be reduced to about 1/1000 compared to the device using Si.
  • a cut-off frequency (fT) as an index representing the high-speed response of the device.
  • the cutoff frequency is a frequency at which the current gain of the device is 1, and is inversely proportional to the length WD of the drift layer. Therefore, in a device using a wide gap semiconductor, since the length of the drift layer can be set to 1/10 compared to Si, it can be used at a frequency one digit higher than Si.
  • the device As a device mounting method using the above wide gap semiconductor, as shown in Patent Documents 1 and 2, the device is fixed on the die pad of the lead frame in which the drain lead and the die pad are connected, and the device and the drain lead, the source lead, A method of connecting to the gate lead by wire bonding has been conventionally used.
  • the present invention realizes a reduction in parasitic inductance from the surface of a device mounting structure so that parasitic oscillation can be suppressed without adding a large gate resistance in a device using GaN. Accordingly, it is an object to realize a power device that takes advantage of the low power consumption and high-speed response characteristics that are characteristic of GaN.
  • a semiconductor device provides: A power device using GaN, in which at least three terminals of a source terminal, a drain terminal, and a gate terminal are provided on the substrate surface side, is mounted on the die pad part of a lead frame in which a source lead part and a die pad part are integrally formed, The source terminal of the power device is wire-connected to the die pad portion;
  • the power device has a device mounting structure in which the drain terminal of the power device is connected to a drain lead, and the gate terminal of the power device is connected to the gate lead by wire.
  • the drain lead is disposed between the gate lead and the source lead portion of the lead frame.
  • the transistor constituting the power device further includes: A source electrode connected to the source terminal; a drain electrode connected to the drain terminal; and a gate electrode connected to the gate terminal, wherein the gate electrode is arranged closer to the source electrode side than the drain electrode. It preferably has an asymmetric structure.
  • the area of the inner lead portion to be resin-sealed in the drain lead is larger than the area of the inner lead portion to be resin-sealed in the gate lead.
  • a lower voltage is supplied to the source lead of the lead frame than to the drain lead.
  • the inventors of the present invention have intensively researched and found that by reducing the parasitic inductance of the source-side wiring, oscillation can be suppressed and stable switching can be performed with respect to ON / OFF of the gate voltage.
  • Fig. 5 shows the circuit configuration used in the simulation.
  • Ld, Ls1, Ls2, and Lgs are parasitic inductances of wirings, respectively, and Cgd, Cgs, and Cds are parasitic capacitances of GaN-FETs.
  • the LC series circuit from Ld to Coss, Ls1, and Ls2 resonates.
  • the voltage across Ls1 vibrates.
  • the vibration of the voltage across Ls1 becomes a voltage noise source for the gate driver.
  • the resonance of the LC series circuit via Coss, Ls1, and Ls2 from Ld and the resonance of the LC series circuit via Cgs and Ls1 are mutually induced.
  • the oscillation of the gate voltage Vg is amplified.
  • the switching noise increases, and in the worst case, the FET may oscillate and the circuit may be destroyed.
  • Ld and Ls1 should be made as small as possible in order to prevent resonance by the LC circuit.
  • FIG. 6 shows the result of simulating changes in the gate voltage rising and falling during switching when the parasitic inductance Ls1 of the source side wiring and the parasitic inductance Ld of the drain side wiring are changed. From FIG. 6, the gate voltage oscillation is prevented by reducing the parasitic inductance Ls1 of the source side wiring (FIG. 6A) rather than reducing the parasitic inductance Ld of the drain side wiring (FIG. 6B). It can be seen that there is a remarkable effect.
  • the parasitic inductance Ld of the drain side wiring is made smaller (FIG. 7B) than the source side. It can be seen that the loss is reduced when the parasitic inductance Ls1 of the wiring is reduced (FIG. 7A).
  • the device mounting method is changed, and in the conventional SiMOSFET, the die pad connected to the drain lead is connected to the source lead, and the die pad and the source terminal of the device are connected.
  • the connection was made by wire bonding.
  • the potential difference between the source terminal of the GaN chip and the back surface of the chip can be reduced as compared with the conventional structure in which the die pad and the drain lead are integrally formed, thereby reducing the leakage current from the back surface of the chip and reducing the on-resistance. it can.
  • the loop current between the gate and the source is reduced, the parasitic inductance of the source wiring is suppressed, and the oscillation of the LC series circuit via Cgs can be suppressed.
  • parasitic oscillation can be suppressed without adding a large gate resistance, and a power device utilizing the low power consumption and high-speed response characteristics of GaN is realized. be able to.
  • Chip mounting example of semiconductor device according to the present invention Example of chip mounting of a semiconductor device according to the prior art Sectional drawing which shows the device structure of the power device using GaN.
  • Other chip mounting examples of the semiconductor device according to the present invention Circuit diagram for explaining the problem of the present invention It is a graph for demonstrating the effect of this invention, and is a graph which shows the change of the gate voltage of the rise and fall of the gate voltage at the time of switching It is a graph for demonstrating the effect of this invention, and is a graph which shows the time change of the power loss produced in FET at the time of switching
  • FIG. 1 is a schematic diagram of a form after the semiconductor device 10 is mounted.
  • FIG. 2 shows a schematic diagram of a form after mounting when the semiconductor device 10 is mounted on a chip by a conventional method.
  • the same components are denoted by the same reference numerals, and the names and functions are also the same, so the same description will not be repeated.
  • the semiconductor device 10 is a power device configured using GaN, and a source terminal 11, a drain terminal 12, and a gate terminal 13 are formed on the substrate surface side.
  • the semiconductor device 10 is mounted and fixed on the die pad 14.
  • FIG. 3 shows a schematic cross-sectional view of the device structure of the power device using GaN.
  • the device shown in FIG. 3 is an FET having a HEMT (High Electron Mobility Transistor) structure, and a GaN layer 22 is formed on a Si substrate 20 via a buffer layer 21 made of an AlGaN multilayer film having different composition ratios of Al and Ga.
  • the AlGaN layer 23 is laminated on the GaN layer 22.
  • a source electrode 24 and a drain electrode 25 are formed in a predetermined region on the GaN layer 22 so as to penetrate the AlGaN layer 23, and a gate electrode 26 is formed in the predetermined region on the AlGaN layer 23.
  • the electrodes 25 are formed so as to face each other with the gate electrode 26 interposed therebetween.
  • the drain electrode 25 is electrically connected to the drain terminal 12 formed on the insulating film 27 through the contact hole 28.
  • the source electrode 24 is electrically connected to the source terminal 11 formed on the insulating film 27 in another cross section
  • the gate electrode 25 is formed on the insulating film 27 in another cross section. Are electrically connected to the gate terminal 13 formed in the circuit.
  • a two-dimensional electron gas layer 29 is formed, and by applying a voltage (gate voltage) to the gate electrode 26, the two-dimensional electron gas layer 29 below the gate electrode 26.
  • the concentration of the electron gas layer is modulated, and the current flowing between the source electrode 24 and the drain electrode 25 is controlled.
  • the distance between the gate electrode 26 and the drain electrode 25 is set so as not to discharge.
  • the device has an asymmetric device structure in which the gate electrode 26 is arranged closer to the source electrode 24 side than the drain electrode 25 with a distance greater than the distance from the source electrode 24.
  • the source lead 15, the drain lead 16, and the gate lead 17 are formed in this order adjacent to the semiconductor device 10. That is, the drain lead 16 is disposed between the gate lead 17 and the source lead 15. These lead terminals 15, 16, and 17 are respectively connected to the source terminal 11, the drain terminal 12, and the gate terminal 13 of the semiconductor device 1 by wire connection (wire bonding). Further, resin sealing is performed so as to cover the wire-connected portion in the region 18 indicated by the dotted line in FIG. 1 or FIG. 2, and the semiconductor device 10 is packaged.
  • the source lead 15 and the die pad 14 are integrally formed to form a lead frame, and the connection between the source terminal 11 and the source lead 15 is connected to the source terminal 11 and the die pad 14. Are made by wire bonding.
  • the drain lead 16 and the gate lead 17 are formed separately from the die pad 14, and the drain lead 16 and the drain terminal 12, and the gate lead 17 and the gate terminal 13 are connected by wire bonding.
  • the drain lead 16 and the die pad 14 are integrally formed to constitute a lead frame, and the connection between the drain terminal 12 and the drain lead 16 is connected to the drain terminal 12 and the die pad. 14 is formed by wire bonding.
  • the source lead 15 and the gate lead 17 are formed separately from the die pad 14, and the source lead 15 and the source terminal 11 and the gate lead 17 and the gate terminal 13 are connected by wire bonding.
  • the potential of the substrate becomes the source voltage via the potential on the back surface of the chip.
  • the leakage current that is fixed and flows to the back surface of the chip via the substrate can be reduced, and as a result, the on-resistance can be reduced. Further, the parasitic inductance of the source wiring is suppressed, and the oscillation of the gate voltage can be suppressed.
  • the drain lead 16 is wire-bonded to the drain terminal 12.
  • the drain lead 16 and the die pad 14 are integrally formed, and the drain terminal 12 and the die pad 14 are wire-bonded in a conventional configuration (FIG. Compared with 2), the parasitic inductance of the drain wiring increases on the contrary.
  • reducing the parasitic inductance on the source wiring side suppresses the oscillation of the gate voltage than reducing the parasitic inductance on the drain wiring side (Ld in FIG. 5). In that respect.
  • FIG. 6 reducing the parasitic inductance on the source wiring side (Ls1 in FIG. 5) suppresses the oscillation of the gate voltage than reducing the parasitic inductance on the drain wiring side (Ld in FIG. 5). In that respect.
  • FIG. 6 reducing the parasitic inductance on the source wiring side (Ls1 in FIG. 5) suppresses the oscillation of the gate voltage than reducing the parasitic inductance on the drain wiring side (Ld in FIG. 5).
  • FIG. 4 another mounting example of the semiconductor device 10 is shown in FIG.
  • the area of the portion of the drain lead 16 overlapping the region 18, that is, the area of the resin lead-sealed portion (inner lead) in the drain lead 16 is the same as the portion of the gate lead 17 overlapping the region 18, that is, the gate lead 17.
  • the area is larger than the area of the resin-sealed portion.
  • the resin-sealed portion of the drain lead 16 (gate lead 17) corresponds to the area of the portion where wire bonding is possible.
  • the present invention can be used for mounting a power device using GaN as a switching element.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

L'invention concerne une structure de montage de dispositif qui peut utiliser les mérites d'une faible consommation de puissance et de caractéristiques de réponse rapide d'un dispositif semi-conducteur utilisant du GaN. Un dispositif au GaN (10) est monté sur une pastille de puce (14) au moyen d'une grille de connexion dans laquelle un conducteur de source (15) et la pastille de puce sont formés en un bloc. Ensuite, une borne de source (11) du dispositif au GaN est montée en étant liée par câble à la pastille de puce (14). Par conséquent, un courant de fuite depuis la surface arrière de la puce est réduit, la résistance à l'état passant est réduite, un courant de boucle entre la gâchette et la source est réduit, et l'inductance parasite du côté du câblage de la source est réduite, supprimant ainsi l'oscillation de la tension de gâchette via une capacité parasite entre la gâchette et la source.
PCT/JP2012/051405 2011-03-09 2012-01-24 Structure de montage de dispositif de dispositif semi-conducteur WO2012120930A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2012800122915A CN103415924A (zh) 2011-03-09 2012-01-24 半导体装置的器件安装构造

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2011052083A JP2012190936A (ja) 2011-03-09 2011-03-09 半導体装置のデバイス実装構造
JP2011-052083 2011-03-09

Publications (1)

Publication Number Publication Date
WO2012120930A1 true WO2012120930A1 (fr) 2012-09-13

Family

ID=46797901

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2012/051405 WO2012120930A1 (fr) 2011-03-09 2012-01-24 Structure de montage de dispositif de dispositif semi-conducteur

Country Status (3)

Country Link
JP (1) JP2012190936A (fr)
CN (1) CN103415924A (fr)
WO (1) WO2012120930A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103578985A (zh) * 2013-11-01 2014-02-12 中航（重庆）微电子有限公司 半导体器件及其制作方法
WO2017017901A1 (fr) * 2015-07-29 2017-02-02 パナソニックＩｐマネジメント株式会社 Dispositif à semi-conducteur
CN112420681A (zh) * 2019-08-20 2021-02-26 苏州捷芯威半导体有限公司 一种芯片封装结构

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5815976B2 (ja) * 2011-04-21 2015-11-17 トランスフォーム・ジャパン株式会社 半導体装置
JP6352009B2 (ja) 2013-04-16 2018-07-04 ローム株式会社 半導体装置
JP6535509B2 (ja) 2014-05-12 2019-06-26 ローム株式会社 半導体装置
CN116093058B (zh) * 2023-02-28 2024-01-09 中科华艺(天津)科技有限公司 一种氮化镓半导体抗干扰封装结构

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10261756A (ja) * 1997-03-19 1998-09-29 Hitachi Ltd 半導体装置およびその製造方法
JP2006005005A (ja) * 2004-06-15 2006-01-05 Toshiba Corp 窒素化合物含有半導体装置
JP2008066553A (ja) * 2006-09-08 2008-03-21 Furukawa Electric Co Ltd:The 半導体装置
JP2010238892A (ja) * 2009-03-31 2010-10-21 Sharp Corp 半導体装置およびその製造方法
JP2011129875A (ja) * 2009-11-20 2011-06-30 Panasonic Corp 半導体装置及びそのリードフレーム

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10261756A (ja) * 1997-03-19 1998-09-29 Hitachi Ltd 半導体装置およびその製造方法
JP2006005005A (ja) * 2004-06-15 2006-01-05 Toshiba Corp 窒素化合物含有半導体装置
JP2008066553A (ja) * 2006-09-08 2008-03-21 Furukawa Electric Co Ltd:The 半導体装置
JP2010238892A (ja) * 2009-03-31 2010-10-21 Sharp Corp 半導体装置およびその製造方法
JP2011129875A (ja) * 2009-11-20 2011-06-30 Panasonic Corp 半導体装置及びそのリードフレーム

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103578985A (zh) * 2013-11-01 2014-02-12 中航（重庆）微电子有限公司 半导体器件及其制作方法
WO2017017901A1 (fr) * 2015-07-29 2017-02-02 パナソニックＩｐマネジメント株式会社 Dispositif à semi-conducteur
JPWO2017017901A1 (ja) * 2015-07-29 2018-04-05 パナソニックＩｐマネジメント株式会社 半導体装置
US10211144B2 (en) 2015-07-29 2019-02-19 Panasonic Intellectual Property Management Co., Ltd. Semiconductor device having a plurality of top surface connection terminals
CN112420681A (zh) * 2019-08-20 2021-02-26 苏州捷芯威半导体有限公司 一种芯片封装结构
CN112420681B (zh) * 2019-08-20 2024-02-27 苏州捷芯威半导体有限公司 一种芯片封装结构

Also Published As

Publication number Publication date
CN103415924A (zh) 2013-11-27
JP2012190936A (ja) 2012-10-04

Similar Documents

Publication Publication Date Title
WO2012120930A1 (fr) Structure de montage de dispositif de dispositif semi-conducteur
JP6909881B2 (ja) フェライトビーズを有するスイッチング回路
JP6827776B2 (ja) 半導体デバイス
US9041456B2 (en) Power semiconductor device
JP5883392B2 (ja) 低ｅｍｉ回路のためのパッケージ構成
JP6277429B2 (ja) 半導体装置
US9171837B2 (en) Cascode circuit
JP5789967B2 (ja) 半導体装置及びその製造方法、電源装置
JP5653326B2 (ja) 窒化物半導体装置
JP6565223B2 (ja) 半導体装置及びその製造方法、電源装置、高周波増幅器
WO2013077081A1 (fr) Dispositif semi-conducteur et appareil électronique
US20220392887A1 (en) Semiconductor device
JP6996241B2 (ja) 化合物半導体装置及びその製造方法、電源装置、高周波増幅器
WO2014192348A1 (fr) Dispositif semi-conducteur
WO2013157300A1 (fr) Structure de montage de dispositif dans un dispositif à semiconducteur
JP2013026342A (ja) 窒化物半導体装置
TWI777389B (zh) 雙電晶體的封裝結構
CN214477434U (zh) 双电晶体的封装结构
CN214477435U (zh) 双电晶体的封装结构
TWI751009B (zh) 雙電晶體的封裝結構
TWI751008B (zh) 雙電晶體的封裝結構
JP5935425B2 (ja) 半導体装置
CN115810624A (zh) 半导体装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12755596

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 12755596

Country of ref document: EP

Kind code of ref document: A1