WO2013157300A1 - Structure de montage de dispositif dans un dispositif à semiconducteur - Google Patents
Structure de montage de dispositif dans un dispositif à semiconducteur Download PDFInfo
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- WO2013157300A1 WO2013157300A1 PCT/JP2013/054757 JP2013054757W WO2013157300A1 WO 2013157300 A1 WO2013157300 A1 WO 2013157300A1 JP 2013054757 W JP2013054757 W JP 2013054757W WO 2013157300 A1 WO2013157300 A1 WO 2013157300A1
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- Prior art keywords
- drain
- source
- die pad
- lead
- gate
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 230000003071 parasitic effect Effects 0.000 abstract description 34
- 230000010355 oscillation Effects 0.000 abstract description 17
- 230000004044 response Effects 0.000 abstract description 6
- 230000008901 benefit Effects 0.000 abstract description 5
- 230000003247 decreasing effect Effects 0.000 abstract 2
- 229910002601 GaN Inorganic materials 0.000 description 29
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 29
- 229920005989 resin Polymers 0.000 description 13
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- 238000007789 sealing Methods 0.000 description 13
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- 229910002704 AlGaN Inorganic materials 0.000 description 6
- 230000005684 electric field Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 4
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- 230000002093 peripheral effect Effects 0.000 description 2
- 230000005533 two-dimensional electron gas Effects 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
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- 229920006223 adhesive resin Polymers 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
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Definitions
- the present invention relates to a semiconductor device, and more particularly to a device mounting structure when a power device chip using GaN is mounted on a frame.
- the breakdown voltage of a device is expressed by the product of the length of the drift layer (WD) and the breakdown electric field (Ec). Therefore, when the breakdown voltage is the same, the length of the drift layer can be shortened when the breakdown electric field is large.
- the length of the drift layer can be reduced to about 1/10.
- the impurity concentration is proportional to the square of the dielectric breakdown electric field, it can be made 100 times higher than Si.
- the on-resistance (Ron) of the device using the wide gap semiconductor can be reduced to about 1/1000 compared to the device using Si.
- a cut-off frequency (fT) as an index representing the high-speed response of the device.
- the cutoff frequency is a frequency at which the current gain of the device is 1, and is inversely proportional to the length WD of the drift layer. Therefore, in a device using a wide gap semiconductor, since the length of the drift layer can be set to 1/10 compared to Si, it can be used at a frequency one digit higher than Si.
- the device As a device mounting method using the above wide gap semiconductor, as shown in Patent Documents 1 and 2, the device is fixed on the die pad of the lead frame in which the drain lead and the die pad are connected, and the device and the drain lead, the source lead, A method of connecting to the gate lead by wire bonding has been conventionally used.
- FIG. 8 is a plan view showing a state of wire bonding between the lead frame and the GaN chip 30 before resin sealing (molding) when chip mounting is performed by the method of the conventional configuration.
- the drain terminal 12 and the drain lead 16 are connected by wire bonding the drain terminal 12 and the die pad 14. It is made by.
- the source lead 15 and the gate lead 17 are formed separately from the die pad 14, and the source lead 15 and the source terminal 11 and the gate lead 17 and the gate terminal 13 are connected by wire bonding.
- the present invention realizes a reduction in parasitic inductance from the surface of a device mounting structure so that parasitic oscillation can be suppressed without adding a large gate resistance in a device using GaN. Accordingly, it is an object to realize a power device that takes advantage of the low power consumption and high-speed response characteristics that are characteristic of GaN.
- a semiconductor device including a power device using GaN, wherein at least three terminals of a source terminal, a drain terminal, and a gate terminal are provided on the substrate surface side, The power device is fixed to a surface side of a die pad portion of a surface mount type lead frame, and the source terminal of the power device is wire-connected to the die pad portion, A device mounting structure in which the drain terminal of the power device is connected to a drain lead, the gate terminal of the power device is connected to a gate lead, and the back surface of the die pad portion is exposed to connect to a source pad on a printed circuit board. It is characterized by having.
- the back surface side corresponding to the connection position of the wire on the die pad portion side in the wire connection between the source terminal and the die pad portion is exposed.
- the area of the inner lead portion to be resin-sealed in the drain lead is larger than the area of the inner lead portion to be resin-sealed in the gate lead.
- the drain lead is arranged so as to be parallel to the longitudinal direction of the drain terminal, and the position on the die pad portion of the power device is a straight line extending the drain lead. It is preferable that the drain terminal is arranged on an extension line and is offset from the drain lead side.
- the transistor constituting the power device further includes: A source electrode connected to the source terminal; a drain electrode connected to the drain terminal; and a gate electrode connected to the gate terminal, wherein the gate electrode is arranged closer to the source electrode side than the drain electrode. It preferably has an asymmetric structure.
- a lower voltage than the drain lead is supplied to the exposed portion of the back surface of the die pad portion.
- the inventors of the present invention have intensively researched and found that by reducing the parasitic inductance of the source-side wiring, oscillation can be suppressed and stable switching can be performed with respect to ON / OFF of the gate voltage.
- Fig. 9 shows the configuration of the circuit used in the simulation.
- Ld, Ls1, Ls2, and Lgs are parasitic inductances of wirings, respectively, and Cgd, Cgs, and Cds are parasitic capacitances of GaN-FETs.
- the LC series circuit from Ld to Coss, Ls1, and Ls2 resonates.
- the voltage across Ls1 vibrates.
- Such oscillation of the voltage across Ls1 becomes a voltage noise source for the gate driver.
- the resonance of the LC series circuit via Coss, Ls1, and Ls2 from Ld and the resonance of the LC series circuit via Cgs and Ls1 are mutually induced.
- the oscillation of the gate voltage Vg is amplified.
- the switching noise increases, and in the worst case, the FET may oscillate and the circuit may be destroyed.
- Ld and Ls1 should be made as small as possible in order to prevent resonance by the LC circuit.
- FIG. 10 shows the result of simulating the rise and fall of the gate voltage during switching when the parasitic inductance Ls1 of the source side wiring and the parasitic inductance Ld of the drain side wiring are changed. From FIG. 10, the gate voltage oscillation is prevented by reducing the parasitic inductance Ls1 of the source wiring rather than reducing the parasitic inductance Ld of the drain wiring (FIG. 10B) (FIG. 10A). It can be seen that there is a remarkable effect.
- the device mounting method is changed, and in the surface mounting type device mounting structure, the back surface of the GaN chip is electrically connected to the surface of the die pad portion, and the die pad portion and the source terminal of the device are connected. It was decided to make a connection with the wire bonding. The back surface of the die pad portion is exposed, and the die pad portion can be electrically connected to an electrode pad (source pad) on the printed circuit board.
- the thickness of the die pad portion corresponds to the length of the source lead in the conventional configuration, the parasitic inductance of the source side wiring is greatly reduced, and the oscillation of the gate voltage can be suppressed. Further, since the conventional source lead is shortened to the die pad thickness, the on-resistance can be reduced.
- the potential difference between the source terminal of the GaN chip and the back surface of the chip can be reduced as compared with the structure in which the conventional die pad and drain lead are integrally formed, the leakage current from the back surface of the chip can be reduced. Further, since the loop current between the gate and the source is reduced, voltage fluctuation (induced voltage) due to the parasitic inductance of the source wiring is suppressed, and oscillation of the LC series circuit via Cgs can be suppressed.
- parasitic oscillation can be suppressed without adding a large gate resistance, and a power device utilizing the low power consumption and high-speed response characteristics of GaN is realized. be able to.
- the top view before resin sealing which shows the chip mounting example of the semiconductor device which concerns on this invention
- Bird's-eye view after resin sealing showing a chip mounting example of a semiconductor device according to the present invention
- Sectional drawing after resin sealing showing a chip mounting example of a semiconductor device according to the present invention
- Sectional drawing which shows the device structure of the power device using GaN.
- FIG. 1 to 3 show a configuration example of a semiconductor device 10 having a chip mounting structure according to the present invention.
- 1 to 3 are schematic views showing a form after the semiconductor device 10 is mounted.
- FIG. 1 is a plan view showing a state of wire bonding between a lead frame and a GaN chip before resin sealing (molding).
- FIG. 2 is a bird's-eye view showing a state where the semiconductor device 10 after resin sealing is mounted on a printed board. 3 shows the direction of AA ′ (on the drain terminal 12 and the drain lead 16 and the direction parallel to the drain lead 16) and the direction of BB ′ (on the source terminal 11, the drain lead of FIG. 1 and FIG. 2).
- the semiconductor device 10 is a power device configured using GaN, and includes a chip 30 in which a source terminal 11, a drain terminal 12, and a gate terminal 13 are formed on the substrate surface side.
- FIG. 4 shows a schematic cross-sectional view of a device structure of a power device using GaN.
- the device shown in FIG. 4 is an HEMT (High-Electron-Mobility-Transistor) FET, and a GaN layer 22 is formed on a Si substrate 20 via a buffer layer 21 made of an AlGaN multilayer film having different composition ratios of Al and Ga.
- the AlGaN layer 23 is laminated on the GaN layer 22.
- a source electrode 24 and a drain electrode 25 are formed in a predetermined region on the GaN layer 22 so as to penetrate the AlGaN layer 23, and a gate electrode 26 is formed in the predetermined region on the AlGaN layer 23.
- the electrodes 25 are formed so as to face each other with the gate electrode 26 interposed therebetween.
- the drain electrode 25 is electrically connected to the drain terminal 12 formed on the insulating film 27 through the contact hole 28.
- the source electrode 24 is electrically connected to the source terminal 11 formed on the insulating film 27 in another cross section
- the gate electrode 25 is formed on the insulating film 27 in another cross section. Are electrically connected to the gate terminal 13 formed in the circuit.
- a two-dimensional electron gas layer 29 is formed in the vicinity of the heterojunction interface between the AlGaN layer 23 and the GaN layer 22, a two-dimensional electron gas layer 29 is formed.
- a voltage gate voltage
- two-dimensional electrons below the gate electrode 26 are formed.
- the concentration of the gas layer 29 is modulated, and the current flowing between the source electrode 24 and the drain electrode 25 is controlled.
- a high voltage of about 200 V to 600 V is applied to the drain electrode 25 with respect to the source electrode 24.
- the distance between the gate electrode 26 and the drain electrode 25 is set so as not to discharge.
- the device has an asymmetric device structure in which the gate electrode 26 is arranged closer to the source electrode 24 side than the drain electrode 25 with a distance greater than the distance from the source electrode 24.
- the chip 30 is fixed to the surface of the die pad 14 with the conductive adhesive material 33 shown in FIG.
- a drain lead 16 and a gate lead 17 are disposed adjacent to the die pad 14.
- the drain lead 16 is connected to the drain terminal 12 of the chip 30, and the gate lead 17 is connected to the gate terminal 13 of the chip 30. These are respectively connected by wires (wire bonding).
- the source terminal 11 and the die pad 14 are connected by wire bonding on the surface side of the die pad 14.
- the semiconductor device 10 is packaged by sealing with a sealing resin 34 so as to cover a wire-connected portion.
- the semiconductor device 10 packaged in this way has an exposed portion 19 on the back surface of the die pad 14.
- the semiconductor device 10 can be electrically connected to the electrode pad on the printed circuit board 31 by exposing the metal portion of the back surface of the die pad 14 except for the region where the back surface of the die pad 14 is covered with the molding material. It is configured.
- the drain lead 16 and the gate lead 17 are connected to wirings (electrode pads) 32 a and 32 b formed on the printed circuit board 31, respectively, and the back surface of the die pad 14 is exposed.
- the semiconductor device 10 is mounted on the printed circuit board 31 by connecting the portion with a wiring (source pad) 32 c formed on the printed circuit board 31.
- the source terminal 11 and the source pad 32 c on the printed circuit board 31 are connected by wire bonding the source terminal 11 and the die pad 14, and the exposed portion on the back surface of the die pad 14 is brought into contact with the source pad 32 c.
- the die pad 14 corresponds to the source lead in the conventional configuration (FIG. 8).
- the parasitic inductance generated in the die pad 14 becomes very small.
- connection position (position X in FIG. 3) of the wire on the die pad 14 side in the wire bonding between the source terminal 11 and the die pad 14 is set to a position where the corresponding back side is exposed.
- the current path in the die pad 14 flowing from the wire to the source pad 32c becomes the shortest, and most of the current in the die pad 14 flows in the film thickness direction.
- the current component flowing parallel to the flat plate in the die pad 14 can be minimized, and the contribution of the current flowing parallel to the flat plate to the parasitic inductance can be minimized.
- the thickness of the die pad 14 corresponds to the length of the source lead in the conventional configuration, the parasitic inductance of the source side wiring is greatly reduced, and the oscillation of the gate voltage can be suppressed.
- the parasitic inductance can be reduced to 1/10.
- the potential of the substrate 20 is fixed to the source voltage via the die pad 14, whereby the chip back surface, the source electrode 24, Leakage current flowing between the substrate 20, the buffer layer 21, and the end side walls of the GaN layer 22 can be reduced.
- FIG. 5 shows the dependence of the drain voltage Vd and the leakage current Isub flowing on the back surface of the chip when the voltage Vsub applied to the substrate 20 is changed with reference to the source voltage applied to the source electrode 24 via the source terminal 11. Indicates. From FIG. 5, it can be seen that if there is a potential difference between the potential of the substrate 20 and the source voltage, the leakage current increases, and the leakage current can be significantly suppressed by making the potential of the substrate 20 the same as the source voltage.
- the source electrode 24 may be disposed in the peripheral portion of the chip so as to surround the entire circumference of the drain electrode 25. As a result, there is no leakage current path flowing between the chip back surface and the drain electrode via the end side wall of the chip 30, so that the leakage current can be effectively suppressed.
- the position of the chip 30 on the die pad 14 is adjusted so that the distance between the drain terminal 12 and the drain lead 16 is optimized without arranging the chip 30 in the center of the die pad 14.
- the drain terminal 16 is shifted toward the drain lead 16 side, and the drain terminal 12 is arranged on a straight line extending from the drain lead 16.
- the drain lead 15 may be disposed so as to be substantially parallel to the longitudinal direction of the drain terminal 12 and the chip may be disposed close to the drain lead 16.
- the bending angle of the wire for wire bonding the drain terminal 12 and the drain lead 16 can be reduced, and the length can be shortened.
- the parasitic inductance on the drain wiring side can be reduced together with the parasitic inductance on the source wiring side.
- the gate terminal 13 close to the gate lead 17 in order to shorten the length of the wire for wire bonding the gate terminal 13 and the gate lead 17.
- the drain lead 16 is disposed on the right side in FIG.
- the drain lead 16 is disposed on the right side in FIG.
- a lead frame separated from the die pad 14 so as to be positioned at the position is adopted, the position on the die pad 14 of the chip 30 is shifted to the drain lead 16 side, and the drain terminal is on a linear extension line extending the drain lead 16 12 may be arranged.
- FIG. 7 another mounting example of the semiconductor device 10 is shown in a plan view before resin sealing in FIG.
- the area of the portion of the drain lead 16 overlapping with the region 18, that is, the area of the resin lead-sealed portion (inner lead) in the drain lead 16 is shown as the portion of the gate lead 17 overlapping with the region 18, The area is larger than the area of the resin-sealed portion.
- the resin-sealed portion of the drain lead 16 (gate lead 17) corresponds to the area of the portion where wire bonding is possible.
- the drain lead 16 is wire-bonded to the drain terminal 12.
- the parasitic inductance of the drain wiring may increase.
- reducing the parasitic inductance on the source wiring side suppresses the oscillation of the gate voltage than reducing the parasitic inductance on the drain wiring side (Ld in FIG. 9). In that respect.
- FIG. 10 reducing the parasitic inductance on the source wiring side (Ls1 in FIG. 9) suppresses the oscillation of the gate voltage than reducing the parasitic inductance on the drain wiring side (Ld in FIG. 9).
- the semiconductor device 10 of the present invention employs a surface mounting type device mounting structure for mounting a power device using GaN, and electrically connects the back surface of the GaN chip to the surface of the die pad 14.
- the semiconductor device 10 can suppress parasitic oscillation without adding a large gate resistance, and a power device utilizing the low power consumption and high-speed response characteristics that are the characteristics of GaN is realized.
- the present invention can be used for mounting a power device using GaN as a switching element.
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
L'invention concerne une structure de montage de dispositif capable d'exploiter les avantages de la faible consommation d'énergie et des caractéristiques de réponse rapides d'un dispositif à semiconducteur dans lequel est utilisé du GaN. Une structure de montage de dispositif de type à montage en surface est utilisée, la surface inverse d'une puce en GaN (30) est reliée électriquement à la surface d'avers d'une pastille de matrice (14) et la connexion entre la pastille de matrice (14) et la borne source (11) de la puce (30) est établie par liaison par fil. La surface inverse de la pastille de matrice (14) est exposée et configurée de manière à pouvoir être reliée électriquement à la pastille d'électrode (pastille source) du substrat imprimé. Par conséquent, le courant de fuite de la surface inverse de la puce est réduit, la résistance à l'état actif est diminuée, le courant de boucle entre la gâchette et la source est réduit et l'inductance parasite du côté du câblage de la source est diminuée, ce qui supprime l'oscillation de la tension de gâchette résultant d'une capacité parasite entre la gâchette et la source.
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JP2012092575A JP2013222781A (ja) | 2012-04-16 | 2012-04-16 | 半導体装置のデバイス実装構造 |
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CN109300889A (zh) * | 2018-10-30 | 2019-02-01 | 山东晶导微电子股份有限公司 | 一种ac-dc芯片与高压续流二极管集成芯片结构及电源模组 |
CN110429082A (zh) * | 2018-05-01 | 2019-11-08 | 瑞萨电子株式会社 | 半导体装置及其制造方法 |
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JPWO2021002225A1 (fr) * | 2019-07-01 | 2021-01-07 |
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JPH10261756A (ja) * | 1997-03-19 | 1998-09-29 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP2000341001A (ja) * | 1999-05-27 | 2000-12-08 | Denso Corp | 高周波切替装置 |
JP2003347491A (ja) * | 2002-05-28 | 2003-12-05 | Renesas Technology Corp | 半導体装置 |
JP2008166621A (ja) * | 2006-12-29 | 2008-07-17 | Sanyo Electric Co Ltd | 半導体装置およびその製造方法 |
JP2010238892A (ja) * | 2009-03-31 | 2010-10-21 | Sharp Corp | 半導体装置およびその製造方法 |
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JP2522457Y2 (ja) * | 1990-10-16 | 1997-01-16 | 富士通テン株式会社 | 表面実装形電子部品 |
JP4810072B2 (ja) * | 2004-06-15 | 2011-11-09 | 株式会社東芝 | 窒素化合物含有半導体装置 |
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- 2012-04-16 JP JP2012092575A patent/JP2013222781A/ja active Pending
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JPH10261756A (ja) * | 1997-03-19 | 1998-09-29 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP2000341001A (ja) * | 1999-05-27 | 2000-12-08 | Denso Corp | 高周波切替装置 |
JP2003347491A (ja) * | 2002-05-28 | 2003-12-05 | Renesas Technology Corp | 半導体装置 |
JP2008166621A (ja) * | 2006-12-29 | 2008-07-17 | Sanyo Electric Co Ltd | 半導体装置およびその製造方法 |
JP2010238892A (ja) * | 2009-03-31 | 2010-10-21 | Sharp Corp | 半導体装置およびその製造方法 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
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CN110429082A (zh) * | 2018-05-01 | 2019-11-08 | 瑞萨电子株式会社 | 半导体装置及其制造方法 |
CN109300889A (zh) * | 2018-10-30 | 2019-02-01 | 山东晶导微电子股份有限公司 | 一种ac-dc芯片与高压续流二极管集成芯片结构及电源模组 |
CN109300889B (zh) * | 2018-10-30 | 2023-11-24 | 山东晶导微电子股份有限公司 | 一种ac-dc芯片与高压续流二极管集成芯片结构及电源模组 |
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