JP5653326B2 - 窒化物半導体装置 - Google Patents
窒化物半導体装置 Download PDFInfo
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- JP5653326B2 JP5653326B2 JP2011198301A JP2011198301A JP5653326B2 JP 5653326 B2 JP5653326 B2 JP 5653326B2 JP 2011198301 A JP2011198301 A JP 2011198301A JP 2011198301 A JP2011198301 A JP 2011198301A JP 5653326 B2 JP5653326 B2 JP 5653326B2
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- 239000004065 semiconductor Substances 0.000 title claims description 136
- 150000004767 nitrides Chemical class 0.000 title claims description 90
- 239000000758 substrate Substances 0.000 claims description 24
- 239000003990 capacitor Substances 0.000 claims 1
- 229910002704 AlGaN Inorganic materials 0.000 description 62
- 230000004888 barrier function Effects 0.000 description 43
- 230000003071 parasitic effect Effects 0.000 description 19
- 230000005684 electric field Effects 0.000 description 9
- 230000005533 two-dimensional electron gas Effects 0.000 description 8
- 230000008859 change Effects 0.000 description 7
- 230000010287 polarization Effects 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 5
- 230000001419 dependent effect Effects 0.000 description 5
- 238000007599 discharging Methods 0.000 description 5
- 239000012141 concentrate Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
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- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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- Junction Field-Effect Transistors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
図1及び図2を用いて、第1の実施形態に係る窒化物半導体装置について説明する。図1は、本実施形態に係る窒化物半導体装置100の、一部の断面図を模式的に示す。図2は、本実施形態に係る窒化物半導体装置100の要部の等価回路を示す。本実施形態に係る窒化物半導体装置は、図1に示したGaN−HFET101を一部に備える。GaN−HFET101は、GaNチャネル層4(第1の半導体層)と、AlGaNバリア層5(第2の半導体層)と、AlGaNバッファ層3と、p形Si基板2(導電性基板)と、ソース電極6(第1の電極)と、ドレイン電極8(第2の電極)と、ゲート電極7(制御電極)と、を備える。
第2の実施形態に係る窒化物半導体装置について図3を用いて説明する。図3は、本実施形態に係る窒化物半導体装置200の要部等価回路である。なお、第1の実施形態で説明した構成と同じ構成の部分には同じ参照番号または記号を用いその説明は省略する。第1の実施形態との相異点について主に説明する。
第3の実施形態に係る窒化物半導体装置について図4を用いて説明する。図4は、本実施形態に係る窒化物半導体装置300の要部模式断面図である。なお、第1の実施形態で説明した構成と同じ構成の部分には同じ参照番号または記号を用いその説明は省略する。第1の実施形態との相異点について主に説明する。
第4の実施形態に係る窒化物半導体装置について図5を用いて説明する。図5は、本実施形態に係る窒化物半導体装置400の要部模式断面図である。なお、第3の実施形態で説明した構成と同じ構成の部分には同じ参照番号または記号を用いその説明は省略する。第3の実施形態との相異点について主に説明する。
第5の実施形態に係る半導体装置について図6を用いて説明する。図6は、本実施形態に係る窒化物半導体装置500の要部模式断面図である。なお、第4の実施形態で説明した構成と同じ構成の部分には同じ参照番号または記号を用いその説明は省略する。第4の実施形態との相異点について主に説明する。
第6の実施形態に係る半導体装置について図7を用いて説明する。図7は、本実施形態に係る窒化物半導体装置600の要部模式断面図である。なお、第5の実施形態で説明した構成と同じ構成の部分には同じ参照番号または記号を用いその説明は省略する。第5の実施形態との相異点について主に説明する。
2 p形Si基板
3 AlGaNバッファ層
4 GaNチャネル層
5 AlGaNバリア層
6 ソース電極
7 ゲート電極
8 ドレイン電極
9 ソース端子
10 ゲート端子
11 ドレイン端子
12 p形GaN層
13 ゲート絶縁膜
14 リセス
100、200 窒化物半導体装置
101、301、401、501、601 GaN−HFET
102 Si−MOSFET
Claims (5)
- 第1の表面と、前記第1の表面とは反対側の第2の表面と、を有するAlxGa1−xN(0≦x<1)を含む第1の半導体層と、
前記第1の表面に接合しノンドープまたはn形のAlyGa1−yN(0<y≦1、x<y)を含む第2の半導体層と、
前記第1の半導体層の前記第2の表面側に設けられ前記第1の半導体層と電気的に接続された導電性基板と、
前記第2の半導体層の前記第1の半導体層とは反対側の表面に電気的に接続されて設けられた第1の電極と、
前記第2の半導体層の前記表面に電気的に接続されて設けられた第2の電極と、
前記第1の電極と前記第2の電極との間の前記第2の半導体層の前記表面上に設けられた制御電極と、
前記導電性基板の前記第1の半導体層とは反対側の表面に電気的に接続された裏面電極と、
を備え、
前記第1の電極は、Siにより形成されたMOSFETのドレイン電極に電気的に接続され、
前記制御電極は、前記MOSFETのソース電極に電気的に接続され、
前記導電性基板は、前記裏面電極を介して前記MOSFETの前記ゲート電極に電気的に接続され、
さらに、
前記第2の電極に電気的に接続された第1の端子と、
前記MOSFETの前記ゲート電極に電気的に接続された第2の端子と、
前記MOSFETの前記ソース電極に電気的に接続された第3の端子と、
を備え、
前記第1の端子と前記第2の端子との間に容量を有することを特徴とする窒化物半導体装置。 - 前記第2の端子の印加電圧により前記容量を充放電することを特徴とする請求項1記載の窒化物半導体装置。
- 前記導電性基板は、p形の導電形を有することを特徴とする請求項1または2に記載の窒化物半導体装置。
- 第1の表面と、前記第1の表面とは反対側の第2の表面と、を有するAlxGa1−xN(0≦x<1)を含む第1の半導体層と、
前記第1の表面に接合しノンドープまたはn形のAlyGa1−yN(0<y≦1、x<y)を含む第2の半導体層と、
前記第1の半導体層の前記第2の表面側に設けられ前記第1の半導体層と電気的に接続された導電性基板と、
前記第2の半導体層の前記第1の半導体層とは反対側の表面に電気的に接続されて設けられた第1の電極と、
前記第2の半導体層の前記表面に電気的に接続されて設けられた第2の電極と、
前記第1の電極と前記第2の電極との間の前記第2の半導体層の前記表面上に設けられた制御電極と、
前記導電性基板の前記第1の半導体層とは反対側の表面に電気的に接続された裏面電極と、
を備え、
前記第1の電極は、Siにより形成されたMOSFETのドレイン電極に電気的に接続され、
前記制御電極は、前記MOSFETのソース電極に電気的に接続され、
前記導電性基板は、前記裏面電極を介して前記MOSFETの前記ソース電極に電気的に接続され、
さらに、
前記第2の電極に電気的に接続された第1の端子と、
前記MOSFETの前記ゲート電極に電気的に接続された第2の端子と、
前記MOSFETの前記ソース電極に電気的に接続された第3の端子と、
を備え、
前記第1の端子と前記第3の端子との間に容量を有することを特徴とする窒化物半導体装置。 - 前記導電性基板は、p形の導電形を有することを特徴とする請求項4記載の窒化物半導体装置。
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JP2011198301A JP5653326B2 (ja) | 2011-09-12 | 2011-09-12 | 窒化物半導体装置 |
CN201210061235.2A CN103000682B (zh) | 2011-09-12 | 2012-03-09 | 氮化物半导体器件 |
US13/420,559 US8860090B2 (en) | 2011-09-12 | 2012-03-14 | Nitride semiconductor device |
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JP2019009462A (ja) * | 2018-09-13 | 2019-01-17 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
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CN112018175B (zh) * | 2019-05-30 | 2022-04-08 | 苏州捷芯威半导体有限公司 | 一种半导体器件及其制备方法、半导体封装结构 |
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JP2007273640A (ja) * | 2006-03-30 | 2007-10-18 | Sanken Electric Co Ltd | 半導体装置 |
JP2007294769A (ja) | 2006-04-26 | 2007-11-08 | Toshiba Corp | 窒化物半導体素子 |
JP5386785B2 (ja) | 2007-03-26 | 2014-01-15 | サンケン電気株式会社 | 半導体装置およびその製造方法 |
JP5348364B2 (ja) * | 2007-08-27 | 2013-11-20 | サンケン電気株式会社 | ヘテロ接合型電界効果半導体装置 |
JP2009182107A (ja) * | 2008-01-30 | 2009-08-13 | Furukawa Electric Co Ltd:The | 半導体装置 |
JP5386246B2 (ja) * | 2009-06-26 | 2014-01-15 | パナソニック株式会社 | 電力変換装置 |
JP5554024B2 (ja) * | 2009-07-03 | 2014-07-23 | 古河電気工業株式会社 | 窒化物系半導体電界効果トランジスタ |
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2011
- 2011-09-12 JP JP2011198301A patent/JP5653326B2/ja active Active
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JP2013062298A (ja) | 2013-04-04 |
US20130062671A1 (en) | 2013-03-14 |
CN103000682B (zh) | 2015-11-18 |
CN103000682A (zh) | 2013-03-27 |
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