WO2012088996A1 - 半绝缘碳化硅单晶及其生长方法 - Google Patents

半绝缘碳化硅单晶及其生长方法 Download PDF

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WO2012088996A1
WO2012088996A1 PCT/CN2011/083503 CN2011083503W WO2012088996A1 WO 2012088996 A1 WO2012088996 A1 WO 2012088996A1 CN 2011083503 W CN2011083503 W CN 2011083503W WO 2012088996 A1 WO2012088996 A1 WO 2012088996A1
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single crystal
semi
silicon carbide
carbide single
insulating silicon
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PCT/CN2011/083503
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English (en)
French (fr)
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陈小龙
刘春俊
彭同华
李龙远
王波
王刚
王文军
刘宇
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中国科学院物理研究所
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Priority to US13/976,351 priority Critical patent/US9893152B2/en
Priority to JP2013516994A priority patent/JP5657109B2/ja
Priority to EP11854144.0A priority patent/EP2660367A4/en
Publication of WO2012088996A1 publication Critical patent/WO2012088996A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B23/00—Single-crystal growth by condensing evaporated or sublimed materials
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B23/00—Single-crystal growth by condensing evaporated or sublimed materials
    • C30B23/002—Controlling or regulating
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B23/00—Single-crystal growth by condensing evaporated or sublimed materials
    • C30B23/002—Controlling or regulating
    • C30B23/005—Controlling or regulating flux or flow of depositing species or vapour
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B23/00—Single-crystal growth by condensing evaporated or sublimed materials
    • C30B23/02—Epitaxial-layer growth
    • C30B23/06—Heating of the deposition chamber, the substrate or the materials to be evaporated
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/36—Carbides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02529—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/435—Resistive materials for field effect devices, e.g. resistive gate for MOSFET or MESFET

Definitions

  • the present invention relates to the field of preparation and application of silicon carbide single crystals, and more particularly to a semi-insulating silicon carbide single crystal and a growth method thereof.
  • SiC materials have great advantages in high temperature, high frequency, high power, photoelectron and radiation resistance due to wide band gap, high critical breakdown electric field, high thermal conductivity, high carrier saturation drift speed and the like. Application prospects.
  • semi-insulating SiC single crystal substrates have a wide range of applications in the field of microwave devices.
  • SiC microwave devices, such as transistors, fabricated using semi-insulating SiC single crystal substrates can produce five times more than GaAs microwave devices at frequencies up to 10 GHz. Power density power.
  • the "semi-insulating” means that the resistivity at room temperature is greater than 10 5 Q. Cm, which is consistent with the conceptual description of "high resistance”.
  • the intrinsic SiC crystal exhibits semi-insulating properties due to the wide band gap.
  • the SiC raw material contains impurities such as N and B
  • the graphite crucible and the thermal insulation material contain impurities such as B and Al and the residual N impurities in the environment, so that the SiC crystal which is unintentionally mixed is grown.
  • the resistivity is about 0.1 to 100 Q. Cm, this range of resistivity wafers clearly does not meet the needs of making microwave devices.
  • a semi-insulating SiC crystal having a resistivity of more than 10 5 ⁇ is mainly obtained by forming a deep level in the SiC forbidden band.
  • the main principle of the method is to increase the resistivity of the material by introducing a deep level in the silicon carbide forbidden band, where "deep level" means 300meV or higher from the edge of the valence band or conduction band. Energy level.
  • shallow level means 300meV or higher from the edge of the valence band or conduction band.
  • Energy level can also produce shallow levels, such as boron. Specifically, the shallow level increases the conductivity of the material rather than increasing the resistivity of the crystal.
  • the above methods mainly include the following two types: First, by introducing a point defect as a deep The energy level compensates for shallow level impurities to obtain a semi-insulating SiC crystal.
  • U.S. Patent No. 6,218,680 which compensates for shallow donor and shallow acceptor impurities by intrinsic point defects, and requires that the content of heavy metals or transition metals be as small as possible without affecting the electrical properties of the device, especially requiring less than 10 14 vanadium. Cn 3 or less than the detection limit of secondary ion mass spectrometry.
  • methods for effectively increasing or decreasing the concentration of point defects in the crystal are not well understood.
  • the point defect concentration in the SiC crystal may not be sufficient to compensate for the shallow level impurities, which does not meet the semi-insulation properties required by the microwave device.
  • some point defects are thermodynamically unstable. If the SiC crystal is used in a specific environment, its semi-insulating properties are difficult to guarantee. For example, studies have shown that Si vacancies in SiC crystals heal after prolonged annealing at high temperatures, which leads to a decrease in the resistivity of SiC crystals, and thus SiC crystals with stable semi-insulating properties cannot be obtained.
  • Another method is to introduce a dopant as a deep level.
  • U.S. Patent No. 5,611,955 which emphasizes the incorporation of a transitional group element, particularly vanadium, as a deep level compensates for the unintentionally doped N, B in the SiC crystal, thereby obtaining a semi-insulating SiC crystal.
  • the introduction of transitional elements as deep levels into SiC crystals results in semi-insulating SiC crystals, which also has certain disadvantages.
  • vanadium when vanadium is introduced into the SiC crystal as a deep level dopant, a large amount of vanadium will also introduce corresponding crystal defects, when the concentration of vanadium exceeds its solid solubility limit in SiC crystal (5xl0 17 cm' 3 ), it will produce vanadium precipitates and microtubes, which will affect the crystal quality of the crystal.
  • the doping amount of vanadium is too large, the electron mobility of the crystal is lowered, which also affects the performance of the prepared microwave device.
  • a primary object of the present invention is to provide a semi-insulating SiC single crystal and a method for growing the same, which use a deep level dopant and an intrinsic point defect to compensate for background impurities of a shallow level.
  • the requirements of high-performance microwave devices for high-quality semi-insulating SiC single crystal substrates are met.
  • a semi-insulating silicon carbide single crystal containing a background impurity, a deep level dopant, and an intrinsic point defect, wherein the background is heterozygous Quality is an unintentionally doped impurity introduced during production and preparation.
  • Deep level dopants and intrinsic point defects are intentionally doped or added to compensate for the background impurities;
  • the background impurities include shallow a donor impurity and a shallow acceptor impurity, a sum of a concentration of the deep level dopant and an intrinsic point defect being greater than a difference between a concentration of the shallow donor impurity and the shallow acceptor impurity, and the concentration of the intrinsic point defect is less than Describe the concentration of deep level dopants.
  • a method for growing a semi-insulating silicon carbide single crystal comprising: placing a SiC powder doped with a deep level dopant as a raw material into a crucible, and having a lid bonded thereto The seed crystal is covered, and the crucible is placed in a crystal growth furnace, wherein the SiC powder is located in a high temperature region of the crystal growth furnace, and the seed crystal is located in a low temperature region of the crystal growth furnace; the crystal growth furnace is heated to cause the high temperature region to sublimate and decompose the gas phase.
  • the source is deposited as a SiC single crystal on the seed crystal of the low temperature region; and the SiC single crystal is cooled to room temperature.
  • a transistor using a substrate formed of the semi-insulating SiC single crystal is provided.
  • the transistor is a metal-semiconductor field effect transistor, a metal-insulator field effect transistor or a high electron mobility transistor.
  • the present invention has the following beneficial effects:
  • the semi-insulating silicon carbide single crystal and the growth method thereof provided by the invention the semi-insulating silicon carbide single crystal simultaneously utilizing the deep level impurity and the intrinsic point defect to compensate the background impurity of the shallow level, thereby realizing Good semi-insulating properties and good crystal quality meet the requirements of high performance microwave devices for high quality semi-insulating SiC single crystal substrates.
  • the two deep levels simultaneously compensated which reduces the difficulty of obtaining semi-insulating properties; on the other hand, it avoids the excessive concentration of dopants when a single deep level dopant is used.
  • the crystal quality is degraded.
  • the concentration of the intrinsic point defect is smaller than the concentration of the deep level dopant, so that the deep level dopant can play a leading role in compensation, thereby avoiding The instability of the SiC wafer resistivity when the concentration of the intrinsic point defect is too high to dominate the compensation.
  • the final microwave device can be obtained by processes such as warm vapor phase epitaxy and device preparation.
  • the ambient temperature in the subsequent process is as high as 1400 °C - 1700 °C.
  • some point defects are unstable at this temperature range, and some point defects will heal, resulting in a decrease in resistivity, thereby failing to achieve semi-insulating properties and affecting the performance of the final microwave device.
  • the semi-insulating SiC single crystal growth method provided by the invention cools from 1800 ° C to room temperature crystal at a cooling rate ranging from rc/h to 100 ° C/h during the cooling process, which greatly reduces these unstable The concentration of the point defects, so that the point defects finally obtained have good thermal stability, and the stability of the crystal resistivity during use is ensured.
  • the semi-insulating silicon carbide single crystal and the growth method thereof provided by the invention have a corrosion pit density of less than 1000/cm 2 on the surface, and have high crystal quality, satisfying the high-quality requirements of the high-performance microwave device for the silicon carbide single crystal. .
  • Crystal defects include point defects, line defects, surface defects, and body defects.
  • the line defects of the silicon carbide single crystal include screw dislocations, edge dislocations, surface defects including base plane dislocations, and body defects including polytypes, microtubules, and the like. Most of these defects are hereditary, and in the subsequent vapor phase epitaxy, they are easily propagated into the epitaxial layer, greatly reducing the performance of the subsequent preparation of microwave devices. Since these defects exhibit different shapes of etch pits after being etched by molten KOH, the present invention uses surface etch pit densities to characterize these defect densities in the crystal.
  • the semi-insulating single crystal provided by the invention has a corrosion pit density of less than 1000/cm 2 on the surface and has a high crystal quality, which satisfies the requirements for subsequent device preparation.
  • FIG. 1 is a schematic view showing the structure of a growth chamber for growing a SiC single crystal by a physical vapor phase transfer method according to an embodiment of the present invention
  • FIG. 2 is a Raman spectrum diagram of a wafer 1 and a wafer 2 in Embodiment 1 of the present invention
  • Figure 3 is a surface etch pit morphology of a silicon carbide wafer after KOH corrosion
  • a semi-insulating silicon carbide single crystal comprising a background impurity, a deep level dopant, and an intrinsic point defect, wherein the background impurity is Unintentionally doped impurities introduced during production and preparation, including shallow donor impurities and shallow acceptor impurities, while deep level dopants and intrinsic point defects are deliberately doped to compensate for the background impurities or joined.
  • the sum of the concentrations of the deep level dopant and the intrinsic point defect is greater than the difference between the shallow donor impurity and the shallow acceptor impurity concentration to achieve a compensation effect, and the intrinsic point defect concentration should be greater than Lx l0 15 cnT 3 , in order to achieve the purpose of significantly affecting the resistivity of silicon carbide crystals.
  • the concentration of the intrinsic point defect is less than the concentration of the deep level dopant, so that the deep level dopant can play a leading role in the compensation, so as to avoid the dominant compensation when the concentration of the intrinsic point defect is too high. Instability to SiC wafer resistivity.
  • the concentration should be controlled as low as possible during the crystal growth process to ensure that the difference between the concentrations should be less than 5x10 17 cn 3 , preferably less than 5 x 10 16 cm 3 .
  • the shallow donor impurity in the silicon carbide single crystal includes nitrogen
  • the shallow acceptor impurity includes boron or aluminum
  • other background impurities generated in the production process are also included in the scope of the present invention.
  • combinations of other elements or elements of the periodic table ⁇ , IVB, VB, VIB, VIIB, VIIIB, ⁇ , ⁇ are also selected as deep level dopants, for example in
  • the IVB and VB elements preferably vanadium and titanium, have a room temperature resistivity of greater than 1 x 10 5 ⁇ -cm, more preferably greater than ⁇ ⁇ ⁇ ⁇ 9 and are in the SiC crystal. After annealing at a high temperature of about 1800 ° C for a long time, the room temperature resistivity does not vary by more than 10%.
  • a silicon vacancy (v si ) in addition to the carbon vacancy (v e ) and the silicon-carbon double vacancy in the embodiment, a silicon vacancy (v si ), a carbon vacancy substitution combination, a silicon vacancy substitution combination or a double vacancy may be included.
  • the double vacancy includes a double carbon vacancy, a double silicon vacancy, or may also include other complex point defects, such as a cluster of three vacancies.
  • the present invention also provides a method of preparing a semi-insulating SiC single crystal, the method comprising: CD puts the SiC powder of the deep-level dopant as a raw material into the crucible, covers the lid with the seed crystal bonded, and places the crucible into the crystal growth furnace, wherein the SiC powder is located in the crystal growth furnace. In the high temperature zone, the seed crystal is located in the low temperature zone of the crystal growth furnace;
  • the temperature at the crystal growth interface, the vapor-phase silicon-carbon ratio, and the crystal growth rate are kept stable, and at the same time, the background impurities are lowered into the growth crystal to obtain a high-quality semi-insulating SiC crystal.
  • the deep level dopant is uniformly mixed with the SiC raw material in the form of the second phase to form the SiC powder which has been doped with the deep level dopant; or, deep level doping
  • the agent has diffused into the crystal lattice of the SiC raw material to form a SiC powder that has been doped with a deep level dopant.
  • the deep level dopant has diffused into the crystal lattice of the SiC raw material, which ensures that the deep level dopant maintains a stable doping concentration throughout the crystal growth process and does not cause deep crystal growth.
  • the level dopant concentration produces a large non-uniformity.
  • the crystal growth process is desirably carried out under conditions of stable, low fluctuations.
  • the gas phase produced by sublimation of the silicon carbide raw material in the high temperature region is non-stoichiometric, and the atmosphere has a silicon to carbon ratio of more than one.
  • the material gradually begins to graphitize, and in the case of individual powder particles, the surface layer is covered with a layer of residual graphite. Therefore, the silicon-carbon ratio of the atmosphere gradually changes during the growth process, showing a gradual decrease.
  • the decrease of the silicon-to-carbon ratio of the atmosphere often leads to defects such as inclusions and polytypes in the crystal, which significantly reduces the crystal quality of the crystal.
  • the growth method provided by the present invention requires that the temperature at the crystal growth interface, the vapor-phase silicon-carbon ratio, and the crystal growth rate be kept stable during the growth process. Further, the gas-phase silicon-to-carbon ratio and the crystal growth rate at the crystal growth interface are kept stable, including the temperature of the raw material in the high temperature region gradually decreasing during the whole growth process, and the pressure of the growth atmosphere is gradually decreased. As the sublimation temperature decreases, the ratio of the vapor-phase silicon to carbon in the sublimation of the silicon carbide raw material increases, but at the same time, the supply of the gas phase source decreases, and the crystal crystallization rate decreases. Therefore, the present invention combines the reduction of the raw material temperature and the reduction of the growth pressure to achieve a gas-phase silicon-carbon ratio at the final growth interface, and a stable crystal growth rate, thereby ensuring high Crystal quality.
  • the vapor-phase silicon-carbon ratio and the crystal growth rate at the crystal growth interface are maintained throughout the growth process of the present invention, including the temperature of the raw material in the high temperature region. Gradually decrease, while the pressure of the growth atmosphere gradually decreases; further, the temperature of the raw material in the high temperature zone decreases by 30-300 ° C, and the ratio of the pressure reduction amplitude to the initial pressure is between 5% and 90%.
  • the gas-phase silicon-carbon ratio at the crystal growth interface is kept stable, including the introduction of an organic gas-phase carbon source, and the flow rate of the organic vapor phase carbon source is controlled in real time. Reducing background impurities into the growing crystal, including the introduction of an organic gas phase carbon source.
  • the organic gas phase carbon source is preferably methane, ethane, propane or acetylene.
  • the nitrogen in the growth atmosphere replaces the carbon site during crystallization, and the gas phase carbon and nitrogen compete with each other at the interface.
  • an organic vapor phase carbon source is introduced into the atmosphere, the difficulty of nitrogen entering the crystal can be effectively increased, the concentration of the background impurity is lowered, and the resistivity of the semi-insulating crystal is increased.
  • the SiC single crystal is crystallized in a non-thermodynamic equilibrium state, and the crystallization speed of the SiC single crystal reaches a critical speed, thereby forming a higher crystalline SiC single crystal in the SiC single crystal than the thermodynamic equilibrium condition.
  • Primary point defect concentration ranges from 0.6 mm/h to 4 mm/h, preferably from 1.5 to 4 mm/h.
  • the method of crystallizing the silicon carbide crystal in a non-thermodynamic equilibrium state comprises maintaining a lower crystallization temperature at the silicon carbide crystal growth interface, a higher temperature at the silicon carbide raw material, and/or a lower growth chamber pressure. .
  • the crystal is cooled at a sufficiently slow rate from 1800 ° C to room temperature to reduce the concentration of unstable point defects and to ensure the stability of the crystal resistivity during use.
  • the cooling rate range described therein is rc/h -ioo°c/h.
  • the temperature drop rate in the high temperature section is lower than the low temperature section.
  • all SiC crystals are obtained in a growth chamber as shown in FIG. 1 using a conventional SiC crystal preparation method, a physical vapor transport method (Physical Vapor Transport Method).
  • the specific principle is: the temperature in the graphite crucible 2 is raised to 2000 ⁇ 2400 ° C, so that the SiC raw material 3 is sublimated, sublimation produces vapor phase Si 2 C, SiC 2 and Si, and the seed crystal 5 is placed at a lower temperature than the SiC raw material 3
  • the upper part of the crucible (4 is a binder) the gas phase produced by sublimation is transferred from the surface of the raw material to the seed crystal 5 having a lower temperature by a temperature gradient, and crystallized on the seed crystal to form a bulk SiC crystal 6.
  • the graphite crucible and the thermal insulation material are subjected to purification treatment, specifically, the graphite crucible and the thermal insulation material are heated to a high temperature of 2000 ° C in an Ar atmosphere, and impurities (for example, aluminum and boron) are sufficiently volatilized. In this way, the effect of background impurities on the resistivity of the SiC crystal is minimized.
  • impurities for example, aluminum and boron
  • Crystal 1 uses deliberately intensive deep level impurity (for example, vanadium), the specific preparation method is as follows: 80mg vanadium carbide powder (purity 99.999%) is added to 700g silicon powder (purity 99.999%) and 300g toner (purity: 99.999%), fully mixed with a ball mill, and then solid-phase reaction at a high temperature of 2200 ° C to obtain a doped SiC powder; Referring to Figure 1, the SiC powder is used as a raw material 3 in a graphite crucible 2, The lid 1 to which the 4H-SiC seed crystal 5 is bonded is placed in a crystal growth furnace.
  • impurity for example, vanadium
  • the specific preparation method is as follows: 80mg vanadium carbide powder (purity 99.999%) is added to 700g silicon powder (purity 99.999%) and 300g toner (purity: 99.999%), fully mixed with a ball mill, and then solid-phase reaction at a high temperature of 2200 ° C to obtain a doped Si
  • the growth furnace is filled with a mixed gas of argon gas and methane, the proportion of methane is 40%, and the pressure is controlled at about 2000 Pa.
  • the seed crystal temperature is maintained between 2000-2150 ° C and the feed temperature is maintained between 2250-2400 ° C.
  • Gradually reduce methane gas during growth The ratio achieves a stable silicon-to-carbon ratio at the interface, and simultaneously controls the relative positions of the crucible and the graphite cap, stabilizes the temperature at the crystal growth interface, and stabilizes the growth rate, thereby achieving high-quality SiC crystal growth.
  • the crystal growth rate was about 0.8 mm/h, and after cooling, it was cooled to room temperature.
  • the introduction and control of point defects were obtained by the corresponding crystal growth and annealing processes, and the crystal defects were introduced at a growth rate of 0.8 mm/h in a non-thermodynamic equilibrium state to introduce point defects; 80 hours from 1900 ⁇ to room temperature, where the cooling rate was in accordance with the temperature.
  • the decrease is exponentially increased, thereby reducing the unstable point defect concentration in the crystal and achieving the stability of the crystal resistivity.
  • the crystal 2 is not intentionally doped with deep level dopants, and other processes related to crystal growth and annealing are the same as those employed in the crystal 1, and will not be described here.
  • the SiC crystal 1 and the SiC crystal 2 obtained by the above method were sliced perpendicular to the growth direction to obtain a wafer 1 and a wafer 2 having a thickness of 0.4 mm, respectively, in the middle of crystal growth, about 5 mm from the seed crystal, and then the two The wafers were tested for performance.
  • the Raman spectrum of the wafer 1 and the wafer 2 is as shown in Fig. 2, indicating that the crystal form of the wafer 1 and the wafer 2 is 4H-SiC.
  • Non-contact resistivity of the resistance meter test wafer, the wafer 1 resistivity of 6.9x l0 8 Q. Cm, wafer 2 resistivity is 8.4 ⁇ 10 3 ⁇ . ⁇ .
  • the SiC wafer 1 in this example 50kPa pressure Ar atmosphere of 1800 ° C annealing temperature, annealing time is 10 hours after the back end of the fire resistance of a wafer of 6.8x l0 8 Q. Cm, the resistivity changes by 1.5%, indicating that the resistivity does not decrease significantly after annealing, and the semi-insulating properties of the wafer have good stability.
  • the impurity content of the wafer 1 and the wafer 2 was characterized by secondary ion mass spectrometry, and the results are shown in Table 1.
  • crystal 1 and crystal 2 there are shallow donor impurity nitrogen N, shallow acceptor boron B and aluminum A1, and deep level dopant vanadium V.
  • the remaining impurity elements are small, negligible, and the result is negligible. It indicates that the background impurity concentration of both is close.
  • the deep level dopant concentration (2.5E+16) in the wafer 1 is slightly smaller than the difference between the shallow donor impurity and the shallow acceptor impurity concentration (3.4E +16), indicating that the deep energy in the crystal 1 alone Level dopants are not sufficient to compensate for shallow levels and achieve half insulation.
  • Impurity content in SiC wafers (unit: cm- 3 )
  • the positron annihilation lifetime spectrum was further characterized.
  • 138ps and 133ps correspond to the lifetime of SiC crystals
  • 166ps and 158ps correspond to the point defects of carbon vacancies VC or double C vacancies in SiC crystals, indicating the existence of two crystals. Almost the same point defect.
  • the wafer 1 is subjected to molten KOH etching, and the selected etching surface is (0001) facing ⁇ 11-20> to 4 degrees, the etching temperature is 480 ° C, and the etching time is 10 minutes.
  • the corrosion surface is observed by an optical microscope 100 times mode, as shown in the figure.
  • the etch pit density was calculated to be 850/cm 2 , indicating that the wafer had good crystal quality.
  • the resistivity of the wafer 2 has been significantly affected by the point defects, but only the presence of the point defects is insufficient to compensate for the shallow level impurities, so the wafer 2 resistivity is less than semi-insulating. Comparing the wafer 1 and the wafer 2, the resistivity of the wafer 1 is increased by 5 orders of magnitude compared with the wafer 2, and the resistivity is increased much more than the resistivity of the wafer 2, indicating that the deep level dopant acts as a compensation and dominates. The concentration of the dot defects in the wafer 1 is less than the concentration of the deep level dopant. Therefore, the semi-insulating property of crystal 1 is the result of the co-compensation of the dominant deep level dopant and the intrinsic point defect on the shallow acceptor and donor levels.
  • This example employs the same SiC crystal preparation method as in the first embodiment.
  • the graphite crucible and the thermal insulation material are also subjected to purification treatment, specifically, the graphite crucible and the thermal insulation material are heated to a high temperature of 2000 ° C in an Ar atmosphere, and impurities (for example, aluminum and boron) are sufficiently volatilized. In this way, the influence of background impurities on the resistivity of the SiC crystal is minimized.
  • the crystal 3 is selected from a combination of vanadium and titanium as a deep level dopant.
  • the specific preparation process is as follows: 200 mg of vanadium carbide powder (purity 99.999%) and 90 mg of titanium carbide powder (purity 99.999%) are added to 800 g of silicon carbide powder (purity 99.999%), using a ball
  • the mill was sufficiently mixed and hooked, and then loaded into the graphite crucible 2 shown in Fig. 1 as a raw material 3, and covered with a crucible lid 1 to which 6H-SiC seed crystal 5 was adhered, and placed in a crystal growth furnace.
  • the growth furnace is filled with argon gas, the pressure is controlled at 1500 Pa-500 Pa, the temperature of the raw material is controlled between 2250-2400 ° C, and the seed crystal temperature is maintained between 2050-2200 ° C.
  • the stable growth interface temperature is controlled by controlling the relative positions of the crucible and the graphite cap, and the vapor-phase silicon-to-carbon ratio and the growth rate at the growth interface are stabilized by controlling the pressure drop and the temperature of the raw material to achieve high quality SiC crystal.
  • the crystal growth rate was 1.5 mm/h.
  • the control of the point defects in the crystal was achieved by the corresponding annealing, and the growth temperature was lowered to 1800 ° C 2 hours after the end of the growth, and then lowered to the temperature at 40 hours.
  • the crystal 4 is not intentionally doped with deep level dopants, and other processes related to crystal growth and annealing are the same as those used for the crystal 3, and will not be described here.
  • the silicon carbide crystal 3 and the silicon carbide crystal 4 obtained by the above method are sliced in a direction perpendicular to the growth direction to obtain a wafer 3 and a wafer 4 having a thickness of 0.4 mm, respectively, in the middle of crystal growth, about 8 mm from the seed crystal, and then The two wafers were tested for performance.
  • the Raman spectrum of the wafer 3 and the wafer 4 is as shown in Fig. 4, indicating that the crystal form of the wafer 3 and the wafer 4 is 6H-SiC;
  • the resistivity of the wafer was tested using a non-contact resistance measuring instrument, the resistivity of the wafer 3 was 3.9 x 10 9 O»cm, and the resistivity of the wafer 4 was 4.6 > ⁇ 10 3 Q. Cm.
  • the impurity content of the wafer was characterized by secondary ion mass spectrometry. The results are shown in Table 2. The remaining impurity elements were small and negligible.
  • the deep level dopant concentration in wafer 3 (1.1E+17) is slightly less than the difference between the shallow donor impurity and the shallow acceptor impurity concentration (1.4E +17), indicating in the crystal
  • the separate deep level dopants in 3 are not sufficient to compensate for the shallow levels.
  • the positron annihilation lifetime spectrum was characterized.
  • 131 133ps corresponds to the lifetime of the SiC crystal
  • 220ps and 222ps correspond to the point defects associated with the silicon carbon double vacancy v si v c in the SiC crystal.
  • wafer 4 shows that the presence of point defects significantly affects the resistivity of the crystal, but the presence of only a few defects is insufficient to compensate for the shallow impurity level, and the wafer 4 resistivity does not reach a semi-insulating.
  • the resistivity of wafer 3 is increased by six orders of magnitude compared to wafer 4, and the increase in resistivity is much greater than that of wafer 4, indicating that the concentration of point defects in wafer 3 is less than that of deep level dopants.
  • the concentration therefore, the deep level dopant acts as a compensating and dominant.
  • the point defect and the dominant deep level compensation element together compensate the shallow acceptor and donor levels to achieve a semi-insulating performance. Therefore, the deep level dopant acts as a compensation and dominates.
  • the point defect and the dominant deep level compensation element together compensate the shallow acceptor and donor levels to achieve a semi-insulating performance.
  • the growth method of the crystal 5 is the same as that of the crystal 4, and the only difference is that the temperature is lowered from 1800 ° C to room temperature in 5 hours after the end of growth.
  • the silicon carbide crystal 5 obtained by the above method was sliced in a direction perpendicular to the growth direction to obtain a wafer 5 having a thickness of 0.4 mm, which was in the middle of crystal growth, about 8 mm from the seed crystal, and then subjected to a non-contact resistivity test of the wafer. .
  • the wafer 5 has a resistivity of 2.8 x 10 5 Qacm.
  • the SiC wafer 3, the wafer 4, and the wafer 5 of the present example were annealed at 1800 ° C in an Ar protective atmosphere at a pressure of 50 kPa, and the annealing time was 30 hours.
  • the resistivities of the wafer 3, the wafer 4 , and the wafer 5 after the completion of the fire were respectively It is 3.8 ⁇ 10 9 ohm ⁇ cm, 4.6X 10' 3 ohm, cm, 8.6 ⁇ 10 ⁇ 3 ohm ⁇ cm.
  • the comparison of the wafers 4 and 5 shows that the semi-insulating property achieved by a single defect is unstable, and after annealing, the resistivity is remarkably lowered, and the semi-insulating property is not achieved.
  • the results of wafer 3 show that the present invention provides a growth method for the preparation of crystals without significant degradation after annealing, and has good semi-insulation thermal stability.
  • the present invention also provides a semi-insulating silicon carbide single crystal as the substrate A transistor, which may be a metal-semiconductor field effect transistor, a metal-insulator field effect transistor, or a high electron mobility transistor.

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Description

半绝缘碳化硅单晶及其生长方法
技术领域 本发明涉及碳化硅单晶制备及应用技术领域， 尤其涉及一种半绝缘 碳化硅单晶及其生长方法。
背景技术 碳化硅 （SiC) 材料由于具有宽带隙、 高临界击穿电场、 高热导率、 高载流子饱和漂移速度等特点， 在高温、 高频、 大功率、 光电子及抗辐 射等方面具有巨大的应用前景。 特别是半绝缘 SiC单晶衬底， 其在微波 器件领域有着广泛的用途， 采用半绝缘 SiC单晶衬底制备的 SiC微波器 件， 例如晶体管， 能够在高达 10GHz频率下产生超过 GaAs微波器件五 倍功率密度的功率。 但是， 要制备高性能的 SiC微波器件， 制造出高结 晶质量的半绝缘 SiC单晶衬底是前提条件。 其中， 所述"半绝缘"指的是 室温下电阻率大于 105Q。cm， 这与"高阻"在概念上的描述是一致的。
理论上，本征 SiC晶体由于禁带较宽而显现半绝缘特性。然而在 SiC 晶体生长过程中， 由于 SiC 原料中含有 N、 B 等杂质， 石墨坩埚和保温 材料中含有 B、 Al等杂质以及环境中残留的 N杂质的影响， 使得非故 意惨杂生长的 SiC晶体的电阻率约为 0.1〜100 Q。cm， 该电阻率范围的晶 片显然不能满足制作微波器件的需要。
为此， 目前主要采用在 SiC禁带中形成深能级的方法获得电阻率大 于 105Ω· η的半绝缘 SiC 晶体。该方法的主要原理是：通过在碳化硅禁 带中引入深能级作为补偿中心， 从而提高材料的电阻率， 此处"深能级" 是指距离价带或导带的边缘 300meV或者更高的能级。 但是， 某些元素 也能产生浅能级，例如硼。具体来说， 浅能级是提高了材料的导电性能， 而不是提高晶体的电阻率。
具体地， 上述方法主要包括以下两种： 一是通过引入点缺陷作为深 能级补偿浅能级杂质， 获得半绝缘 SiC晶体。 如美国专利 6， 218, 680， 其通过本征点缺陷来补偿浅施主、 浅受主杂质， 同时要求重金属或过渡 族金属的含量尽量小不影响器件的电学性能， 特别是要求钒小于 1014cn 3或者小于二次离子质谱的检测限。 然而， 到目前为止， 有效地 增加或减少晶体中点缺陷浓度的方法还不是很清楚。 在实际晶体生长过 程中， SiC 晶体中的点缺陷浓度可能不足以补偿浅能级杂质， 达不到微 波器件要求的半绝缘性能。 另外， 一些点缺陷在热力学上是不稳定的， 如果 SiC晶体是在特定的环境中使用， 其半绝缘性能很难有效保证。 例 如，研究表明 SiC晶体中 Si空位经过高温长时间退火后会愈合， 这就会 导致 SiC晶体电阻率的下降，从而不能获得稳定半绝缘性能的 SiC晶体。
另一种方法是通过引入掺杂剂作为深能级。如美国专利 5， 611， 955， 其强调掺入过渡族元素， 特别是钒， 作为深能级把 SiC晶体中非故意掺 杂的 N 、 B补偿掉， 从而获得半绝缘 SiC晶体。 然而， 过渡族元素作为 深能级引入 SiC晶体中获得半绝缘 SiC晶体，也会产生某些缺点。例如， 在 SiC晶体中引入钒作为深能级惨杂剂时， 钒的大量存在也会引入相应 的晶体缺陷， 当钒的浓度超出其在 SiC 晶体中的固溶度极限值 ( 5xl017cm'3 ) 时， 其就会产生钒的析出物及微管， 从而影响晶体的结 晶质量。 另一方面， 如果钒的掺杂量太多也会降低晶体的电子迁移率， 从而也会影响制备出来的微波器件的性能。
发明内容 本发明的主要目的在于提供一种半绝缘 SiC单晶及其生长方法， 该 半绝缘 SiC单晶同时利用深能级掺杂剂和本征点缺陷来补偿浅能级的本 底杂质， 以实现较好的半绝缘性能和良好的晶体质量， 满足高性能微波 器件对高质量半绝缘 SiC单晶衬底的要求。
为达到上述目的， 本发明采用了如下技术方案：
根据本发明的一个方面， 提供了一种半绝缘碳化硅单晶， 该半绝缘 碳化硅单晶含有本底杂质、 深能级惨杂剂和本征点缺陷， 其中该本底杂 质是在生产及制备过程中引入的非故意摻杂的杂质， 深能级掺杂剂和本 征点缺陷是为了补偿该本底杂质而故意掺杂或加入的； 所述本底杂质包 括浅施主杂质和浅受主杂质， 所述深能级掺杂剂与本征点缺陷的浓度之 和大于浅施主杂质与浅受主杂质的浓度之差， 且所述本征点缺陷的浓度 小于所述深能级掺杂剂的浓度。
根据本发明的另一方面， 提供了一种半绝缘碳化硅单晶的生长方 法， 包括： 将已掺杂深能级惨杂剂的 SiC粉体作为原料置入坩埚中， 盖 上粘接有籽晶的坩埚盖， 并将坩埚放到晶体生长炉， 其中 SiC粉体位于 晶体生长炉的高温区，籽晶位于晶体生长炉的低温区；加热晶体生长炉， 使高温区原料升华分解的气相源在低温区籽晶上沉积生长成 SiC单晶； 以及将 SiC单晶降温至室温。
根据本发明的再一个方面， 提供了一种使用该半绝缘 SiC单晶所形 成的衬底的晶体管。 该晶体管为金属-半导体场效应晶体管、 金属 -绝缘 体场效应晶体管或高电子迁移率晶体管。
从上述技术方案可以看出， 本发明具有以下有益效果：
1、 本发明提供的半绝缘碳化硅单晶及其生长方法， 在该半绝缘碳 化硅单晶中深能级掺杂剂和本征点缺陷的浓度之和大于浅施主杂质和 浅受主杂质浓度之间差值， 能够实现补偿作用。
2、 本发明提供的半绝缘碳化硅单晶及其生长方法， 该半绝缘碳化 硅单晶同时利用深能级惨杂剂和本征点缺陷来补偿浅能级的本底杂质， 实现了较好的半绝缘性能和良好的晶体质量， 满足了高性能微波器件对 高质量半绝缘 SiC单晶衬底的要求。 具体来说， 一方面， 两种深能级同 时起补偿作用， 降低了获得半绝缘性能的难度； 另一方面， 其避免单一 使用深能级掺杂剂时， 因掺杂剂浓度过大引起的晶体质量下降。
3、 本发明提供的半绝缘碳化硅单晶及其生长方法， 本征点缺陷的 浓度小于深能级掺杂剂的浓度， 使深能级掺杂剂能够在补偿时起主导作 用， 从而避免当本征点缺陷的浓度过高而起主导补偿作用时对 SiC晶片 电阻率造成的不稳定性。
熟悉本领域的技术人员可知， 半绝缘碳化硅单晶还需要经过后续高 温气相外延生长、 器件制备等工艺才能获得最终的微波器件， 后续过程 中的环境温度高达 1400°C-1700°C。 然而， 一些点缺陷在此温度范围时 是不稳定的， 部分点缺陷会愈合， 造成电阻率的下降， 从而达不到半绝 缘性能， 影响最终微波器件的性能。
本发明提供的半绝缘 SiC单晶生长方法， 在降温过程中， 从 1800°C 到室温晶体以冷却速率范围为 rc/h— 100°C/h的速度冷却， 极大地降低 了这些不稳定的点缺陷的浓度， 从而最终获得的点缺陷具有很好的热稳 定性， 保证了晶体电阻率在使用过程中的稳定性。
4、 本发明提供的半绝缘碳化硅单晶及其生长方法， 其表面的腐蚀 坑密度小于 1000/cm2, 具备较高的结晶质量， 满足高性能微波器件对碳 化硅单晶高质量的要求。
晶体缺陷包括点缺陷、 线缺陷、 面缺陷、 体缺陷。 碳化硅单晶的线 缺陷包括螺位错、 刃位错， 面缺陷包括基平面位错， 体缺陷包括多型、 微管等。 这些缺陷大部分具有遗传性， 在后续的气相外延生长中， 极易 繁衍到外延层中， 极大地降低后续制备微波器件的性能。 由于这些缺陷 经过熔融 KOH腐蚀后会呈现不同形状腐蚀坑， 因此本发明采用表面腐 蚀坑密度来表征晶体中这些缺陷密度。 本发明提供的半绝缘单晶， 其表 面的腐蚀坑密度小于 1000/cm2, 具备较高的结晶质量， 满足了后续器件 制备的要求。
附图说明 以下参照附图对本发明实施例作进一步说明， 其中：
图 1为依照本发明实施例采用物理气相传输法生长 SiC单晶的生长 室的结构示意图；
图 2为本发明实施例 1中晶片 1、 晶片 2的拉曼谱图；
图 3为碳化硅晶片经 KOH腐蚀后表面腐蚀坑形貌；
图 4为本发明实施例 2中晶片 3、 晶片 4的拉曼谱图。 具体实施方式 根据本发明的一个实施例， 本发明提供了一种半绝缘碳化硅单晶， 该单晶含有本底杂质、 深能级掺杂剂和本征点缺陷， 其中该本底杂质是 在生产及制备过程中引入的非故意掺杂的杂质， 其包括浅施主杂质和浅 受主杂质， 而深能级掺杂剂和本征点缺陷是为了补偿该本底杂质而故意 掺杂或加入的。
其中， 所述深能级掺杂剂和本征点缺陷的浓度之和大于浅施主杂质 和浅受主杂质浓度之间差值， 以实现补偿作用， 并且所述的本征点缺陷 浓度应大于 lx l015cnT3， 以达到能够明显影响碳化硅晶体电阻率的目的。 同时本征点缺陷的浓度小于深能级掺杂剂的浓度， 以使深能级掺杂剂能 够在补偿时起主导作用， 从而避免当本征点缺陷的浓度过高而起主导补 偿作用时对 SiC晶片电阻率造成的不稳定性。
由于浅施主杂质和浅受主杂质是非故意掺杂的本底杂质， 在晶体生 长过程中应尽量控制其浓度足够低，保证其浓度之差应小于 5xl017cn 3 , 优选小于 5xl016cm_3。 另外， 虽然在实施例中， 该碳化硅单晶中的浅施 主杂质包括氮， 浅受主杂质包括硼、 铝， 但在生产工艺中产生的其他本 底杂质也包括在本发明范围内。
在本发明的其他实施例中， 还选用了周期表 ΠΙΒ、 IVB、 VB、 VIB、 VIIB、 VIIIB、 ΙΒ、 ΠΒ中的其他元素或元素的组合作为深能级惨杂剂进 行了实验， 例如在一个实施例中为 IVB和 VB族元素， 优选为钒和钛， 所测得碳化硅单晶的室温电阻率均大于 l xlO5 Ω-cm , 更优选为大于 Ι χ Ι Ο9 并且在 SiC晶体经过高温约 1800°C长时间退火后， 室温电 阻率变化幅度不超过 10%。
在本发明中， 除了选用实施例中的碳空位 （ve)、 硅碳双空位， 还 可以包括诸如硅空位 （vsi)、 碳空位替位组合、 硅空位替位组合或双空 位的本征点缺陷， 所述双空位包括双碳空位、 双硅空位、 或者还可以包 括其它复杂点缺陷， 例如三空位聚集的团簇等。
进一步地， 本发明还提供了一种制备半绝缘 SiC单晶的方法， 该方 法包括： C D 将已惨杂深能级掺杂剂的 SiC粉体作为原料置入坩埚中， 盖 上粘接有籽晶的坩埚盖， 并将坩埚放到晶体生长炉， 其中 SiC粉体位于 晶体生长炉的高温区， 籽晶位于晶体生长炉的低温区；
( 2 ) 加热晶体生长炉， 使高温区原料升华分解的气相源在低温区 籽晶上沉积生长成 SiC单晶；
在整个生长过程中， 保持晶体生长界面处温度、 气相硅碳比、 晶体 生长速度稳定， 同时， 降低本底杂质进入到生长晶体中， 以获得高质量 的半绝缘 SiC晶体。
( 3 ) 将 SiC单晶降温至室温。
在本发明提供的生长方法中， 深能级掺杂剂是以第二相的形式与 SiC原料均匀混合， 形成已掺杂深能级掺杂剂的 SiC粉体； 或者， 深能 级掺杂剂已扩散至 SiC原料的晶格中， 形成已掺杂深能级掺杂剂的 SiC 粉体。 优选地， 深能级掺杂剂已扩散至 SiC原料的晶格中， 这样可以保 证深能级掺杂剂在整个晶体生长过程中保持一个稳定的掺杂浓度， 不会 导致生长的晶体中深能级掺杂剂浓度产生很大的不均匀性。
再者， 熟悉本领域的技术人员可知， 晶体生长过程都希望在一个稳 定、 波动很小的条件下进行。 然而， 碳化硅晶体生长过程中， 高温区碳 化硅原料升华产生的气相是非化学计量比的，通常气氛的硅碳比大于 1。 随着生长的进行， 原料逐渐开始石墨化， 就单个粉体颗粒来看， 其表层 包裹着一层残留的石墨。 因此， 气氛的硅碳比在生长过程中逐渐变化， 呈现逐步降低的趋势。 而气氛的硅碳比的降低往往会导致晶体产生包裹 物、 多型等缺陷， 显著降低了晶体的结晶质量。 针对此问题， 本发明提 供的生长方法要求在生长过程中保持晶体生长界面处温度、 气相硅碳 比、 晶体生长速度稳定。 进一步， 所述的保持晶体生长界面处气相硅碳 比、 晶体生长速度稳定， 包括在整个生长过程中， 高温区的原料温度逐 渐降低， 同时生长气氛的压力逐渐降低。 随着升华温度的下降， 碳化硅 原料升华出来的气相硅碳比升高， 但同时导致供应的气相源变少， 晶体 结晶速率下降。因此，本发明将降低原料温度和降低生长压力结合起来， 实现最终生长界面处的气相硅碳比、 晶体生长速度稳定， 从而保证了高 的结晶质量。
进一步地， 为了使晶体生长过程在一个稳定、 波动很小的条件下进 行， 在本发明的整个生长过程中， 保持晶体生长界面处气相硅碳比、 晶 体生长速度稳定， 包括高温区的原料温度逐渐降低， 同时生长气氛的压 力逐渐降低； 进一步， 高温区的原料温度降低的幅度在 30-300°C之间， 同时， 压力降低幅度与初始压力的比值在 5%-90%之间。
在整个生长过程中， 保持晶体生长界面处气相硅碳比稳定， 包括通 入有机的气相碳源， 同时实时控制有机气相碳源流量。 降低本底杂质进 入到生长晶体中， 包括通入有机的气相碳源。 所述的有机的气相碳源优 选甲烷、 乙烷、 丙烷、 乙炔。
在碳化硅晶体生长过程中， 生长气氛中的氮在结晶时取代碳位， 气 相碳与氮在界面处存在相互竞争。 当气氛中引入有机气相碳源后， 可以 有效增加氮进入到晶体的难度， 降低本底杂质的浓度， 提高了半绝缘晶 体的电阻率。
在整个生长过程中， 使 SiC单晶在非热力学平衡状态下结晶生长， 并且使 SiC单晶的结晶速度达到临界速度， 从而在 SiC单晶中生成比热 力学平衡条件下结晶 SiC单晶更高的原生点缺陷浓度。 其中， 所述临界 速度的范围为 0.6mm/h-4mm/h， 优选 1.5-4 mm/h。 其中， 使碳化硅晶体 在非热力学平衡状态下结晶生长的方法包括维持较低的碳化硅晶体生 长界面处的结晶温度、较高的碳化硅原料处的温度、和 /或较低的生长室 内压力。
在上述生长方法中， 降温过程中， 从 1800°C到室温晶体以足够慢的 速度冷却， 以减少不稳定的点缺陷的浓度， 保证晶体电阻率在使用过程 中的稳定性。其中所述的冷却速率范围为 rc/h -ioo°c/h。在降温过程中， 优选， 高温段降温速率低于低温段。
下面通过具体的实施例对本发明进行详细说明， 即通过具体的实施 例来详细描述高质量半绝缘 SiC单晶的半绝缘性质为什么是占主导的深 能级掺杂剂与本征点缺陷对浅施主杂质能级和浅受主杂质能级的共同 补偿作用的结果， 或者通过具体的实施例来详细描述本发明提供的半绝 缘碳化硅单晶为什么同时利用深能级掺杂剂和本征点缺陷来补偿浅能 级的本底杂质， 就能够实现较好的半绝缘性能和良好的晶体质量， 满足 高性能微波器件对高质量半绝缘 SiC单晶衬底的要求。
在本发明的以下实施例中， 所有 SiC晶体均采用常用的 SiC晶体制 备方法——物理气相传输法（Physical Vapor Transport Method)在如图 1 所示的生长室中获得， 该物理气相传输法的具体原理是： 将石墨埚 2内 的温度升至 2000〜2400°C， 使得 SiC原料 3升华， 升华产生气相 Si2C、 SiC2和 Si，将籽晶 5置于比 SiC原料 3温度低的坩埚上部（4为粘合剂）， 升华所产生的气相在温度梯度的作用下从原料的表面传输到温度较低 的籽晶 5处， 并在籽晶上结晶形成块状的 SiC晶体 6。
有关 SiC晶体生长装置及物理气相传输法的具体信息披露在申请人 2006年 3月 29 日授权公告的名称为"一种碳化硅晶体生长装置"的中国 发明专利 ZL 200310113521.X以及 2006年 6月 28日授权公告的名称为 "物理气相传输生长碳化硅单晶的方法及其装置 "的中国发明专利 ZL200310113523.9中。 本领域普通技术人员应该理解， 通过如高温化学 气相沉积法（HTCVD)、液相法或其他方法， 同样能够获得本发明的 SiC 单晶， 本发明的下述方法仅为优选。 另外， 本实施例中， 对石墨坩埚、 保温材料进行纯化处理， 具体是在 Ar气氛将石墨坩埚、 保温材料加热 到 2000°C高温处理， 让其中杂质（例如铝、 硼） 充分挥发走。 这样， 尽 可能减少本底杂质对 SiC晶体电阻率的影响。
实施例 1
晶体 1 采用故意惨入深能级惨杂剂 （以钒为例）， 其具体制备方法 如下： 将 80mg碳化钒粉体 （纯度 99.999%) 添加到 700g硅粉 （纯度 99.999%)和 300g碳粉（纯度 99.999%)， 用球磨机充分混合均匀， 然后 经 2200°C高温固相反应得到己掾杂的 SiC粉体； 参照图 1， 将该 SiC粉 体作为原料 3装到石墨埚 2中， 盖上粘接了 4H-SiC籽晶 5的坩埚盖 1， 放入到晶体生长炉中。 生长炉中充入氩气和甲烷的混合气体， 甲烷的比 例为 40%，压力控制在 2000Pa左右。籽晶温度保持在 2000-2150°C之间， 原料温度保持在 2250-2400°C之间。 生长过程中通过逐渐降低甲烷气体 的比例实现界面处稳定的硅碳比， 同时控制坩埚和石墨盖的相对位置、 实现晶体生长界面处的温度、 生长速率的稳定， 从而实现高质量 SiC晶 体的生长。 晶体生长速率约 0.8mm/h， 生长结束后冷却到室温。 点缺陷 的引入、控制通过相应的晶体生长、退火工艺获得， 以 0.8mm/h 的生长 速率在非热力学平衡状态下结晶生长引入点缺陷； 80 小时从 1900Ό降 低到室温， 其中冷却速率随着温度的下降呈指数增加， 从而降低晶体中 不稳定的点缺陷浓度， 实现晶体电阻率的稳定性。
晶体 2没有故意掺入深能级掺杂剂， 其他有关晶体生长、 退火的工 艺同晶体 1采用的工艺， 这里就不再赘述。
将通过上述方法获得的 SiC晶体 1和 SiC晶体 2沿垂直于生长方向 进行切片， 分别获得 0.4mm厚度的晶片 1和晶片 2， 其处于晶体生长中 期， 距籽晶约 5mm位置， 然后对该两种晶片进行性能测试。
晶片 1、 晶片 2的拉曼谱图如图 2所示， 表明晶片 1和晶片 2的晶 型为 4H-SiC。采用非接触式电阻测量仪测试晶片的电阻率， 晶片 1电阻 率为 6.9x l08Q。cm， 晶片 2电阻率为 8.4χ 103Ω。 η。进一步， 对本实例的 SiC晶片 1在 50kPa压力的 Ar保护气氛中进行 1800°C高温退火， 退火 时间为 10小时， 退完火后的晶片 1的电阻率为 6.8x l08Q。cm， 电阻率变 化幅度为 1.5%，表明退火后其电阻率没有明显下降， 晶片的半绝缘特性 具有良好的稳定性。
采用二次离子质谱表征晶片 1、 晶片 2的杂质含量， 结果见表 1所 示。 在晶体 1和晶体 2中， 包含有浅施主杂质氮 N， 浅受主杂质硼 B和 铝 A1, 以及深能级掺杂剂钒 V， 其余杂质元素含量很小， 相比可忽略不 计， 结果表明两者的本底杂质浓度接近。 另外， 晶片 1中的深能级掺杂 剂浓度（2.5E+16 )略小于浅施主杂质和浅受主杂质浓度之间差值（3.4E +16)， 表明在晶体 1中单独的深能级掺杂剂不足以补偿浅能级， 达到半 绝缘。 表 1、 SiC晶片中的杂质含量 （单位： cm—3 )
Figure imgf000012_0001
进一步对晶片做了正电子湮灭寿命谱表征，晶片 1结果为 T l=138ps， T2=166PS; 晶片 2结果为 Tl=133ps， i2=158ps, 两者结果相差不大。 通 过与文献报道的实验和理论计算结果比较分析， 其中 138ps、 133ps对应 SiC晶体的体寿命， 166ps、 158ps对应 SiC晶体中的碳空位 VC或双 C 空位的点缺陷， 这说明两种晶体中存在几乎相同的点缺陷。
进一步对晶片 1进行熔融 KOH腐蚀， 选择的腐蚀表面为 （0001 ) 面向 <11-20>偏4度， 腐蚀温度 480°C， 腐蚀时间 10分钟， 采用光学显 微镜 100倍模式观察腐蚀表面，如图 3所示，计算腐蚀坑密度为 850/cm2， 表明晶片具备良好的结晶质量。
由以上结果可以看出，晶片 2的电阻率已经明显受到点缺陷的影响， 但仅有点缺陷的存在是不足以补偿浅能级杂质的， 所以晶片 2电阻率达 不到半绝缘。 通过晶片 1和晶片 2对比可知， 晶片 1的电阻率较晶片 2 提高了 5个数量级， 电阻率提高幅度远大于晶片 2的电阻率， 表明深能 级摻杂剂起了补偿作用并占主导， 晶片 1中点缺陷的浓度小于深能级摻 杂剂的浓度。 因此， 晶体 1的半绝缘性质是占主导的深能级掺杂剂与本 征点缺陷对浅受主、 施主能级的共同补偿作用的结果。
实施例 2
本实例采用与实施例 1中相同的 SiC晶体制备方法。在本实施例中， 同样对石墨坩埚、 保温材料进行纯化处理， 具体是在 Ar气氛将石墨坩 埚、 保温材料加热到 2000°C高温处理， 让其中杂质（例如铝、 硼）充分 挥发走。 这样， 尽可能减少本底杂质对 SiC晶体电阻率的影响。
在本实施例中， 晶体 3选择钒、 钛组合作为深能级掺杂剂。 具体制 备过程如下： 将 200mg碳化钒粉体 （纯度 99.999% ) 和 90mg碳化钛粉 体（纯度 99.999%)添加到 800g碳化硅粉体 （纯度 99.999%) 中， 用球 磨机充分混合均勾后作为原料 3装到图 1所示的石墨埚 2中， 盖上粘接 了 6H-SiC籽晶 5的坩埚盖 1，放入到晶体生长炉中。生长炉中充入氩气， 压力控制在 1500Pa-500Pa， 原料温度控制在 2250-2400°C之间， 籽晶温 度保持在 2050-2200°C之间。 生长过程中通过控制坩埚和石墨盖的相对 位置实现稳定的生长界面温度， 通过控制压力的降低和原料温度的降低 实现生长界面处气相硅碳比、 生长速率的稳定， 以实现高质量 SiC晶体 的生长。 晶体生长速率为 1.5mm/h。 晶体中点缺陷的控制通过相应的退 火实现， 生长结束后 2小时从生长温度降低到 1800°C， 再 40小时降低 到至温。
晶体 4没有故意掺入深能级掺杂剂， 其他有关晶体生长、 退火的工 艺同晶体 3采用的工艺， 这里就不再赘述。
将通过上述方法获得的碳化硅晶体 3和碳化硅晶体 4沿垂直于生长 方向进行切片， 分别获得 0.4mm厚度的晶片 3和晶片 4， 其处于晶体生 长中期， 距籽晶约 8mm位置， 然后对该两种晶片进行性能测试。
晶片 3、 晶片 4的拉曼谱图如图 4所示， 表明晶片 3和晶片 4的晶 型为 6H-SiC；。采用非接触式电阻测量仪测试晶片的电阻率， 晶片 3电阻 率为 3.9xl09O»cm, 晶片 4电阻率为 4.6><103Q。cm。
采用二次离子质谱表征晶片的杂质含量， 结果见表 2， 其余杂质元 素含量很小，相比可忽略不计。晶片 3中的深能级掺杂剂浓度（1.1E+17) 略小于浅施主杂质和浅受主杂质浓度之间差值（1.4E +17)， 表明在晶体
3中单独的深能级掺杂剂不足以补偿浅能级。
表 2、 SiC晶片中的杂质含量 （单位： cm—3 )
Figure imgf000013_0001
进一步对晶片做了正电子湮灭寿命谱表征， 晶片 3 的结果为 xl=131ps, x2=220ps, 晶片 4结果为 d=133ps, x2=222ps, 两者结果相 差不大。 通过与文献报道的实验和理论计算结果比较分析， 其中 131、 133ps对应 SiC晶体的体寿命， 220ps、 222ps对应 SiC晶体中硅碳双空 位 vsivc相关的点缺陷。
晶片 4的结果表明点缺陷的存在明显地影响了晶体的电阻率， 但仅 有点缺陷的存在是不足以补偿浅杂质能级的， 晶片 4电阻率达不到半绝 缘。 通过晶片 3和晶片 4对比， 晶片 3的电阻率较晶片 4提高了 6个数 量级， 电阻率提高幅度远大于晶片 4的电阻率， 表明晶片 3中点缺陷的 浓度小于深能级掺杂剂的浓度， 因此深能级掺杂剂起了补偿作用并占主 导。 在晶片 3中， 点缺陷和占主导的深能级补偿元素共同对浅受主、 施 主能级起到补偿作用， 使晶片达到半绝缘性能。 因此， 深能级掺杂剂起 了补偿作用并占主导， 点缺陷和占主导的深能级补偿元素共同对浅受 主、 施主能级起到补偿作用， 使晶片达到半绝缘性能。
进一步， 晶体 5的有关生长方法同晶体 4， 唯一不同的是生长结束 后用 5小时从 1800°C降到室温。将通过上述方法获得的碳化硅晶体 5沿 垂直于生长方向进行切片， 获得 0.4mm厚度的晶片 5， 其处于晶体生长 中期， 距籽晶约 8mm位置， 然后对该晶片进行非接触式电阻率测试。 晶片 5电阻率为 2.8xl05Qacm。
对本实例的 SiC晶片 3、 晶片 4、 晶片 5在 50kPa压力的 Ar保护气 氛中进行 1800°C高温退火， 退火时间为 30小时， 退完火后的晶片 3、 晶片 4、 晶片 5的电阻率分别为 3.8χ 109欧姆 ·厘米、 4.6X 10'3欧姆，厘米、 8.6Χ 10·3欧姆 ·厘米。 晶片 4、 5对比说明， 单一点缺陷实现的半绝缘性能 是不稳定的， 经过退火后， 电阻率明显下降， 达不到半绝缘性能。 晶片 3 结果表明， 本发明提供生长方法制备晶体的电阻率退火后没有明显下 降， 具备良好的半绝缘热稳定性。
从以上两个实施例可以看出， 要想得到高质量的半绝缘 SiC单晶， 需要通过使占主导的深能级掺杂剂与本征点缺陷共同作用来补偿浅能 级的本底杂质才能实现， 即高质量半绝缘 SiC单晶的半绝缘性质是占主 导的深能级掺杂剂与本征点缺陷对浅施主杂质能级和浅受主杂质能级 共同补偿作用的结果。
进一步地， 本发明还提供一种将上述半绝缘碳化硅单晶作为衬底的 晶体管， 所述晶体管可以为金属-半导体场效应晶体管、 金属-绝缘体场 效应晶体管或高电子迁移率晶体管。
应该指出， 上文己经对本发明构思和原理进行了解释和说明， 尽管 使用了一些特定术语， 但这些术语不应理解为是对本发明的限制， 上述 实施例也仅为示意性目的。 在不偏离权利要求所限定的本发明的宗旨和 范围的情况下， 本领域的技术人员可以对本发明做出各种修改和变形。

Claims

权利要求
1、 一种半绝缘碳化硅单晶， 其特征在于， 该半绝缘碳化硅单晶含 有本底杂质、 深能级惨杂剂和本征点缺陷， 其中该本底杂质是在生产及 制备过程中引入的非故意掺杂的杂质， 深能级掺杂剂和本征点缺陷是为 了补偿该本底杂质而故意掺杂或加入的；
所述本底杂质包括浅施主杂质和浅受主杂质， 所述深能级掺杂剂与 本征点缺陷的浓度之和大于浅施主杂质与浅受主杂质的浓度之差， 且所 述本征点缺陷的浓度小于所述深能级掺杂剂的浓度。
2、 根据权利要求 1 所述的半绝缘碳化硅单晶， 其特征在于， 所述 深能级掺杂剂包括元素周期表 IIIB、 IVB、 VB、 VIB、 VIIB、 VIIIB、 IB、 IIB中的至少一种元素。
3、 根据权利要求 2 所述的半绝缘碳化硅单晶， 其特征在于， 所述 深能级惨杂剂为钪、 钒和钛中的至少一种。
4、 根据权利要求 1 所述的半绝缘碳化硅单晶， 其特征在于， 所述 本征点缺陷为碳空位、 硅空位、 碳空位替位组合、 硅空位替位组合、 双 空位和复杂点缺陷所组成的群组中的一种或多种。
5、 根据权利要求 4 所述的半绝缘碳化硅单晶， 其特征在于， 所述 双空位包括双碳空位、 双硅空位或碳空位与硅空位， 所述复杂点缺陷包 括三空位聚集的团簇。
6、 根据权利要求 1 所述的半绝缘碳化硅单晶， 其特征在于， 所述 本征点缺陷的浓度大于 l xl015cnT3。
7、 根据权利要求 1 所述的半绝缘碳化硅单晶， 其特征在于， 所述 浅施主杂质包括氮， 所述浅受主杂质包括硼、 铝。
8、 根据权利要求 1 所述的半绝缘碳化硅单晶， 其特征在于， 所述 浅施主杂质与浅受主杂质的浓度之差小于 5xl017cm— 3。
9、 根据权利要求 8 所述的半绝缘碳化硅单晶， 其特征在于， 所述 浅施主杂质与浅受主杂质的浓度之差小于 5xl016cm—3。
10、 根据权利要求 1所述的半绝缘碳化硅单晶， 其特征在于， 在室 温条件下该半绝缘碳化硅单晶的电阻率大于 Ι χ ΐθ5 Ω·οιη。
11、 根据权利要求 10 所述的半绝缘碳化硅单晶， 其特征在于， 在 室温条件下该半绝缘碳化硅单晶的电阻率大于 l xlO9 Q。cm。
12、 根据权利要求 1所述的半绝缘碳化硅单晶， 其特征在于， 该半 绝缘碳化硅单晶经过高温 1800Ό退火后，室温条件下电阻率变化幅度不 超过 10%。
13、 根据权利要求 1所述的半绝缘碳化硅单晶， 其特征在于， 该半 绝缘碳化硅单晶表面的腐蚀坑密度小于 1000/cm2, 其中该半绝缘碳化硅 单晶表面是经过熔融 KOH腐蚀后出现基平面位错的表面。
1.4、 一种半绝缘碳化硅单晶的生长方法， 其特征在于， 包括： 将已惨杂深能级掺杂剂的 SiC粉体作为原料置入坩埚中， 盖上粘接 有籽晶的坩埚盖， 并将坩埚放到晶体生长炉， 其中 SiC粉体位于晶体生 长炉的高温区， 籽晶位于晶体生长炉的低温区；
加热晶体生长炉， 使高温区原料升华分解的气相源在低温区籽晶上 沉积生长成 SiC单晶； 以及
将 SiC单晶降温至室温。
15、 根据权利要求 14所述的半绝缘碳化硅单晶的生长方法， 其特 征在于， 在所述已掺杂深能级掺杂剂的 SiC粉体中， 所述深能级掺杂剂 以第二相的形式与 SiC原料均匀混合， 形成已惨杂深能级掺杂剂的 SiC 粉体。
16、 根据权利要求 14所述的半绝缘碳化硅单晶的生长方法， 其特 征在于， 在所述已掺杂深能级掺杂剂的 SiC粉体中， 所述深能级掺杂剂 已扩散至 SiC原料的晶格中， 形成己掺杂深能级掺杂剂的 SiC粉体， 原 料中没有第二相存在。
17、 根据权利要求 14所述的半绝缘碳化硅单晶的生长方法， 其特 征在于， 所述加热晶体生长炉使高温区原料升华分解的气相源在低温区 籽晶上沉积生长成 SiC单晶的过程中， 保持晶体生长界面处温度、 气相 硅碳比、 晶体生长速度稳定， 同时降低本底杂质进入到生长晶体中。
18、 根据权利要求 17所述的半绝缘碳化硅单晶的生长方法， 其特 征在于， 所述保持晶体生长界面处温度、 气相硅碳比、 晶体生长速度稳 定， 是在整个生长过程中， 高温区的原料温度逐渐降低， 同时生长气氛 的压力逐渐降低。
19、 根据权利要求 18 所述的半绝缘碳化硅单晶的生长方法， 其特 征在于， 在整个生长过程中， 高温区的原料温度降低的幅度在 30-300°C 之间， 同时， 压力降低幅度与初始压力的比值在 5%- 90%之间。
20、 根据权利要求 17所述的半绝缘碳化硅单晶的生长方法， 其特 征在于， 所述保持晶体生长界面处气相硅碳比稳定， 是通过在整个生长 过程中通入有机气相碳源并实时控制有机气相碳源流量来实现的。
21、 根据权利要求 17所述的半绝缘碳化硅单晶的生长方法， 其特 征在于， 所述降低本底杂质进入到生长晶体中， 是通过在整个生长过程 中通入有机气相碳源来实现的。
22、 根据权利要求 20或 21所述的半绝缘碳化硅单晶的生长方法， 其特征在于， 所述有机气相碳源包括甲烷、 乙烷、 丙烷或乙炔。
23、 根据权利要求 17所述的半绝缘碳化硅单晶的生长方法， 其特 征在于， 在整个生长过程中， SiC单晶在非热力学平衡状态下结晶生长， 且 SiC单晶的结晶速度达到临界速度， 从而在 SiC单晶中生成比热力学 平衡条件下结晶 SiC单晶更高的原生点缺陷浓度。
24、 根据权利要求 23 所述的半绝缘碳化硅单晶的生长方法， 其特 征在于， 所述临界速度的范围为 0.6mm/h-4mm/h。
25、 根据权利要求 14所述的半绝缘碳化硅单晶的生长方法， 其特 征在于， 所述将 SiC单晶降温至室温， 是在降温过程中， 从 1800°C到室 温晶体以冷却速率范围为 l °C/h -100°C/h的速度冷却， 以减少不稳定的 点缺陷的浓度， 保证晶体电阻率在使用过程中的稳定性。
26、 一种晶体管， 其特征在于， 该晶体管包含由权利要求 1 至 13 中任一项所述半绝缘 SiC单晶所形成的衬底。
27、 根据权利要求 26所述的晶体管， 其特征在于， 所述晶体管为 金属-半导体场效应晶体管、 金属-绝缘体场效应晶体管或高电子迁移率
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