WO2020077846A1 - 掺杂少量钒的半绝缘碳化硅单晶、衬底、制备方法 - Google Patents

掺杂少量钒的半绝缘碳化硅单晶、衬底、制备方法 Download PDF

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WO2020077846A1
WO2020077846A1 PCT/CN2018/123707 CN2018123707W WO2020077846A1 WO 2020077846 A1 WO2020077846 A1 WO 2020077846A1 CN 2018123707 W CN2018123707 W CN 2018123707W WO 2020077846 A1 WO2020077846 A1 WO 2020077846A1
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silicon carbide
single crystal
carbide single
semi
concentration
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PCT/CN2018/123707
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English (en)
French (fr)
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高超
刘家朋
李加林
李长进
柏文文
宗艳民
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山东天岳先进材料科技有限公司
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Priority claimed from CN201811204702.6A external-priority patent/CN109280966B/zh
Priority claimed from CN201811204690.7A external-priority patent/CN109280965B/zh
Application filed by 山东天岳先进材料科技有限公司 filed Critical 山东天岳先进材料科技有限公司
Priority to JP2019571538A priority Critical patent/JP7235318B2/ja
Priority to KR1020197037935A priority patent/KR102375530B1/ko
Priority to EP18922091.6A priority patent/EP3666936A4/en
Publication of WO2020077846A1 publication Critical patent/WO2020077846A1/zh

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    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/36—Carbides
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B23/00—Single-crystal growth by condensing evaporated or sublimed materials
    • C30B23/02—Epitaxial-layer growth
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • C30B33/02—Heat treatment
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B35/00—Apparatus not otherwise provided for, specially adapted for the growth, production or after-treatment of single crystals or of a homogeneous polycrystalline material with defined structure
    • C30B35/002—Crucibles or containers
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B35/00—Apparatus not otherwise provided for, specially adapted for the growth, production or after-treatment of single crystals or of a homogeneous polycrystalline material with defined structure
    • C30B35/007—Apparatus for preparing, pre-treating the source material to be used for crystal growth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02529—Silicon carbide

Definitions

  • the application relates to a high-quality semi-insulating silicon carbide single crystal doped with a small amount of vanadium, a substrate and a preparation method thereof, which belong to the field of semiconductor materials.
  • SiC single crystal substrates are excellent semiconductor materials for the preparation of GaN-based high-frequency microwave devices due to their excellent physical properties such as large forbidden band width, high resistivity and thermal conductivity, and strong breakdown field.
  • SiC silicon carbide
  • the preparation of semi-insulating silicon carbide single crystals that have been industrialized is based on the physical vapor phase method (PVT), by introducing high concentrations of vanadium impurities as deep-level compensation centers to achieve semi-insulating properties, and thus prepared silicon carbide single crystals It is called doped semi-insulating silicon carbide single crystal; or it can achieve its semi-insulating properties by continuously reducing the concentration of shallow-level impurities in the crystal and introducing a certain number of intrinsic point defects during the crystal preparation process.
  • the crystal is called high-purity semi-insulating silicon carbide single crystal.
  • the low-level impurities in the high-purity semi-insulating silicon carbide single crystal can reduce the effective carrier concentration in the crystal, while pinning the Fermi level to the center of the forbidden band by introducing a specific number of intrinsic point defects Thereby achieving the semi-insulating characteristics of the crystal.
  • intrinsic point defects have a higher migration rate in the crystal, and migration and diffusion will occur at a certain temperature (such as the temperature conditions of GaN epitaxial layer preparation), which will cause the instability of the substrate resistivity. It also affects the stability of device performance.
  • the vanadium concentration [V] in the doped semi-insulating silicon carbide single crystal is usually 1 ⁇ 10 17 ⁇ 1 ⁇ 10 18 cm ⁇ 3 , and the corresponding nitrogen concentration [N] is higher than 10 17 cm ⁇ 3 in the preparation process
  • the high-concentration vanadium doping has higher technical barriers, and it is easy to form impurity concentrations containing a large number of defects and uncontrollable shallow energy levels in the prepared crystals, resulting in uncontrollable crystal quality.
  • High purity semi-insulating silicon carbide single crystal [N] is in the order of 10 15 cm -3
  • the corresponding point defect concentration is in the order of 1 ⁇ 10 15 cm -3 and above
  • the present application provides a high-quality lightly doped semi-insulating silicon carbide single crystal, substrate, and preparation method.
  • the resistivity of the semi-insulating silicon carbide single crystal is more stable and does not exist because of high concentration doping
  • the precipitate defects and electron capture problems caused by the silicon carbide single crystal substrate prepared from the silicon carbide single crystal have high uniformity of resistivity and low stress, making the silicon carbide single crystal substrate have excellent surface quality, Thereby ensuring the stability and consistency of the subsequent epitaxial quality, the silicon carbide single crystal substrate helps to improve the performance of the device.
  • the present application provides a high-quality semi-insulating silicon carbide single crystal doped with a small amount of vanadium, which is characterized by containing shallow level impurities, low concentration deep level dopants and a very small amount of intrinsic point defects
  • the deep level dopant and the intrinsic point defects together compensate for shallow level impurities, and the concentration of the deep level dopant is less than that of the deep level dopant doped in the semi-insulating silicon carbide single crystal Concentration;
  • the concentration of the intrinsic point defects is the original concentration of the intrinsic point defects in the silicon carbide single crystal at room temperature, and the concentration of the intrinsic point defects does not affect the stability of the electrical properties of the silicon carbide single crystal.
  • the native concentration of intrinsic point defects mentioned in this application is the concentration of intrinsic point defects formed by self-heating during the growth of silicon carbide single crystals, excluding the concentration of intrinsic point defects introduced during subsequent processing of silicon carbide single crystals.
  • the concentration of the deep-level dopant in the doped semi-insulating silicon carbide single crystal described in this application is generally 5 ⁇ 10 17 -1 ⁇ 10 18 cm ⁇ 3 .
  • the silicon carbide single crystal is achieved by reducing the shallow-level impurities in the silicon carbide crystal while introducing a small amount of deep-level dopant to replace the intrinsic point defects in the silicon carbide single crystal to achieve its semi-insulating properties.
  • the sum of the concentrations of the shallow-level impurities is lower than 1 ⁇ 10 17 cm -3
  • the concentration of the deep-level dopants is lower than 1 ⁇ 10 17 cm -3
  • the intrinsic point defects The concentration at room temperature is not higher than 1 ⁇ 10 15 cm ⁇ 3 .
  • the sum of the concentration of the shallow-level impurities is less than 1 ⁇ 10 17 cm ⁇ 3
  • the concentration of the deep-level dopant is less than 1 ⁇ 10 17 cm ⁇ 3
  • the intrinsic point defects at room temperature The concentration is greater than 1 ⁇ 10 15 cm ⁇ 3 .
  • the concentration of the intrinsic point defect at room temperature is not higher than 1 ⁇ 10 14 cm ⁇ 3 . Further, the concentration of the intrinsic point defects at room temperature is greater than 1 ⁇ 10 14 cm ⁇ 3 .
  • the sum of the concentrations of the shallow-level impurities is not less than 1 ⁇ 10 15 cm ⁇ 3
  • the concentration of the deep-level dopants is not less than 1 ⁇ 10 15 cm ⁇ 3
  • the intrinsic The concentration of point defects at room temperature is not higher than 1 ⁇ 10 14 cm ⁇ 3 .
  • the sum of the concentrations of the shallow-level impurities is greater than 1 ⁇ 10 15 cm ⁇ 3
  • the concentration of the deep-level dopants is greater than 1 ⁇ 10 15 cm ⁇ 3
  • the intrinsic point defects at room temperature The concentration is less than 1 ⁇ 10 14 cm ⁇ 3 .
  • the sum of the concentrations of the shallow-level impurities is higher than 1 ⁇ 10 15 cm ⁇ 3 , and the concentration of the deep-level dopants is 5 ⁇ 10 15 ⁇ 1 ⁇ 10 17 cm -3 , the The concentration of intrinsic point defects at room temperature is not higher than 1 ⁇ 10 14 cm ⁇ 3 . Further, the sum of the concentration of the shallow-level impurities is greater than 1 ⁇ 10 15 cm ⁇ 3 , and the concentration of the deep-level dopant is 5 ⁇ 10 15 ⁇ 1 ⁇ 10 17 cm -3 , the intrinsic The concentration of point defects at room temperature is less than 1 ⁇ 10 14 cm ⁇ 3 .
  • the sum of the concentrations of the shallow-level impurities is not less than 5 ⁇ 10 15 cm ⁇ 3 . Further, the sum of the concentrations of the shallow-level impurities is greater than 5 ⁇ 10 15 cm ⁇ 3 .
  • the sum of the concentrations of the shallow-level impurities is not less than 1 ⁇ 10 16 cm ⁇ 3 . Further, the sum of the concentrations of the shallow-level impurities is greater than 1 ⁇ 10 16 cm ⁇ 3 .
  • the concentration of the deep level dopant is 1 ⁇ 10 16 cm ⁇ 3 to 5 ⁇ 10 16 cm ⁇ 3 .
  • the concentration of the intrinsic point defects is not higher than the intrinsic concentration at room temperature.
  • the concentration of the intrinsic point defects is not higher than 1 ⁇ 10 12 cm ⁇ 3 . Further, the concentration of the intrinsic point defects is less than 1 ⁇ 10 12 cm ⁇ 3 .
  • the average change value of the resistivity of the silicon carbide single crystal before and after the epitaxial annealing process is less than 55%.
  • the silicon carbide single crystal can be prepared as a single crystal substrate, and the epitaxial process annealing includes: maintaining the temperature at 900-1200 ° C for 0.5-10 hours.
  • the silicon carbide single crystal has a mean change value of resistivity before and after treatment at 900-1200 ° C for 0.5-10 hours before and after treatment of less than 55%.
  • the silicon carbide single crystal is maintained at a temperature of 900-1200 ° C for 0.5-10h before and after the treatment, and the average change in resistivity is less than 50%; further, the silicon carbide single crystal is maintained at a temperature of 900-1200 ° C for 0.5-10h
  • the average change of resistivity before and after treatment is less than 30%.
  • the shallow-level impurities include one or more of IIIA and VA main group elements in the periodic table.
  • the shallow-level impurities include one or more of nitrogen, boron, and aluminum.
  • the shallow energy impurities include nitrogen, boron and aluminum.
  • the deep-level dopant is selected from at least one element of group VB in the periodic table.
  • the deep-level dopant is vanadium.
  • the crystal form of the silicon carbide crystal is 4H-SiC, 6H-SiC or 3C-SiC. Further, the crystal form of the silicon carbide single crystal is 4H-SiC.
  • the resistivity of the silicon carbide crystal is greater than 1 ⁇ 10 11 ⁇ ⁇ cm. Further, the resistivity of the silicon carbide crystal is greater than 3 ⁇ 10 11 ⁇ ⁇ cm. Further, the silicon carbide The resistivity of the crystal is greater than 6 ⁇ 10 11 ⁇ ⁇ cm.
  • a method for preparing a high-quality semi-insulating silicon carbide single crystal doped with a small amount of vanadium is provided, which is characterized by including the following steps:
  • Crystal growth place the silicon carbide powder doped with deep level dopant prepared in step 2) into the thermal field device treated in step 1) to start crystal growth, and the deep level doping after the end of the crystal growth
  • concentration of the impurity center element is 5 ⁇ 10 15 -1 ⁇ 10 17 cm -3 ;
  • the semi-insulating silicon carbide single crystal is prepared by a method including the following steps:
  • the crystal growth step includes a high-temperature pretreatment stage and a crystal growth stage.
  • the deep-level dopant element is selected from at least one element of group VB in the periodic table.
  • the deep-level dopant is vanadium.
  • the thermal field device includes a graphite insulation structure and a graphite crucible.
  • the graphite insulation structure is graphite insulation felt.
  • the impurity removal of the thermal field device in step 1) includes: placing the silicon carbide powder in a graphite crucible, and maintaining it at a temperature of 1800-2500 ° C. and a pressure of 5-50 mbar for 20-100 hours.
  • the step 1) of the thermal field device for removing impurities includes: after placing the silicon carbide powder in a graphite crucible, and maintaining it at a temperature of 2200-2400 ° C and a pressure of 20-30 mbar for 50-100 hours.
  • the concentration of the deep-level dopant element in the mixture of step 2) is 1 ⁇ 10 16 cm -3 to 1 ⁇ 10 17 cm -3 . Further, the concentration of the deep-level dopant element in the mixture of the step 2) is 2 ⁇ 10 16 cm -3 to 5 ⁇ 10 16 cm -3 .
  • the step of growing crystals in step 3) includes: a high-temperature pretreatment stage and a growing crystal stage;
  • the conditions of the high-temperature pretreatment stage are: holding time 5-50 h at a temperature of 1200 ° C.-2000 ° C. and a pressure of 800-1000 mbar;
  • the conditions of the crystal growth stage are: increasing to a temperature above 2200 ° C at a rate of 10-50 ° C / min, while reducing the pressure to 5-50mbar. This method of crystal growth stage fully sublimates the silicon carbide powder in the graphite crucible.
  • the crystal growth step in the step 3) includes: a high-temperature pretreatment stage and a crystal growth stage;
  • the conditions of the high-temperature pretreatment stage are: holding time 30-50 hours at a temperature of 1800 ° C-2000 ° C and a pressure of 800-900 mbar;
  • the conditions of the crystal growth stage are: increasing to a temperature above 2200 ° C at a rate of 10-30 ° C / min, while reducing the pressure to 5-50mbar.
  • the annealing treatment condition of the step 4) is that the silicon carbide single crystal initial product of the step 3) is placed in an annealing furnace and maintained at a temperature of 1800-2200 ° C for 10-50 hours.
  • the annealing treatment conditions in step 4) are as follows: the initial silicon carbide single crystal product in step 3) is placed in an annealing furnace and maintained at a temperature of 2000-2200 ° C for 30-50 hours.
  • the semi-insulating silicon carbide single crystal is prepared by a method including the following steps:
  • the vanadium element is uniformly doped in the silicon carbide powder.
  • the doping of vanadium element in the synthesis process of silicon carbide powder can be carried out by mixing with silicon carbide powder, or it can be built in a graphite container and buried in the mixed silicon carbide powder.
  • the vanadium doping concentration in the silicon carbide powder should be controlled accordingly. 0.01-1g of vanadium should be placed in each 1kg of the reaction source powder.
  • the concentration in silicon carbide powder should be on the order of 1 ⁇ 10 16 cm -3 to 1 ⁇ 10 17 cm -3 , in order to achieve the purpose of a small amount of vanadium content in the subsequent growth process.
  • the silicon carbide powder is mixed with vanadium uniformly, or the reaction process of the silicon carbide powder after the vanadium doping concentration is placed in the graphite container, refer to the published patent documents.
  • a silicon carbide powder containing a certain concentration of doped vanadium through the reaction, a small amount of vanadium-doped silicon carbide powder is placed in a graphite crucible and encapsulated in a long crystal furnace chamber to start crystal growth.
  • the crystal growth process includes high-temperature pretreatment at 1200 °C -2000 °C, 800-1000mbar, and 5-50h to remove impurities such as nitrogen adsorbed in the furnace.
  • This application introduces a small amount of vanadium element, so compared with high purity semi-insulating silicon carbide single crystal, the purification process of this step can be greatly simplified, only need to remove excess nitrogen element, compared with high purity semi-insulating carbonization
  • the preparation process of silicon single crystal can reduce the technical cost and seed cost.
  • the vanadium element will occupy a part of the lattice position of the crystal growth interface during the crystal growth process, thereby achieving the doping of the vanadium element.
  • vanadium doped in vanadium-doped silicon carbide powder Since a small amount of vanadium doped in vanadium-doped silicon carbide powder has been limited to the content of 1 ⁇ 10 16 cm -3 to 1 ⁇ 10 17 cm -3 , after the gas phase transmission process, due to the loss of the transmission process and the vanadium element After recombination with silicon carbide powder, the final concentration of vanadium element doped into the crystal should be between 5 ⁇ 10 15 cm -3 to 1 ⁇ 10 17 cm -3 .
  • These vanadium elements that enter the silicon carbide single crystal can exist as both donors and acceptors, thereby compensating for shallow-level impurities in the silicon carbide single crystal.
  • the silicon carbide single crystal is taken out of the graphite crucible. Since the growth interface is at a relatively high temperature during the growth of the silicon carbide single crystal, some atoms at the growth interface depart from the lattice position to form a certain concentration of intrinsic point defects.
  • the silicon carbide single crystal is placed in an annealing furnace and annealed at 1800-2000 °C for 10-50 hours to remove intrinsic point defects. During the annealing process, the intrinsic point defects existing in the silicon carbide single crystal are annihilated through migration, and the concentration of the intrinsic point defects decreases to a level that does not affect the electrical properties of the crystal.
  • the resistivity of the silicon carbide single crystal prepared by the present application is determined by the residual shallow-level impurities and a small amount of vanadium. Since the shallow-level impurities and a small amount of vanadium elements occupy the lattice position, they have high thermal stability, which means that the silicon carbide single crystal of the present application can obtain highly stable resistivity.
  • a semi-insulating silicon carbide single crystal substrate characterized in that the semi-insulating silicon carbide single crystal described above or the semi-insulating silicon carbide single crystal prepared by any of the above methods is provided Prepared.
  • a method for preparing a high-quality semi-insulating silicon carbide single crystal substrate doped with a small amount of vanadium characterized in that any of the above-mentioned high-quality semi-insulating high-quality semi-insulating doped with a small amount of vanadium
  • the silicon single crystal is cut and polished to prepare the semi-insulating silicon carbide single crystal substrate.
  • the average change value of the resistivity before and after the silicon carbide single crystal substrate is annealed by the epitaxial process is less than 55%.
  • the average change value of the resistivity before and after the silicon carbide single crystal substrate is maintained at 900-1200 ° C for 0.5-10 hours is less than 55%.
  • the average change value of the resistivity before and after the silicon carbide single crystal substrate is maintained at 900-1200 ° C. for 0.5-10 hours is less than 50%. Further, the average change value of the resistivity before and after the silicon carbide single crystal substrate is maintained at 900-1200 ° C. for 0.5-10 h is less than 30%.
  • an epitaxial wafer and / or a transistor which is characterized by comprising any of the foregoing semi-insulating silicon carbide single crystal substrates.
  • the silicon carbide single crystal of this application is a semi-insulating single crystal doped with a small amount of vanadium. This application replaces the intrinsic point in the silicon carbide single crystal by reducing the shallow energy impurities in the silicon carbide crystal and introducing a small amount of vanadium doping Defects, to achieve the semi-insulating characteristics of silicon carbide single crystal.
  • the resistivity of the silicon carbide single crystal of this application is determined by the remaining shallow-level impurities and a small amount of vanadium elements. Since these impurities occupy the lattice position, it has high thermal stability, which means that the crystal It is possible to obtain a highly stable resistivity and a high uniformity of resistivity.
  • the preparation of the silicon carbide single crystal of the present application combines the existing preparation technology of doped semi-insulating silicon carbide single crystal and high-purity semi-insulating silicon carbide single crystal, by controlling the shallow energy level impurity concentration and deep energy in the silicon carbide crystal
  • concentration of high-grade dopants can realize semi-insulating silicon carbide single crystals and substrates with higher resistivity stability, while avoiding precipitation defects and electron capture problems caused by high concentration doping, thereby improving silicon carbide
  • the quality of the single crystal substrate also contributes to the improvement of the performance of devices using the substrate.
  • the shallow-level impurity concentration in the silicon carbide single crystal of the present application does not need to be reduced to the level of high-purity semi-insulating silicon carbide single crystal, which can save costs and reduce the difficulty of the process.
  • the silicon carbide single crystal of this application as a substrate has good electrical performance stability; at the same time, the surface shape test of the silicon carbide single crystal substrate before and after annealing, the absolute value of the curvature and warpage changes far Less than the control line of 5 ⁇ m before and after annealing required by the epitaxy process, indicating that the internal stress of the silicon carbide single crystal substrate is extremely small, which can guarantee the substrate with excellent surface quality, thereby ensuring the stability and stability of the substrate quality in the subsequent epitaxy process consistency.
  • a semi-insulating single crystal / single crystal substrate doped with a small amount of vanadium is prepared by the method of the present application, and a small amount of vanadium doping in the silicon carbide single crystal is simultaneously introduced to replace the intrinsic point defects in the crystal to achieve Due to its semi-insulating properties, the technical cost and capital cost of the preparation method are low.
  • FIG. 1 is a scan diagram of the resistivity surface of silicon carbide single crystal substrate 1 # before annealing.
  • FIG. 2 is a scan diagram of the resistivity surface of silicon carbide single crystal substrate 1 # after annealing.
  • the silicon carbide single crystal crystal form test adopts Horiba's HR800 type confocal Raman spectrometer.
  • the surface test of silicon carbide single crystal substrate adopts MicroProf @ TTV200 type automatic surface tester of FRT company.
  • the resistivity test uses Semimap's COREMA-WT non-contact semi-insulation resistivity tester.
  • the element content test uses Cameca's IMS 7f-Auto secondary ion mass spectrometry instrument.
  • the preparation process of the silicon carbide single crystal includes the following steps:
  • the vanadium element is uniformly doped in the silicon carbide powder, and the concentration of vanadium in the silicon carbide powder is 1 ⁇ 10 16 cm -3 to 1 ⁇ 10 17 cm -3 ;
  • step 3 Crystal growth: After placing the vanadium-doped silicon carbide powder prepared in step 2) in the graphite crucible treated in step 1), crystal growth begins, and the crystal growth step includes a high-temperature pretreatment stage and a crystal growth stage, The concentration of vanadium after the growth of crystals is 5 ⁇ 10 15 cm -3 to 1 ⁇ 10 17 cm -3 .
  • the thermal field device includes a graphite crucible and a graphite insulation felt, and the graphite insulation felt and the graphite crucible used for preparing silicon carbide single crystal are purified at high temperature.
  • the high-temperature purification steps include: placing silicon carbide powder in the graphite crucible, the particle size of the powder is controlled at 50-500 ⁇ m, and the quantity is controlled at 50% -80% of the crucible volume. After placing the graphite crucible in the graphite insulation blanket and encapsulating it in the silicon carbide growth furnace, it is kept at a certain temperature and pressure for a period of time to remove impurities in the thermal field device.
  • the specific treatment temperature, pressure and time of thermal field 1 #, thermal field 2 #, thermal field 3 #, thermal field 4 # and thermal field 5 # are shown in Table 1.
  • the thermal field devices in Table 1 include graphite crucible and graphite Insulation felt.
  • the silicon carbide powder in the graphite crucible during the processing of thermal field 1 #, thermal field 2 #, thermal field 3 #, thermal field 4 # and thermal field 5 # sublimates and forms a high-temperature gas. It can infiltrate into the graphite crucible and graphite insulation felt and expel the nitrogen and other impurity elements it adsorbs, so as to obtain high-purity graphite materials, thereby removing the prepared thermal field 1 #, thermal field 2 #, thermal field 3 #, thermal field 4 # and thermal field 5 # impurities, so as to control the introduction of impurities in the process of preparing semi-insulating silicon carbide single crystal.
  • Doping silicon carbide powder with vanadium element to produce a small amount of vanadium-doped silicon carbide powder, 0.01-1g vanadium element should be placed in 1kg of reacted silicon carbide powder, and the concentration of vanadium in silicon carbide powder after reaction It should be on the order of 1 ⁇ 10 16 cm -3 to 1 ⁇ 10 17 cm -3 in order to achieve the range of vanadium content in the subsequent growth process.
  • the crystal growth step in this embodiment includes a high temperature pretreatment stage and a crystal growth stage.
  • the high temperature pretreatment stage removes impurities such as nitrogen adsorbed in the furnace. Since the purpose of this embodiment is to introduce a small amount of vanadium, the comparison For high-purity semi-insulating silicon carbide single crystals, the purification process of this step can be greatly simplified by removing excess nitrogen, which can reduce technical costs and Seed cost.
  • the parameter control of the crystal growth stage of the present application allows a small amount of vanadium-doped silicon carbide powder in the graphite crucible to fully sublimate. Seed crystals and crystallize. According to the growth process of the heavily doped semi-insulating silicon carbide single crystal, the vanadium element will occupy a part of the lattice position of the crystal growth interface during the crystal growth process, thereby achieving the doping of vanadium.
  • vanadium-doped silicon carbide powder Since a small amount of vanadium contained in the vanadium-doped silicon carbide powder has been limited to the content of 1 ⁇ 10 16 cm -3 to 1 ⁇ 10 17 cm -3 , after the gas phase transmission process, due to the loss of the transmission process, vanadium and After recombination of silicon carbide powder, the concentration of vanadium element doped into the silicon carbide single crystal is between 5 ⁇ 10 15 cm -3 and 1 ⁇ 10 17 cm -3 . These vanadium elements that enter the silicon carbide single crystal can exist as both donors and acceptors, thereby compensating for shallow-level impurities in the silicon carbide single crystal.
  • the preliminary silicon carbide single crystal product prepared in Example 2 is further annealed to prepare a semi-insulating silicon carbide single crystal.
  • a semi-insulating silicon carbide single crystal Taking the annealing process of the silicon carbide single crystal primary product produced by performing the silicon carbide single crystal long crystal step in the thermal field 1 # as an example, the steps for preparing the silicon carbide single crystal are described.
  • the semi-insulating silicon carbide single crystal primary products obtained by the thermal field 1 # of Example 2 through the crystal growth steps of Table 2 were respectively annealed to obtain silicon carbide single crystal 1 #, silicon carbide single crystal 2 #, silicon carbide Single crystal 3 #, silicon carbide single crystal 4 # and silicon carbide single crystal 5 #, the specific annealing treatment conditions are shown in Table 2.
  • the silicon carbide single crystal is taken out of the graphite crucible. Since the growth interface is at a relatively high temperature during the crystal growth process, some atoms at the growth interface depart from the lattice position to form a certain concentration of intrinsic point defects.
  • the silicon carbide single crystal is placed in an annealing furnace and annealed at 1800-2000 °C for 10-50 hours to remove intrinsic point defects. During the annealing process, the intrinsic point defects existing in the silicon carbide single crystal are annihilated through migration, and the concentration of the intrinsic point defects decreases to a level below its intrinsic concentration at room temperature and does not affect the stability of the crystal's electrical properties.
  • the resistivity of the silicon carbide single crystal prepared by the present application is determined by the remaining shallow-level impurities and a small amount of vanadium. Since the shallow-level impurities and a small amount of vanadium elements occupy the lattice position, they have high thermal stability, which means that the silicon carbide single crystal of the present application can obtain highly stable resistivity.
  • the growth interface is at a relatively high temperature during crystal growth, some atoms at the growth interface depart from the lattice position to form point defects with a certain concentration.
  • the point defects existing in the crystal are annihilated through migration, so that the concentration drops to a level that does not affect the electrical properties of the crystal.
  • the resistivity of the crystal is determined by the remaining shallow-level impurities and a small amount of vanadium. Since these impurities occupy the lattice position, they have high thermal stability, which means that the crystal can obtain a highly stable resistivity.
  • the test results show that the prepared silicon carbide single crystal has semi-insulating properties, and the resistivity is high, after epitaxy After the process annealing (900-1200 °C / 0.5-10h), the average change of resistivity is less than 55%.
  • silicon carbide single crystal 1 #, silicon carbide single crystal 2 #, silicon carbide single crystal 3 #, silicon carbide single crystal 4 # and silicon carbide single crystal 5 # as examples to illustrate the test of resistivity, crystal type, impurity content, cost
  • the results of the point defects and resistivity are shown in Table 3, where the shallow level impurity content includes N, B, and Al.
  • Example 3 Separately cut, grind and polish the silicon carbide single crystal prepared in Example 3 to obtain a 4-8 inch semi-insulating silicon carbide single crystal substrate, and perform annealing treatment on the prepared semi-insulating silicon carbide single crystal substrate.
  • the resistivity and surface shape of the silicon carbide single crystal substrate before and after annealing were tested.
  • the test results showed that the silicon carbide single crystal substrate prepared in Example 3 had good electrical performance stability, and the internal stress of the substrate was extremely small.
  • a 4-inch silicon carbide single crystal substrate 1 # made of silicon carbide single crystal 1 # will be described as an example. After silicon carbide single crystal substrate 1 # was annealed at 1200 ° C for 2h. The scan diagram of the resistivity surface of the test silicon carbide single crystal substrate 1 # before annealing is shown in FIG. 1, and the scan diagram of the resistivity surface of the silicon carbide single crystal substrate 1 # after annealing is shown in FIG. 2.
  • the average value of test resistivity changed from 4.22 ⁇ 10 11 ⁇ ⁇ cm to 3.17 ⁇ 10 11 ⁇ ⁇ cm, the resistivity attenuation was less than 50%; meanwhile, the surface shape test of silicon carbide single crystal substrate 1 # before and after annealing
  • the WARP value of single crystal substrate 1 # before and after annealing changed from 8.35 ⁇ m to 8.42 ⁇ m, the BOW value changed from 9.62 ⁇ m to 9.87 ⁇ m, and the absolute value of the curvature and warpage was much smaller than the 5 ⁇ m before and after annealing required by the epitaxy
  • the control line indicates that the internal stress of the silicon carbide single crystal substrate is extremely small, which can guarantee the substrate with excellent surface quality, thereby ensuring the stability and consistency of the quality of the silicon carbide single crystal substrate in the subsequent epitaxy process.

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Abstract

本申请公开了一种掺杂少量钒的半绝缘碳化硅单晶、衬底、制备方法，属于半导体材料领域。该半绝缘碳化硅单晶包含浅能级杂质、低浓度深能级掺杂剂和极少量本征点缺陷；所述深能级掺杂剂与所述本征点缺陷共同补偿浅能级杂质，所述深能级掺杂剂的浓度小于掺杂半绝缘碳化硅单晶中深能级掺杂剂的浓度；所述本征点缺陷的浓度为室温下碳化硅单晶中的本征点缺陷原生浓度，所述本征点缺陷浓度不影响碳化硅单晶电学性能的稳定性。该半绝缘碳化硅单晶具有高度稳定的电阻率，并且具有高的电阻率均匀性。由该碳化硅单晶制备的碳化硅单晶衬底具有高的电阻率均匀性、低应力，使得碳化硅单晶衬底具有优异的面型质量，从而保证了后续外延质量的稳定性和一致性。

Description

掺杂少量钒的半绝缘碳化硅单晶、衬底、制备方法 技术领域
本申请涉及一种掺杂少量钒的高质量半绝缘碳化硅单晶、衬底及其制备方法，属于半导体材料领域。
背景技术
半绝缘碳化硅(SiC)单晶衬底由于具有禁带宽度大、电阻率及热导率高、击穿场强大等优异的物理性能而成为制备GaN基高频微波器件的优选半导体材料。随着5G技术的不断发展，市场端对半绝缘碳化硅单晶衬底的需求数量不断扩大，更重要的，批量商业化的应用对碳化硅半绝缘单晶衬底的质量要求也提出了更高的要求。
目前已经产业化的半绝缘碳化硅单晶制备是在物理气相法(PVT)的基础上，通过引入高浓度的钒杂质作为深能级补偿中心实现半绝缘特性，由此制备的碳化硅单晶称为掺杂半绝缘碳化硅单晶；或者通过在晶体制备过程中不断降低晶体中的浅能级杂质浓度并引入一定数量的本征点缺陷实现其半绝缘特性，由此制备的碳化硅单晶称为高纯半绝缘碳化硅单晶。
掺杂半绝缘碳化硅单晶在制备过程中由于有高浓度钒引入，容易在晶体中形成钒的沉淀物并诱生微管缺陷，降低晶体质量；此外，研究表明高浓度的钒在器件中作为电子俘获中心，会引起背栅效应，降低甚至破坏器件性能。因此，随着衬底制备技术和器件制备技术的发展，高纯半绝缘碳化硅单晶衬底逐渐成为主流。高纯半绝缘碳化硅单晶中较低的浅能级杂质能够降低晶体中的有效载流子浓度，同时通过引入的特定数量的本征点缺陷将费米能级钉扎在禁带中心，从而实现晶体的半绝缘特 性。然而，本征点缺陷在晶体中具有较高的迁移速率，在一定温度下(如GaN外延层制备的温度条件下)会发生迁移扩散并湮灭，这会引起衬底电阻率的不稳定性，同样对器件性能的稳定性造成影响。
掺杂半绝缘碳化硅单晶中钒浓度[V]通常为1×10 17～1×10 18cm ‐3，相应的氮浓度[N]高于10 17cm ‐3量级，其制备过程中的高浓度钒掺杂具有较高的技术壁垒，且制备晶体中易形成含大量缺陷和不可控的浅能级杂质浓度，造成晶体质量不可控。高纯半绝缘碳化硅单晶中[N]为10 15cm ‐3量级，相应的点缺陷浓度为1×10 15cm ‐3量级及以上，其制备过程中的氮等浅能级杂质浓度去除需要较高的技术成本和资金成本。
发明内容
为了解决上述问题，本申请提供了一种高质量轻掺杂的半绝缘碳化硅单晶、衬底、制备方法，该半绝缘碳化硅单晶的电阻率更稳定，不存在因为高浓度掺杂而引起的沉淀物缺陷和电子俘获问题；由该碳化硅单晶制备的碳化硅单晶衬底具有高的电阻率均匀性、低应力，使得碳化硅单晶衬底具有优异的面型质量，从而保证了后续外延质量的稳定性和一致性，该碳化硅单晶衬底有助于器件性能的提升。
一方面，本申请提供了一种杂掺杂少量钒的高质量半绝缘碳化硅单晶，其特征在于，包含浅能级杂质、低浓度深能级掺杂剂和极少量的本征点缺陷；所述深能级掺杂剂与所述本征点缺陷共同补偿浅能级杂质，所述深能级掺杂剂的浓度小于掺杂半绝缘碳化硅单晶中深能级掺杂剂的浓度；所述本征点缺陷的浓度为室温下碳化硅单晶中的本征点缺陷原生浓度，所述本征点缺陷浓度不影响碳化硅单晶电学性能的稳定性。
本申请中所述的本征点缺陷的原生浓度为生长碳化硅单晶过程中自热形成的本征点缺陷的浓度，不包括在碳化硅单晶后续处理时引入的本 征点缺陷浓度。
本申请中所述掺杂半绝缘碳化硅单晶中深能级掺杂剂的浓度通常为5×10 17～1×10 18cm ‐3。
可选地，所述碳化硅单晶是通过降低碳化硅晶体中的浅能级杂质同时引入少量的深能级掺杂剂替代碳化硅单晶中的本征点缺陷，实现其半绝缘特性。
可选地，所述浅能级杂质的浓度之和低于1×10 17cm ‐3，所述深能级掺杂剂的浓度低于1×10 17cm ‐3，所述本征点缺陷室温下的浓度不高于1×10 15cm ‐3。进一步地，所述浅能级杂质的浓度之和小于1×10 17cm ‐3，所述深能级掺杂剂的浓度小于1×10 17cm ‐3，所述本征点缺陷室温下的浓度大于1×10 15cm ‐3。
可选地，所述本征点缺陷室温下的浓度不高于1×10 14cm ‐3。进一步地，所述本征点缺陷室温下的浓度大于1×10 14cm ‐3。
可选地，所述浅能级杂质的浓度之和不低于1×10 15cm ‐3，所述深能级掺杂剂的浓度不低于1×10 15cm ‐3，所述本征点缺陷室温下的浓度不高于1×10 14cm ‐3。进一步地，所述浅能级杂质的浓度之和大于1×10 15cm ‐3，所述深能级掺杂剂的浓度大于1×10 15cm ‐3，所述本征点缺陷室温下的浓度小于1×10 14cm ‐3。
可选地，所述浅能级杂质的浓度之和高于1×10 15cm ‐3，所述深能级掺杂剂的浓度为5×10 15～1×10 17cm ‐3，所述本征点缺陷室温下的浓度不高于1×10 14cm ‐3。进一步地，所述浅能级杂质的浓度之和大于1×10 15cm ‐3，所述深能级掺杂剂的浓度为5×10 15～1×10 17cm ‐3，所述本征点缺陷室温下的浓度小于1×10 14cm ‐3。
优选地，所述浅能级杂质的浓度之和不低于5×10 15cm ‐3。进一步地，所述浅能级杂质的浓度之和大于5×10 15cm ‐3。
更优选地，所述浅能级杂质的浓度之和不低于1×10 16cm ‐3。进一步地，所述浅能级杂质的浓度之和大于1×10 16cm ‐3。
优选地，所述深能级掺杂剂的浓度为1×10 16cm ‐3～5×10 16cm ‐3。
优选地，所述本征点缺陷缺陷浓度不高于室温下的本征浓度。
优选地，所述本征点缺陷缺陷浓度不高于1×10 12cm ‐3。进一步地，所述本征点缺陷缺陷浓度小于1×10 12cm ‐3。
可选地，所述碳化硅单晶在外延退火工艺处理前后的电阻率均值变化值小于55％。
可选地，所述碳化硅单晶可制备成单晶衬底，外延工艺退火包括：在900‐1200℃温度保持0.5‐10h。
可选地，所述碳化硅单晶经900‐1200℃温度保持0.5‐10h处理前后的电阻率均值变化值小于55％。
优选地，所述碳化硅单晶经900‐1200℃温度保持0.5‐10h处理前后的电阻率均值变化值小于50％；进一步地，所述碳化硅单晶经900‐1200℃温度保持0.5‐10h处理前后的电阻率均值变化值小于30％。
可选地，所述浅能级杂质包括元素周期表中的IIIA和VA主族元素中的一种或多种。
可选地，所述浅能级杂质包括氮、硼和铝中的一种或多种。
优选地，所述浅能级杂质包括氮、硼和铝。
可选地，所述深能级掺杂剂选自元素周期表中的ⅤB族元素中的至少一种。
优选地，所述深能级掺杂剂为钒。
可选地，所述的碳化硅晶体的晶型为4H‐SiC、6H‐SiC或3C‐SiC。进一步地，所述的碳化硅单晶的晶型为4H‐SiC。
可选地，所述的碳化硅晶体的电阻率大于1×10 11Ω·cm，进一步地， 所述碳化硅晶体的电阻率大于3×10 11Ω·cm，更进一步地，所述碳化硅晶体的电阻率大于6×10 11Ω·cm。
根据本申请的又一方面，提供了一种掺杂少量钒的高质量半绝缘碳化硅单晶的制备方法，其特征在于，包括下述步骤：
1)热场装置除杂；
2)混料：将深能级掺杂剂掺杂于碳化硅粉料中；
3)长晶：将步骤2)制得的掺杂深能级掺杂剂的碳化硅粉置于经步骤1)处理的热场装置后，开始长晶，长晶结束后的深能级掺杂中心元素的浓度为5×10 15‐1×10 17cm ‐3；
4)退火：将经过步骤3)处理的碳化硅单晶初品进行退火处理，即制得所述的碳化硅单晶。
可选地，所述的半绝缘碳化硅单晶由包括下述步骤的方法制备得到：
1)热场装置除杂：对石墨保温结构和石墨坩埚进行高温提纯；
2)混料：将深能级掺杂剂元素掺杂于碳化硅粉料中，碳化硅粉料中的深能级掺杂剂的浓度为1×10 16cm ‐3～1×10 17cm ‐3；
3)长晶：将步骤2)制得的掺杂深能级掺杂剂元素的碳化硅粉放置在经步骤1)处理的石墨坩埚后，开始长晶步骤，长晶步骤结束后的深能级掺杂中心元素的浓度为5×10 15cm ‐3～1×10 17cm ‐3；
4)退火：将经过步骤3)处理的碳化硅单晶进行退火处理。
优选地，所述长晶步骤包括高温预处理阶段和长晶阶段。
所述的深能级掺杂剂元素选自元素周期表中的ⅤB族元素中的至少一种。
优选地，所述深能级掺杂剂为钒。
可选地，所述热场装置包括石墨保温结构和石墨坩埚。进一步地，所述石墨保温结构为石墨保温毡。
优选地，所述步骤1)的热场装置除杂包括：将碳化硅粉料放置在石墨坩埚后，在温度1800‐2500℃、压力5‐50mbar下保持20‐100h。进一步地，所述步骤1)的热场装置除杂步骤包括：将碳化硅粉料放置在石墨坩埚后，在温度2200‐2400℃、压力20‐30mbar下保持50‐100h。
可选地，所述步骤2)的混料中的深能级掺杂剂元素的浓度为1×10 16cm ‐3～1×10 17cm ‐3。进一步地，所述步骤2)的混料中的深能级掺杂剂元素的浓度为2×10 16cm ‐3～5×10 16cm ‐3。
可选地，所述步骤3)中的长晶步骤包括：高温预处理阶段和长晶阶段；
所述高温预处理阶段的条件为：在温度1200℃‐2000℃和压力800‐1000mbar下保持时间5‐50h；
所述长晶阶段的条件为：以10‐50℃/min的速率提高至2200℃以上的温度，同时将压力降至5‐50mbar。该长晶阶段方法使得石墨坩埚内的碳化硅粉料充分升华。
进一步地，所述步骤3)中的长晶步骤包括：高温预处理阶段和长晶阶段；
所述高温预处理阶段的条件为：在温度1800℃‐2000℃和压力800‐900mbar下保持时间30‐50h；
所述长晶阶段的条件为：以10‐30℃/min的速率提高至2200℃以上的温度，同时将压力降至5‐50mbar。
可选地，所述步骤4)的退火处理条件为：将步骤3)的碳化硅单晶初品置于退火炉中并在1800‐2200℃温度下保持10‐50h。进一步地，所述步骤4)的退火处理条件为：将步骤3)的碳化硅单晶初品置于退火炉中并在2000‐2200℃温度下保持30‐50h。
作为一种实施方式，所述的半绝缘碳化硅单晶由包括下述步骤的方 法制备：
(1)对碳化硅单晶长晶使用的石墨保温毡和石墨坩埚进行高温提纯。石墨坩埚内放置碳化硅粉料，粉料粒度控制在50‐500μm，数量控制在坩埚容积的50％‐80％。将石墨坩埚置于石墨保温并封装于碳化硅长晶炉后，在温度1800‐2500℃、压力5‐50mbar下高温处理20‐100h。该步骤使坩埚内的粉料升华并形成高温气体，高温气体在逸散的过程中能够浸润到石墨坩埚和石墨保温毡中并驱逐其吸附的氮等杂质元素，从而获得高纯度的石墨材料。
(2)将钒元素均匀的掺杂于碳化硅粉料中。钒元素在碳化硅粉料合成过程中的掺杂可以通过与碳化硅粉料混合的方式进行，也可以内置于石墨容器中后埋于混合后的碳化硅粉料中。为了控制后续引入到碳化硅单晶中的钒掺杂浓度，碳化硅粉料中的钒掺杂浓度应相应的进行控制，每1kg反应源粉中应放置0.01‐1g钒元素，其反应后在碳化硅粉料中的浓度应在1×10 16cm ‐3～1×10 17cm ‐3量级，以实现后续长晶过程中的少量钒的含量范围目的。具体的，碳化硅粉料经过与钒混合均匀后，或在石墨容器中放置钒掺杂浓度后的碳化硅粉料反应过程可参考已公开的专利文件。
(3)通过反应获得含有一定掺杂钒浓度的碳化硅粉料后，将少量钒掺杂碳化硅粉料置于石墨坩埚中并封装入长晶炉膛，开始晶体生长。晶体生长过程包括1200℃‐2000℃、800‐1000mbar、5‐50h的高温预处理以去除炉膛内吸附的氮等杂质。本申请引入少量的钒元素，因此相比于高纯半绝缘碳化硅单晶，本步骤的提纯过程可以较大的简化，只需将过量的氮元素去除即可，相比高纯半绝缘碳化硅单晶的制备过程可以降低技术成本和籽晶成本。完成炉膛内的提纯预处理后，将温度以10‐30℃/min的速率提高至2200℃以上的温度，同时将压力降至5‐50mbar，以使石墨坩埚内的少量钒掺杂碳化硅粉料充分升华。升华后的气相及释放出的钒 元素随着温度梯度传输至籽晶处并结晶。根据重掺杂半绝缘碳化硅单晶生长过程可知，钒元素会在晶体生长过程中占据晶体生长界面一部分晶格位置，从而实现钒元素的掺杂。由于少量钒掺杂碳化硅粉料中含有的钒元素已被限制在1×10 16cm ‐3～1×10 17cm ‐3的含量，经过气相传输过程后，由于传输过程的损耗及钒元素与碳化硅粉料的再结合，最终掺杂进入到晶体中的钒元素浓度应在5×10 15cm ‐3～1×10 17cm ‐3之间。这些进入到碳化硅单晶的钒元素既能作为施主存在，也能作为受主存在，从而补偿掉碳化硅单晶中的浅能级杂质。
(4)碳化硅单晶生长结束后，将碳化硅单晶取出石墨坩埚。由于在碳化硅单晶生长过程中生长界面处于较高的温度，生长界面处部分原子脱离晶格位置形成一定浓度的本征点缺陷。将碳化硅单晶放置于退火炉中，在1800‐2000℃温度下进行10‐50h的退火处理，可去除本征点缺陷。退火过程中，存在于碳化硅单晶中的本征点缺陷经过迁移而湮灭，本征点缺陷的浓度下降至不影响晶体电学性能的水平。
本申请制备的碳化硅单晶的电阻率由残余的浅能级杂质和少量的钒元素决定。由于浅能级杂质和少量的钒元素都占据晶格位置，其具有很高的热稳定性，这也就意味着本申请的碳化硅单晶可以获得具有高度稳定的电阻率。
本申请中的“不高于”、“不低于”、“高于”和“低于”包含端点值。
根据本申请的另一方面，提供了一种半绝缘碳化硅单晶衬底，其特征在于，由任一项上述的半绝缘碳化硅单晶或上述任一方法制备的半绝缘碳化硅单晶制备得到。
根据本申请的又一方面，提供了一种掺杂少量钒的高质量半绝缘碳化硅单晶衬底的制备方法，其特征在于，将任一上述的掺杂少量钒的高质量半绝缘碳化硅单晶进行切割、抛光，即制得所述的半绝缘碳化硅单 晶衬底。
可选地，所述碳化硅单晶衬底经外延工艺退火处理前后的电阻率均值变化值小于55％。
可选地，所述碳化硅单晶衬底经900‐1200℃温度保持0.5‐10h处理前后的电阻率均值变化值小于55％。
进一步地，所述碳化硅单晶衬底经900‐1200℃温度保持0.5‐10h处理前后的电阻率均值变化值小于50％。进一步地，所述碳化硅单晶衬底经900‐1200℃温度保持0.5‐10h处理前后的电阻率均值变化值小于30％。
根据本申请的又一方面，提供了一种外延晶片和/或晶体管，其特征在于，包括任一上述的半绝缘碳化硅单晶衬底。
本申请的有益效果包括但不限于：
1)本申请的碳化硅单晶为少量钒掺杂的半绝缘单晶，本申请通过降低碳化硅晶体中的浅能级杂质同时引入少量的钒掺杂替代碳化硅单晶中的本征点缺陷，实现碳化硅单晶的半绝缘特性。
2)本申请的碳化硅单晶的电阻率由残余的浅能级杂质和少量的钒元素决定，由于这些杂质都占据晶格位置，其具有很高的热稳定性，这也就意味着晶体可以获得具有高度稳定的电阻率，并且具有高的电阻率均匀性。
3)本申请的碳化硅单晶的制备结合现有的掺杂半绝缘碳化硅单晶和高纯半绝缘碳化硅单晶制备技术，通过控制碳化硅晶体中的浅能级杂质浓度和深能级掺杂剂的浓度，可以实现具有更高电阻率稳定性的半绝缘碳化硅单晶和衬底，同时可以避免因高浓度掺杂而引起的沉淀物缺陷和电子俘获问题，从而提高碳化硅单晶衬底的质量并有助于使用该衬底的器件性能的提升。
4)本申请的碳化硅单晶中的浅能级杂质浓度不需要降到高纯半绝缘碳化硅单晶的水平，可以节约成本，并且降低工艺的难度。
5)本申请的碳化硅单晶作为衬底，具有良好的电学性能稳定性；同时，对碳化硅单晶衬底进行退火前后的面型测试，弯曲度和翘曲度的绝对值变化远远小于外延工艺所要求的退火前后5μm的控制线，表明碳化硅单晶衬底内部应力极小，能够保证衬底具有优异的面型质量，从而保证了后续外延过程中衬底质量的稳定性和一致性。
6)本申请的方法制备掺杂少量钒的半绝缘单晶/单晶衬底，通过碳化硅单晶中的浅能级杂质同时引入少量的钒掺杂替代晶体中的本征点缺陷，实现其半绝缘特性，该制备方法的技术成本和资金成本低。
附图说明
图1为退火前的碳化硅单晶衬底1#电阻率面扫描图。
图2为退火后的碳化硅单晶衬底1#电阻率面扫描图。
具体实施方式
下面结合实施例详述本申请，但本申请并不局限于这些实施例。
如无特别说明，本申请的实施例中的涉及的原料等均通过商业途径购买。
本申请的实施例中分析方法如下：
碳化硅单晶晶型测试采用Horiba公司的HR800型共聚焦拉曼光谱仪。
碳化硅单晶衬底的面型测试采用FRT公司的MicroProf@TTV200型全自动面型测试仪。
电阻率测试采用Semimap公司的COREMA‐WT型非接触式半绝缘电阻率测试仪。
元素含量测试采用Cameca公司的IMS 7f‐Auto型二次离子质谱仪器。
本申请的实施方式中，碳化硅单晶的制备流程包括下述步骤：
1)热场装置除杂：对石墨保温毡和石墨坩埚进行高温提纯；
2)混料：将钒元素均匀的掺杂于碳化硅粉料中，碳化硅粉中的钒浓度为1×10 16cm ‐3～1×10 17cm ‐3；
3)长晶：将步骤2)制得的掺杂钒的碳化硅粉放置在经步骤1)处理的石墨坩埚后，开始长晶，所述长晶步骤包括高温预处理阶段和长晶阶段，长晶结束后的钒的浓度为5×10 15cm ‐3～1×10 17cm ‐3；
4)退火：将经过步骤3)处理的碳化硅单晶进行退火处理，即制得所述的半绝缘碳化硅单晶。
实施例1 半绝缘碳化硅单晶的制备—热场装置除杂
热场装置包括石墨坩埚和石墨保温毡，将制备碳化硅单晶使用的石墨保温毡和石墨坩埚进行高温提纯。高温提纯步骤包括：将石墨坩埚内放置碳化硅粉料，粉料粒度控制在50‐500μm，数量控制在坩埚容积的50％‐80％。将石墨坩埚置于石墨保温毡并封装于碳化硅长晶炉后，在一定温度、压力下保持一段时间，进行热场装置除杂。热场1#、热场2#、热场3#、热场4#和热场5#的具体处理温度、压力和时间如表1所示，表1中的热场装置包括石墨坩埚和石墨保温毡。
表1
  温度/℃ 压力/mbar 时间/h
热场1# 2300 30 50
热场2# 1800 5 100
热场3# 1900 10 80
热场4# 2400 40 30
热场5# 2500 50 20
热场1#、热场2#、热场3#、热场4#和热场5#的处理过程中的石墨坩埚内的碳化硅粉料升华并形成高温气体，高温气体在逸散的过程中能 够浸润到石墨坩埚和石墨保温毡中并驱逐其吸附的氮等杂质元素，从而获得高纯度的石墨材料，从而除去制备的热场1#、热场2#、热场3#、热场4#和热场5#中的杂质，从而控制制备半绝缘碳化硅单晶的过程中引入杂质。
实施例2 半绝缘碳化硅单晶初品的制备—混料、长晶
将碳化硅粉料与钒元素进行掺杂，制得少量钒掺杂碳化硅粉料，每1kg反应碳化硅粉料中应放置0.01‐1g钒元素，反应后钒在碳化硅粉料中的浓度应在1×10 16cm ‐3～1×10 17cm ‐3量级，以实现后续长晶过程中的钒元素的含量范围。
将少量钒掺杂碳化硅粉分别放置于实施例1处理后的热场1#、热场2#、热场3#、热场4#和热场5#的石墨坩埚中，并封装入长晶炉膛，进行长晶步骤。以热场1#为例说明长晶步骤，长晶步骤的具体长晶条件如表2所示。
本实施例中的长晶步骤包括高温预处理阶段和长晶阶段，高温预处理阶段将炉膛内吸附的氮等杂质去除干净，由于本实施例的目的是通过引入少量的钒元素，因此相比于高纯半绝缘碳化硅单晶，本步骤的提纯过程可以较大的简化，只需将过量的氮元素去除即可，相比高纯半绝缘碳化硅单晶的制备过程可以降低技术成本和籽晶成本。
完成炉膛内的提纯预处理后，本申请的长晶阶段的参数控制使得石墨坩埚内的少量钒掺杂碳化硅粉料充分升华，升华后的气相及释放出的钒元素随着温度梯度传输至籽晶处并结晶。根据重掺杂半绝缘碳化硅单晶生长过程可知，钒元素会在晶体生长过程中占据晶体生长界面一部分晶格位置，从而实现钒的掺杂。由于少量钒掺杂碳化硅粉料中含有的钒元素已被限制在1×10 16cm ‐3～1×10 17cm ‐3的含量，经过气相传输过程后，由于传输过程的损耗、钒与碳化硅粉料的再结合，最终掺杂进入到碳化 硅单晶中的钒元素浓度在5×10 15cm ‐3～1×10 17cm ‐3之间。这些进入到碳化硅单晶的钒元素既能作为施主存在，也能作为受主存在，从而补偿掉碳化硅单晶中的浅能级杂质。
实施例3 半绝缘碳化硅单晶的制备—退火
将实施例2制备的碳化硅单晶初品继续进行退火处理，制备得到半绝缘碳化硅单晶。以热场1#进行碳化硅单晶长晶步骤制成的碳化硅单晶初品进行退火处理为例，说明制备碳化硅单晶的步骤。将实施例2的热场1#分别经过表2的长晶步骤制得的半绝缘碳化硅单晶初品进行退火处理分别制得碳化硅单晶1#、碳化硅单晶2#、碳化硅单晶3#、碳化硅单晶4#和碳化硅单晶5#，具体退火处理条件如表2所示。
碳化硅单晶生长结束后，将碳化硅单晶取出石墨坩埚。由于在晶体生长过程中生长界面处于较高的温度，生长界面处部分原子脱离晶格位置形成一定浓度的本征点缺陷。将碳化硅单晶放置于退火炉中，在1800‐2000℃温度下进行10‐50h的退火处理，可去除本征点缺陷。退火过程中，存在于碳化硅单晶中的本征点缺陷经过迁移而湮灭，本征点缺陷的浓度下降至室温下其本征浓度以下且不影响晶体电学性能稳定性的水平。至此，本申请制备的碳化硅单晶的电阻率由残余的浅能级杂质和少量的钒元素决定。由于浅能级杂质和少量的钒元素都占据晶格位置，其具有很高的热稳定性，这也就意味着本申请的碳化硅单晶可以获得具有高度稳定的电阻率。
表2
Figure PCTCN2018123707-appb-000001
Figure PCTCN2018123707-appb-000002
由于在晶体生长过程中生长界面处于较高的温度，生长界面处部分原子脱离晶格位置形成一定浓度的点缺陷。经过本申请的退火处理，存在于晶体中的点缺陷经过迁移而湮灭，从而浓度下降至不影响晶体电学性能的水平。至此，晶体的电阻率由残余的浅能级杂质和少量的钒元素决定。由于这些杂质都占据晶格位置，其具有很高的热稳定性，这也就意味着晶体可以获得具有高度稳定的电阻率。
实施例4 半绝缘碳化硅单晶的表征
测试实施例3制备的碳化硅单晶的电阻率、晶型、杂质含量、本征点缺陷和电阻率，测试结果表明制得的碳化硅单晶具有半绝缘性，且电阻率高，经过外延工艺退火(900‐1200℃/0.5‐10h)之后的电阻率均值变化值小于55％。以碳化硅单晶1#、碳化硅单晶2#、碳化硅单晶3#、碳化硅单晶4#和碳化硅单晶5#为例说明测试的电阻率、晶型、杂质含量、本征点缺陷和电阻率的结果，如表3所示，其中，浅能级杂质含量包括N、B和Al。
表3
Figure PCTCN2018123707-appb-000003
实施例5 半绝缘碳化硅单晶衬底的性能测试
分别将实施例3制备的碳化硅单晶进行切割、研磨和抛光制得4‐8英寸的半绝缘碳化硅单晶衬底，将制得的半绝缘碳化硅单晶衬底进行退火处理，同时测试碳化硅单晶衬底在退火前后的电阻率和面型，测试结果显示，实施例3制备的碳化硅单晶衬底具有良好的电学性能稳定性，且衬底的内部应力极小。
以碳化硅单晶1#制得的4英寸的碳化硅单晶衬底1#为例进行说明。碳化硅单晶衬底1#经过1200℃退火2h后。测试碳化硅单晶衬底1#退火前的电阻率面扫描图如图1所示，碳化硅单晶衬底1#退火后的电阻率面 扫描图如图2所示。测试电阻率均值由4.22×10 11Ω·cm变为3.17×10 11Ω·cm，电阻率衰减＜50％；同时，对碳化硅单晶衬底1#进行退火前后的面型测试，碳化硅单晶衬底1#退火前后的WARP值由8.35μm变为8.42μm，BOW值由9.62μm变为9.87μm，弯曲度和翘曲度的绝对值变化远远小于外延工艺所要求的退火前后5μm的控制线，表明碳化硅单晶衬底内部应力极小，能够保证衬底具有优异的面型质量，从而保证了后续外延过程中碳化硅单晶衬底质量的稳定性和一致性。
以上所述，仅为本申请的实施例而已，本申请的保护范围并不受这些具体实施例的限制，而是由本申请的权利要求书来确定。对于本领域技术人员来说，本申请可以有各种更改和变化。凡在本申请的技术思想和原理之内所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (25)

  1. 一种掺杂少量钒的高质量半绝缘碳化硅单晶，其特征在于，包含浅能级杂质、低浓度深能级掺杂剂和极少量的本征点缺陷；
    所述深能级掺杂剂与所述本征点缺陷共同补偿浅能级杂质，所述深能级掺杂剂的浓度小于掺杂半绝缘碳化硅单晶中深能级掺杂剂的浓度；
    所述本征点缺陷的浓度为室温下碳化硅单晶中的本征点缺陷原生浓度，所述本征点缺陷浓度不影响碳化硅单晶电学性能的稳定性。
  2. 根据权利要求1所述的半绝缘碳化硅单晶，其特征在于，所述浅能级杂质的浓度之和低于1×10 17cm ‐3，所述深能级掺杂剂的浓度低于1×10 17cm ‐3，所述本征点缺陷的浓度在室温下不高于1×10 15cm ‐3。
  3. 根据权利要求2所述的半绝缘碳化硅单晶，其特征在于，所述浅能级杂质的浓度之和不低于1×10 15cm ‐3，所述深能级掺杂剂的浓度不低于1×10 15cm ‐3，所述本征点缺陷的浓度室温下不高于1×10 14cm ‐3。
  4. 根据权利要求3所述的半绝缘碳化硅单晶，其特征在于，所述浅能级杂质的浓度之和不低于5×10 15cm ‐3。
  5. 根据权利要求4所述的半绝缘碳化硅单晶，其特征在于，所述浅能级杂质的浓度之和不低于1×10 16cm ‐3。
  6. 根据权利要求1所述的半绝缘碳化硅单晶，其特征在于，所述浅能级杂质包括元素周期表中的IIIA和VA主族元素中的一种或多种。
  7. 根据权利要求1所述的半绝缘碳化硅单晶，其特征在于，所述深能级掺杂剂选自元素周期表中的ⅤB族中的至少一种。
  8. 根据权利要求7所述的半绝缘碳化硅单晶，其特征在于，所述深能级掺杂剂为钒。
  9. 根据权利要求1所述的半绝缘碳化硅单晶，其特征在于，所述的 碳化硅单晶的晶型为4H‐SiC、6H‐SiC或3C‐SiC。
  10. 根据权利要求1所述的半绝缘碳化硅单晶，其特征在于，其由包括下述步骤的方法制备得到：
    1)热场装置除杂：对石墨保温结构和石墨坩埚进行高温提纯；
    2)混料：将深能级掺杂剂元素掺杂于碳化硅粉料中，碳化硅粉料中的深能级掺杂剂的浓度为1×10 16cm ‐3～1×10 17cm ‐3；
    3)长晶：将步骤2)制得的掺杂深能级掺杂剂元素的碳化硅粉放置在经步骤1)处理的石墨坩埚后，开始长晶，长晶结束后的深能级掺杂中心元素的浓度为5×10 15cm ‐3～1×10 17cm ‐3；
    4)退火：将经过步骤3)处理的碳化硅单晶进行退火处理。
  11. 一种半绝缘碳化硅单晶衬底，其特征在于，由权利要求1‐10中任一项所述的半绝缘碳化硅单晶制备得到。
  12. 根据权利要求11所述的半绝缘碳化硅单晶衬底，其特征在于，所述碳化硅单晶衬底经外延工艺退火处理前后的电阻率均值变化值小于55％；
    优选地，所述碳化硅单晶衬底经900‐1200℃温度保持0.5‐10h处理前后的电阻率均值变化值小于55％；
    更优选地，所述碳化硅单晶衬底经900‐1200℃温度保持0.5‐10h处理前后的电阻率均值变化值小于50％。
  13. 一种外延晶片和/或晶体管，其特征在于，包括权利要求11或12所述的半绝缘碳化硅单晶衬底。
  14. 一种掺杂少量钒的高质量半绝缘碳化硅单晶的制备方法，其特征在于，包括下述步骤：
    1)热场装置除杂；
    2)混料：将一定量的深能级掺杂剂掺杂于碳化硅粉料中；
    3)长晶：将步骤2)制得的掺杂深能级掺杂剂的碳化硅粉置于经步骤1)处理的热场装置后，开始长晶，长晶结束后的深能级掺杂中心元素的浓度为5×10 15cm ‐3～1×10 17cm ‐3；
    4)退火：将经过步骤3)处理的碳化硅单晶初品进行退火处理，即制得所述的半绝缘碳化硅单晶。
  15. 根据权利要求14所述的制备方法，其特征在于，所述半绝缘碳化硅单晶包含浅能级杂质、深能级掺杂剂和少量本征点缺陷，所述深能级掺杂剂与所述本征点缺陷共同补偿浅能级杂质，所述深能级掺杂剂的浓度小于掺杂半绝缘碳化硅单晶中深能级掺杂剂的浓度，所述本征点缺陷的浓度室温下不高于1×10 15cm ‐3，不会影响碳化硅晶体电学性能稳定性。
  16. 根据权利要求15所述的制备方法，其特征在于，所述浅能级杂质的浓度之和低于1×10 17cm ‐3，所述深能级掺杂剂的浓度低于1×10 17cm ‐3，所述本征点缺陷的浓度在室温下不高于1×10 14cm ‐3；
    优选地，所述浅能级杂质包括元素周期表中的IIIA和VA主族元素中的一种或多种。
  17. 根据权利要求15所述的制备方法，其特征在于，所述深能级掺杂剂选自元素周期表中的ⅤB族元素中的至少一种；优选地，所述深能级掺杂剂为钒元素。
  18. 根据权利要求14所述的制备方法，其特征在于，所述热场装置包括石墨保温结构和石墨坩埚。
  19. 根据权利要求14所述的制备方法，其特征在于，所述步骤1)的热场装置除杂包括：将碳化硅粉料放置在石墨坩埚后，在温度1800‐2500℃和压力5‐50mbar下保持20‐100h。
  20. 根据权利要求14所述的制备方法，其特征在于，所述步骤2) 的混料中的深能级掺杂剂的浓度为1×10 16cm ‐3～1×10 17cm ‐3。
  21. 根据权利要求14所述的制备方法，其特征在于，所述步骤3)中的长晶步骤包括：高温预处理阶段和长晶阶段；
    所述高温预处理阶段的包括：在温度1800℃‐2000℃和压力800‐900mbar下保持时间30‐50h；
    所述长晶阶段的条件为：以10‐30℃/min的速率提高至2200℃以上的温度，同时将压力降至5‐50mbar。
  22. 根据权利要求14所述的制备方法，其特征在于，所述步骤4)的退火处理条件为：将步骤3)制得的碳化硅单晶初品置于退火炉中，在1800‐2200℃温度下保持10‐50h。
  23. 一种掺杂少量钒的高质量半绝缘碳化硅单晶，其特征在于，由权利要求14‐22中任一项所述的方法制备得到。
  24. 一种掺杂少量钒的高质量半绝缘碳化硅单晶衬底的制备方法，其特征在于，将权利要求23所述的掺杂少量钒的高质量半绝缘碳化硅单晶进行切割、研磨和抛光，即制得所述的半绝缘碳化硅单晶衬底。
  25. 权利要求23所述的半绝缘碳化硅单晶和/或由权利要求10的制备方法制得的半绝缘碳化硅单晶衬底在制备外延晶片和/或晶体管中应用。
PCT/CN2018/123707 2018-10-16 2018-12-26 掺杂少量钒的半绝缘碳化硅单晶、衬底、制备方法 WO2020077846A1 (zh)

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