WO2011143848A1 - Soi横向mosfet器件 - Google Patents

Soi横向mosfet器件 Download PDF

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Publication number
WO2011143848A1
WO2011143848A1 PCT/CN2010/075849 CN2010075849W WO2011143848A1 WO 2011143848 A1 WO2011143848 A1 WO 2011143848A1 CN 2010075849 W CN2010075849 W CN 2010075849W WO 2011143848 A1 WO2011143848 A1 WO 2011143848A1
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Prior art keywords
dielectric
gate
trench
lateral mosfet
region
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PCT/CN2010/075849
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English (en)
French (fr)
Inventor
罗小蓉
乌德雷亚·弗罗林
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电子科技大学
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Priority to US13/131,779 priority Critical patent/US8716794B2/en
Publication of WO2011143848A1 publication Critical patent/WO2011143848A1/zh

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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
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    • H01L29/42312—Gate electrodes for field effect devices
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    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7809—Vertical DMOS transistors, i.e. VDMOS transistors having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7812—Vertical DMOS transistors, i.e. VDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-VDMOS transistors
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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    • H01L29/42312—Gate electrodes for field effect devices
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    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Definitions

  • the present invention relates to a semiconductor power device and a power integrated circuit, and more particularly to an SOI (Semiconductor On Insulator) lateral MOSFET (Metal-Oxide-Semiconductor Field- for a power integrated circuit or a radio frequency power integrated circuit) Effect-Transistor, metal-oxide-semiconductor field effect transistor) device, especially related to a high withstand voltage, low power lateral MOSFET device.
  • SOI semiconductor On Insulator
  • MOSFET Metal-Oxide-Semiconductor Field- for a power integrated circuit or a radio frequency power integrated circuit
  • the SOI introduces a dielectric buried layer between a top-level semiconductor (referred to as an active layer) and a substrate layer (which may be a semiconductor or an insulating medium), and a semiconductor device or circuit is formed in the active layer.
  • the isolation trench 30 is usually isolated between the high voltage device and the low voltage circuit in the integrated circuit, and the active layer 3 and the substrate layer 1 are separated by the dielectric layer 2 (as shown in Fig. 1). Therefore, compared with bulk silicon (semiconductor) technology, S0I technology has the advantages of small parasitic effect, small leakage current, high integration, strong radiation resistance and self-locking effect of thyristor, high speed, high temperature and low power consumption. And the field of anti-radiation and other fields have received extensive attention and application.
  • S0I power integrated circuit technology is to achieve high withstand voltage, low power consumption and effective isolation between high voltage unit and low voltage unit.
  • S0I lateral devices such as LDM0SFET (Lateral Double-diffused Metal-Oxide-Semiconductor Field-Effect-Transistor), become SOI power integrated circuits due to their ease of integration and relatively low on-resistance
  • LDM0SFET Longeral Double-diffused Metal-Oxide-Semiconductor Field-Effect-Transistor
  • the core components are popular in applications such as plasma displays, motor drives, automotive electronics, portable power management products, and personal computers.
  • VDMOSFET Very Double-diffused Metal-Oxide-Semiconductor Field-Effect-Transistor VDMOS, vertical double-diffused metal oxide semiconductor field effect transistor
  • the drift region length monotonically increases with increasing device breakdown voltage. This not only increases the chip area of the device (or circuit), increases the cost, but also is disadvantageous for miniaturization. More seriously, the on-resistance of the device increases with the length of the drift region (or the withstand voltage of the device).
  • the relationship between the on-resistance and the withstand voltage of the device can be expressed as: Ron BV 2 5 , where BV is the device. Withstand voltage, Ron is the on-resistance). The increase in on-resistance leads to a sharp increase in power consumption and a reduction in the switching speed of the device.
  • a MOSFET having a trench gate structure can increase the packing density, thereby increasing the channel density and current density.
  • the length of the channel of the trench gate MOSFET is not limited by the photolithography process, and the channel can be made shorter, thereby reducing the on-resistance. Both of the above points increase the MOSFET current withstand capability of the trench gate structure.
  • the trench gate MOSFET can avoid the JFET (Junction Field-Effect-Transistor) Effect transistor) Effect and latch-up effect.
  • the oxide trench 31 lowers the high electric field of the silicon surface below the G gate end of the gate electrode, avoids premature breakdown here, and reduces the surface electric field peak at the edge of the drain region, thereby reducing the on-resistance.
  • Improve the device withstand voltage The device has a maximum withstand voltage of 356V in the drift region of 16 ⁇ m, and the dielectric buried layer 2 and active layer 3 are 3 ⁇ m and 8 ⁇ m, respectively.
  • the LDMOSFET of this type has a specific on-resistance of about 9 ⁇ ⁇ * ⁇ 2 at 250V. It can be seen that the effect of the structure to reduce the length of the drift region and the specific on-resistance is very limited.
  • the SOI lateral MOSFET device includes a bottom-up substrate layer, a dielectric buried layer and an active layer, and a trench gate is formed in the active layer.
  • the gate is composed of a gate dielectric and a conductive material surrounded by the same, and the conductive material is terminated by a trench gate electrode; wherein the longitudinal length of the trench gate passes through the active layer until the dielectric buried layer;
  • the surface of the source layer has a body region and a drain region, and there is a space between the body region and the drain region, and the drain terminal is a drain electrode; the surface of the body region is sequentially a source region a, a body contact region, and a source a common source terminal of the source region a, the source region b and the body contact region is a source electrode;
  • the trench gate is in contact with the body region and the source region a; and a dielectric trench is formed between the source region b and the drain region.
  • the dielectric groove is in contact with the source region b and the body region, the dielectric coefficient of the medium in the dielectric groove is smaller than the dielectric constant of the active layer material, and the longitudinal depth of the dielectric groove is greater than the longitudinal depth of the body region and less than the thickness of the active layer
  • the dielectric groove is buried by a conductive material
  • the buried gate is close to the source region b and is surrounded by a medium in the dielectric trench, the buried gate depth is smaller than the dielectric trench depth, the buried gate depth is the body region depth, and the buried gate terminal is a buried gate electrode.
  • the buried gate electrode is electrically connected to the trench gate electrode, and the common lead terminal is a gate electrode.
  • the S0I lateral MOSFET device has a symmetrical structure, and the drain region is located at the center of the device, and the central drain region is outwardly a dielectric trench, a source region b, a body contact region, a source region a, and a trench gate, and the trench gate is located at the periphery of the device. Easily isolate devices or circuits with trench gate media.
  • the S0I lateral MOSFET device has a plane symmetrical structure, and a plane that evenly divides the drain region and does not pass through the dielectric trench and the gate trench is a symmetrical plane thereof.
  • the S0I lateral MOSFET device is an axisymmetric structure, and the longitudinal axis of the center of the overdrain region is its axis of symmetry.
  • the cross-sectional shape of the drain region may be a circular or a regular polygon other than an equilateral triangle
  • the cross-sectional shape of the matching medium groove, source region b, body contact region, source region a, and trench gate is It is a circular orthodontic band or a regular polygonal band other than the equilateral toroidal band.
  • the source region a, the source region b, the body contact region, and the trench gate are circular ring-shaped device structures, having an optimal symmetry type and attenuating the curvature effect Therefore, the withstand voltage is the highest and the chip area is saved.
  • the use of other regular polygonal structures is also a common choice.
  • the cross-sectional shape of the drain region of the same device matches the cross-sectional shape of the periphery such as the gate trench and the dielectric trench, such as a drain region having a regular hexagon, a dielectric trench, a source region a, a source region b, a body contact region, and a trench gate.
  • a regular hexagonal belt is also a regular hexagonal belt.
  • the gate dielectric is longitudinally formed into a thin and thick structure. This solution can further improve the withstand voltage of the device.
  • the media slots have a total of n strips, n 2 , with a spacing between each of the media slots; the buried gate is located in a dielectric slot in contact with the body region. This scheme appropriately increases the number of dielectric slots, which is beneficial to increase the withstand voltage of the device.
  • the active layer materials between the dielectric slots have the same or different conductivity types.
  • the program is easy to choose according to the needs of the production Process, manufacturing steps, thereby increasing process flexibility.
  • the longitudinal depths, lateral widths and spacings of the media grooves are equal or unequal.
  • the depth of the intermediate media grooves is greater than the depth of the media grooves on both sides. This structure is advantageous for increasing the withstand voltage.
  • the drain region is in contact with or not in contact with the media slot.
  • the leakage region is not in contact with the dielectric groove, and the withstand voltage is increased.
  • the contact between the drain region and the dielectric groove is less than that of the structure, and the on-resistance is reduced.
  • the S0I lateral MOSFET device is used for active devices of integrated circuits.
  • the integrated circuit is a power integrated circuit or a radio frequency power integrated circuit.
  • the active layer material includes, but is not limited to, Si, SiC, SiGe, GaAs, or GaN.
  • the materials listed in the scheme are mature and easy to obtain.
  • the active layer material is Si
  • the medium in the dielectric groove is Si0 2
  • SiO media is commonly used in the industry, and the process is mature. Since the relative dielectric constant of ⁇ 10 2 is lower than the relative dielectric constant of 1.19, the electric field of the medium in the dielectric tank is enhanced to increase the withstand voltage of the device; the relative dielectric constant is lower than Si0 2 and the critical strike is selected. A medium with an electric field higher than three times the critical breakdown electric field of Si is more favorable for increasing the withstand voltage of the device.
  • the active layer material is Si; the gate dielectric is Si0 2 , or the dielectric constant is higher than the Si0 medium: including but not limited to Si, A1 2 0 3 , A1N or Hf0 2 .
  • a high dielectric constant gate dielectric can enhance the gate voltage control capability of the gate charge and increase the transconductance; or in the same gate structure MIS (Metal-Insulator-Semiconductor, gate-gate dielectric-gate dielectric
  • MIS Metal-Insulator-Semiconductor, gate-gate dielectric-gate dielectric
  • the semiconductor forms the MIS structure. Under the capacitor, the gate dielectric can be made thicker, the tunnel current can be reduced, the tunneling effect can be avoided, and the stability and reliability of the device or chip can be enhanced.
  • the active layer material is Si
  • the dielectric buried material is SiO 2 ; or a medium having a dielectric constant lower than SiO 2 and a critical breakdown electric field higher than 3 times the critical breakdown electric field of Si: including but not limited to SiOF, CD0 or SiC0F.
  • the medium buried layer uses a medium with a low dielectric constant, which can enhance the electric field of the buried layer of the medium, which is beneficial to the improvement of the withstand voltage of the device.
  • the beneficial effects of the present invention are as follows: 1 In the blocking state, in the lateral direction, the medium in the dielectric groove between the drain region and the source region b participates in withstand voltage, since the dielectric coefficient of the medium (such as Si0 2 ) is smaller than that of the semiconductor active.
  • the dielectric constant of the layer (such as Si) so the electric field in the dielectric trench is much larger than the electric field in the active layer; in the longitudinal direction, the trench gate structure and the dielectric trench enhance the multi-dimensional depletion in the active layer. Both of them increase the withstand voltage of the device, so the device withstand voltage is greatly improved for the same device lateral dimension; or for the same withstand voltage, the drift region and device length are greatly reduced, thereby reducing on-resistance and power consumption.
  • the dielectric slot folds the drift region in the longitudinal direction, reducing the lateral dimension of the device, thereby reducing the specific on-resistance and chip cost, and increasing the switching speed.
  • 3 in the on state The slot extending longitudinally to the buried layer of the dielectric extends the longitudinal effective conduction region of the drift region, greatly reducing on-resistance and power consumption. At the same time, the buried gate structure further increases the channel density and current density of the device, reducing power consumption.
  • an advantage of the present invention is to provide a SOI lateral MOSFET that is high withstand voltage, high speed, low power consumption, low cost, miniaturization, and easy to integrate with a power integrated circuit.
  • FIG. 1 is a schematic cross-sectional view of a conventional S0I technology high voltage integrated circuit.
  • Figure 2 is a schematic diagram showing the structure of a SOI RESURF LDM0SFET device having a trench.
  • Figure 3 is a schematic diagram of the structure of the TLPM/D MOSFET.
  • Figure 4 is a schematic diagram of the structure of the TLPM/S MOSFET.
  • FIG. 5 is a schematic diagram of a cell structure (xz plane) of a S0I lateral MOSFET device having a plane symmetry structure;
  • FIG. 6 is a schematic diagram of a cell structure (xz plane) of a S0I lateral MOSFET device having an axisymmetric structure;
  • AA ' is along the X direction; the longitudinal direction is the y direction; the device has the y-axis of the center of the drain electrode D as the axis of symmetry.
  • Figure 7 is a cross-sectional view of the N-channel S0I lateral MOSFET cell structure (longitudinal section along the line AA' in Figure 5 or Figure 6, i.e., xy plan, the same below).
  • FIG. 8 is a cross-sectional view showing a cell structure of an N-channel S0I lateral MOSFET device in which a drain region is not in contact with a dielectric trench; and FIG. 9 is a cross-sectional view showing a cell structure of a thin and thick N-channel S0I lateral MOSFET device on a gate dielectric;
  • Figure 10a is a cross-sectional view (half cell) of an N-channel SOI lateral MOSFET device with two dielectric slots
  • Figure 10b is a schematic diagram of an N-channel SOI lateral MOSFET device with different conductivity types between dielectric trenches (half cell) ) ;
  • Figure 11a shows the structure of an N-channel S0I lateral MOSFET device with three dielectric trenches with different media trench depths (half cell);
  • Figure l ib has three dielectric slots, and the active layer material between the dielectric slots has different conductivity types of N-channel S0I transverse MOSFET structure (half cell);
  • Figure 12 is a cross-sectional view showing the cell structure of a P-channel S0I lateral MOSFET device
  • Figure 13 is a schematic diagram showing the distribution of two-dimensional equipotential lines (half a cell).
  • Figure 14 is a schematic diagram of a two-dimensional current line distribution comparison (half a cell);
  • Figure 15 is a diagram showing the isolation of a high voltage SOI lateral MOSFET device from a low voltage circuit for use in an integrated circuit of the present invention.
  • the technical solution of the present invention makes full use of the trench gate, the dielectric trench and the buried gate, and comprehensively improves and improves the electrical performance of the S0I lateral MOSFET device.
  • the S0I lateral MOSFET device of the present invention is also referred to as a device.
  • FIG. 5 this is a schematic representation of a S0I lateral MOSFET device cell layout layout with a plane-symmetric structure.
  • the figure is an xz plan view, where AA 'is along the X direction, BB ' is along the z direction, and the longitudinal direction is the y direction.
  • the symmetry plane of the device is the yz plane over BB '.
  • the figure includes a layout of the dielectric trench 61 and the trench gate 8, and a layout of the metal electrodes: a trench gate electrode 21, a buried gate electrode 22, a gate electrode G, a source electrode S, and a drain electrode 0.
  • the active source region, the drain region, the trench gate 8, the dielectric trench 61, and the buried gate are all strip-shaped.
  • the drain electrode D is located at the center of the device, and the drain electrode D is a dielectric trench 61 on both sides.
  • the outside of the dielectric slot 61 is the source electrode S, and the slot gate 8 is located at the outermost side of the device to achieve isolation of the high and low voltage units in the integrated circuit.
  • the conductive material in the dielectric trench 61 forms a buried gate which is led out by the buried gate electrode 22.
  • the conductive material in the trench gate 8 is led out by the trench gate electrode 21, and their common terminal is the gate electrode G of the device.
  • the gate electrode G and the source electrode S adopt a conventional interdigital structure.
  • Figure 6 shows a SOI lateral MOSFET device cell layout layout with an axisymmetric structure, i.e., xz plan view, where AA 'is along the X direction.
  • the figure depicts a circular symmetry structure using a circular figure as an example.
  • the drain region D is located at the center of the device and is separated from the source region b by the dielectric trench 61.
  • the device has the y-axis of the center of the drain electrode D as the axis of symmetry.
  • the buried gate in the dielectric trench 61 is led out by the buried gate electrode 22, and is electrically connected to the leading end trench gate electrode 21 of the conductive material in the trench gate 8 at the outermost periphery of the device to constitute the gate electrode G of the device.
  • the trench gate 8 is located on the outermost side of the device for high and low voltage unit isolation in the integrated circuit.
  • Figure 7 shows a cross-sectional view of the N-channel SOI lateral MOSFET device cell.
  • the figure is an xy plan view. It comprises a longitudinal (y-axis) bottom-up substrate layer 1, a dielectric buried layer 2 and an active layer 3.
  • a trench gate 8 is formed in the active layer 3.
  • the trench gate 8 is composed of a gate dielectric 4 and a conductive material 5 surrounded by the conductive material 5, and the leading end of the conductive material 5 is a trench gate electrode.
  • the slot 8 is longitudinally long The degree passes through the active layer 3 up to the dielectric buried layer 2.
  • the surface of the active layer on one side of the trench gate has a body region 9 and a drain region, and the drain terminal is a drain electrode D.
  • the surface of the body region 9 is sequentially the source region a (labeled as 11a in the figure), the body contact region 10, and the source region b (identified as l ib in the figure).
  • the common terminal of the source region a, the source region b and the body contact region 10 is the source electrode S.
  • the trench gate 8 is in contact with the body region 9 and the source region a, a dielectric trench 61 is formed between the source region b and the drain region, and the dielectric trench 61 is filled with the dielectric 6.
  • the dielectric constant of the dielectric 6 is smaller than the dielectric constant of the active layer 3 material. .
  • the longitudinal depth of the dielectric groove 61 is greater than the longitudinal depth of the body region 9 and less than the thickness of the active layer 3.
  • a buried gate 7 is formed in the dielectric trench 61 by a conductive material, and the buried gate 7 is close to the source region b and surrounded by the medium 6 in the dielectric trench.
  • the depth of the buried gate 7 is smaller than the depth of the dielectric trench, and the depth of the buried gate 7 is deep.
  • the terminal of the buried gate 7 is a buried gate electrode, and the buried gate electrode is electrically connected to the trench gate electrode, and the common terminal is the gate electrode 6 of the device.
  • the introduction of the trench gate structure increases the effective longitudinal conductive area of the device, thereby greatly reducing the specific on-resistance.
  • the double gate structure of the trench gate and the buried gate in turn increases the channel density and reduces the on-resistance with the same device size.
  • the introduction of the dielectric trench not only increases the withstand voltage of the device, but also reduces the lateral size of the device or chip, thereby reducing on-resistance and power consumption, and thus saving cost.
  • Figure 7 shows an N-channel S0I lateral MOSFET device with a single dielectric slot 61. This structurally shaped device process is easier to implement and the device has the best symmetry.
  • the drain region n + of the device of this example is not in contact with the dielectric trench 61, and the rest of the structure is the same as that of the first embodiment, as shown in FIG. Compared with the structure shown in Fig. 7, the withstand voltage of the device in this example is somewhat improved, but the on-resistance is slightly increased.
  • the gate dielectric 4 is formed into a thin and thick structure in the longitudinal direction, as shown in FIG.
  • the structure of the trench gate 8 is advantageous for increasing the withstand voltage of the device.
  • the device in this example has two dielectric slots 61, which are also N-channel S0I lateral MOSFET devices.
  • the media grooves 61 have the same longitudinal depth.
  • the active layer material 60 between the dielectric trenches of FIG. 10a and the active layer 3 have the same conductivity type.
  • the dielectric trench 61 and the filling dielectric 6 can be used, and then implanted and diffused to form the body region 9, the source region and the drain region. And body contact zone 10.
  • the active layer material 60 and the active layer 3 have different conductivity types between the dielectric trenches.
  • the body region 9 may be epitaxially formed on the active layer 3, and then the dielectric trench 61 and the filling medium 6 may be formed.
  • Figures 10a, b show only half of the cells of the device.
  • the longitudinal depths of the media slots 61 are not equal.
  • the depth of the media slots 61 in the middle is greater than the depth of the media slots 61 on both sides, as shown in FIGS.
  • the media groove 61 in the middle is deeper than the two sides.
  • the depth of the groove 61 is such a structure that it is advantageous to increase the withstand voltage.
  • the material conductivity type between the dielectric grooves 61 in Fig. 11a is the same as that of the active layer 3, and the material conductivity type between the dielectric grooves 61 in Fig. 1b is different from that of the active layer 3.
  • the device of this example is a P-channel S0I lateral MOSFET device with a single dielectric slot 61.
  • the material conductivity type of the active layer 3, the source region a, the source region b, the drain region, the body region 9 and the body contact region 10 of this example is exactly the same as the N-channel SOI lateral MOSFET device (shown in Figures 7 and 8). anti. See Example 1 for other structures.
  • Embodiment 2 The structure of Embodiment 5 is applicable to a P-channel S0I lateral MOSFET device.
  • the P-channel SOI lateral MOSFET device active layer 3 source region a, source region b, drain region, body region 9 and body contact region 10 material conductivity type and N-channel SOI lateral MOSFET device (shown in Figure 7-11) Just right.
  • the S0I lateral MOSFET device of the present invention is most suitable for active devices of integrated circuits, particularly for power integrated circuits and RF power integrated circuits.
  • the device described in the above several embodiments of the present invention can be fabricated using Si, SiC, SiGe, GaAs or GaN as the material of the source layer 3, and these materials are mature in technology and convenient in drawing. Can meet different device or circuit performance requirements.
  • the active layer material is Si
  • the recommended conductive material 5 and the buried gate conductive material are polysilicon.
  • the medium 6 in the dielectric tank is Si0 2 , or a medium having a dielectric constant lower than Si0 2 and a critical breakdown electric field higher than three times the critical breakdown electric field of Si, such as SiOF, CD0 or SiCOF, may be used. Since the relative dielectric constant of SiO 2 is lower than the relative dielectric constant of 1.9, the electric field of the medium in the dielectric tank is enhanced, and the withstand voltage of the device is improved. The relative dielectric constant is lower than Si0 2 and the critical breakdown electric field is selected. A medium that is three times higher than the critical breakdown electric field of Si is more advantageous for increasing the withstand voltage.
  • the low dielectric constant of the dielectric 6 in the dielectric trench 61 also helps to reduce the gate-drain capacitance of the device and improve the switching speed of the device.
  • Si0 2 may be used, or a dielectric coefficient of more than the critical Si0 2 and the dielectric breakdown field comparable to or higher Si0 2: such as Si, A1N, A1 2 0 3 or Hf0 2 and the like.
  • the gate dielectric uses a higher dielectric constant, which enhances the gate voltage control of the gate charge and increases the transconductance.
  • MIS Metal-Insulator-Semiconductor, gate-gate dielectric-gate dielectric semiconductor formation MIS structure
  • the gate dielectric can be made thicker, reduce tunneling current, avoid tunneling effect , enhance the stability and reliability of the device or chip.
  • Si0 2 is commonly used in the industry, or uses a dielectric constant lower than Si0 2 and critical breakdown.
  • the dielectric of the dielectric buried layer 2 can be enhanced by using a medium having a low dielectric constant, which is advantageous for improving the withstand voltage of the device.
  • the technical solution of the present invention has almost no requirement for the substrate material, and may be an n-type or p-type semiconductor material, or even an insulating dielectric material, or the same dielectric material as the dielectric buried layer.
  • Figure 13 is a schematic diagram showing the distribution of two-dimensional equipotential lines (half of cells).
  • a represents a conventional planar gate LDMMOSFET (without trench gate, buried gate, and dielectric trench);
  • b represents a lateral MOSFET having a trench gate but no dielectric trench;
  • c represents a SOI lateral MOSFET having a trench gate, a buried gate, and a dielectric trench disclosed herein Device.
  • the voltage difference between two adjacent equipotential lines is 10V
  • the breakdown voltages of the three structures are 254V, 130V, and 109V, respectively. Comparing Fig.
  • the introduction of the trench gate structure increases the withstand voltage from 109V to 130V of the conventional SOI LDM0S. Comparing Fig. 13 (b) and (c), the dielectric tank increases the withstand voltage of 130V to 254V, nearly doubled.
  • Figure 14 is a two-dimensional current line distribution (the current intensity difference between two adjacent current lines is 1 X 10 - 6 ⁇ / ⁇ ⁇ ).
  • a represents a conventional planar gate LDMMOSFET (without trench gate, buried gate, and dielectric trench);
  • b represents a lateral MOSFET having a trench gate but no dielectric trench;
  • c represents a SOI lateral MOSFET having a trench gate, a buried gate, and a dielectric trench disclosed herein Device.
  • current flows only through the thin layer of the device surface, and the effective conductive area is small.
  • the technology of the present invention greatly improves the device withstand voltage and reduces the lateral dimension of the device, and plays a major role in the dielectric slot 61.
  • the trench gate 8 increases the effective longitudinal conductive area of the device and greatly reduces the ratio
  • the two structures of the trench gate 8 buried gate 7 increase the channel density and current density, significantly reduce the specific on-resistance, thereby reducing power consumption; further, the dielectric trench reduces the gate-drain capacitance and improves the device. Frequency and output power.
  • Figure 15 is a diagram showing the isolation of a high voltage device from a voltage circuit in an integrated circuit of the present invention. It can be seen that, by adopting the technical solution of the present invention, a special isolation trench (such as 30 in FIG. 1) is not required between the high voltage device and the low voltage circuit, and the trench gate of the present invention has perfect isolation effect, and the technology is reduced. The manufacturing cost and process difficulty of the integrated circuit.

Description

SOI横向 MOSFET器件 技术领域
本发明涉及半导体功率器件和功率集成电路， 确切地说涉及一种用于功率集成电路 或射频功率集成电路的 SOI ( Semiconductor On Insulator, 绝缘衬底上半导体） 横向 MOSFET (Metal-Oxide-Semiconductor Field-Effect-Transistor, 金属-氧化物-半导体 场效应晶体管） 器件， 特别涉及一种高耐压、 低功耗的横向 MOSFET器件。
背景技术
S0I是在顶层半导体（称为有源层）和衬底层（可以为半导体或绝缘介质）之间引入 介质埋层， 将半导体器件或电路制作在有源层中。 集成电路中高压器件、 低压电路之间 通常采用隔离槽 30进行隔离，有源层 3与衬底层 1之间则由介质层 2进行隔离 （如图 1 所示）。 因此， 与体硅 （半导体） 技术相比， S0I技术具有寄生效应小， 泄漏电流小， 集 成度高、 抗辐射能力强以及无可控硅自锁效应等优点， 在高速、 高温、 低功耗以及抗辐 射等领域得到广泛关注和应用。
S0I功率集成电路技术的关键是实现高耐压、低功耗以及高压单元和低压单元之间的 有 效 隔 离 。 S0I 横 向 器 件 ， 如 LDM0SFET ( Lateral Double-diffused Metal-Oxide-Semiconductor Field-Effect-Transistor, 横向双扩散金属氧化物场效应 晶体管） 因其便于集成和相对较低的导通电阻而成为 S0I功率集成电路的核心器件， 在 等离子显示屏、 马达驱动、 汽车电子、 便携式电源管理产品以及个人电脑等应用中倍受 青睐。 同时， 较之于 VDMOSFET (Vertical Double-diffused Metal-Oxide-Semiconductor Field-Effect- Transistor VDMOS, 垂直双扩散金属氧化物半导体场效应晶体管）， 横向 MOSFET更高的开关速度， 使其在射频领域应用广泛。
对于常规 LDM0SFET器件而言， 漂移区长度随器件击穿电压的升高单调增加。这不仅 使器件 （或电路） 的芯片面积增加、 成本增大， 而且不利于小型化。 更为严重的是， 器 件的导通电阻随漂移区长度 （或器件耐压） 的增加而增大 （导通电阻与器件耐压的关系 式可以表达为： Ron BV 2 5, 其中 BV为器件耐压， Ron为导通电阻）， 导通电阻的增加导 致功耗急剧增加， 并且器件开关速度也随之降低。
与平面栅结构的 MOSFET相比， 具有槽栅结构的 MOSFET, —方面可以增加封装密度， 从而提高沟道密度和电流密度。另一方面槽栅 MOSFET的沟道的长度不受光刻工艺的限制， 沟道可以做得较短， 从而降低导通电阻。 以上两点均增加槽栅结构的 MOSFET电流承受能 力。 再者， 槽栅 MOSFET能够避免 JFET (Junction Field-Effect-Transistor, 结型场 效应晶体管） 效应和闭锁效应。
为了克服上面提到的常规 LDM0SFET存在的问题， 业内研究者利用槽栅 MOSFET的优 点， 提出了基于槽技术的 SOI LDM0SFET器件结构。 文献 （Won-So Son, Young-Ho Sohn, Sie-Young Choi , [Effects of a trench under the gate in high voltage RE SURF LDMOSFET for SOI power integrated circuits】 Sol id-State Electronics 48 (2004) 1629 - 1635 ) 提出具有槽的 RESURF LDMOSFET, 其器件结构如图 2所示。 该器件将氧化物槽 31引入栅 电极 G末端附近直至漏区之间的漂移区。 当掺杂浓度过高时， 氧化物槽 31降低栅电极 G 末端之下硅表面的高电场， 避免此处提前击穿， 并降低漏区边缘的表面电场峰值， 从而 在降低导通电阻的基础上提高器件耐压。该器件在漂移区长度为 16 μ πι，介质埋层 2和有 源层 3厚度分别为 3 μ m和 8 μ m时的最高耐压可达 356V。 该文献报道其实验结果耐压为 352V, 比导通电阻约为 18. 8 ΙΉ Ω · cm 2。 该类结构的 LDMOSFET在 250V时， 比导通电阻约 为 9 πι Ω * ^2。 可见， 该结构降低漂移区长度和比导通电阻的效果非常有限。
文献 Naoto Fuj ishima and C. Andre T. Salama, 【A trench lateral power MOSFET using self-al igned trench bottom contact holes】 IEDM 1997， 359-362中将漏电极 D和栅电极 G设计在同一阶梯型状的槽中， 且槽的下半部分（靠近漏区）侧壁有厚氧化物 层 32。 文中将其称为槽底部具有漏接触的槽型横向功率 MOSFET ( Trench Lateral Power MOSFET with Trench Bottom Drain Contact ) ， 称为 TLPM/D MOSFET, 器件结构如图 3 所示。 美国专利（US 7005352B2, 2006. 2. 28, [ trench-type MOSFET having a reduced device pitch and on-resistance ])将源电极 S和栅电极 G设计在同一槽中，称为 TLPM/S MOSFET, 结构如图 4所示。 以上两种结构均是采用槽型结构以降低器件横向尺寸 （或芯 片面积）， 进而降低器件的导通电阻并保持较高耐压； 前者更适于耐压高于 80V的槽型低 阻 M0SFET, 后者更适于耐压低于 80V的槽型低阻小尺寸 M0SFET, 且工艺较前者更简单。 但对于耐压超过 100V的 TLPM/D MOSFET, 一方面槽下部分的厚氧化物层 32厚度增加， 削 弱了缩小器件横向尺寸的优势； 另一方面， 槽的深度随耐压增加， 将漏电极和栅电极制 作在同一个深而窄的槽内工艺难度增大。 以上两种结构均需将漏电极与栅电极或源电极 与栅电极制作在同一槽中， 其工艺难度随耐压的提高 （槽的深度增加） 而增大， 而且该 结构减小器件横向尺寸的效果随耐压的升高而削弱。 美国专利 （US 2007/0298562A1 , 2007. 12. 27, 【method of manufacturing a semiconductor integrated circuit device】) 将上面提到的 TLPM/S器件用于集成电路， 但集成电路中的各个器件之间须采用 PN结隔 离和浅槽隔离， 且将高压 MOSFET的源电极和栅电极设计在同一槽中， 工艺较复杂。 发明内容 本发明所要解决的技术问题， 就是提供一种 S0I横向 M0SFET器件， 利用槽栅结构配 合介质槽及其中的埋栅电极， 提高 LDM0SFET耐压， 降低比导通电阻和功耗， 降低器件横 向尺寸和芯片面积。
本发明解决所述技术问题， 采用的技术方案是， S0I横向 M0SFET器件， 包括纵向自 下而上的衬底层、 介质埋层和有源层， 所述有源层中形成槽栅， 所述槽栅由栅介质及其 包围的导电材料构成， 所述导电材料引出端为槽栅电极； 其特征在于， 所述槽栅纵向长 度穿过有源层直到介质埋层； 在槽栅一侧的有源层表面具有体区和漏区， 所述体区和漏 区之间有间距， 所述漏区引出端为漏电极； 所述体区的表面顺次是源区 a， 体接触区， 源 区 b; 所述源区 a、 源区 b和体接触区的共同引出端为源电极； 所述槽栅与体区和源区 a 接触； 源区 b和漏区之间形成介质槽， 所述介质槽与源区 b和体区接触， 所述介质槽中 介质的介电系数小于有源层材料的介电系数， 所述介质槽纵向深度大于体区纵向深度且 小于有源层的厚度； 所述介质槽中由导电材料形成埋栅， 所述埋栅靠近源区 b， 且被介质 槽中介质包围， 所述埋栅深度小于介质槽深度， 所述埋栅深度 所述体区深度， 所述埋 栅引出端为埋栅电极， 所述埋栅电极与槽栅电极电气连接， 其共同引出端为栅电极。
所述 S0I横向 M0SFET器件为对称结构， 所述漏区位于器件中心， 由中心漏区向外依 次是介质槽、 源区 b、 体接触区、 源区 a和槽栅， 槽栅位于器件外围。 便于利用槽栅介质 实现器件或电路间的隔离。
所述 S0I横向 M0SFET器件为面对称结构，平分漏区且不穿过介质槽和栅槽的平面为 其对称面。
所述 S0I横向 M0SFET器件为轴对称结构， 过漏区中心的纵轴为其对称轴。
该方案在版图设计中， 漏区剖面形状可以为圆形或除正三角形之外的正多边形， 与 之匹配的介质槽、源区 b、体接触区、源区 a和槽栅的剖面形状则为圆环形环带或除正三 角形环带之外的正多边形环带。对于剖面形状为圆形的漏区， 且介质槽、源区 a、源区 b、 体接触区和槽栅为圆环形环带的器件结构， 具有最佳的对称型， 且减弱了曲率效应， 因 而耐压最高， 且节省芯片面积。 采用其他正多边形结构， 如正六边形等也是一种常用的 选择。 一般而言， 同一器件的漏区剖面形状与外围如栅槽和介质槽的剖面形状相匹配， 如漏区为正六边形， 介质槽、 源区 a、 源区 b、 体接触区和槽栅也为正六边形环带。
所述栅介质纵向成上薄下厚的结构。 该方案可以进一步提高器件耐压。
所述介质槽共有 n条， n 2， 每条介质槽之间有间距； 埋栅位于与体区接触的介质 槽中。 该方案适当增加介质槽的条数， 有利于提高器件耐压。
所述介质槽之间的有源层材料导电类型相同或不同。 该方案便于根据需要选择制作 工艺、 制作步骤， 从而增加工艺的灵活性。
所述介质槽纵向深度， 横向宽度及间距相等或不相等。
所述介质槽的条数大于 3时， 中间的介质槽深度大于两侧介质槽深度。 这种结构有 利于提高耐压。
所述漏区与介质槽接触或不接触。 该方案中， 漏区与介质槽不接触较之接触的结构 形式， 耐压有一定提高； 漏区与介质槽接触较之不接触的结构， 导通电阻有一定降低。
所述 S0I横向 M0SFET器件用于集成电路的有源器件。
所述集成电路为功率集成电路或射频功率集成电路。
所述有源层材料包括但不限于 Si、 SiC、 SiGe、 GaAs或 GaN。 该方案中列举的这几种 材料技术成熟， 取材方便。
所述有源层材料为 Si， 所述介质槽中介质为 Si02， 或介电系数低于 Si02且临界击穿 电场高于 Si临界击穿电场 3倍的介质： 包括但不限于 SiOF、 CD0或 SiC0F。
对于 Si半导体， 业界常用使用 SiO 介质， 工艺成熟。 由于≤102的相对介电系数 3. 9低于 Si的相对介电系数 11. 9， 所以增强介质槽内介质的电场， 提高器件耐压； 选用 相对介电系数低于 Si02且临界击穿电场高于 Si临界击穿电场 3倍的介质更有利于提高器 件耐压。
所述有源层材料为 Si ; 所述栅介质为 Si02， 或介电系数高于 Si0 介质： 包括但不 限于 Si 、 A1203、 A1N或 Hf02。 该方案中， 高介电系数的栅介质可以增强栅电压对栅电 荷的控制能力， 增大跨导； 或者在相同的栅结构 MIS (Metal-Insulator-Semiconductor, 栅电极 -栅介质-栅介质下的半导体形成 MIS结构） 电容下， 可以将栅介质做得更厚， 减 小隧道电流， 避免隧穿效应， 增强器件或芯片的稳定性与可靠性。
所述有源层材料为 Si， 所述介质埋层材料为 Si02 ; 或介电系数低于 Si02且临界击穿 电场高于 Si临界击穿电场 3倍的介质： 包括但不限于 SiOF、 CD0或 SiC0F。 介质埋层采 用介电系数较低的介质， 可以增强介质埋层的电场， 有利于器件耐压的提高。
本发明的有益效果是： ①阻断状态下， 在横向， 位于漏区和源区 b 之间的介质槽内 的介质参与耐压， 由于介质 （比如 Si02 ) 的介电系数小于半导体有源层 （比如 Si ) 的介 电系数， 所以介质槽内电场远大于有源层内的电场； 在纵向， 槽栅结构和介质槽增强了 有源层内的多维度耗尽。 二者均使器件耐压提高， 因此， 对于相同的器件横向尺寸， 器 件耐压大幅度提高； 或对于相同的耐压， 漂移区和器件长度大幅度减小， 从而降低导通 电阻和功耗， 可以满足降低芯片成本和小型化的要求。 ②介质槽使漂移区沿纵向折叠， 缩小器件横向尺寸， 进而降低比导通电阻和芯片成本， 并增加开关速度。 ③导通状态下， 纵向延伸至介质埋层的槽栅扩展漂移区纵向有效导电区域， 大大降低导通电阻和功耗。 同时， 埋栅结构进一步增加器件的沟道密度和电流密度， 降低功耗。 Φ高压截止状态时， 纵向延伸至介质埋层上界面的栅介质将来自于器件中心的漏区的高电位终止于槽栅以 内， 避免高电位对槽栅以外低压电路的影响。 因此， 栅槽同时也作为介质隔离槽， 这不 仅节省了介质隔离槽的面积， 而且不需要象常规 S0I高压集成电路那样， 采用专门工艺 流程制作介质隔离槽， 简化了功率集成电路工艺， 节约了成本。 简言之， 本发明的优点 是提供了高耐压、 高速、 低功耗、 低成本、 小型化以及便于与功率集成电路集成的 S0I 横向 M0SFET。
附图说明
图 1是常规 S0I技术高压集成电路剖面结构示意图。
图 2是具有槽的 SOI RESURF LDM0SFET器件结构示意图。
图 3是 TLPM/D M0SFET结构示意图。
图 4是 TLPM/S M0SFET结构示意图。
图 5是具有面对称结构的 S0I 横向 M0SFET器件元胞结构示意图 （xz平面） ；
AA ' 沿 X方向， BB ' 沿 z方向，纵向即为 y方向；器件结构以过 BB ' 的 yz平面对称。 图 6是具有轴对称结构的 S0I 横向 M0SFET器件元胞结构示意图 （xz平面） ；
AA ' 沿 X方向； 纵向即为 y方向； 器件以过漏电极 D中心的 y轴为对称轴。
图 7是 N沟道 S0I 横向 M0SFET元胞结构剖视图 （沿图 5或图 6中 AA'线的纵剖面， 即 xy平面图， 下同） 。
图 8是漏区不与介质槽接触的 N沟道 S0I横向 M0SFET器件元胞结构剖视图； 图 9是栅介质上薄下厚的 N沟道 S0I横向 M0SFET器件元胞结构剖视图；
图 10a具有 2个介质槽的 N沟道 S0I横向 M0SFET器件剖视图 （半个元胞） ； 图 10b是介质槽之间材料具有不同导电类型的 N沟道 S0I横向 M0SFET器件 结构示 意图 （半个元胞） ；
图 11a具有三个介质槽， 且介质槽深度不同的 N沟道 S0I 横向 M0SFET 器件结构示 意图 （半个元胞） ；
图 l ib具有三个介质槽， 且介质槽之间的有源层材料导电类型不同的 N沟道 S0I横 向 M0SFET 结构示意图 （半个元胞） ；
图 12是 P沟道 S0I横向 M0SFET器件元胞结构剖视图；
图 13是二维等势线分布比较示意图 （半个元胞） ；
图 14是二维电流线分布比较示意图 （半个元胞） ； 图 15是本发明用于集成电路中， 高压 S0I横向 M0SFET器件与低压电路的隔离示意 图。
附图标记：
1、 衬底层； 2、 介质层； 3、 有源层； 4、 栅介质； 5、 导电材料； 61 为介质槽； 6 为介质槽内填充介质； 7为埋栅； 8为栅槽； 9为体区； 10为体接触区； 11a为源区 a; l ib为源区 b; 21表示槽栅电极； 22表示埋栅电极； 30为介质隔离槽； 31为氧化物槽； 32为厚氧化物层； 60为介质槽之间的有源层材料； S为源电极； D为漏电极； G为栅电极。 具体实施方式
下面结合附图及实施例， 详细描述本发明的技术方案。
本发明的技术方案， 充分利用槽栅、 介质槽及埋栅， 对 S0I横向 M0SFET器件的电气 性能进行了综合改进和提高。 为了方便描述， 本发明的 S0I横向 M0SFET器件有的地方也 简称为器件。
实施例 1
参见图 5所示，这是一种面对称结构的一个 S0I横向 M0SFET器件元胞版图布局示意 图。 该图为 xz平面图， 其中 AA ' 沿 X方向， BB ' 沿 z方向， 纵向即为 y方向。 该器件的 对称面为过 BB ' 的 yz平面。该图包含介质槽 61和槽栅 8的版图，还有金属电极的版图： 槽栅电极 21、 埋栅电极 22、 栅电极 G、 源电极 S和漏电极0。 在该版图布局上， 电学起 作用的源区、 漏区， 槽栅 8， 介质槽 61， 埋柵等图形均为条形， 图中漏电极 D位于器件 中心， 漏电极 D两边为介质槽 61， 介质槽 61外侧为源电极 S， 槽栅 8位于器件最外侧以 便实现集成电路中高、低压单元隔离。介质槽 61中的导电材料形成埋栅， 由埋栅电极 22 引出， 槽栅 8中的导电材料由槽栅电极 21引出， 他们的共同引出端为器件的栅电极 G。 图中栅电极 G和源电极 S采用了惯用的叉指状结构。
图 6示出了一种具有轴对称结构的一个 S0I横向 M0SFET器件元胞版图布局图，即 xz 平面图， 其中 AA ' 沿 X方向。 该图以圆形图形为例描述轴对称结构。 漏区 D位于器件中 心， 与源区 b被介质槽 61隔开。 器件以过漏电极 D中心的 y轴为对称轴。 介质槽 61中 的埋栅由埋栅电极 22引出， 与器件最外围的槽栅 8中的导电材料的引出端槽栅电极 21 电气连接， 构成器件的栅电极 G。槽栅 8位于器件最外侧以便实现集成电路中高、低压单 元隔离。
图 7示出了 N沟道 S0I横向 M0SFET器件元胞剖视图。 该图为 xy平面图。 其包括纵 向 （y轴） 自下而上的衬底层 1、 介质埋层 2和有源层 3。 有源层 3中形成槽栅 8， 槽栅 8 由栅介质 4及其包围的导电材料 5构成， 导电材料 5引出端为槽栅电极。 槽栅 8纵向长 度穿过有源层 3直到介质埋层 2。在槽栅一侧的有源层表面具有体区 9和漏区，漏区引出 端为漏电极 D。体区 9和漏区之间有间距。体区 9的表面顺次是源区 a (图中标识为 11a)， 体接触区 10， 源区 b (图中标识为 l ib)。 源区 a、 源区 b和体接触区 10的共同引出端为 源电极 S。 槽栅 8与体区 9和源区 a接触， 源区 b和漏区之间形成介质槽 61， 介质槽 61 中填充介质 6， 介质 6的介电系数小于有源层 3材料的介电系数。 介质槽 61纵向深度大 于体区 9纵向深度且小于有源层 3的厚度。 介质槽 61中由导电材料形成埋栅 7， 埋栅 7 靠近源区 b， 且被介质槽中介质 6包围。埋栅 7深度小于介质槽深度， 埋栅 7深度 体区 9深度， 埋栅 7引出端为埋栅电极， 埋栅电极与槽栅电极电气连接， 其共同引出端为器件 的栅电极6。
槽栅结构的引入增大了器件的有效纵向导电面积， 从而大大降低比导通电阻。 槽栅 和埋栅的双栅结构又使沟道密度增加， 在相同器件大小的情况下比导通电阻降低。 介质 槽的引入不仅提高了器件耐压， 而且减小了器件或芯片的横向尺寸， 从而降低导通电阻 和功耗， 并因此节约成本。 图 7示出的是具有单介质槽 61的 N沟道 S0I横向 M0SFET器 件。 这种结构形状的器件工艺更容易实现， 器件具有最佳的对称性。
实施例 2
与实施例 1相比， 本例器件漏区 n+与介质槽 61不接触， 其余结构与实施例 1相同， 如图 8所示。 与图 7所示结构相比， 本例中器件耐压有一定提高， 但导通电阻略有上升。
实施例 3
本例器件栅介质 4纵向成上薄下厚的结构， 如图 9所示。 这种槽栅 8的结构有利于 提高器件耐压。
实施例 4
如图 10a和图 10b所示， 本例器件共有 2条介质槽 61， 也是 N沟道 S0I横向 M0SFET 器件。 介质槽 61的纵向深度相同。 图 10a介质槽之间有源层材料 60与有源层 3的材料 导电类型相同， 制造时， 可以采用先刻介质槽 61和填充介质 6， 再注入、 扩散形成体区 9， 源区、 漏区和体接触区 10。 图 10b介质槽之间有源层材料 60与有源层 3的材料导电 类型不同， 制造时， 可以采用先在有源层 3上外延形成体区 9， 之后刻介质槽 61和填充 介质 6， 再注入、 扩散形成体接触区、 漏区 n、 源区和体区 9的工艺。 图 10a、 b仅示出 了器件的半个元胞。
实施例 5
本例器件介质槽 61共有 3条， 介质槽 61的纵向深度不相等， 位于中间的介质槽 61 深度大于其两边的介质槽 61深度， 如图 l la、 b所示。 中间的介质槽 61深度大于两侧介 质槽 61深度， 这种结构有利于提高耐压。 图 11a中介质槽 61之间材料导电类型与有源 层 3相同， 图 l ib中介质槽 61之间材料导电类型与有源层 3不同。
实施例 6
参加图 12， 本例器件为具有单介质槽 61的 P沟道 S0I横向 M0SFET器件。 本例器件 有源层 3、 源区 a、 源区 b、 漏区、 体区 9和体接触区 10的材料导电类型与 N沟道 S0I 横向 M0SFET器件（图 7和图 8所示）正好向反。 其他结构参见实施例 1。
实施例 2-实施例 5的结构均适用于 P沟道 S0I横向 M0SFET器件。 不过 P沟道 S0I 横向 M0SFET器件有源层 3、 源区 a、 源区 b、 漏区、 体区 9和体接触区 10的材料导电类 型与 N沟道 S0I横向 M0SFET器件（图 7_11所示）正好向反。
适当增加介质槽 61的条数， 可以提高器件耐压。 但条数过多使得图形线条变窄， 工 艺难度增加。 当采用多条介质槽的结构时， 每条介质槽纵向深度， 横向宽度及间距可以 相等或不相等。
本发明的 S0I横向 M0SFET器件最适合由于集成电路的有源器件，特别是用于功率集 成电路和射频功率集成电路。
本发明的上述几种实施例描述的器件， 可以采用 Si、 SiC、 SiGe、 GaAs或 GaN等作 为源层 3的材料制作器件或集成电路， 这几种材料技术成熟， 取材方便。 可以满足不同 器件或电路性能要求。
如果有源层材料采用 Si， 推荐的导电材料 5和埋柵导电材料为多晶硅。
作为业界常用的介质， 介质槽中介质 6为 Si02， 或可以采用介电系数低于 Si02且临 界击穿电场高于 Si临界击穿电场 3倍的介质， 如 SiOF、 CD0或 SiCOF等。 由于 Si02相对 介电系数 3. 9低于 Si相对介电系数 11. 9，所以增强了介质槽内介质的电场，提高器件耐 压，选用相对介电系数低于 Si02且临界击穿电场高于 Si临界击穿电场 3倍的介质更有利 于提高耐压。 介质槽 61中介质 6的低介电系数， 还有利于降低器件栅-漏电容， 提高器 件开关速度。
栅介质 4的选择， 也可以采用 Si02， 或介电系数高于 Si02且临界击穿电场与 Si02相 当或更高的介质： 如 Si 、 A1N、 A1203或 Hf02等。 栅介质采用较高的介电系数， 可以增 强栅电压对栅电荷的控制能力， 增大跨导。 或者在相同的栅结构 MIS (Metal-Insulator-Semiconductor，栅电极 -栅介质-栅介质下的半导体形成 MIS结构） 电容下， 可以将栅介质做得更厚， 减小隧道电流， 避免隧穿效应， 增强器件或芯片的稳 定性与可靠性。
对于介质埋层 2的材料， Si02是业界常用的， 或采用介电系数低于 Si02且临界击穿 电场高于 Si临界击穿电场 3倍的介质， 如 SiOF、 CD0或 SiCOF等。 采用介电系数较低的 介质， 可以增强介质埋层 2的电场， 有利于器件耐压的提高。
本发明的技术方案， 对衬底材料几乎没有要求， 可以是 n型或 p型半导体材料， 甚 至可以是绝缘介质材料， 或与介质埋层为同一种介质材料。
图 13是二维等势线分布比较示意图 （半个元胞） 。 a代表常规平面栅 LDM0SFET (无 槽栅、 埋栅和介质槽） ； b代表具有槽栅但无介质槽的横向 MOSFET; c代表本发明公开的 具有槽栅、埋栅和介质槽的 S0I横向 MOSFET器件。图中 2根相邻等势线的电压差为 10V， 三种结构击穿电压分别为 254V， 130V, 109V。 对比图 13 (a) 和（b)可知， 槽栅结构的引 入使耐压从常规 SOI LDM0S的 109V提高到 130V; 对比图 13 (b) 和（c)可知， 介质槽使 耐压 130V提高到 254V, 提高了接近 1倍。
图 14是二维电流线分布 （2根相邻电流线的电流强度差为 1 X 10— 6Α/ μ πι)。 a代表常 规平面栅 LDM0SFET (无槽栅、埋栅和介质槽） ； b代表具有槽栅但无介质槽的横向 MOSFET; c代表本发明公开的具有槽栅、 埋栅和介质槽的 S0I横向 MOSFET器件。 在图 14 (a)的常 规 SOI LDM0SFET器件中， 电流仅流经器件表面薄层，有效的导电面积较小。对比图 14 (a) 和 (b)可知， 槽栅 8的引入增大了器件的有效纵向导电面积， 从而大大降低比导通电阻。 因此， 器件的比导通电阻从图 14 (a)的 7. 7m Q . cm 2降低为 4m Q . cm 2。 对比图 14 (b)和（c) 可知，尽管介质槽 61占据了漂移区中较大的导电区域，但优化的漂移区浓度因此而增大； 而且， 槽栅和埋栅使沟道密度增加， 所以， 本发明技术在相同的器件大小的情况下比导 通电阻降低为 3. 5ΙΉ Ω . CM 2。
综上， 本发明的技术一方面使器件耐压大大提高并缩小器件横向尺寸， 起主要作用 的是介质槽 61 ; 另一方面， 槽栅 8增大了器件有效纵向导电面积， 大大降低比导通电阻; 同时， 槽栅 8埋栅 7两种结构使沟道密度和电流密度增加， 显著降低比导通电阻， 进而 降低功耗； 再者， 介质槽降低了栅-漏电容， 提高器件的频率和输出功率。
图 15是本发明用于集成电路中， 高压器件与电压电路的隔离示意图。 可以看出， 采 用本发明的技术方案， 高压器件与低压电路之间不需要形成专门的隔离槽 （如图 1 中的 30)， 本发明的槽栅本身就具有完善的隔离作用， 该技术降低了集成电路的制造成本和工 艺难度。

Claims

权利要求书
1、 SOI横向 M0SFET器件， 包括纵向自下而上的衬底层、 介质埋层和有源层， 所述有 源层中形成槽栅， 所述槽栅由栅介质及其包围的导电材料构成， 所述导电材料引出端为 槽栅电极； 其特征在于， 所述槽栅纵向长度穿过有源层直到介质埋层； 在槽栅一侧的有 源层表面具有体区和漏区， 所述体区和漏区之间有间距， 所述漏区引出端为漏电极； 所 述体区的表面顺次是源区 a， 体接触区， 源区 b ; 所述源区 a、 源区 b和体接触区的共同 引出端为源电极； 所述槽栅与体区和源区 a接触； 源区 b和漏区之间形成介质槽， 所述 介质槽与源区 b和体区接触，所述介质槽中介质的介电系数小于有源层材料的介电系数， 所述介质槽纵向深度大于体区纵向深度且小于有源层的厚度； 所述介质槽中由导电材料 形成埋栅，所述埋栅靠近源区 b，且被介质槽中介质包围，所述埋栅深度小于介质槽深度， 所述埋栅深度 所述体区深度， 所述埋栅引出端为埋栅电极， 所述埋栅电极与槽栅电极 电气连接， 其共同引出端为栅电极。
2、根据权利要求 1所述的 S0I横向 M0SFET器件，其特征在于，所述 S0I横向 M0SFET 器件为对称结构， 所述漏区位于器件中心， 由中心漏区向外依次是介质槽、源区 b、 体接 触区、 源区 a和槽栅， 槽栅位于器件外围。
3、 根据权利要求 2所述 S0I横向 M0SFET器件， 其特征在于， 所述 S0I横向 M0SFET 器件为面对称结构， 平分漏区且不穿过介质槽和栅槽的平面为其对称面。
4、 根据权利要求 1所述的 S0I横向 M0SFET器件，其特征在于，所述 S0I横向 M0SFET 器件为轴对称结构， 过漏区中心的纵轴为其对称轴。
5、 根据权利要求 1〜4任意一项所述的 S0I横向 M0SFET器件， 其特征在于， 所述栅 介质纵向成上薄下厚的结构。
6、 根据权利要求 1〜5任意一项所述的 S0I横向 M0SFET器件， 其特征在于， 所述介 质槽共有 n条， n 2， 每条介质槽之间有间距； 埋栅位于与体区接触的介质槽中。
7、 根据权利要求 6所述的 S0I横向 M0SFET器件， 其特征在于， 所述介质槽之间的 有源层材料导电类型相同或不同。
8、 根据权利要求 6所述的 S0I横向 M0SFET器件， 其特征在于， 所述介质槽纵向深 度， 横向宽度及间距相等或不相等。
9、 根据权利要求 6所述的 S0I横向 M0SFET器件， 其特征在于， 所述介质槽的条数 大于 3时， 中间的介质槽深度大于两侧介质槽深度。
10、 根据权利要求 1〜9任意一项所述的 SOI横向 MOSFET器件， 其特征在于， 所述 漏区与介质槽接触或不接触。
11、 根据权利要求 1〜10任意一项所述的 S0I横向 MOSFET器件， 其特征在于， 所述 S0I横向 MOSFET器件用于集成电路的有源器件。
12、 根据权利要求 11所述的 S0I横向 MOSFET器件， 其特征在于， 所述集成电路为 功率集成电路或射频功率集成电路。
13、 根据权利要求 1〜12任意一项所述的 S0I横向 MOSFET器件， 其特征在于， 所述 有源层材料包括但不限于 Si、 SiC、 SiGe、 GaAs或 GaN。
14、 根据权利要求 13所述的 SOI横向 MOSFET器件， 其特征在于， 所述有源层材料 为 Si， 所述介质槽中介质为 Si02， 或介电系数低于 Si02且临界击穿电场高于 Si临界击 穿电场 3倍的介质： 包括但不限于 SiOF、 CD0或 SiC0F。
15、 根据权利要求 13所述的 SOI横向 MOSFET器件， 其特征在于， 所述有源层材料 为 Si， 所述栅介质为 Si02 ; 或介电系数高于≤102的介质： 包括但不限于 Si 、 A1203、 A1N 或 Hf02。
16、 根据权利要求 13所述的 SOI横向 MOSFET器件， 其特征在于， 所述有源层材料 为 Si， 所述介质埋层材料为 Si02 ; 或介电系数低于 Si02且临界击穿电场高于 Si临界击 穿电场 3倍的介质： 包括但不限于 SiOF、 CD0或 SiC0F。
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