CN103915505A - 一种槽栅槽源soi ldmos器件 - Google Patents

一种槽栅槽源soi ldmos器件 Download PDF

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CN103915505A
CN103915505A CN201410158931.4A CN201410158931A CN103915505A CN 103915505 A CN103915505 A CN 103915505A CN 201410158931 A CN201410158931 A CN 201410158931A CN 103915505 A CN103915505 A CN 103915505A
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石艳梅
刘继芝
代红丽
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Tianjin University of Technology
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0886—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode

Abstract

一种槽栅槽源SOILDMOS器件，包括衬底层、埋氧层、有源半导体层、n+漏区、槽栅、栅氧层、介质埋层、槽源、源电极、栅电极、p阱和漏电极并组成SOILDMOS器件，p阱内设有n+源区和p+p阱欧姆接触区，槽栅和槽源之间通过介质埋层隔离；n+源区的上部与栅氧层、介质埋层和槽源相接，p+p阱欧姆接触区的上部与槽源相接；p阱的底部与埋氧层相接。本发明的优点是：该槽栅槽源SOILDMOS器件中，纵向槽栅聚集了高电场，提高了器件横向耐压；有源半导体层的纵向电场在槽栅的作用下分布均匀，提高了器件纵向耐压；由于采用了槽栅、槽源结构，P阱与纵向槽栅形成了纵向导电沟道，显著的降低了器件导通电阻。

Description

一种槽栅槽源SOI LDMOS器件
技术领域
 本发明属于半导体功率器件技术领域，特别涉及一种槽栅槽源SOI LDMOS器件。
背景技术
SOI(Silicon On Insulator)器件具有更高的转换速度、理想的介质隔离、低漏电流等优点，在智能集成电路设计中备受关注。高击穿电压和低比导通电阻一直是SOI功率器件研究的热点方向，各种新的器件结构不断被提出。随着集成电路集成度的不断提高，器件尺寸越来越小。在小器件尺寸下如何提高器件击穿电压，同时降低比导通电阻，成为SOI功率器件研究的一个难点。
传统SOI LDMOS器件中，对于小尺寸器件，横向耐压通常低于纵向耐压，所以击穿电压主要有横向耐压决定。随着器件尺寸的减小，漂移区长度也随之减小，器件所能承受的耐压越来越低。影响SOI LDMOS器件比导通电阻的两个关键因素为：电流传导路径和传导面积。对于传统SOI LDMOS结构，由于电流传导区域主要集中在器件表面附近，导致其比导通电阻非常大。
为了提高小尺寸SOI LDMOS器件的击穿电压，同时降低比导通电阻，槽（Trench）技术得到了广泛的应用。槽技术的应用主要包括槽栅（Trench Gate，TG）结构、槽漏（Trench Drain，TD）结构、槽栅槽漏（Trench Gate and Trench Drain，TGTD）结构。在槽栅结构中，贯穿于漂移区的纵向槽栅调制了漂移区电场，使漂移区电场分布更加均匀，提高了器件击穿电压。同时，该结构在纵向扩展了电流传导区域，使器件比导通电阻显著下降。但是，随着器件尺寸的缩小，槽栅结构在提高击穿电压及降低导通电阻方面的优势越来越弱。槽栅槽漏结构，在纵向具有宽的电流传导区域，同时，在横向缩短了电流传导路径，进一步降低了器件导通电阻。但槽栅槽漏结构的击穿电压比较低。
发明内容
本发明的目的在于针对上述存在问题，提供一种槽栅槽源SOI LDMOS器件，以实现进一步降低SOI LDMOS器件的比导通电阻，同时保持较高的器件击穿电压。
本发明的技术方案：
一种槽栅槽源SOI LDMOS器件，包括衬底层、埋氧层、有源半导体层、n+漏区、槽栅、栅氧层、介质埋层、槽源、源电极、栅电极、p阱和漏电极并组成SOI LDMOS器件，p阱内设有n+源区和p+p阱欧姆接触区，其特征在于:槽栅和槽源之间通过介质埋层隔离；n+源区的上部与栅氧层、介质埋层和槽源相接，p+p阱欧姆接触区的上部与槽源相接；p阱的底部与埋氧层相接。
所述槽栅、槽源材料为重掺杂多晶硅。
所述介质埋层和埋氧层材料均为二氧化硅。
本发明的优点是：
该槽栅槽源SOI LDMOS器件中，纵向槽栅聚集了高电场，使硅层电场减小，提高了器件横向耐压；作为器件漂移区的有源半导体层的纵向电场在槽栅的作用下分布均匀，提高了器件纵向耐压；由于采用了槽栅、槽源结构，使得源区位于硅层的底部，P阱与纵向槽栅形成了纵向导电沟道，在槽栅的作用下，p阱上方的漂移区内形成了较长的电子积累层，使电流在纵向传导面积扩大，同时电流在横向保持了较短的传导路径，显著的降低了器件导通电阻；该槽栅槽源SOI LDMOS不仅提高了器件耐压，还降低了器件导通电阻。
附图说明
图1为该槽栅槽源SOI LDMOS器件结构示意图。
图中：1.衬底层    2.埋氧层    3.有源半导体层    4. n+源区 
5. p+p阱欧姆接触区    6. n+漏区    7.槽栅    8.栅氧层   9.介质埋层  10.槽源    11.源电极   12.栅电极    13.p阱    14.漏电极。
图2为该槽栅槽源SOI LDMOS在反向击穿时的表面电场分布图。
图3为该槽栅槽源SOI LDMOS在反向击穿时的漏端纵向电场分布图。
图4为该槽栅槽源SOI LDMOS导通时电流线分布图。
具体实施方式
下面结合附图对本发明作进一步的具体说明。
实施例：
一种槽栅槽源SOI LDMOS器件，如图1所示，包括衬底层1、埋氧层2、有源半导体层3、n+漏区6、槽栅7、栅氧层8、介质埋层9、槽源10、源电极11、栅电极12、p阱13和漏电极14并组成SOI LDMOS器件，p阱13内设有n+源区4和p+p阱欧姆接触区5，槽栅7和槽源10之间通过介质埋层9隔离； n+源区4的上部与栅氧层8、介质埋层9和槽源10相接，p+p阱欧姆接触区5的上部与槽源10相接；p阱13的底部与埋氧层2相接。
该槽栅槽源SOI LDMOS器件性能检测：
图2为该槽栅槽源SOI LDMOS在反向击穿时的表面电场分布图，图中表明：纵向槽栅聚集了高电场，使硅层电场减小，提高了器件横向耐压。
图3为该槽栅槽源SOI LDMOS在反向击穿时的漏端纵向电场分布图，图中表明：器件漂移区（有源半导体层）的纵向电场在槽栅的作用下分布也非常均匀，提高了器件纵向耐压。
图4为该槽栅槽源SOI LDMOS导通时电流线分布图，图中表明：由于采用了槽栅、槽漏结构，使得源区位于硅层的底部。P阱与纵向槽栅形成了纵向导电沟道。在槽栅的作用下，p阱上方的漂移区内形成了较长的电子积累层，使电流在纵向传导面积扩大。同时电流在横向保持了较短的传导路径，显著的降低了器件导通电阻。
综上所述，本发明提出的槽栅槽漏SOI LDMOS不仅提高了器件耐压，还降低了器件导通电阻。

Claims (3)

1.一种槽栅槽源SOI LDMOS器件，包括衬底层、埋氧层、有源半导体层、n+漏区、槽栅、栅氧层、介质埋层、槽源、源电极、栅电极、p阱和漏电极并组成SOI LDMOS器件，p阱内设有n+源区和p+p阱欧姆接触区，其特征在于:槽栅和槽源之间通过介质埋层隔离； n+源区的上部与栅氧层、介质埋层和槽源相接，p+p阱欧姆接触区的上部与槽源相接；p阱的底部与埋氧层相接。
2.根据权利要求1所述槽栅槽源SOI LDMOS器件，其特征在于:所述槽栅、槽源材料为重掺杂多晶硅。
3.根据权利要求1所述槽栅槽源SOI LDMOS器件，其特征在于所述介质埋层和埋氧层材料均为二氧化硅。
CN201410158931.4A 2014-04-21 2014-04-21 一种槽栅槽源soi ldmos器件 Pending CN103915505A (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116705849A (zh) * 2022-09-29 2023-09-05 荣耀终端有限公司 一种半导体结构及半导体结构的制备方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1222789A (zh) * 1997-06-30 1999-07-14 松下电工株式会社 固态继电器
US20060166419A1 (en) * 2005-01-21 2006-07-27 Kazuo Shimoyama Method for manufacturing semiconductor device
CN101840935A (zh) * 2010-05-17 2010-09-22 电子科技大学 Soi横向mosfet器件

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1222789A (zh) * 1997-06-30 1999-07-14 松下电工株式会社 固态继电器
US20060166419A1 (en) * 2005-01-21 2006-07-27 Kazuo Shimoyama Method for manufacturing semiconductor device
CN101840935A (zh) * 2010-05-17 2010-09-22 电子科技大学 Soi横向mosfet器件

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116705849A (zh) * 2022-09-29 2023-09-05 荣耀终端有限公司 一种半导体结构及半导体结构的制备方法

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Application publication date: 20140709