WO2011101918A1 - 発光装置とその製造方法 - Google Patents
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- WO2011101918A1 WO2011101918A1 PCT/JP2010/001118 JP2010001118W WO2011101918A1 WO 2011101918 A1 WO2011101918 A1 WO 2011101918A1 JP 2010001118 W JP2010001118 W JP 2010001118W WO 2011101918 A1 WO2011101918 A1 WO 2011101918A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/122—Pixel-defining structures or layers, e.g. banks
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B33/00—Electroluminescent light sources
- H05B33/10—Apparatus or processes specially adapted to the manufacture of electroluminescent light sources
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/1201—Manufacture or treatment
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/124—Insulating layers formed between TFT elements and OLED elements
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K2102/00—Constructional details relating to the organic devices covered by this subclass
- H10K2102/301—Details of OLEDs
- H10K2102/341—Short-circuit prevention
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K2102/00—Constructional details relating to the organic devices covered by this subclass
- H10K2102/301—Details of OLEDs
- H10K2102/351—Thickness
Definitions
- the present invention relates to a light emitting device and a manufacturing method thereof.
- organic electroluminescence (organic EL) display devices have been researched and developed (for example, see Patent Documents 1 and 2).
- the organic EL display device has a configuration in which organic EL elements are provided in units of subpixels, and each organic EL element emits light by utilizing an electroluminescence phenomenon of a solid fluorescent material.
- the configuration of the organic EL display device according to the prior art will be described with reference to FIG.
- a TFT (Thin Film Transistor) layer (only the source 901a as a part thereof is shown in the figure) is formed on a substrate 900, and a passivation film 902 and A planarizing film 903 is formed. Furthermore, an anode layer 910 is formed on the planarizing film 903 in a state corresponding to each subpixel.
- the lower electrode layer (anode layer) 910 has a stacked structure of a metal layer 9101 and a transparent conductive layer 9102 and is connected to the source 901a of the TFT layer through a contact hole 904.
- the lower electrode layer 910 is provided for each subpixel, such as a first lower electrode layer 910a and a second lower electrode layer 910b. That is, in the adjacent subpixels, the first metal layer 9101a and the first transparent conductive layer 9102a of the first lower electrode layer 910a and the second metal layer 9101b and the second transparent conductive layer 9102b of the second lower electrode layer 910b are Are electrically separated from each other.
- a light emitting laminate 920 On the lower electrode layer 910 and the planarizing film 903 between the sub-pixels, a light emitting laminate 920, an upper electrode layer (cathode layer) 930, and a sealing layer 931 are sequentially laminated.
- the light emitting laminate 920 includes a semiconductor intermediate layer 921, a light emitting layer 922, an electron injection layer 924, and a partition wall 923 that are sequentially stacked from the upper surface side of the planarization film 903.
- the partition wall 923 partitions the light emitting layer 922 for each subpixel. Specifically, the partition 923 partitions the light emitting layer 922a on the first lower electrode layer 910a and the light emitting layer 922b on the second lower electrode layer 910b.
- the lower electrode layer 910 (first lower portion) of the adjacent subpixel is formed.
- a leakage current flows between the electrode layer 910a and the second lower electrode layer 910b, and crosstalk occurs.
- an organic EL display device is taken as an example as a conventional technique, but a similar problem occurs with a light emitting device including the organic EL display device.
- the present invention has been made to solve the above-described problems, and provides a light-emitting device capable of suppressing leakage current between adjacent lower electrode layers and effectively preventing the occurrence of crosstalk, and a method for manufacturing the same. For the purpose.
- a light-emitting device employs the following configuration.
- a light-emitting device includes a planarization film formed above a substrate and having a depression, and a first lower electrode formed on the planarization film and outside the formation area of the depression
- a second lower electrode layer formed on the planarizing film and adjacent to the first lower electrode layer with the recess portion outside the formation region of the recess portion, and the first lower electrode
- a semiconducting intermediate layer formed above the layer and the second lower electrode layer, an end of the first lower electrode layer, an end of the second lower electrode layer adjacent to the first lower electrode layer, and
- a barrier rib formed to cover the recess portion of the planarization film, and the recess portion of the planarization film is formed between the first lower electrode layer and the second lower electrode layer.
- the upper surface of the depression of the planarization film is the same as the semiconducting intermediate layer.
- the layer of the material is formed, and the film thickness of the end portion of the layer made of the same material as the semiconductive intermediate layer formed on the upper surface of the recess portion of the planarization film is on the upper surface of the recess portion of the planarization film. It is thinner than the film thickness of the central part of the layer made of the same material as the semiconductive intermediate layer formed.
- a recess is provided between the first lower electrode layer and the second lower electrode layer in the planarization film.
- the depression in the planarization film is submerged from the other upper surface of the planarization film, and a layer made of the same material as the semiconductive intermediate layer is formed on the upper surface of the depression.
- the layer of the same material as that of the semiconductive intermediate film formed on the upper surface of the recess portion of the planarizing film is thinner at the end than at the center.
- the same material as the semiconductive intermediate layer formed on the upper surface of the recess portion of the planarization film due to the film thickness relationship of the same material as the semiconductive intermediate layer as described above.
- the conductivity is low at the end of the layer.
- the layer made of the same material as the semiconductive intermediate layer formed on the upper surface of the recess portion of the planarization film substantially separates the first lower electrode layer and the second lower electrode layer. Thus, a leakage current between the first lower electrode layer and the second lower electrode layer is prevented.
- FIG. 1 is a schematic block diagram illustrating an overall configuration of an organic EL display device 1 according to Embodiment 1.
- FIG. 1 is a schematic bird's-eye view showing a display panel 10 of an organic EL display device 1.
- 3 is a schematic end view showing a partial configuration of the display panel 10.
- FIG. 3 is a schematic plan view showing a partition wall 123 in the display panel 10.
- FIG. 4 is a schematic end view showing a manufacturing process of the display panel 10.
- FIG. 4 is a schematic end view showing a manufacturing process of the display panel 10.
- FIG. 4 is a schematic end view showing a manufacturing process of the display panel 10.
- FIG. 5 is a schematic end view showing a partial configuration of a display panel unit 12 of an organic EL display device according to Embodiment 2.
- FIG. 1 is a schematic bird's-eye view showing a display panel 10 of an organic EL display device 1.
- 3 is a schematic end view showing a partial configuration of the display panel 10.
- FIG. 3 is
- FIG. 5 is a schematic end view showing a manufacturing process of the display panel 12.
- FIG. 5 is a schematic end view showing a manufacturing process of the display panel 12.
- FIG. 10 is a schematic end view showing a partial configuration of a display panel unit 14 of an organic EL display device according to Embodiment 3.
- FIG. 5 is a schematic end view showing a manufacturing process of the display panel 14.
- FIG. 5 is a schematic end view showing a manufacturing process of the display panel 14.
- FIG. 6 is a schematic end view showing a partial configuration of a display panel unit 16 of an organic EL display device according to Embodiment 4.
- FIG. 5 is a schematic end view showing a manufacturing process of the display panel 16.
- FIG. 5 is a schematic end view showing a manufacturing process of the display panel 16.
- FIG. 5 is a schematic end view showing a manufacturing process of the display panel 16.
- FIG. 5 is a schematic end view showing a manufacturing process of the display panel 16.
- FIG. It is a schematic plan view which shows the partition 263 in the display panel 18 which concerns on a modification. It is a model end elevation which shows a partial structure of the display panel which concerns on a prior art.
- a light-emitting device includes a planarization film formed above a substrate and having a depression, and a first lower electrode formed on the planarization film and outside the formation area of the depression
- a second lower electrode layer formed on the planarizing film and adjacent to the first lower electrode layer with the recess portion outside the formation region of the recess portion, and the first lower electrode
- a semiconducting intermediate layer formed above the layer and the second lower electrode layer; an end of the first lower electrode layer; an end of the second lower electrode layer adjacent to the first lower electrode layer; and
- a barrier rib formed to cover the recess portion of the planarization film, and the recess portion of the planarization film is formed between the first lower electrode layer and the second lower electrode layer.
- the same material as the semiconducting intermediate layer is formed on the upper surface of the recess portion of the planarizing film, sinking from the other upper surface of the film
- the thickness of the end of the layer made of the same material as the semiconductive intermediate layer formed on the upper surface of the recess portion of the planarization film is formed on the upper surface of the recess portion of the planarization film. It is thinner than the thickness of the central part of the layer made of the same material as the semiconductive intermediate layer.
- a recess is provided between the first lower electrode layer and the second lower electrode layer in the planarization film.
- the depression in the planarization film is submerged from the other upper surface of the planarization film, and a layer made of the same material as the semiconductive intermediate layer is formed on the upper surface of the depression. Then, the layer of the same material as the semiconductive intermediate film formed on the upper surface of the recess portion of the planarizing film has a thickness that is thinner at the end than at the center.
- the same material as the semiconductive intermediate layer formed on the upper surface of the recess portion of the planarization film due to the film thickness relationship of the same material as the semiconductive intermediate layer as described above.
- the conductivity is low at the end of the layer.
- the layer made of the same material as the semiconductive intermediate layer formed on the upper surface of the recess portion of the planarization film substantially separates the first lower electrode layer and the second lower electrode layer. Thus, a leakage current between the first lower electrode layer and the second lower electrode layer is prevented.
- a partition wall formed so as to cover the depression of the planarization film, the depression of the planarization film between the first lower electrode layer and the second lower electrode layer,
- the lower surface of the planarization film sinks below the upper surface of the recess of the planarization film, and the semiconductive intermediate A layer of the same material is formed, and a side surface of the recess has a region where a layer of the same material as the semiconductive intermediate layer
- a recess is provided between the first lower electrode layer and the second lower electrode layer in the flat film.
- the depression in the planarization film is submerged from the other upper surface of the planarization film, and a layer made of the same material as the semiconductive intermediate layer is formed on the upper surface of the depression.
- the side surface of the hollow part of a planarization film has the area
- the semiconductive intermediate layer is divided at the portion by having a region where the semiconductive intermediate layer is not formed on the side surface of the indented portion.
- the first lower electrode layer and the second lower electrode layer formed across the depression are not formed continuously.
- the semiconductive intermediate layer does not electrically connect the first lower electrode layer and the second lower electrode layer, and can prevent a leakage current between the first lower electrode layer and the second lower electrode layer.
- the partition wall of the light-emitting device according to one embodiment of the present invention is formed so as to enter into a shape portion that is recessed in the direction of the pixel region, adhesion with the planarization film is improved. As a result, in the light-emitting device of one embodiment of the present invention, the partition wall is hardly peeled off and has high reliability.
- a side surface of the recess is shaped to enter below each of the first lower electrode layer and the second lower electrode layer.
- the side surface of the indented portion has a shape that penetrates below each of the first lower electrode layer and the second lower electrode layer.
- the side surface of the recess portion of the chemical film has a region where the semiconductive intermediate layer is not formed.
- the first lower electrode layer and the second lower electrode layer tail are physically electrically connected at the end of the upper surface of the recess portion of the planarization film. Since there is no medium to perform, leakage current between the first lower electrode layer and the second lower electrode layer can be completely prevented.
- the first lower electrode layer includes a layer made of a first transparent conductive film on the semiconductive intermediate layer side
- the second lower electrode layer includes A layer made of a second transparent conductive film is included on the semiconductive intermediate layer side, and the semiconductive intermediate layer is formed on the layer made of the first transparent conductive film and on the layer made of the second transparent conductive film.
- a TFT layer is formed between the substrate and the planarization film, and the planarization film is formed over the TFT layer.
- the TFT layer is formed between the substrate and the planarization film, and the planarization film is formed on the TFT layer.
- the recess portion of the planarization film is submerged between the first lower electrode layer and the second lower electrode layer from the other upper surface of the planarization film, so that the TFT layer is formed.
- the thickness of the upper planarizing film can be larger than the thickness of the planarizing film formed between the first lower electrode layer and the second lower electrode layer.
- the first light-emitting layer formed on the semiconductive intermediate layer above the first lower electrode layer and the second lower electrode layer And a second light emitting layer formed on the semiconducting intermediate layer, and the partition partitions the first light emitting layer and the second light emitting layer.
- the partition includes the first light-emitting layer formed on the semiconductive intermediate layer above the first lower electrode layer, and the second lower electrode layer. It is the structure which divides the 2nd light emitting layer formed on the upper side and semiconductive intermediate
- the first light emitting layer and the second light emitting layer are also separated from each other, the light emitted from the first light emitting layer and the light emitted from the second light emitting layer are not mixed.
- the light-emitting device according to one embodiment of the present invention has excellent light-emitting characteristics.
- the light-emitting device includes the upper electrode layer formed above the first light-emitting layer and the second light-emitting layer in the above structure.
- the light emitting device can include an upper electrode layer formed above the first light emitting layer and the second light emitting layer.
- the upper electrode layer is a cathode layer.
- the upper electrode layer may be a cathode layer.
- the first lower electrode layer and the second lower electrode layer are anode layers
- the semiconducting intermediate layer is a hole injection layer.
- the semiconducting intermediate layer is a hole injection layer.
- injection of holes from the first lower electrode layer to the first light emission layer and injection of holes from the second lower electrode layer to the second light emission layer are performed. Injection is facilitated by the hole injection layer.
- the driving voltage is low and the power consumption is small.
- the depth of the recess is the center of the same material layer as the semiconductive intermediate layer formed on the upper surface of the recess of the planarization film. It is larger than the film thickness of the part.
- the depth of the recess in the planarization film is the center of the layer made of the same material as the semiconductive intermediate layer formed on the upper surface of the recess in the planarization film. It is larger than the film thickness of the part. That is, in the light-emitting device according to one embodiment of the present invention, a semiconducting intermediate layer is formed on the side surface of the recess portion of the planarization film so as to enter the lower side of each of the first lower electrode layer and the second lower electrode layer.
- the thickness of the end portion of the layer made of the same material as the semiconductive intermediate layer formed on the upper surface of the recess portion of the planarization film is increased on the upper surface of the recess portion of the planarization film. It becomes easy to make it thinner than the film thickness of the center part of the layer of the same material as the formed semiconductive intermediate layer.
- the width of the region where the semiconducting intermediate layer is not formed on the side surface of the recess of the planarization film is increased. Therefore, even if the thickness of the semiconducting intermediate layer and the layer of the same material as the semiconducting intermediate layer is increased, the semiconductive intermediate layer above the first lower electrode layer and the semiconductive intermediate layer above the second lower electrode layer Is easily divided, and the semiconducting intermediate layer is not formed across the first lower electrode layer and the second lower electrode layer formed across the recess of the planarization film.
- the semiconductive intermediate layer does not electrically connect the first lower electrode layer and the second lower electrode layer, and can further prevent leakage current between the first lower electrode layer and the second lower electrode layer. Is preferred.
- crosstalk due to leakage current does not occur between adjacent subpixels.
- a first step of preparing a substrate, a second step of forming a planarizing film above the substrate, and a first lower portion on the planarizing film A third step of forming an electrode layer and a second lower electrode layer; a fourth step of forming a resist on the first lower electrode layer and the second lower electrode layer; and the first lower electrode layer; By etching the region of the planarization film where the resist is not formed between the second electrode layer, the upper surface of the planarization film in the region of the planarization film where the resist is not formed
- a fifth step of forming a depressed portion that sinks below the other upper surface of the planarizing film; and a semiconducting intermediate on the first lower electrode layer, the second lower electrode layer, and the bottom surface of the depressed portion A third step of forming an electrode layer and a second lower electrode layer; a fourth step of forming a resist on the first lower electrode layer and the second lower electrode layer; and the first lower electrode layer; By etching the region of the planarization film where the
- a sixth step of forming a layer, and an upper surface of the recess portion of the planarization film The thickness of the end portion of the formed the semiconductor intermediate layer, thinner form than the thickness of the central portion of the formed on the upper surface of the recessed portion of the planarization film the semiconductor intermediate layer.
- a depressed portion is formed between the first lower electrode layer and the second lower electrode layer in the planarization film, which is sunk more than the other upper surface of the planarization film.
- a semiconducting intermediate layer is formed on the upper surface of the recess of the planarizing film.
- the film thickness of the edge of the semiconducting intermediate layer formed on the upper surface of the recess of the planarizing film is that the semiconducting intermediate layer is cut off by the shadowing effect on the side of the indentation when forming the semiconductive intermediate layer. Therefore, it becomes thinner than the film thickness of the central part of the semiconductive intermediate layer formed on the upper surface of the recess part of the planarizing film.
- the conductivity of the semiconductive intermediate layer is reduced at the end of the semiconductive intermediate layer formed on the upper surface of the recess of the planarization film.
- the semiconducting intermediate layer formed on the upper surface of the recess of the planarizing film does not substantially electrically connect the first lower electrode layer and the second lower electrode layer, so the first lower electrode layer and the second lower electrode layer Leakage current between the electrode layers can be prevented.
- a light-emitting device that does not generate crosstalk can be realized.
- a first step of preparing a substrate, a second step of forming a planarizing film above the substrate, and a first lower portion on the planarizing film A third step of forming an electrode layer and a second lower electrode layer; and using the first lower electrode layer and the second lower electrode layer itself as a mask, the first lower electrode layer and the second lower electrode layer Etching the region of the planarization film between the first lower electrode layer and the second lower electrode layer in the region of the planarization film to sink more than the other upper surface of the planarization film
- a fourth step of forming a depressed portion, and a fifth step of forming a semiconducting intermediate layer on the first lower electrode layer, the second lower electrode layer, and the bottom surface of the depressed portion The side surface of the recess has a region where the semiconducting intermediate layer is not formed, The conductive intermediate layer, wherein the dividing the semiconductor intermediate layer is not formed region in the side surface of the rece
- a planarization film is formed by etching a planarization film between the first lower electrode layer and the second lower electrode layer, and etching in the fourth process.
- a depression is formed which is depressed below the other upper surface of the planarizing film, and a region in which the semiconductive intermediate layer is not formed is formed on the side surface of the depression, so that the semiconductive intermediate above the first lower electrode layer is formed.
- the layer is separated from the semiconductive intermediate layer above the second lower electrode layer.
- the semiconductive intermediate layer above the first lower electrode layer and the semiconductive intermediate layer above the second lower electrode layer are semiconductive intermediate on the side surface of the recess.
- the semiconductor intermediate layer is formed continuously across the first lower electrode layer and the second lower electrode layer formed with the recess in between because the layer is divided in the region where the layer is not formed. Is something that disappears.
- an electrode remaining after the first lower electrode layer and the second lower electrode layer are formed in the third step.
- the metal film residue for forming the layer can also be completely removed. Therefore, leakage current between the first lower electrode layer and the second lower electrode layer can be prevented.
- a short circuit between the first lower electrode layer and the second lower electrode layer and a leakage current of the semiconducting intermediate layer are caused between adjacent subpixels.
- a light-emitting device that does not cause crosstalk can be manufactured.
- the partition wall is formed so as to enter into a shape portion that is recessed in the direction of the sub-pixel region, so that the adhesion with the planarization film is improved.
- the planarization between the first lower electrode layer and the second lower electrode layer is performed by etching in the fourth step.
- the recess formed in the film has a shape in which a side surface enters below each of the first lower electrode layer and the second lower electrode layer.
- the side surface has a recess having a shape that enters under each of the first lower electrode layer and the second lower electrode layer. Since it forms in a planarization film
- the electrical connection between the first lower electrode layer and the second lower electrode layer tail is physically performed at the end portion of the upper surface of the recess portion of the planarization film. Since there is no connection medium, leakage current between the first lower electrode layer and the second lower electrode layer can be completely prevented.
- a light-emitting device in which occurrence of crosstalk is prevented can be manufactured.
- the etching is dry etching.
- the first lower electrode layer includes a layer made of a first transparent conductive film on the semiconducting intermediate layer side
- the second The lower electrode layer includes a layer made of a second transparent conductive film on the semiconductive intermediate layer side, and when forming the semiconductive intermediate layer, the layer on the first transparent conductive film and the second transparent conductive film A semiconducting intermediate layer is formed on the layer.
- the first lower electrode layer and the second lower electrode layer including a layer made of the first transparent conductive film or a layer made of the second transparent conductive film on each semiconductive intermediate layer side.
- Form. In forming the layer of the first transparent conductive film in the first lower electrode layer and the layer of the second transparent conductive film layer in the second lower electrode layer, patterning is performed by wet etching, and the first lower electrode layer and the second lower electrode are formed. The transparent conductive film formed between the layers is removed.
- dry etching is performed using the layer made of the first transparent conductive film and the layer made of the second transparent conductive film patterned by the wet etching as a mask. Etching is performed.
- planarization film is dry-etched using the layer made of the first transparent conductive film and the layer made of the second transparent conductive film as a mask, a new mask for dry etching is used to form a recess in the planarization film. There is no need, and the manufacturing process can be simplified.
- the organic EL display device 1 includes a display panel 10 and a drive control unit 20 connected thereto.
- the display panel 10 is an organic EL panel using an electroluminescent phenomenon of an organic material, and a plurality of organic EL elements are arranged and configured.
- TFTs 101 are formed on a substrate 100 corresponding to the respective subpixels, and source signal lines 31 and power supply lines 32 are connected to the TFTs 101.
- a lower electrode layer 110, a light emitting laminate 120, and an upper electrode layer 130 are sequentially laminated on the substrate 100 on which the TFT 101 is formed. The detailed configuration of the display panel 10 will be described later.
- the drive control unit 20 includes four drive circuits 21 to 24 and a control circuit 25.
- the arrangement of the drive control unit 20 with respect to the display panel 10 is not limited to this.
- subpixels 11a, 11b, and 11c each including an organic light emitting layer having an emission color of red (R), green (G), or blue (B) are adjacently formed.
- R red
- G green
- B blue
- the display panel 10 is a top emission type organic EL display.
- a TFT layer (only the source 101a is shown in FIG. 3) and a passivation film 102 are formed, and a planarizing film 103 is laminated thereon.
- a lower electrode layer (anode layer) 110 is formed corresponding to each of the subpixels 11a, 11b, and 11c.
- the lower electrode layer 110 belonging to the subpixel 11a may be referred to as a first lower electrode layer 110a
- the lower electrode layer 110 belonging to the subpixel 11b may be referred to as a second lower electrode layer.
- the lower electrode layer 110 and the source 101a of the TFT layer are connected by a contact hole 104 that penetrates the planarization film 103 vertically.
- a semiconductive intermediate layer 121a is formed on the lower electrode layer 110.
- the semiconducting intermediate layer 121a functions as a hole injection layer, a hole transport layer, or a hole injection / transport layer.
- a portion between the adjacent lower electrode layers 110 has a depressed portion 103a that is sunk more than the upper surface of the other portion.
- a recess-inside formation layer 121b that is a layer made of the same material as the semiconductive intermediate layer 121a is also formed on the upper surface of each recess 103a.
- the semiconductive intermediate layer 121a and the in-dent formation layer 121b may be collectively referred to as the semiconductive layer 121.
- a light emitting layer 122 is formed on the lower electrode layer 110 for each of the subpixels 11a, 11b, and 11c.
- a partition wall 123 made of an insulating material is erected on the in-dent formation layer 121b and on a part of the end of the semiconductive intermediate layer 121a. .
- the light emitting layer 122 is partitioned for each of the subpixels 11a, 11b, and 11c.
- the light emitting layer 122 belonging to the subpixel 11a may be referred to as a first light emitting layer 122a
- the light emitting layer 122 belonging to the subpixel 11b may be referred to as a second light emitting layer 122b.
- the partition wall 123 is integrally formed with the partition element 123 a extending in the Y-axis direction and the partition element 123 b extending in the X-axis direction.
- a so-called pixel bank is employed.
- the subpixels 11a, 11b, and 11c adjacent in the X-axis direction are partitioned by the partition element 123a, and similarly, the subpixels adjacent in the Y-axis direction are partitioned by the partition element 123b.
- the electron injection layer 124, the upper electrode layer (cathode layer) 130, and the sealing layer 131 are continuously formed on the light emitting layer 122 over the region defined by the partition wall 104. It is formed to do. Note that the stacked structure of the semiconducting layer 121, the light emitting layer 122, the partition wall 123, and the electron injection layer 124 corresponds to the light emitting stacked body 120 in FIG.
- the three sub-pixels 11a, 11b, and 11c formed adjacent to each other correspond to each color of red (R), green (G), and blue (B), and set them as one set.
- One pixel (pixel) is configured.
- the substrate 100 is, for example, alkali-free glass, soda glass, non-fluorescent glass, phosphoric acid glass, boric acid glass, quartz, acrylic resin, styrene resin, polycarbonate resin, epoxy resin, polyethylene, polyester, silicone resin. Or an insulating material such as alumina.
- planarization film 103 is formed using an organic compound such as polyimide, polyamide, or acrylic resin material.
- the lower electrode layer 110 includes, for example, Ag (silver), APC (silver, palladium, copper alloy), ARA (silver, rubidium, gold alloy), MoCr (molybdenum and chromium alloy), NiCr (nickel and chromium alloy). Alloy). Note that, in the case of a top emission type organic EL as in the present embodiment, it is preferably formed using a highly reflective material.
- the semiconductor layer 121 is formed using, for example, a metal oxide such as WO X (tungsten oxide) or MoWO X (molybdenum-tungsten oxide), or a metal nitride or metal oxynitride.
- a metal oxide such as WO X (tungsten oxide) or MoWO X (molybdenum-tungsten oxide)
- a metal nitride or metal oxynitride tungsten oxide
- the light-emitting layer 122 has a function of emitting light by generating an excited state when holes and electrons are injected and recombined.
- the material used for forming the light-emitting layer 122 needs to be a light-emitting organic material that can be formed by a wet printing method.
- the oxinoid compound, perylene compound, coumarin compound, azacoumarin compound, oxazole compound, oxadiazole compound, perinone compound, pyrrolopyrrole described in Japanese Patent Publication (JP-A-5-163488) Compound, naphthalene compound, anthracene compound, fluorene compound, fluoranthene compound, tetracene compound, pyrene compound, coronene compound, quinolone compound and azaquinolone compound, pyrazoline derivative and pyrazolone derivative, rhodamine compound, chrysene compound, phenanthrene compound, cyclopentadiene compound, stilbene compound , Diphenylquinone compound, styryl compound, butadiene compound, dicyanomethylenepyran compound, dicyanomethylenethiopyran compound, fluoro Cein compound, pyrylium compound, thiapyrylium compound, seren
- the partition wall 123 is made of an organic material such as resin and has an insulating property.
- the organic material used for forming the partition wall 123 include acrylic resin, polyimide resin, and novolac type phenol resin.
- the partition wall 123 preferably has organic solvent resistance. Further, since the partition wall 123 may be subjected to an etching process, a baking process, or the like, it is preferable that the partition wall 123 be formed of a highly resistant material that does not excessively deform or alter the process. In addition, the surface can be treated with fluorine to give water repellency.
- the insulating material used for forming the partition wall 123 a material having a water repellency that has a resistivity of 10 5 [ ⁇ ⁇ cm] or more, in particular, the above-described materials can be used. This is because when a material having a resistivity of 10 5 [ ⁇ ⁇ cm] or less is used, a leakage current between the lower electrode layer 110 and the upper electrode layer 130 or between adjacent elements is caused by the partition wall 123. This is because the generation of a leakage current in the case causes various problems such as an increase in power consumption.
- the partition wall 123 is formed using a hydrophilic material, so that the difference in affinity / water repellency between the surface of the partition wall 123 and the surface of the semiconductive intermediate layer 121a is reduced, so that the light emitting layer 122 is formed. This is because it becomes difficult to selectively hold the ink containing an organic substance in the opening of the partition wall 123.
- the structure of the partition wall 123 not only a single layer structure as shown in FIG. 3 but also a multilayer structure of two or more layers can be adopted.
- the above materials can be combined for each layer, and an inorganic material and an organic material can be used for each layer.
- Electron injection layer 124 has a function of transporting electrons injected from the upper electrode layer 130 to the light emitting layer 122, and is preferably formed of, for example, barium, phthalocyanine, lithium fluoride, or a combination thereof.
- Upper electrode layer 130 The upper electrode layer (cathode layer) 130 is made of, for example, ITO or IZO (indium zinc oxide). In the case of the top emission type organic EL elements 100a, 100b, and 100c, it is preferably formed of a light transmissive material. About light transmittance, it is preferable that the transmittance is 80% or more.
- the upper electrode layer 130 As a material used for forming the upper electrode layer 130, in addition to the above, for example, a structure in which a layer containing an alkali metal, an alkaline earth metal, or a halide thereof and a layer containing silver are stacked in this order is used. You can also In the above, the layer containing silver may be formed of silver alone, or may be formed of a silver alloy. In order to improve the light extraction efficiency, a highly transparent refractive index adjusting layer can be provided on the silver-containing layer.
- the sealing layer 131 has a function of suppressing the light emitting layer 122 or the like from being exposed to moisture or air, and for example, a material such as SiN (silicon nitride) or SiON (silicon oxynitride) is used. Formed using. In the case of the top emission type, it is preferably formed of a light transmissive material.
- Indentation 103a and semiconducting layer 121 in planarization film 103 As shown in FIG. 3, in the organic EL display device 1 according to the present embodiment, in the display panel 10, a depression 103 a is provided between the first lower electrode layer 110 a and the second lower electrode layer 110 b in the planarization film 103. Is provided. The depression 103a in the planarization film 103 is submerged from the other upper surface of the planarization film 103a, and a depression-part forming layer 121b is formed on the upper surface of the depression 103a. Then, as shown in a portion surrounded by the two-dot chain line in FIG. 3, the recess portion forming layer 121b in the recess 103a of the planarization film 103, the film thickness t 2 at the end portion, the central portion side of the membrane than it It is thinner than the thickness t 1 .
- the organic EL display device 1 at the end portion (the portion of the film thickness t 2 ) of the in-cavity forming layer 121 b in the indentation portion 103 a of the planarization film 103 due to the relationship between the film thicknesses t 1 and t 2 as described above.
- the conductivity is lowered, and the indentation portion formation layer 121b in the indentation portion 103a of the planarizing film 103 includes the first lower electrode layer 110a and the semiconductive intermediate layer 121a thereon, the second lower electrode layer 110b and the upper portion thereof. Leakage current between the first lower electrode layer 110a and the second lower electrode layer 110b is prevented by making the semiconductor intermediate layer 121a substantially not electrically connected.
- the partition wall 123 is formed so as to enter into the recessed portion with the formation of the recess portion 103 a in the planarization film 103.
- the partition wall 123 is difficult to peel off. Therefore, the organic EL display device 1 according to the present embodiment has high reliability.
- a substrate 100 is prepared.
- a TFT layer and a passivation film 102 are formed on the Z-axis upper main surface 100f of the substrate 100, and a flattening film 1030 is laminated so as to cover the TFT layer (see FIG. 5B).
- a flattening film 1030 is laminated so as to cover the TFT layer (see FIG. 5B).
- FIG. 5B for the sake of illustration, only the source 101a is shown in the configuration of the TFT layer.
- a flattened film 1031 having contact holes 104 formed at locations corresponding to the respective sources 101a of the TFT layer is formed, and a metal film (for example, an Ag thin film) 1100 is formed thereon.
- the metal film 1100 can be formed using, for example, a sputtering method or a vacuum evaporation method.
- a photosensitive resist 500 is deposited on a region of the metal film 1100 where the lower electrode layer 110 is to be formed.
- patterning is performed by a photolithography method and an etching method to form the lower electrode layer 110 including the first lower electrode layer 110a and the second lower electrode layer 110b.
- both edges 110 s of the lower electrode layer 110 enter a state below the resist 500.
- etching for example, dry etching
- etching is performed in a state where the resist 500 remains on the lower electrode layer 110, whereby the first lower electrode layer 110a and the second lower electrode layer 110b are formed in the planarization film 103.
- a recess 103a is formed in a region 1031f where the resist 500 is not formed (see FIG. 6C).
- FIG. 6C a slight distance is maintained between both edges 110s of the lower electrode layer 110 (see FIG. 6B) and the opening edge of the recess 103a. . This is because both edges 110 s of the lower electrode layer 110 enter below the resist 500, as shown in FIGS. 6B and 6C.
- the formation of the depression 103a of the planarizing film 103 in FIG. 6C is not limited to dry etching, and can be performed by wet etching.
- a semiconducting material is deposited on the bottom surface of the recess 103a in the lower electrode layer 110 and the planarizing film 103 to form a semiconducting layer 121 in a stacked manner.
- the semiconducting layer 121 includes a semiconducting intermediate layer 121 a on the lower electrode layer 110, and a recess-inside formation layer 121 b on the bottom surface of the recess 103 a of the planarizing film 103.
- an insulating material layer for forming the partition wall 123 is formed on the semiconducting layer 121 by, for example, a spin coating method, and patterned by exposure and development using a photomask. Thereafter, the partition wall 123 is formed by performing cleaning with a cleaning liquid as shown in FIG.
- the light-emitting layer 122 is formed by dropping a composition ink containing the material of the light-emitting layer 122 into the region defined by the partition wall 123 by an inkjet method and drying the ink. . Further, the electron injection layer 124, the upper electrode layer 130, and the sealing layer 131 are stacked on the light emitting layer 122.
- a dispenser method for example, a dispenser method, a nozzle coating method, a spin coating method, an intaglio printing method, a relief printing method, or the like can be used.
- a dispenser method for example, a dispenser method, a nozzle coating method, a spin coating method, an intaglio printing method, a relief printing method, or the like.
- a vacuum deposition method can be used to form the electron injection layer 124
- a plasma coating method can be used to form the upper electrode layer 130, for example.
- the depression 103 a is formed between the first lower electrode layer 110 a and the second lower electrode layer 110 b in the planarization film 103. Since the semiconductor layer 121 is formed in the formed state, the film thickness t 2 at the end of the in-dent formation layer 121b is larger than the film thickness t 1 at the center due to the shadowing effect on the side surface of the depression 103a. It becomes thinner (see the portion surrounded by the two-dot chain line in FIG. 3).
- the semiconducting intermediate layer 121a on the first lower electrode layer 110a and the in-cavity-forming layer 121b adjacent to the first intermediate electrode 121a are substantially reduced in conductivity due to the side surface portion of the indentation 103. Is not electrically connected to. The same applies to the semiconductive intermediate layer 121a on the second lower electrode layer 110b and the in-dent formation layer 121b adjacent thereto.
- a resist 500 for forming the lower electrode layer 110 is formed after the lower electrode layer 110 is formed. Without being removed, it is used as it is as a mask when forming the depression 103a of the planarizing film 103. Therefore, it is not necessary to use a new mask for forming the depression 103a, the manufacturing process can be simplified, and the manufacturing cost can be reduced.
- the organic EL display device according to the present embodiment has the same configuration as that of the organic EL display device 1 according to Embodiment 1 except for the configuration of the display panel 12.
- the configuration of the display panel 12 will be described with reference to FIG.
- the display panel 12 also includes sub-pixels 13a including organic light-emitting layers each having a light emission color of red (R), green (G), or blue (B). 13b and 13c are formed adjacent to each other, which is a top emission type organic EL display.
- the display panel according to the first embodiment is used. 10 has the same configuration.
- the display panel 12 also has a recess 143a formed in a region between the lower electrode layers (anode layers) 150.
- the semiconducting layer 161 is formed on the lower electrode layer 150 and has a semiconductive intermediate layer 161a that functions as a hole injection layer, a hole transport layer, or a hole injection / transport layer, and a recess 143a in the planarization film 143.
- the in-recessed portion forming layer 161b which is a layer of the same material as the semiconductive intermediate layer 161a.
- a light emitting layer 162, an electron injection layer 164, an upper electrode layer (cathode layer) 170, and a sealing layer 171 are sequentially stacked on the semiconducting intermediate layer 161a.
- a partition wall 163 for partitioning 13a, 13b, 13c is provided upright.
- the light-emitting stacked body 160 is configured by the semiconductor intermediate layer 161 a, the light-emitting layer 162, the partition 163, and the electron injection layer 164.
- the first light emitting layer 162a formed above the first lower electrode layer 150a and the second lower electrode layer 150b are disposed above. And the formed second light emitting layer 162b.
- partition 163 of the display panel 12 according to the present embodiment is not particularly shown in a planar shape, but a so-called pixel bank is adopted as with the partition 123 of the display panel 10 according to the first embodiment. ing.
- Indentation 143a and semiconductor layer 161 in planarization film 143 As shown in FIG. 8, also in the display panel 12 according to the present embodiment, a recess 143a is provided in a region between the first lower electrode layer 150a and the second lower electrode layer 150b in the planarization film 143. Yes.
- the depression 143a in the flattening film 143 is the same as the display panel 10 according to the first embodiment in that it is depressed below the other upper surface of the flattening film 143a.
- the point in which the hollow part formation layer 161b is formed on the bottom face of the hollow part 143a is the same as that of the display panel 10 according to the first embodiment.
- a part of the side surface 143 s of the recess 143 a in the planarization film 143 has a region where the semiconducting layer 161 is not formed.
- the semiconductive intermediate layer 161a on the electrode layer 150a and the semiconductive intermediate layer 161a on the second lower electrode layer 150b are divided. For this reason, each semiconducting intermediate layer 161a in the subpixels 13a, 13b, and 13c is not continuously formed across the recess 143a between them. Therefore, in the display panel 12, the semiconductive layer 161 does not electrically connect the first lower electrode layer 150a and the second lower electrode layer 150b, and the first lower electrode layer 150a and the second lower electrode layer 150b are not electrically connected. Leakage current can be prevented.
- the partition wall 163 is formed so as to enter the recessed portion with the recess portion 143 a of the planarization film 143.
- the adhesiveness of the partition wall 163 is difficult to peel off. Therefore, the organic EL display device according to this embodiment also has high reliability.
- the TFT layer (FIG. 9A) is formed on the substrate 100 by executing the steps shown in FIGS. 5A to 5C in the first embodiment. ), Only the source 101a is shown), the passivation film 102, the planarization film 1431, the contact hole 104, and the metal film 1500 are formed.
- a photosensitive resist 501 is deposited on a region on the metal film 1500 where the lower electrode layer 150 is to be formed. Then, as shown in FIG. 9B, the lower electrode layer 150 including the first lower electrode layer 150a and the second lower electrode layer 150b is formed by patterning by a photolithography method and an etching method.
- both edges 110s of the lower electrode layer 110 enter the lower side of the resist 500 after the etching.
- FIG. 9B after etching, both edges 150 s of the lower electrode layer 150 are made to coincide with the edges of the resist 501.
- etching for example, dry etching
- the resist 501 remaining on the lower electrode layer 150.
- a recess 143a is formed in a region 1431f where the resist 501 is not formed between the first lower electrode layer 150a and the second lower electrode layer 150b (FIG. 9C). See).
- the formation of the depressed portion 143a of the planarization film 143 is not limited to dry etching, and can be performed by wet etching.
- a semiconducting material is deposited on the bottom surfaces of the recesses 143a in the lower electrode layer 150 and the planarizing film 143 to form a semiconducting layer 161.
- the semiconducting layer 161 includes a semiconducting intermediate layer 161 a on the lower electrode layer 150, and a recess-forming layer 161 b on the bottom surface of the recess 143 a of the planarizing film 143.
- an insulating material layer for forming the partition wall 163 is formed on the semiconducting layer 161 by, for example, a spin coating method, and patterned by exposure and development using a photomask. Thereafter, the partition wall 163 is formed by performing cleaning with a cleaning liquid as shown in FIG.
- the composition ink containing the material of the light emitting layer 162 is dropped onto the region defined by the partition wall 163 by an ink jet method and dried to form the light emitting layer 162. Further, an electron injection layer 164, an upper electrode layer 170, and a sealing layer 171 are stacked on the light emitting layer 162.
- a dispenser method for example, a dispenser method, a nozzle coating method, a spin coating method, an intaglio printing method, or a relief printing, as in the manufacturing method according to the first embodiment.
- a printing method or the like can also be used.
- vacuum drying and drying in a nitrogen atmosphere are sequentially performed.
- a vacuum deposition method can be used as in the manufacturing method according to the first embodiment.
- a plasma coating method is used for the formation of the upper electrode layer 170. Can be used.
- the recess 143a is formed between the first lower electrode layer 150a and the second lower electrode layer 150b in the planarization film 143. Since the semiconductor layer 161 is formed in a state where the semiconductor layer 161 is formed, a region where the semiconductor layer 161 is not formed in a part of the side surface 143s of the recess portion 143a is generated due to the shadowing effect (a portion surrounded by a two-dot chain line in FIG. 8). See). For this reason, the semiconductive intermediate layer 161a on the first lower electrode layer 150a is not electrically connected to the in-dent formation layer 161b adjacent thereto. The same applies to the semiconductive intermediate layer 161a on the second lower electrode layer 150b and the in-dent formation layer 161b adjacent thereto.
- the leakage current between the first lower electrode layer 150a and the second lower electrode layer 150b can be prevented more reliably and crosstalk can be prevented than in the display panel 10 according to the first embodiment. Does not occur.
- the resist 501 for forming the lower electrode layer 150 is formed. Without being removed, it is used as it is as a mask when forming the recess 143a of the planarizing film 143. Therefore, it is not necessary to use a new mask for forming the recess 143a, the manufacturing process can be simplified, and the manufacturing cost can be reduced.
- the depth of the recess 143a in the planarizing film 143 is set to the thickness of the recess-forming layer 161b formed on the bottom surface of the recess 143a (the center of the recess 143a).
- the film thickness is deeper than the thickness of the film. This is for the purpose of completely separating the in-cavity forming layer 161b from the semiconductive intermediate layer 161a or the lower electrode layer 150.
- Embodiment 3 Configuration of Display Panel 14
- the organic EL display device according to the present embodiment also has the same configuration as the organic EL display devices 1,... According to Embodiments 1 and 2 except for the configuration of the display panel 14. Below, the structure of the display panel 14 is demonstrated using FIG.
- the display panel 14 also includes sub-pixels 15a each including an organic light-emitting layer having a light emission color of red (R), green (G), or blue (B). 15b and 15c are adjacently formed, and are a top emission type organic EL display.
- sub-pixels 15a each including an organic light-emitting layer having a light emission color of red (R), green (G), or blue (B).
- 15b and 15c are adjacently formed, and are a top emission type organic EL display.
- the TFT layer formed on the substrate 100 (only the source 101a is also shown in FIG. 11), the passivation film 102, and the contact hole 104 provided in the planarization film 183 are related to the first and second embodiments. It has the same configuration as the display panels 10 and 12.
- a recess 183 a is formed in a region between the lower electrode layers (anode layers) 190 in the planarization film 183.
- the semiconducting layer 201 is formed on the lower electrode layer 190 and has a semiconducting intermediate layer 201a that functions as a hole injection layer, a hole transport layer, or a hole injection / transport layer, and a depression 183a in the planarization film 183.
- the in-recessed portion forming layer 201b which is a layer made of the same material as the semiconductive intermediate layer 201a.
- a light emitting layer 202, an electron injection layer 204, an upper electrode layer (cathode layer) 210, and a sealing layer 211 are stacked in this order on the semiconducting intermediate layer 201a.
- a partition wall 203 that divides 15a, 15b, and 15c is provided upright.
- a light emitting laminate 200 is configured by the semiconductive intermediate layer 201 a, the light emitting layer 202, the partition wall 203, and the electron injection layer 204.
- the first light emitting layer 202a formed above the first lower electrode layer 190a and the second lower electrode layer are formed as in the display panels 10 and 12 according to the first and second embodiments.
- a so-called pixel bank is also used for the partition wall 203 of the display panel 14 according to the present embodiment.
- a recess 183a is provided in a region between the first lower electrode layer 190 a and the second lower electrode layer 190 b in the planarization film 183.
- the depression 183a in the flattening film 183 is the same as the display panels 10 and 12 according to the first and second embodiments described above in that the depressed portion 183a sinks from the other upper surface of the flattening film 183a.
- the point that the dent part forming layer 201b is formed on the bottom surface of the dent part 183a is the same as the display panels 10 and 12 according to the first and second embodiments.
- the upper end edge (location P 3 ) of the recess 183 a in the planarization film 183 is the end of the lower electrode layer 190. It is in a state of entering the lower electrode layer 190 below the edge (location P 4 ). Therefore, in the display panel 14 according to the present embodiment, the portion of the side surface 183s of the recess 183a in the planarization film 183 that enters the lower electrode layer 190 (the portion indicated by the arrow B) has a semiconductor layer. By having a region where 201 is not formed, the semiconductive intermediate layer 201a on the first lower electrode layer 190a and the semiconductive intermediate layer 201a on the second lower electrode layer 190b are separated in this region.
- the semiconductor intermediate layers 201a in the subpixels 15a, 15b, and 15c are not continuously formed across the recess 183a between them. Therefore, in the display panel 14, the semiconductive layer 201 does not electrically connect the first lower electrode layer 190a and the second lower electrode layer 190b, and the first lower electrode layer 190a and the second lower electrode layer 190b are not connected. Leakage current can be prevented. In the present embodiment, since at least a part of the recess 183a enters the lower electrode layer 190 and the semiconductor layer 201 is divided at the entered portion, the display according to the second embodiment Leakage current between the first lower electrode layer 190a and the second lower electrode layer 190b can be prevented more reliably than the panel 12.
- the partition wall 203 is also formed so as to enter the recessed shape portion with the formation of the recessed portion 183 a of the planarization film 183. As described above, the partition wall 203 is difficult to peel off, and the organic EL display device has high reliability.
- the TFT layer (FIG. 12A) is formed on the substrate 100 by executing the steps shown in FIGS. 5A to 5C in the first embodiment. ), Only the source 101a is shown), the passivation film 102, the planarization film 1831, the contact hole 104, and the metal film 1900 are formed.
- a photosensitive resist 502 is deposited on the region on the metal film 1900 where the lower electrode layer 190 is to be formed. Then, as shown in FIG. 12B, patterning is performed by photolithography and etching to form the lower electrode layer 190 including the first lower electrode layer 190a and the second lower electrode layer 190b. In the manufacturing method according to the present embodiment, both edges 190 s of the lower electrode layer 190 coincide with the edges of the resist 502 after etching as shown in FIG.
- etching for example, dry etching
- a recess 183a is formed in a region 1831f where the resist 502 is not formed between the first lower electrode layer 190a and the second lower electrode layer 190b (FIG. 12C). See).
- the manufacturing method according to the present embodiment at least a part of the side surface 183s of the recess 183a is obtained by changing the etching conditions (for example, the etching time) with respect to the manufacturing method according to the second embodiment.
- the lower electrode layer 190 may enter below.
- the formation of the recessed portion 183a of the planarizing film 183 is not limited to dry etching, and can be performed by wet etching.
- a semiconducting material 201 is deposited on the bottom surfaces of the recesses 183a in the lower electrode layer 190 and the planarizing film 183, and the semiconducting layer 201 is laminated.
- the semiconducting layer 201 includes a semiconducting intermediate layer 201 a on the lower electrode layer 190, and a indentation portion forming layer 201 b on the bottom surface of the indentation portion 183 a of the planarization film 183.
- the recess 183a is deposited in a state where a semiconductor material is deposited.
- the semiconductor layer 201 is surely divided at at least a part of the side surface 183s.
- an insulating material layer for forming the partition wall 203 is formed on the semiconducting layer 201 by, for example, a spin coating method, and patterned by exposure and development using a photomask. Thereafter, the partition 203 is formed by performing cleaning with a cleaning liquid as shown in FIG.
- the composition ink containing the material of the light emitting layer 202 is dropped onto the region defined by the partition wall 203 by an ink jet method and dried to form the light emitting layer 202. Further, an electron injection layer 204, an upper electrode layer 210, and a sealing layer 211 are stacked on the light emitting layer 202.
- the light emitting layer 202 in addition to the inkjet method, for example, a dispenser method, a nozzle coating method, a spin coating method, an intaglio printing method, as in the manufacturing methods according to the first and second embodiments.
- a relief printing method or the like can be used.
- vacuum drying and drying in a nitrogen atmosphere are sequentially performed.
- the electron injection layer 204 can be formed by using, for example, a vacuum deposition method, as in the manufacturing methods according to the first and second embodiments.
- a vacuum deposition method for example, plasma coating is used. Can be used.
- a recess 183a is formed between the first lower electrode layer 190a and the second lower electrode layer 190b in the planarization film 183. Since the semiconductor layer 201 is formed in a state where the semiconductor layer 201 is formed, a region where the semiconductor layer 201 is not formed in at least a part of the side surface 183s of the recess 183a is generated due to the shadowing effect (enclosed by a two-dot chain line in FIG. 11). See section). For this reason, the semiconductive intermediate layer 201a on the first lower electrode layer 190a is not electrically connected to the in-dent formation layer 201b adjacent thereto. The same applies to the semiconducting intermediate layer 201a on the second lower electrode layer 190b and the in-dent formation layer 201b adjacent thereto.
- the semiconductor layer 201 can be more reliably divided.
- the display panel 14 can more reliably prevent the leakage current between the first lower electrode layer 190a and the second lower electrode layer 190b than the display panels 10 and 12 according to the first and second embodiments. No crosstalk.
- the resist 502 for forming the lower electrode layer 190 is formed. Without being removed, it is used as it is as a mask when forming the recess 183a of the planarization film 183. Therefore, it is not necessary to use a new mask for forming the recess 183a, the manufacturing process can be simplified, and the manufacturing cost can be reduced.
- the depth of the depression 183a in the planarization film 183 is set to the thickness of the in-well formation layer 201b formed on the bottom surface of the depression 183a (the center of the depression 183a).
- the film thickness is deeper than the film thickness at the portion. This is for the purpose of completely separating the in-dent formation layer 201b from the semiconductive intermediate layer 201a or the lower electrode layer 190.
- the organic EL display device according to the present embodiment also has the same configuration as the organic EL display devices 1,... According to the above-described first, second, and third embodiments except for the configuration of the display panel 16. . Below, the structure of the display panel 16 is demonstrated using FIG.
- the display panel 16 also includes sub-pixels 17a each including an organic light-emitting layer having a light emission color of red (R), green (G), or blue (B). 17b and 17c are formed adjacent to each other, which is a top emission type organic EL display.
- the TFT layer formed on the substrate 100 (only the source 101a is shown in FIG. 14), the passivation film 102, and the contact hole 104 provided in the planarization film 223 are implemented as described above.
- the display panels 10 and 12 according to the first and second embodiments have the same configuration.
- a recess 223 a is formed in a region between the lower electrode layers (anode layers) 230 in the planarizing film 223.
- the semiconducting layer 241 is formed on the lower electrode layer 230 and has a semiconducting intermediate layer 241a functioning as a hole injection layer, a hole transport layer, or a hole injection / transport layer, and a recess 223a in the planarization film 223.
- the hollow intermediate layer 241a is formed on the bottom surface of each of the first and second recess formation layers 241b, which are layers of the same material.
- the lower electrode layer 230 has a laminated structure of the metal layer 2301 and the transparent conductive layer 2302.
- the first lower electrode layer 230a belonging to the subpixel 17a has a stacked structure of the first metal layer 2301a and the first transparent conductive layer 2302a.
- the second lower electrode layer 230b belonging to the subpixel 17b The second metal layer 2301b and the second transparent conductive layer 2302b have a laminated structure.
- a light emitting layer 242, an electron injection layer 244, an upper electrode layer (cathode layer) 250, and a sealing layer 251 are sequentially stacked on the semiconductive intermediate layer 241a.
- a partition wall 243 that divides 17a, 17b, and 17c is provided upright.
- a light emitting laminate 240 is configured by the semiconductive intermediate layer 241 a, the light emitting layer 242, the partition 243, and the electron injection layer 244. Note that, in the light emitting layer 242, as in the display panels 10, 12, and 14 according to the first, second, and third embodiments, the first light emitting layer 242 is formed above the first transparent conductive layer 2302a in the first lower electrode layer 230a.
- the first light emitting layer 242a and the second light emitting layer 242b formed above the second transparent conductive layer 2302b in the second lower electrode layer 230b are included.
- a so-called pixel bank is also used for the partition 243 of the display panel 16 according to the present embodiment.
- a recess 223 a is provided in a region between the first lower electrode layer 230 a and the second lower electrode layer 230 b in the planarization film 223.
- the depression 223a in the flattening film 223 is the same as the display panels 10, 12, and 14 according to the first, second, and third embodiments, in that the hollow portion 223a is depressed below the other upper surface of the flattening film 223a.
- the point in which the hollow part formation layer 241b is formed on the bottom surface of the hollow part 223a is the same as that of the display panels 10, 12, and 14 according to the first, second, and third embodiments.
- the display panel 16 As shown in a portion surrounded by a two-dot chain line in FIG. 14, the display panel 16 according to the present embodiment, the upper edge of the recess 223a in the planarization film 223 (portion P 5), to the third embodiment Similar to the display panel 14, the lower electrode layer 230 enters the lower electrode layer 230 below the edge (location P 6 ) of the transparent conductive layer 2302. In the lower electrode layer 230, the side edge of the metal layer 2301 is covered with the transparent conductive layer 2302.
- the portion of the side surface 223 s of the recess 223 a in the planarization film 223 that enters the lower electrode layer 230 below the transparent conductive layer 2302. By having a region in which the semiconducting layer 241 is not formed in the portion (indicated by arrow C), the semiconductor intermediate layer 241a on the first lower electrode layer 230a and the semiconductor on the second lower electrode layer 230b in the region.
- the intermediate layer 241a is divided.
- the semiconductor intermediate layers 241a in the sub-pixels 17a, 17b, and 17c are not continuously formed across the depressions 223a between each other. Therefore, in the display panel 16, the semiconductive layer 241 does not electrically connect the first lower electrode layer 230a and the second lower electrode layer 230b, and the first lower electrode layer 230a and the second lower electrode layer 230b are not connected. Leakage current can be prevented.
- the recess 223a enters below the transparent conductive layer 2302 of the lower electrode layer 230, and the semiconductor layer 241 is divided at the entered part, so that Similarly to the display panel 14 according to the third aspect, it is possible to reliably prevent a leakage current between the first lower electrode layer 230a and the second lower electrode layer 230b.
- the partition wall 243 is formed so as to enter the recessed shape portion with the formation of the recessed portion 223 a of the planarizing film 223. Similarly to the above, the partition wall 243 is hardly peeled off, and the organic EL display device has high reliability.
- the TFT layer (FIG. 15A) is formed on the substrate 100 by executing the steps shown in FIGS. 5A to 5C in the first embodiment. ), Only the source 101a is shown), a passivation film 102, a planarization film 2231, a contact hole 104, and a metal film 2303 are formed.
- a photosensitive resist 503 is deposited on the metal film 2303 in a region where the metal layer 2301 of the lower electrode layer 230 is to be formed.
- patterning is performed by a photolithography method and an etching method, and the lower electrode layer 230 including the metal layer 2301a in the first lower electrode layer 230a and the metal layer 2301b in the second lower electrode layer 230b is formed.
- a metal layer 2301 is formed.
- both edges 2301s of the metal layer 2301 in the lower electrode layer 230 coincide with the edges of the resist 503 after the etching, as shown in FIG. To do.
- the resist 503 is removed from the metal layer 2301 of the lower electrode layer 230. Then, as shown in FIG. 15C, a transparent conductive film 2304 is formed so as to cover the metal layer 2301 and the exposed surface 2231f of the planarization film 2231 exposed between the metal layers 2301. For example, a sputtering method can be used for forming the transparent conductive film 2304.
- a photosensitive resist 504 is deposited on the transparent conductive film 2304 in a region of the lower electrode layer 230 where the transparent conductive layer 2302 is to be formed.
- the transparent conductive layer 2302 including the transparent conductive layer 2302a and the transparent conductive layer 2302b can be patterned.
- the lower electrode layer 230 including the first lower electrode layer 230a and the second lower electrode layer 230b can be formed.
- etching for example, dry etching
- etching is performed using the transparent conductive layer 2302 in the lower electrode layer 230 as a mask.
- etching for example, dry etching
- the planarizing film 223 a recess 223a is formed in a region 2231g between the first lower electrode layer 230a and the second lower electrode layer 230b (see FIG. 16B).
- the etching conditions for example, the etching time.
- the lower electrode layer 230 may enter below the transparent conductive layer 2302.
- the formation of the recess 223a of the planarization film 223 is not limited to dry etching, and can be performed by wet etching.
- a semiconducting material is deposited on the transparent conductive layer 2302 in the lower electrode layer 230 and on the bottom surface of the recess 223 a in the planarizing film 223, thereby forming the semiconducting layer.
- 241 is laminated.
- the semiconducting layer 241 includes a semiconducting intermediate layer 241 a on the transparent conductive layer 2302 in the lower electrode layer 230, and an indentation portion forming layer 241 b on the bottom surface of the indentation portion 223 a of the planarizing film 223. Note that, as shown in FIG.
- the semiconductor material is deposited.
- the semiconductor layer 241 is reliably divided at at least a part of the side surface 223s of the recess 223a.
- an insulating material layer for forming the partition wall 243 is formed on the semiconducting layer 241 by, for example, a spin coating method, and patterned by exposure and development using a photomask. Thereafter, the partition wall 243 is formed by performing cleaning with a cleaning liquid as shown in FIG.
- the composition ink containing the material of the light emitting layer 242 is dropped onto the region defined by the partition wall 243 by an ink jet method and dried to form the light emitting layer 242. Further, an electron injection layer 244, an upper electrode layer 250, and a sealing layer 251 are stacked on the light emitting layer 242.
- a dispenser method for example, a dispenser method, a nozzle coating method, a spin coating method, intaglio printing, as in the manufacturing methods according to the first, second, and third embodiments.
- a letterpress printing method can be used.
- drying the composition ink vacuum drying and drying in a nitrogen atmosphere are sequentially performed.
- a vacuum deposition method can be used as in the manufacturing methods according to the first, second, and third embodiments.
- a plasma coating method can be used for the formation of the upper electrode layer 250.
- a recess 223a is formed between the first lower electrode layer 230a and the second lower electrode layer 230b in the planarization film 223. Since the semiconducting layer 241 is formed in a state in which the semiconducting layer is formed, a region where the semiconducting layer 241 is not formed in at least a part of the side surface 223s of the recess 223a is generated due to the shadowing effect (enclosed by a two-dot chain line in FIG. See section). For this reason, the semiconductive intermediate layer 201a on the first lower electrode layer 190a is not electrically connected to the in-dent formation layer 241b adjacent thereto. The same applies to the semiconductive intermediate layer 241a on the second lower electrode layer 230b and the in-dent formation layer 241b adjacent thereto.
- the semiconductor layer 241 is more surely formed. Can be divided.
- the leakage current between the first lower electrode layer 230a and the second lower electrode layer 230b can be more reliably prevented, and crosstalk can be prevented. Does not occur.
- the transparent conductive layer 2302 in the lower electrode layer 230 is formed, and the recess 223a of the planarizing film 223 is formed. It is used as a mask when Therefore, it is not necessary to use a new mask for forming the recess 223a, the manufacturing process can be simplified, and the manufacturing cost can be reduced.
- the depth of the recess 223a in the planarizing film 223 is set to the thickness of the recess-forming layer 241b formed on the bottom surface of the recess 223a (the center of the recess 223a).
- the film thickness is deeper than the film thickness at the portion. This is for the purpose of completely separating the in-dent formation layer 241b from the semiconductive intermediate layer 241a or the lower electrode layer 230.
- so-called pixel banks are used for the partition walls 123, 163, 203, and 243, but the present invention is not limited to this.
- a so-called line bank-structured partition wall 263 may be employed to partition the light emitting layers of the subpixels 19a, 19b, and 19c in the X-axis direction.
- the organic EL display device 1,... is used as an example of the light emitting device, but the present invention is not limited to this.
- the present invention can be applied to a lighting device.
- the configuration of the lower electrode layer 230 according to the fourth embodiment can be applied instead of the lower electrode layers 110 and 150 according to the first and second embodiments.
- the lower electrode layers 110, 150, 190, and 230 are anodes
- the upper electrode layers 130, 170, 210, and 250 are cathodes.
- a configuration in which the positions of the anode and the cathode are reversed may be employed.
- the top emission type organic EL display device is used.
- a bottom emission type organic EL display device may be used.
- the shape and size of the recesses 103a, 143a, 183a, and 223a of the planarizing films 103, 143, 183, and 223 are not limited to those shown in the attached drawings.
- the leakage current between the lower electrode layers can be more reliably prevented by increasing the depth of the recess.
- the present invention is useful for realizing a light emitting device having no light emission performance and no crosstalk.
- Subpixel 20. Drive control unit 21, 22, 23, 24. Drive circuit 25.
- Control circuit 31. Source signal wiring 32. Power supply wiring 100.
- Source 102. Passivation film 103,143,183,223. Planarization films 103a, 143a, 183a, 223a. Hollow part 104.
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Abstract
Description
本発明の一態様に係る発光装置は、基板の上方に形成され、窪み部を有する平坦化膜と、前記平坦化膜上であって前記窪み部の形成領域外に形成された第1下部電極層と、前記平坦化膜上であって前記窪み部の形成領域外に前記窪み部を挟んで前記第1下部電極層と隣接して形成された第2下部電極層と、前記第1下部電極層および前記第2下部電極層の上方に形成された半導体性中間層と、 前記第1下部電極層の端部、前記第1下部電極層と隣接する前記第2下部電極層の端部、および前記平坦化膜の窪み部を覆って形成された隔壁と、を具備し、前記平坦化膜の窪み部は、前記第1下部電極層および前記第2下部電極層との間で、前記平坦化膜の他の上面よりも沈下し、前記平坦化膜の窪み部の上面には、前記半導体性中間層と同一材料の層が形成されており、前記平坦化膜の窪み部の上面に形成された前記半導体性中間層と同一材料の層の端部の膜厚は、前記平坦化膜の窪み部の上面に形成された前記半導体性中間層と同一材料の層の中央部の膜厚よりも薄い。
1.表示装置1の全体構成
以下では、発光装置の一例としての有機EL表示装置1で説明する。
表示パネル10の構成について、図3および図4を用い説明する。
基板100は、例えば、無アルカリガラス、ソーダガラス、無蛍光ガラス、燐酸系ガラス、硼酸系ガラス、石英、アクリル系樹脂、スチレン系樹脂、ポリカーボネート系樹脂、エポキシ系樹脂、ポリエチレン、ポリエステル、シリコーン系樹脂、又はアルミナ等の絶縁性材料をベースとして形成されている。
平坦化膜103は、例えば、ポリイミド、ポリアミド、アクリル系樹脂材料などの有機化合物を用い形成されている。
下部電極層110は、例えば、Ag(銀)、APC(銀、パラジウム、銅の合金)、ARA(銀、ルビジウム、金の合金)、MoCr(モリブデンとクロムの合金)、NiCr(ニッケルとクロムの合金)などから形成されている。なお、本実施の形態のように、トップエミッション型の有機ELの場合には、高反射性の材料を用い形成されていることが好ましい。
半導体性層121は、例えば、WOX(酸化タングステン)またはMoWOX(モリブデン-タングステン酸化物)などの金属酸化物、あるいは金属窒化物または金属酸窒化物を用い形成されている。
発光層122は、ホールと電子とが注入され再結合されることにより励起状態が生成され発光する機能を有する。発光層122の形成に用いる材料は、湿式印刷法を用い製膜できる発光性の有機材料を用いることが必要である。
隔壁123は、樹脂等の有機材料で形成されており絶縁性を有する。隔壁123の形成に用いる有機材料の例としては、アクリル系樹脂、ポリイミド系樹脂、ノボラック型フェノール樹脂等があげられる。隔壁123は、有機溶剤耐性を有することが好ましい。さらに、隔壁123はエッチング処理、ベーク処理など施されることがあるので、それらの処理に対して過度に変形、変質などをしないような耐性の高い材料で形成されることが好ましい。また、撥水性をもたせるために、表面をフッ素処理することもできる。
電子注入層124は、上部電極層130から注入された電子を発光層122へ輸送する機能を有し、例えば、バリウム、フタロシアニン、フッ化リチウム、あるいはこれらの組み合わせで形成されることが好ましい。
上部電極層(陰極層)130は、例えば、ITO、IZO(酸化インジウム亜鉛)などで形成される。トップエミッション型の有機EL素子100a,100b,100cの場合においては、光透過性の材料で形成されることが好ましい。光透過性については、透過率が80[%]以上とすることが好ましい。
封止層131は、発光層122などが水分に晒されたり、空気に晒されたりすることを抑制する機能を有し、例えば、SiN(窒化シリコン)、SiON(酸窒化シリコン)などの材料を用い形成される。トップエミッション型の場合においては、光透過性の材料で形成されることが好ましい。
図3に示すように、本実施の形態に係る有機EL表示装置1では、表示パネル10において、平坦化膜103における第1下部電極層110aと第2下部電極層110bとの間に窪み部103aが設けられている。平坦化膜103における窪み部103aは、平坦化膜103aの他の上面よりも沈下しており、窪み部103aの上面には、窪み部内形成層121bが形成されている。そして、図3の二点鎖線で囲む部分に示すように、平坦化膜103の窪み部103aにおける窪み部内形成層121bは、端部での膜厚t2が、それよりも中央部側の膜厚t1よりも薄くなっている。
表示パネル10の製造方法について、図5から図7を用い説明する。なお、図5から図7においても、一部を抜き出し、模式的に示している。
1.表示パネル10の構成
本実施の形態に係る有機EL表示装置では、表示パネル12の構成を除き、上記実施の形態1に係る有機EL表示装置1と同一の構成を有する。以下では、表示パネル12の構成について、図8を用い説明する。
図8に示すように、本実施の形態に係る表示パネル12においても、平坦化膜143における第1下部電極層150aと第2下部電極層150bとの間の領域に窪み部143aが設けられている。平坦化膜143における窪み部143aは、平坦化膜143aの他の上面よりも沈下している点で、上記実施の形態1に係る表示パネル10と同様である。また、窪み部143aの底面上に、窪み部内形成層161bが形成されている点も、上記実施の形態1に係る表示パネル10と同様である。
表示パネル12の製造方法について、図9および図10を用い説明する。なお、図9および図10においても、一部を抜き出し、模式的に示している。
1.表示パネル14の構成
本実施の形態に係る有機EL表示装置でも、表示パネル14の構成を除き、上記実施の形態1,2に係る有機EL表示装置1,・・と同一の構成を有する。以下では、表示パネル14の構成について、図11を用い説明する。
図11に示すように、本実施の形態に係る表示パネル14においても、平坦化膜183における第1下部電極層190aと第2下部電極層190bとの間の領域に窪み部183aが設けられている。平坦化膜183における窪み部183aは、平坦化膜183aの他の上面よりも沈下している点で、上記実施の形態1,2に係る表示パネル10,12と同様である。また、窪み部183aの底面上に、窪み部内形成層201bが形成されている点も、上記実施の形態1,2に係る表示パネル10,12と同様である。
表示パネル14の製造方法について、図12および図13を用い説明する。なお、図12および図13においても、一部を抜き出し、模式的に示している。
1.表示パネル16の構成
本実施の形態に係る有機EL表示装置でも、表示パネル16の構成を除き、上記実施の形態1,2,3に係る有機EL表示装置1,・・と同一の構成を有する。以下では、表示パネル16の構成について、図14を用い説明する。
図14に示すように、本実施の形態に係る表示パネル16においても、平坦化膜223における第1下部電極層230aと第2下部電極層230bとの間の領域に窪み部223aが設けられている。平坦化膜223における窪み部223aは、平坦化膜223aの他の上面よりも沈下している点で、上記実施の形態1,2,3に係る表示パネル10,12,14と同様である。また、窪み部223aの底面上に、窪み部内形成層241bが形成されている点も、上記実施の形態1,2,3に係る表示パネル10,12,14と同様である。
表示パネル16の製造方法について、図15から図17を用い説明する。なお、図15から図17においても、一部を抜き出し、模式的に示している。
上記実施の形態1,2,3,4では、隔壁123,163,203,243について、所謂、ピクセルバンクを採用したが、必ずしもこれに限られない。例えば、図18に示すように、所謂、ラインバンク構造の隔壁263を採用し、これにより、X軸方向でのサブピクセル19a,19b,19cの各発光層を区画することとしてもよい。
10,12,14,16,18.表示パネル
11a,11b,11c,13a,13b,13c,15a,15b,15c,17a,17b,17c,19a,19b,19c.サブピクセル
20.駆動制御部
21,22,23,24.駆動回路
25.制御回路
31.ソース信号配線
32.電源配線
100.基板
101.TFT
101a.ソース
102.パッシベーション膜
103,143,183,223.平坦化膜
103a,143a,183a,223a.窪み部
104.コンタクトホール
110,150,190,230.下部電極層
110a,150a,190a,230a.第1下部電極層
110b,150b,190b,230b.第2下部電極層
120,160,200,240.発光積層体
121,161,201,241.半導体性層
121a,161a,201a,241a.半導体性中間層
121b,161b,201b,241b.窪み部内形成層
122,162,202,242.発光層
122a,162a,202a,242a.第1発光層
122b,162b,202b,242b.第2発光層
123,163,203,243,263.隔壁
124,164,204,244.電子注入層
130,170,210,250.上部電極層
131,171,211,251.封止層
143s,183s,223s.窪み部側面
500,501,502,503,504.レジスト
1030,1031,1431,1831,2231.平坦化膜
1100,1500,1900.金属膜
2301.金属層
2301a.第1金属層
2301b.第2金属層
2302.透明導電層
2302a.第1透明導電層
2302b.第2透明導電層
2303.金属膜
2304.透明導電膜
Claims (16)
- 基板の上方に形成され、窪み部を有する平坦化膜と、
前記平坦化膜上であって前記窪み部の形成領域外に形成された第1下部電極層と、
前記平坦化膜上であって前記窪み部の形成領域外に前記窪み部を挟んで前記第1下部電極層と隣接して形成された第2下部電極層と、
前記第1下部電極層および前記第2下部電極層の上方に形成された半導体性中間層と、
前記第1下部電極層の端部、前記第1下部電極層と隣接する前記第2下部電極層の端部、および前記平坦化膜の窪み部を覆って形成された隔壁と、を具備し、
前記平坦化膜の窪み部は、前記第1下部電極層および前記第2下部電極層との間で、前記平坦化膜の他の上面よりも沈下し、
前記平坦化膜の窪み部の上面には、前記半導体性中間層と同一材料の層が形成されており、
前記平坦化膜の窪み部の上面に形成された前記半導体性中間層と同一材料の層の端部の膜厚は、前記平坦化膜の窪み部の上面に形成された前記半導体性中間層と同一材料の層の中央部の膜厚よりも薄い
発光装置。 - 基板の上方に形成され、窪み部を有する平坦化膜と、
前記平坦化膜上であって前記窪み部の形成領域外に形成された第1下部電極層と、
前記平坦化膜上であって前記窪み部の形成領域外に前記窪み部を挟んで前記第1下部電極層と隣接して形成された第2下部電極層と、
前記第1下部電極層および前記第2下部電極層の上方に形成された半導体性中間層と、
前記第1下部電極層の端部、前記第1下部電極層と隣接する前記第2下部電極層の端部、および前記平坦化膜の窪み部を覆って形成された隔壁と、を具備し、
前記平坦化膜の窪み部は、前記第1下部電極層および前記第2下部電極層との間で、前記平坦化膜の他の上面よりも沈下し、
前記平坦化膜の窪み部の上面には、前記半導体性中間層と同一材料の層が形成されており、
前記窪み部の側面は、前記半導体性中間層と同一材料の層が形成されていない領域を有し、
前記半導体性中間層と、前記平坦化膜の窪み部の上面に形成された前記半導体性中間層と同一材料の層とは、前記窪み部の側面において前記半導体性中間層と同一材料の層が形成されていない領域により分断されている
発光装置。 - 前記窪み部の側面は、前記第1下部電極層および前記第2下部電極層の各々の下方に入り込んだ形状である
請求項2に記載の発光装置。 - 前記第1下部電極層には、前記半導体性中間層側に第1透明導電膜による層が含まれ、
前記第2下部電極層には、前記半導体性中間層側に第2透明導電膜による層が含まれ、
前記半導体性中間層は、前記第1透明導電膜による層上および前記第2透明導電膜による層上に形成されている
請求項1から請求項3の何れか1項に記載の発光装置。 - 前記基板と前記平坦化膜との間には、TFT層が形成され、
前記平坦化膜は、前記TFT層上に形成されている
請求項1から請求項4の何れか1項に記載の発光装置。 - 前記第1下部電極層の上方であって前記半導体性中間層上に形成された第1発光層と、
前記第2下部電極層の上方であって前記半導体性中間層上に形成された第2発光層と、を具備し、
前記隔壁は、前記第1発光層と前記第2発光層とを区画する
請求項1から請求項4の何れか1項に記載の発光装置。 - 前記第1発光層および前記第2発光層の上方に形成された上部電極層を具備する
請求項6に記載の発光装置。 - 前記上部電極層は、陰極層である
請求項6に記載の発光装置。 - 前記第1下部電極層および前記第2下部電極層は、陽極層であり、
前記半導体性中間層は、正孔注入層である
請求項1から請求項8の何れか1項に記載の発光装置。 - 前記窪み部の深さは、前記平坦化膜の窪み部の上面に形成された前記半導体性中間層と同一材料の層の中央部の膜厚よりも大きい
請求項1から請求項9の何れか1項に記載の発光装置。 - 基板を準備する第1工程と、
前記基板の上方に平坦化膜を形成する第2工程と、
前記平坦化膜上に第1下部電極層と第2下部電極層とを形成する第3工程と、
前記第1下部電極層と前記第2下部電極層との上にレジストを形成する第4工程と、
前記第1下部電極層と前記第2電極層との間の、前記レジストが形成されていない前記平坦化膜の領域をエッチングすることにより、前記レジストが形成されていない前記平坦化膜の領域の前記平坦化膜の上面が、前記平坦化膜の他の上面よりも沈下した窪み部を形成する第5工程と、
前記第1下部電極層上、前記第2下部電極層上、および前記窪み部の底面上に半導体性中間層を形成する第6工程と、を含み、
前記平坦化膜の窪み部の上面に形成された前記半導体性中間層の端部の膜厚を、前記平坦化膜の窪み部の上面に形成された前記半導体性中間層の中央部の膜厚よりも薄く形成する
発光装置の製造方法。 - 基板を準備する第1工程と、
前記基板の上方に平坦化膜を形成する第2工程と、
前記平坦化膜上に第1下部電極層と第2下部電極層とを形成する第3工程と、
前記第1下部電極層および前記第2下部電極層自体をマスクとして、前記第1下部電極層と前記第2下部電極層との間の前記平坦化膜の領域をエッチングすることにより、前記第1下部電極層と前記第2下部電極層との間の前記平坦化膜の領域に、前記平坦化膜の他の上面よりも沈下した窪み部を形成する第4工程と、
前記第1下部電極層上、前記第2下部電極層上、および前記窪み部の底面上に半導体性中間層を形成する第5工程と、を含み、
前記窪み部の側面は、前記半導体性中間層が形成されていない領域を有し、
前記半導体性中間層を、前記窪み部の側面において前記半導体性中間層が形成されていない領域により分断する
発光装置の製造方法。 - 前記第4工程において、
前記第4工程のエッチングにより、前記第1下部電極層と前記第2下部電極層との間の前記平坦化膜に形成された窪み部は、その側面が前記第1下部電極層および前記第2下部電極層の各々の下方に入り込んだ形状である
請求項12に記載の発光装置の製造方法。 - 前記エッチングは、ドライエッチングである
請求項12または請求項13に記載の発光装置の製造方法。 - 前記第1下部電極層には、前記半導体性中間層側に第1透明導電膜による層が含まれ、
前記第2下部電極層には、前記半導体性中間層側に第2透明導電膜による層が含まれ、
前記第6工程において、前記半導体性中間層は、前記第1透明導電膜による層上および前記第2透明導電膜による層上に形成される
請求項11に記載の発光装置の製造方法。 - 前記第1下部電極層には、前記半導体性中間層側に第1透明導電膜による層が含まれ、
前記第2下部電極層には、前記半導体性中間層側に第2透明導電膜による層が含まれ、
前記第5工程において、前記半導体性中間層は、前記第1透明導電膜による層上および前記第2透明導電膜による層上に形成される
請求項12に記載の発光装置の製造方法。
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