WO2011030559A1 - 不揮発性記憶装置及びその製造方法 - Google Patents
不揮発性記憶装置及びその製造方法 Download PDFInfo
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- WO2011030559A1 WO2011030559A1 PCT/JP2010/005565 JP2010005565W WO2011030559A1 WO 2011030559 A1 WO2011030559 A1 WO 2011030559A1 JP 2010005565 W JP2010005565 W JP 2010005565W WO 2011030559 A1 WO2011030559 A1 WO 2011030559A1
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Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/021—Formation of switching materials, e.g. deposition of layers
- H10N70/026—Formation of switching materials, e.g. deposition of layers by physical vapor deposition, e.g. sputtering
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Shaping switching materials
- H10N70/063—Shaping switching materials by etching of pre-deposited switching material layers, e.g. lithography
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/883—Oxides or nitrides
- H10N70/8833—Binary metal oxides, e.g. TaOx
Definitions
- the present invention relates to a variable resistance nonvolatile memory device in which a resistance value is changed by application of a voltage pulse.
- variable resistance nonvolatile memory element is an element that has a property that the resistance value reversibly changes by an electrical signal, and that can store information corresponding to the resistance value in a nonvolatile manner.
- Patent Document 1 discloses that an oxidation / reduction reaction is selectively generated at an electrode interface in contact with a resistance change layer having a high oxygen content to stabilize the resistance change.
- the above-described conventional resistance change element includes a lower electrode, a resistance change layer, and an upper electrode, and the resistance change elements are arranged two-dimensionally or three-dimensionally to form a memory array.
- the variable resistance layer has a stacked structure of a first variable resistance layer and a second variable resistance layer, and the first and second variable resistance layers are made of the same kind of transition metal oxide.
- the oxygen content of the transition metal oxide forming the second resistance change layer is higher than the oxygen content of the transition metal oxide forming the first resistance change layer.
- the break voltage applied to the variable resistance element in the initial stage in order to make a transition to the state where the resistance change starts is high, and the resistance that constitutes the memory array
- the break voltage varies from one change element to another.
- the present invention has been made in order to solve the above-described problems, and is a resistance change type non-volatile that can lower the break voltage and suppress the variation of the break voltage among the resistance change elements. It is an object of the present invention to provide a storage device and a manufacturing method thereof.
- a first nonvolatile memory device of the present invention includes a substrate, a lower electrode formed on the substrate, and a first transition metal oxide formed on the lower electrode.
- a first variable resistance layer formed on the first variable resistance layer and a second transition metal oxide having an oxygen content higher than that of the first transition metal oxide.
- a top electrode formed on the second variable resistance layer, and there is a step at the interface between the first variable resistance layer and the second variable resistance layer, and the second variable resistance layer
- the layer is formed to cover the step and has a bent portion above the step.
- the bent portion refers to a portion where the second resistance change layer is bent in the stacking direction under the influence of a discontinuous step formed on the base, and has a gently stepped shape that changes continuously.
- a bent portion is formed in the second variable resistance layer on the step reflecting the step shape of the first variable resistance layer, so that the electric field starts from the bent portion.
- the concentration can cause a break phenomenon even at a low voltage.
- the step shape can be intentionally controlled, the break voltage variation does not increase by stabilizing the shape of the bent portion of the second resistance change layer. Therefore, it is possible to achieve both lowering of the break voltage and suppression of variation thereof, and it is possible to realize miniaturization and large capacity of the memory.
- a contact plug be provided below the lower electrode and the interface between the lower electrode and the first resistance change layer be flat.
- the lower electrode above the recess becomes thick, so that the surface of the lower electrode can be flattened.
- the shape and film thickness of the second resistance change layer in the bent portion depend only on the step shape of the first resistance change layer, and are not affected by the shape of the underlying layer. Therefore, it is possible to reduce variations in resistance change characteristics for each bit due to the base.
- a second nonvolatile memory device of the present invention includes a substrate, a lower electrode formed on the substrate, and a second transition metal oxide formed on the lower electrode.
- a first resistance metal layer formed on the second resistance change layer and a first transition metal oxide having an oxygen content lower than that of the second transition metal oxide.
- a resistance change layer and an upper electrode formed on the first resistance change layer, and there is a step at the interface between the lower electrode and the second resistance change layer. And having a bent portion above the step.
- the bent portion is formed in the second resistance change layer on the step reflecting the step shape of the lower electrode. Even a voltage can cause a break phenomenon.
- the step shape is intentionally controlled, the shape of the bent portion of the second variable resistance layer is stabilized, and the variation in the break voltage does not increase. Therefore, it is possible to achieve both lowering of the break voltage and suppression of variation thereof, and it is possible to realize miniaturization and large capacity of the memory.
- the bent portion of the second resistance change layer has a line shape when the second resistance change layer is viewed from above.
- a linear step pattern can be formed in the same pattern on the first variable resistance layer or the lower electrode across a plurality of adjacent variable resistance elements. Refinement is not a problem when forming. Therefore, since a low-cost mask can be used, the manufacturing cost can be reduced, and a manufacturing method for forming a line-shaped step pattern is also easy.
- the bent portion of the second variable resistance layer is ring-shaped when the second variable resistance layer is viewed from above. It is good also as a characteristic structure. With such a configuration, a longer step pattern can be formed in one resistance change element as compared with a line-shaped step pattern. Therefore, the length of the bent portion of the second variable resistance layer can be expanded, and the break voltage can be further reduced by increasing the region that is the starting point of the break. In some cases, it can be used in common with a mask for forming contact holes above and below the variable resistance element, so that the manufacturing cost can be reduced.
- the step of the first resistance change layer is composed of a plurality of steps, and there is an intersection where the plurality of steps intersect. It is good also as composition to do.
- the second resistance change layer formed on the second resistance change layer formed on the intersection at the intersection of the plurality of steps becomes more bent, so that the second resistance The change layer tends to be a thin film locally. Therefore, the electric field concentrates easily at this intersection, and the break location can be fixed.
- a filament can be formed in a portion where the influence of the oxidized region due to etching damage or the layer film insulating film is small. Therefore, variation in resistance change characteristics is extremely reduced, so that a nonvolatile memory device with little bit variation and good manufacturing yield can be realized.
- the first variable resistance layer and the second variable resistance layer may be composed of an oxide layer of tantalum, hafnium, or zirconium. These materials are excellent in the retention characteristics of the resistance change element and are capable of high-speed operation.Even if the material of the resistance change layer requires an initial break at the start of resistance change, The break characteristic can be extremely stabilized.
- a diode element may be formed in contact with the lower electrode or the upper electrode of the variable resistance element.
- a voltage distributed to the diode element must be added to increase the voltage applied to the memory cell, and there is a demand for lower voltage. Is big.
- the break voltage of the resistance change element can be lowered, the applied voltage of the memory cell can be lowered.
- the break phenomenon of the resistance change element occurs locally, the transient current that flows during the break can be reduced. Thereby, destruction of the diode element can also be prevented.
- a step of forming a lower electrode on a substrate and a first variable resistance layer made of a first transition metal oxide are formed on the lower electrode.
- the second method for manufacturing a non-volatile memory device includes a step of forming a lower electrode on a substrate, a step of forming a step on the surface of the lower electrode, and covering the step of the lower electrode.
- a step of forming a second variable resistance layer composed of two transition metal oxides and having a bent portion above the step, and an oxygen content ratio of the second transition on the second variable resistance layer Forming a first variable resistance layer composed of a first transition metal oxide having an oxygen content lower than that of the metal oxide; and forming an upper electrode on the first variable resistance layer. It is characterized by.
- the bent portion can be stably formed in the second variable resistance layer on the step reflecting the step shape of the base, and the bent portion serves as a starting point by electric field concentration. Even at a low voltage, a break phenomenon can occur. Further, since the step shape can be formed by intentionally controlling, the shape of the bent portion of the second variable resistance layer is stabilized, so that the variation in the break voltage does not increase. Therefore, it is possible to achieve both lowering of the break voltage and suppression of variation thereof, and it is possible to realize miniaturization and large capacity of the memory.
- the third method for manufacturing a nonvolatile memory device includes a step of forming a lower electrode on a substrate, and a first resistance change layer made of a first transition metal oxide on the lower electrode. And forming a second resistance change layer composed of a second transition metal oxide having an oxygen content higher than that of the first transition metal oxide on the first resistance change layer. Forming a step in the second variable resistance layer, then covering the step and further stacking the second variable resistance layer, and forming an upper electrode on the stacked second variable resistance layer And a step of forming.
- the above manufacturing method it is possible to form a thin film region where the electric field tends to concentrate on the second variable resistance layer, and a break phenomenon can occur even at a low voltage starting from this thin film region.
- the step shape can be intentionally controlled, the thickness variation of the second variable resistance layer can be stabilized, so that the variation of the break voltage does not increase. Therefore, it is possible to achieve both lowering of the break voltage and suppression of variation thereof, and it is possible to realize miniaturization and large capacity of the memory.
- a step is intentionally formed on the surface of the base layer of the second variable resistance layer, whereby the second variable resistance layer on the step is locally thinned or bent.
- the break voltage is reduced and the variation is reduced.
- the reduction of the break voltage and the improvement of the bit-by-bit variation can greatly contribute to the miniaturization and capacity increase of the memory.
- FIG. 1A is a cross-sectional view showing a configuration example of the nonvolatile memory device according to Embodiment 1 of the present invention.
- FIG. 1B is a plan view of a first variable resistance layer in the nonvolatile memory device.
- 2 (a) to 2 (k) are cross-sectional views illustrating a method for manufacturing the main part of the nonvolatile memory device according to Embodiment 1 of the present invention.
- 3 (a) to 3 (b) are cross-sectional views illustrating a method for manufacturing the main part of the nonvolatile memory device according to Embodiment 1 of the present invention.
- FIG. 4 (a) to 4 (e) are plan views showing a method for manufacturing the main part of the nonvolatile memory device according to Embodiment 1 of the present invention.
- FIG. 5A is a cross-sectional view showing a configuration example of the nonvolatile memory device according to Embodiment 2 of the present invention.
- FIG. 5B is a plan view of the first variable resistance layer in the nonvolatile memory device.
- 6 (a) to 6 (f) are cross-sectional views showing a method for manufacturing the main part of the nonvolatile memory device according to Embodiment 2 of the present invention.
- FIG. 7A to FIG. 7E are plan views showing a method for manufacturing the main part of the nonvolatile memory device according to Embodiment 2 of the present invention.
- FIG. 7A to FIG. 7E are plan views showing a method for manufacturing the main part of the nonvolatile memory device according to Embodiment 2 of the present invention.
- FIG. 8A is a cross-sectional view by SEM image of the main part in the step of forming a step in the first resistance change layer in the method for manufacturing the nonvolatile memory device in the second embodiment of the present invention.
- FIG. 8B is a graph showing a break voltage characteristic of the nonvolatile memory device according to Embodiment 2 of the present invention.
- FIG. 9A is a cross-sectional view showing a configuration example of the nonvolatile memory device according to Embodiment 3 of the present invention.
- FIG. 9B is a plan view of the lower electrode in the nonvolatile memory device.
- 10 (a) to 10 (g) are cross-sectional views illustrating a method for manufacturing the main part of the nonvolatile memory device according to Embodiment 3 of the present invention.
- FIG. 11 (a) to 11 (f) are plan views showing a method for manufacturing the main part of the nonvolatile memory device according to Embodiment 3 of the present invention.
- FIG. 12A is a cross-sectional view showing a configuration example of the nonvolatile memory device according to Embodiment 4 of the present invention.
- FIG. 12B is a plan view of the lower electrode in the nonvolatile memory device.
- 13 (a) to 13 (g) are cross-sectional views illustrating a method for manufacturing the main part of the nonvolatile memory device according to Embodiment 4 of the present invention.
- 14 (a) to 14 (f) are plan views showing a method for manufacturing the main part of the nonvolatile memory device according to Embodiment 4 of the present invention.
- FIG. 12A is a cross-sectional view showing a configuration example of the nonvolatile memory device according to Embodiment 4 of the present invention.
- FIG. 12B is a plan view of the lower electrode in the nonvol
- FIG. 15 is a cross-sectional view by SEM image of the main part in the step of forming a step in the lower electrode in the method for manufacturing the nonvolatile memory device in the fourth embodiment of the present invention.
- FIG. 16A is a cross-sectional view showing a configuration example of the nonvolatile memory device according to Embodiment 5 of the present invention.
- FIG. 16B is a plan view of the first variable resistance layer in the nonvolatile memory device.
- FIG. 16C is a perspective view of the first variable resistance layer in the nonvolatile memory device.
- 17 (a) to 17 (g) are cross-sectional views illustrating a method for manufacturing the main part of the nonvolatile memory device according to Embodiment 5 of the present invention.
- FIG. 18 (a) to 18 (c) are perspective views showing a method for manufacturing the main part of the nonvolatile memory device according to Embodiment 5 of the present invention.
- FIG. 19A is a cross-sectional view showing a configuration example of the nonvolatile memory device according to Embodiment 6 of the present invention.
- FIG. 19B is a plan view of the first variable resistance layer in the nonvolatile memory device.
- 20 (a) to 20 (g) are cross-sectional views showing a method for manufacturing the main part of the nonvolatile memory device according to Embodiment 6 of the present invention.
- FIG. 21A is a cross-sectional view showing a configuration example of the nonvolatile memory device according to Embodiment 7 of the present invention.
- 21B is a plan view of the first variable resistance layer in the nonvolatile memory device.
- 22 (a) to 22 (i) are cross-sectional views illustrating a method for manufacturing the main part of the nonvolatile memory device according to Embodiment 7 of the present invention.
- FIG. 23A is a cross-sectional view showing a configuration example of the nonvolatile memory device according to the modification of the seventh embodiment of the present invention.
- FIG. 23B is a plan view of the first variable resistance layer in the nonvolatile memory device.
- FIG. 24 is a cross-sectional view illustrating a configuration example of the nonvolatile memory device of the first comparative example.
- FIG. 25 is a cross-sectional view illustrating a configuration example of the nonvolatile memory device according to the second comparative example.
- FIG. 26A is a cross-sectional view of an SEM image of the nonvolatile memory device of the first comparative example.
- FIG. 26B is a cross-sectional view of the non-volatile memory device of the second comparative example based on the SEM image.
- FIG. 27 is a graph showing break voltage characteristics of the nonvolatile memory devices of the first and second comparative examples.
- FIG. 24 shows a variable resistance nonvolatile memory device 50 equipped with a variable resistance element as a first comparative example.
- the first wiring 101 is formed on the substrate 100, and the first interlayer insulating layer 102 is formed so as to cover the first wiring 101.
- a first contact hole 103 that penetrates through the first interlayer insulating layer 102 and reaches the first wiring 101 is formed, and a first contact plug 104 is embedded therein.
- a resistance change element including a lower electrode 105, a resistance change layer 106, and an upper electrode 107 is formed on the first interlayer insulating layer 102 so as to cover the first contact plug 104.
- a second interlayer insulating layer 108 is formed so as to cover the variable resistance element, and a second contact plug 110 is embedded in the second contact hole 109 penetrating the second interlayer insulating layer 108.
- the resistance change layer 106 has a stacked structure of a first resistance change layer 106a and a second resistance change layer 106b, and the first resistance change layer 106a and the second resistance change layer 106b are the same type of transition metal oxide.
- the oxygen content of the transition metal oxide forming the second resistance change layer 106b is higher than the oxygen content of the transition metal oxide forming the first resistance change layer 106a.
- FIG. 25 shows a variable resistance nonvolatile memory device 60 equipped with a variable resistance element as a second comparative example.
- the difference between the nonvolatile memory device 50 and the nonvolatile memory device 60 in FIG. 24 described above is that the surface of the lower electrode 105 is flattened.
- the upper surface of the first contact plug 104 and the upper surface of the first interlayer insulating layer 102 are not continuous, and a recess (5 to 50 nm) is generated in the discontinuous portion, but the lower electrode 105 is the first contact.
- the recess 103 formed above the first contact plug 104 inside the hole 103 is also formed so that the surface of the lower electrode 105 is flat.
- the thickness of the lower electrode 105 on the recess is the same as that on the first interlayer insulating layer 102. It is formed thicker than the thickness. According to such a structure, since the flatness of the surface of the lower electrode 105 can be improved, variations in the shape and film thickness of the resistance change layer 106 formed on the lower electrode 105 are suppressed, and variations in resistance change characteristics are reduced. can do.
- the second variable resistance layer 106b which has a small thickness and a high oxygen content and has a high resistance, are suppressed, and an initial break operation (the second variable resistance layer 106b) for causing a resistance change.
- Stable operation by locally short-circuiting a part of the memory and transitioning to a state in which the resistance change starts, it is possible to significantly reduce the variation for each bit and realize a large-capacity nonvolatile memory. it can.
- FIG. 26A and 26B show specific configuration examples corresponding to the structures of FIGS. 24 and 25, respectively.
- FIG. 26A is a SEM photograph cross-sectional view of a resistance change element actually manufactured as a prototype of the nonvolatile memory device 50 as the first comparative example
- FIG. 26B is a nonvolatile memory device 60 as the second comparative example.
- the first contact plug 104 is composed of tungsten (W)
- the lower electrode 105 is composed of a laminated structure of tantalum nitride (TaN), titanium nitride aluminum (TiAlN), and titanium nitride (TiN) from the upper surface. .
- the resistance change layer 106 is made of tantalum oxide, and the first resistance change layer 106a having a relatively low oxygen content relative to the stoichiometric composition is an oxygen-deficient TaO x (0 ⁇ x ⁇ 2.5)
- the second resistance change layer 106b having a relatively high oxygen content relative to the first resistance change layer 106a is made of an oxide having a composition close to Ta 2 O 5 .
- the upper electrode 107 is made of iridium (Ir), and the second contact plug 110 is made of tungsten (W). As shown in FIG.
- the resistance change layer 106 formed thereabove has a shape in which the central portion is recessed, and is slightly thinner at the central portion.
- the second resistance change layer 106b that is effectively applied when a voltage is applied to the element is as thin as several nanometers, variations in shape and film thickness affect variations in resistance change characteristics. ing.
- the first resistance change layer 106a and the second resistance layer 106a formed thereon are formed. Both the resistance change layers 106b have a flat shape, and the film thickness variation is extremely small.
- FIG. 27 is a graph showing the initial break voltage of the above-described nonvolatile memory devices 50 and 60 (the error bar indicates the maximum value and the minimum value).
- “Initial break” means that a part of the second resistance change layer 106b having a high oxygen content and a high resistance value is locally short-circuited when a voltage is first applied to the resistance change element immediately after manufacture. And transition to a state where resistance change starts (the same applies to the following).
- an initial break voltage required when a variable resistance element and a load resistance of 5 k ⁇ are connected in series is evaluated.
- the break voltage is greatly varied as 2 to 6 V (average value 5 V).
- the thickness of the second variable resistance layer 106b varies in the direction of thinning or local short-circuiting due to the occurrence of the recess and the variation in the recess amount (0 to 50 nm).
- the absolute value thereof is as high as about 6V. This is considered to be because the variation in the break voltage is suppressed because the structure that hardly affects the variation in the film thickness of the second resistance change layer 106b even if the recess amount varies.
- the second resistance change layer 106b is considered to have a high break voltage because there are no locally thinned portions or bent portions, that is, no breakable portions exist. It is done.
- the present invention solves the above-described problem and intentionally forms a step on the surface of the first variable resistance layer or the lower electrode that is the base of the second variable resistance layer that determines the initial break characteristics.
- the initial break voltage is reduced and the variation is reduced.
- the reduction of the initial break voltage and the improvement of the bit-by-bit variation can greatly contribute to miniaturization and large capacity of the memory. That is, the present invention can provide a variable resistance nonvolatile memory device suitable for increasing the capacity and a manufacturing method thereof.
- FIG. 1A is a cross-sectional view of the nonvolatile memory device 10 according to Embodiment 1 of the present invention
- FIG. 1B is a plan view of the first variable resistance layer 106a.
- the cross-sectional view shows an in-plane view including a line parallel to the stacking direction of the resistance change element
- the plan view shows a view when viewed from the stacking direction of the resistance change element.
- the nonvolatile memory device 10 includes a substrate 100 such as a semiconductor substrate on which a first wiring 101 is formed, and the substrate 100.
- a first interlayer insulating layer 102 composed of a silicon oxide film (film thickness 500 to 1000 nm) formed to cover the first wiring 101, and a first interlayer insulating layer 102 penetrating through the first interlayer insulating layer 102
- the first contact hole 103 (diameter: 50 to 300 nm) reaching the wiring 101 is provided with a first contact plug 104 formed by burying tungsten (W) as a main component.
- the upper surface of the first contact plug 104 and the upper surface of the first interlayer insulating layer 102 are not continuous (that is, not on the same plane), and a recess (depth: 5 to 50 nm) occurs in the discontinuous portion. ing. Then, the first contact plug 104 is covered, and a lower electrode 105 (film thickness: 5 to 100 nm) made of tantalum nitride (TaN) and a resistance change layer 106 (on the first interlayer insulating layer 102) are formed.
- variable resistance element 20 to 100 nm and a variable resistance element (500 nm square) having an upper electrode 107 (film thickness: 5 to 100 nm) made of a noble metal (platinum (Pt), iridium (Ir), palladium (Pd), etc.).
- a second interlayer insulating layer 108 composed of a silicon oxide film (SiO, 500 to 1000 nm) is formed so as to cover the variable resistance element, and penetrates through the second interlayer insulating layer 108 to pass through the upper electrode 107.
- a second contact hole 109 (diameter: 50 to 300 nm) reaching the thickness of 2 is formed, and a second contact plug 110 containing tungsten (W) as a main component is formed therein.
- a second wiring 111 is formed on the second interlayer insulating layer 108 so as to cover the second contact plug 110.
- the surface of the lower electrode 105 is not transferred with the step generated on the first contact plug 104, has a very high flatness over the entire surface of the lower electrode 105, and maintains a continuous surface (flat surface). is doing. Accordingly, the nonvolatile memory device 10 includes the first contact plug 104 below the lower electrode 105, but the interface between the lower electrode 105 and the first variable resistance layer 106a is flat.
- the resistance change layer 106 has a stacked structure of a first resistance change layer 106a (film thickness: 18 to 95 nm) and a second resistance change layer 106b (film thickness: 2 to 10 nm).
- the resistance change layer 106a is composed of a first transition metal oxide, for example, a transition metal oxide mainly containing oxygen-deficient tantalum oxide (TaO x , 0 ⁇ x ⁇ 2.5).
- the oxygen content of the second transition metal oxide forming the second resistance change layer 106b is higher than the oxygen content of the first transition metal oxide forming the first resistance change layer 106a.
- the oxygen composition ratio of the second transition metal oxide is higher than the oxygen composition ratio of the first transition metal oxide.
- the second resistance change layer 106b is composed of tantalum oxide (TaO y ), x ⁇ y.
- TaO y tantalum oxide
- a material having a small oxygen deficiency from a stoichiometric composition that exhibits insulation properties is used. Composed. Even if another oxide of hafnium (Hf) or zirconium (Zr) is used as a material constituting the resistance change layer 106, a resistance change film having a similar laminated structure can be formed.
- an oxygen-deficient transition metal oxide is an oxide having a lower oxygen content (atomic ratio: ratio of the number of oxygen atoms to the total number of atoms) than an oxide having a stoichiometric composition.
- the transition metal is Ta
- the stoichiometric oxide composition is Ta 2 O 5 and the ratio of the number of Ta and O atoms (O / Ta) is 2.5. Therefore, in the oxygen-deficient Ta oxide, the atomic ratio of Ta and O is larger than 0 and smaller than 2.5.
- the first resistance change layer 106a On the surface of the first resistance change layer 106a (interface with the second resistance change layer 106b), there is a line-shaped step 106ax (height 1 to 30 nm, length 500 nm) as shown in FIG.
- the second resistance change layer 106b is formed so as to cover the step 106ax.
- a line-shaped bent portion 106bx is generated above the step 106ax of the second resistance change layer 106b.
- the step 106ax is located so as to be sandwiched between the first contact plug 104 and the second contact plug 110 (the first contact hole 103 and the second contact hole 109), and the first resistance change layer 106a and the second contact plug 110 This is a portion that causes a change in height at the interface with the resistance change layer 106b.
- the step 106ax includes a side surface that connects a first main surface that is a boundary surface between the first resistance change layer 106a and the second resistance change layer 106b and a second main surface that is lower than the first main surface.
- the side surface is formed so as to form 90 ° with respect to one or both of the first main surface and the second main surface.
- the step 106ax is a portion including an inflection point at which the flatness changes abruptly at the interface between the first resistance change layer 106a and the second resistance change layer 106b, in other words, a point at which the flatness continuity is interrupted.
- the step 106ax is arranged in a line when the first variable resistance layer 106a and the second variable resistance layer 106b are viewed from above or below (when viewed from the side where the upper electrode 107 or the lower electrode 105 is provided).
- the step 106ax is preferably formed at substantially the center in the radial direction of the first contact hole 103 and the second contact hole 109.
- the bent portion 106bx is located so as to be sandwiched between the first contact plug 104 and the second contact plug 110 (the first contact hole 103 and the second contact hole 109). This is a part of the second resistance change layer 106b that is bent in the stacking direction of 106a and the second resistance change layer 106b.
- the bent portion 106bx is provided along the step 106ax, and is configured by a portion on the side surface of the step 106ax.
- the bent portion 106bx of the second variable resistance layer 106b is formed on the step 106ax of the first variable resistance layer 106a. Therefore, even at a low voltage, the initial break is caused by the bent portion 106bx. A phenomenon can be caused. Further, since the step shape is intentionally controlled, the shape of the bent portion 106bx of the second resistance change layer 106b is stabilized, so that the variation in the break voltage does not increase.
- only one line-shaped step 106ax is formed, but a plurality of line-shaped steps 106ax may be formed. In the case where a plurality of lines are formed, there is an effect in that the area where the break starts can be enlarged. As described above, it is possible to achieve both reduction of the initial break voltage and suppression of variation thereof, and it is possible to realize miniaturization and large capacity of the memory.
- the lower electrode 105 is also formed so as to enter the recessed portion generated above the first contact plug 104 in the first contact hole 103, and the surface of the lower electrode 105 is formed to be flat. . Therefore, the shape and film thickness of the second resistance change layer 106b in the bent portion 106bx depend only on the shape of the step 106ax of the first resistance change layer 106a, and the shape of the underlying layer under the first resistance change layer 106a. Is not affected. Therefore, it is possible to reduce variations in resistance change characteristics for each bit due to the base.
- FIGS. 3 (a) to 3 (b) are cross-sectional views illustrating a method of manufacturing the main part of the nonvolatile memory device 10 according to Embodiment 1 of the present invention.
- FIGS. 4A to 4E are plan views of the nonvolatile memory device 10 corresponding to the steps of FIGS. 2H to 3A as viewed from above. The manufacturing method of the principal part of the nonvolatile memory device 10 of the first embodiment will be described using these.
- a conductive layer (film thickness: 400) made of aluminum is formed on a substrate 100 on which transistors, lower layer wirings, and the like are formed. And the first wiring 101 is formed by patterning this.
- the surface of the insulating layer is formed after covering the first wiring 101 and forming the insulating layer on the substrate 100.
- the first interlayer insulating layer 102 (film thickness: 500 to 1000 nm) is formed.
- a plasma TEOS film, a fluorine-containing oxide (for example, FSG), a low-k material, or the like is used to reduce parasitic capacitance between wirings.
- the first interlayer insulating layer 102 is patterned by using a desired mask.
- a first contact hole 103 (thickness: 50 to 300 nm ⁇ ) that reaches the first wiring 101 is formed.
- the width of the first wiring 101 is smaller than the diameter of the first contact hole 103, the contact area between the first wiring 101 and the first contact plug 104 changes due to the effect of mask misalignment. For example, the cell current varies. From the viewpoint of preventing this, the width of the first wiring 101 is made larger than the diameter of the first contact hole 103.
- the first contact plug 104 first, an adhesion layer as a lower layer and a TiN / Ti layer (film thickness: 5 to 30 nm) functioning as a diffusion barrier are formed by a sputtering method, and the upper layer as a main component Tungsten (W, film thickness: 200 to 400 nm) is formed by CVD.
- the first contact hole 103 is filled with a conductive layer 104 ′ having a laminated structure to be the first contact plug 104.
- a recess depth: 5 to 100 nm
- the entire surface of the wafer is planarized and polished by using a chemical mechanical polishing method (CMP method), and the first interlayer insulation is performed.
- CMP method chemical mechanical polishing method
- the unnecessary conductive layer 104 ′ on the layer 102 is removed, and the first contact plug 104 is formed in the first contact hole 103.
- the upper surface of the first contact plug 104 and the upper surface of the first interlayer insulating layer 102 are not continuous, and a recess (depth: 5 to 50 nm) is generated in the discontinuous portion.
- the first contact plug 104 is covered and formed on the first interlayer insulating layer 102 later.
- a conductive layer 105 ′ (film thickness: 50 to 200 nm) made of tantalum nitride to be the lower electrode 105 is formed by sputtering.
- a conductive layer 105 ′ is formed so as to also enter the recessed portion generated above the first contact plug 104 in the first contact hole 103.
- the upper surface of the conductive layer 105 ′ on the first contact plug 104 reflects the shape of the base and has a dent.
- the entire surface of the wafer is planarized and polished by using the CMP method, and the conductive layer that becomes the lower electrode 105 after patterning is performed.
- 105 ′′ film thickness: 20 to 100 nm
- the point of this process is to planarize and polish the conductive layer 105 ′ until the dent of the conductive layer 105 ′ generated in FIG. 2F disappears, and to leave the conductive layer 105 ′′ on the entire surface.
- the step generated on the first contact plug 104 is not transferred to the surface of the conductive layer 105 ′′, and the lower electrode 105 has an extremely high flatness over the entire surface.
- the continuous surface can be maintained above the first contact plug 104 and above the first interlayer insulating layer 102. Unlike the case where the first contact plug 104 is formed, this is because, in principle, the polishing target is always the same material and the polishing rate of the CMP method is different in order to stop the polishing of the conductive layer 105 ′′. This is because it can be avoided.
- the conductive layer 105 ′′ is formed of the first transition metal oxide.
- the first variable resistance layer 106a ′ is formed by a so-called reactive sputtering method in which a tantalum target is sputtered in an argon gas atmosphere with argon (Ar).
- the oxygen content is 50 to 65 atm%
- the resistivity is 2 to 50 m ⁇ cm
- the film thickness is 20 to 100 nm.
- a desired mask is used to straddle the adjacent variable resistance elements.
- a line-shaped step 106ax (height: 1 to 30 nm) is formed on the surface of the first resistance change layer 106a ′.
- an inert gas such as Ar is used in order not to cause etching damage that deteriorates the film quality of the resistance change layer by entering fluorine (F) or the like contained in the etching gas into the first resistance change layer 106a ′. Is preferably used as the etching gas.
- fluorine (F) contained in the etching solution does not enter the resistance change layer and does not deteriorate the resistance change layer.
- the first variable resistance layer is formed on the first variable resistance layer 106a ′.
- the resistance change layer 106b ′ is formed.
- the second variable resistance layer 106b ′ was formed by a reactive sputtering method in which a tantalum target was sputtered in an oxygen gas atmosphere.
- a bent portion 106bx of the second resistance change layer 106b ′ is formed above the step 106ax on the surface of the first resistance change layer 106a ′.
- the film thickness of the bent portion 106bx (the film thickness on the side wall of the step 106ax) of the second resistance change layer 106b ′ can be adjusted thinly according to the height of the base step 106ax. In particular, the thin film portion can be formed stably.
- the variable resistance layer is formed by using reactive sputtering.
- a reactive sputtering method in which a tantalum oxide target is sputtered in an oxygen gas atmosphere may be used, or plasma oxidation may be performed in an atmosphere containing oxygen.
- a resistance change layer may be formed.
- the upper electrode 107 after patterning is formed on the second variable resistance layer 106b ′.
- a conductive layer 107 ′ made of a noble metal platinum, iridium, palladium, or the like is formed.
- the resistance change layer 106a ′, the second resistance change layer 106b ′, and the conductive layer 107 ′ are patterned to form a resistance change layer 106 that is formed by stacking the first resistance change layer 106a and the second resistance change layer 106b. Is formed between the lower electrode 105 and the upper electrode 107. Since a noble metal represented by a material having a high standard electrode potential is difficult to etch, when it is used for the upper electrode 107, it is hardened. In this process, the resistance change elements can be formed by using the same mask for the layers of the variable resistance elements, but the layers may be patterned for each layer. Mawa not.
- a second interlayer insulating layer 108 (film thickness 500 to 1000 nm) is formed so as to cover the variable resistance element, and FIG. 2B and FIG.
- the second contact hole 109 and the second contact plug 110 are formed by the same manufacturing method. Thereafter, the second contact plug 110 is covered to form the second wiring 111, whereby the nonvolatile memory device 10 is completed.
- the bent portion 106bx can be stably formed in the second resistance change layer 106b on the step 106ax, reflecting the step shape on the surface of the first resistance change layer 106a.
- the bent portion 106bx as a starting point, a break phenomenon can be caused even at a low voltage.
- the step shape can be intentionally controlled and formed, the shape of the bent portion 106bx of the second variable resistance layer 106b is stabilized, so that the initial break voltage variation does not increase. Therefore, it is possible to achieve both lowering of the break voltage and suppression of variation thereof, and it is possible to realize miniaturization and large capacity of the memory.
- FIG. 5A is a cross-sectional view of the nonvolatile memory device 20 according to Embodiment 2 of the present invention
- FIG. 5B is a plan view of the first variable resistance layer 106a.
- the same components as those in FIG. 5 are identical to FIG. 5A.
- the difference between the nonvolatile memory device 20 of the second embodiment and the nonvolatile memory device 10 of the first embodiment is the first resistance change layer. It is in the shape of a step formed in 106a.
- the step 106ax formed on the surface of the first resistance change layer 106a is in a line shape
- the bent portion 106by of the second resistance change layer 106b also has a ring shape.
- a longer step pattern can be formed in one resistance change element as compared with a line-shaped step pattern, so the area of the bent portion 106by of the second resistance change layer 106b is enlarged.
- the break voltage can be further reduced by increasing the region that is the starting point of the break.
- the step 106ay is located so as to be sandwiched between the first contact plug 104 and the second contact plug 110 (the first contact hole 103 and the second contact hole 109), and the first resistance change layer 106a and the second contact plug 110 This is a portion that causes a change in height at the interface with the resistance change layer 106b.
- the step 106ay includes a side surface that connects a first main surface that is a boundary surface between the first resistance change layer 106a and the second resistance change layer 106b and a second main surface that is lower than the first main surface.
- the side surface is formed so as to form 90 ° with respect to any one or all of the first main surface and the second main surface.
- the step 106ay is a portion including an inflection point at which the flatness changes abruptly at the interface between the first resistance change layer 106a and the second resistance change layer 106b, in other words, a point at which the continuity of flatness is interrupted.
- the step 106ay is arranged in a ring shape when the first variable resistance layer 106a and the second variable resistance layer 106b are viewed from above or below (when viewed from the side where the upper electrode 107 or the lower electrode 105 is provided). . It is preferable that the center of the ring-shaped step 106 ay be formed at the approximate center in the radial direction of the first contact hole 103 and the second contact hole 109.
- the bent portion 106by is located so as to be sandwiched between the first contact plug 104 and the second contact plug 110 (the first contact hole 103 and the second contact hole 109).
- the second resistance change layer 106b is bent in the stacking direction of the 106a and the second resistance change layer 106b.
- the bent portion 106by is provided along the step 106ay and includes a portion on the side surface of the step 106ay.
- the bent portion 106by of the second variable resistance layer 106b is formed on the step 106ay of the first variable resistance layer 106a. Therefore, the break phenomenon is caused even at a low voltage from the bent portion 106by. Can occur. Further, since the shape of the step is intentionally controlled, the shape of the bent portion 106by of the second resistance change layer 106b is stabilized, and the variation in the break voltage does not increase.
- only one ring-shaped step 106ay is formed, but a plurality of steps 106ay may be formed. When a plurality of layers are formed, there is an effect in that the region that is the starting point of the break can be further expanded. As described above, it is possible to achieve both reduction of the break voltage and suppression of variation thereof, and it is possible to realize miniaturization and large capacity of the memory.
- FIGS. 7A to 7E are plan views of the nonvolatile memory device 20 as viewed from above, corresponding to the steps of FIGS. 6A to 6E.
- the manufacturing method of the principal part of the non-volatile memory device 20 of this Embodiment 2 is demonstrated using these. Further, since the steps before FIG. 6A are the same as those in FIGS. 2A to 2G, the description thereof is omitted.
- the first variable resistance layer 106a ′ is formed by a so-called reactive sputtering method in which a tantalum target is sputtered in an atmosphere of argon and oxygen gas, and the oxygen content is 50%.
- the resistivity is 2 to 50 m ⁇ cm, and the film thickness is 20 to 100 nm.
- a subsequent variable resistance element is formed using a desired mask.
- a ring-shaped step 106ay (height: 1 to 30 nm) is formed on the surface of the first resistance change layer 106a ′ so that sometimes one ring-shaped step 106ay is always included.
- an inert gas such as Ar is used in order not to cause etching damage that deteriorates the film quality of the resistance change layer by entering fluorine (F) or the like contained in the etching gas into the first resistance change layer 106a ′. Is preferably used as the etching gas.
- fluorine (F) contained in the etching solution does not enter the resistance change layer and does not deteriorate the resistance change layer.
- FIG. 8A shows a cross-sectional view of an SEM image immediately after forming a ring-shaped step 106ay in the first resistance change layer 106a ′ made of tantalum oxide (TaO x ). It can be seen that a ring-shaped step having a height of 30 nm and a ring diameter of 250 nm is formed using the resist mask.
- TaO x tantalum oxide
- the oxygen content rate is first on the first resistance change layer 106 a ′.
- the second resistance change layer 106b ′ higher than the resistance change layer 106a ′ is formed.
- the second variable resistance layer 106b ′ was formed by a reactive sputtering method in which a tantalum target was sputtered in an oxygen gas atmosphere. Its oxygen content is 67 to 71 atm%, its resistivity is 10 7 m ⁇ cm or more, and its film thickness is 2 to 10 nm.
- a bent portion 106by of the second resistance change layer 106b ′ is formed on the step 106ay on the surface of the first resistance change layer 106a ′.
- the bent portion 106by of the second variable resistance layer 106b ′ has a tendency that the film quality tends to be sparse compared to the flat portion, and a film that is easily broken can be realized.
- variable resistance layer is formed by using reactive sputtering.
- a reactive sputtering method in which a tantalum oxide target is sputtered in an oxygen gas atmosphere may be used, or plasma oxidation may be performed in an atmosphere containing oxygen.
- a resistance change layer may be formed.
- the upper electrode 107 after patterning is formed on the second variable resistance layer 106b ′.
- a conductive layer 107 ′ made of a noble metal platinum (Pt), iridium (Ir), palladium (Pd), etc. is formed.
- the conductive layer 105 ′′, the first resistance change layer 106a ′, the first resistance change layer are formed using a desired mask.
- the resistance change layer 106b ′ and the conductive layer 107 ′ are patterned to form the resistance change layer 106 formed by stacking the first resistance change layer 106a and the second resistance change layer 106b as the lower electrode 105 and the upper electrode 107.
- the etching volume differs on the left and right with the step 106ax as an axis, and there is a concern that the etching may be left behind or the substrate may be dug due to excessive etching.
- the ring-shaped step 106ay is included in the variable resistance element, the volume of the first variable resistance layer 106a ′ to be etched is not changed. Chi, can be etched rest, digging base by etching the excess to improve the manufacturing yield hardly occurs.
- a second interlayer insulating layer 108 (film thickness 500 to 1000 nm) is formed so as to cover the resistance change element, and the second contact hole 109 and the second contact are formed. Plug 110 is formed. Thereafter, the second contact plug 110 is covered to form the second wiring 111, whereby the nonvolatile memory device 20 is completed.
- the bent portion 106by can be stably formed in the second resistance change layer 106b on the step 106ay, reflecting the step shape on the surface of the first resistance change layer 106a.
- the bent portion 106by as a starting point, a break phenomenon can occur even at a low voltage.
- the step shape can be intentionally controlled and formed, the shape of the bent portion 106by of the second resistance change layer 106b is stabilized, so that variations in the initial break voltage do not increase. Therefore, it is possible to achieve both lowering of the break voltage and suppression of variation thereof, and it is possible to realize miniaturization and large capacity of the memory.
- FIG. 8B is a graph showing an initial break voltage of the nonvolatile memory device 20 described above. This graph also evaluates the initial break voltage required when a variable resistance element and a load resistance of 5 k ⁇ are connected in series as in FIG.
- the break voltage of the nonvolatile memory device 60 that does not form a step in the first resistance change layer 106 a is normalized to 1 to indicate the break voltage.
- the break voltage can be lowered.
- the step amount difference in the height of the surface at the step 106ay
- the tendency of the breakdown voltage to decrease is also increased, so that the break voltage can be controlled by the step amount.
- FIG. 9A is a cross-sectional view of the nonvolatile memory device 30 according to Embodiment 3 of the present invention
- FIG. 9B is a plan view of the surface of the lower electrode 105 among them. 9, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted.
- the difference between the nonvolatile memory device 30 of the third embodiment and the nonvolatile memory device 10 of the first embodiment is the first resistance change layer.
- 106a and the second resistance change layer 106b are arranged upside down.
- the bent portion 106bx of the second resistance change layer 106b is formed on the step 106ax formed on the surface of the first resistance change layer 106a.
- the second resistance change layer 106b is formed on the line-shaped step 105s formed on the surface of the lower electrode 105 (interface with the second resistance change layer 106b).
- the first variable resistance layer 106a is formed on the second variable resistance layer 106b.
- the second resistance change layer 106b is formed so as to cover the step 105s, and a bent portion 106bs is formed in the second resistance change layer 106b above the step 105s.
- the upper electrode 107 is formed on the first variable resistance layer 106a.
- the step 105s is positioned so as to be sandwiched between the first contact plug 104 and the second contact plug 110 (the first contact hole 103 and the second contact hole 109), and the lower electrode 105 and the second resistance change layer. This is a portion that causes a change in height at the interface with 106b.
- the step 105s includes a side surface that connects a first main surface that is a boundary surface between the lower electrode 105 and the second variable resistance layer 106b and a second main surface that is lower than the first main surface.
- the side surface is formed so as to form 90 ° with respect to one or both of the first main surface and the second main surface.
- the step 105 s is a portion including an inflection point at which the flatness changes abruptly at the interface between the first resistance change layer 106 a and the second resistance change layer 106 b, in other words, a point where the flatness continuity is interrupted.
- the step 105s is arranged in a line when the lower electrode 105 and the second variable resistance layer 106b are viewed from above or below (when viewed from the side where the upper electrode 107 or the lower electrode 105 is provided).
- the step 105 s is preferably formed at substantially the center in the width direction of the first contact hole 103 and the second contact hole 109.
- the bent portion 106bx is located so as to be sandwiched between the first contact plug 104 and the second contact plug 110 (the first contact hole 103 and the second contact hole 109). This is a part of the second resistance change layer 106b that is bent in the stacking direction of 106a and the second resistance change layer 106b.
- the bent portion 106bx is provided along the step 105s, and is configured from a portion on the side surface of the step 105s.
- the bent portion 106bs of the second resistance change layer 106b is formed on the step 105s of the lower electrode 105, a break phenomenon can be generated even at a low voltage starting from the bent portion 106bs. .
- the step shape is intentionally controlled, the shape of the bent portion 106bs of the second resistance change layer 106b is stabilized, and the initial break voltage variation does not increase.
- only one line-shaped step 105s is formed, but a plurality of line-shaped steps 105s may be formed. In the case where a plurality of lines are formed, there is an effect in that the region that is the starting point of the break can be expanded. As described above, it is possible to achieve both reduction of the break voltage and suppression of variation thereof, and it is possible to realize miniaturization and large capacity of the memory.
- FIGS. 11A to 11F are plan views of the nonvolatile memory device 30 as viewed from above, corresponding to the steps of FIGS. 10A to 10F.
- the manufacturing method of the principal part of the non-volatile memory device 30 of this Embodiment 3 is demonstrated using these. Further, since the steps before FIG. 10A are the same as those in FIGS. 2A to 2F, the description thereof is omitted.
- the entire surface of the wafer is planarized and polished using a chemical mechanical polishing method (CMP method). Then, a conductive layer 105 ′′ (film thickness: 20 to 100 nm) to be the lower electrode 105 after patterning is formed.
- CMP method chemical mechanical polishing method
- the adjacent variable resistance element is used by using a desired mask.
- a line-shaped step 105s (height: 1 to 30 nm) is formed on the surface of the conductive layer 105 ′′ so as to straddle it.
- an inert gas such as Ar as an etching gas.
- the step of the conductive layer 105 ′′ is covered on the conductive layer 105 ′′.
- the second resistance change layer 106b ′ composed of the second transition metal oxide whose oxygen content is higher than the oxygen content of the first transition metal oxide (first resistance change layer 106a ′) is formed.
- the second variable resistance layer 106b ′ is formed by a reactive sputtering method in which a tantalum target is sputtered in an oxygen gas atmosphere. Its oxygen content is 67 to 71 atm%, its resistivity is 10 7 m ⁇ cm or more, and its film thickness is 2 to 10 nm.
- a bent portion 106bs of the second resistance change layer 106b ′ is formed above the step 105s on the surface of the conductive layer 105 ′′.
- the second resistance change is made according to the height of the base step 105s.
- the thickness of the bent portion 106bs of the layer 106b ′ (the thickness on the sidewall on the step 105s) can be adjusted to be thin, and the thin film portion can be locally formed stably.
- the film quality tends to be sparse compared to the flat portion, and a film that is easy to break can be realized.
- the variable resistance layer may be formed by a reactive sputtering method in which a tantalum oxide target is sputtered in an oxygen gas atmosphere.
- the first transition metal oxide is formed on the second resistance change layer 106b ′.
- a first variable resistance layer 106a ′ made of a material is formed.
- the first variable resistance layer 106a ' was formed by a so-called reactive sputtering method in which a tantalum target was sputtered in an argon and oxygen gas atmosphere.
- the oxygen content is 50 to 65 atm%
- the resistivity is 2 to 50 m ⁇ cm
- the film thickness is 20 to 100 nm.
- the upper electrode 107 after patterning is formed on the first variable resistance layer 106a ′.
- a conductive layer 107 ′ made of a noble metal platinum, iridium, palladium, or the like is formed.
- the conductive layer 105 ′′, the second resistance change layer 106b ′, The first resistance change layer 106a ′ and the conductive layer 107 ′ are patterned to form the resistance change layer 106 formed by stacking the second resistance change layer 106b and the first resistance change layer 106a as the lower electrode 105 and the upper electrode 107. A resistance change element sandwiched between the two is formed.
- a second interlayer insulating layer 108 (film thickness: 500 to 1000 nm) is formed so as to cover the variable resistance element, and the second contact hole 109 and the second contact hole 109 are formed.
- Contact plug 110 is formed. Thereafter, the second contact plug 110 is covered to form the second wiring 111, whereby the nonvolatile memory device 30 is completed.
- the bent portion 106bs can be stably formed in the second resistance change layer 106b on the step 105s, reflecting the step shape of the lower electrode 105, and the bent portion 106bs can be formed.
- the break phenomenon can occur even at a low voltage at the starting point.
- the step shape can be intentionally controlled and formed, the shape of the bent portion 106bs of the second resistance change layer 106b is stabilized, and the variation in the break voltage does not increase. Therefore, it is possible to achieve both lowering of the break voltage and suppression of variation thereof, and it is possible to realize miniaturization and large capacity of the memory.
- FIG. 12A is a cross-sectional view of the nonvolatile memory device 40 according to Embodiment 4 of the present invention
- FIG. 12B is a plan view of the surface of the lower electrode 105 among them. 12, the same components as those in FIG. 9 are denoted by the same reference numerals, and description thereof is omitted.
- the difference between the nonvolatile memory device 40 of the fourth embodiment and the nonvolatile memory device 30 of the third embodiment is formed in the lower electrode 105.
- the step 105 s formed on the surface of the lower electrode 105 has a line shape
- the step pattern can be formed in one variable resistance element longer than the line-shaped step pattern, the region of the bent portion 106bt of the second variable resistance layer 106b is enlarged. In addition, since the break and starting region increases, the break voltage can be further reduced.
- the step 105t is located so as to be sandwiched between the first contact plug 104 and the second contact plug 110 (the first contact hole 103 and the second contact hole 109), and the lower electrode 105 and the second resistance change layer. This is a portion that causes a change in height at the interface with 106b.
- the step 105t includes a side surface that connects a first main surface that is a boundary surface between the lower electrode 105 and the second variable resistance layer 106b and a second main surface that is lower than the first main surface.
- the side surface is formed so as to form 90 ° with respect to any one or all of the first main surface and the second main surface.
- the step 105t is a portion including an inflection point at which the flatness changes abruptly at the interface between the first resistance change layer 106a and the second resistance change layer 106b, in other words, a point at which the flatness continuity is interrupted.
- the step 105t is arranged in a ring shape when the lower electrode 105 and the second variable resistance layer 106b are viewed from above or below (from the side where the upper electrode 107 or the lower electrode 105 is provided). It is preferable that the center of the ring-shaped step 105t is formed at the approximate center in the radial direction of the first contact hole 103 and the second contact hole 109.
- the bent portion 106bt is positioned so as to be sandwiched between the first contact plug 104 and the second contact plug 110 (the first contact hole 103 and the second contact hole 109).
- the second resistance change layer 106b is bent in the stacking direction of the 106a and the second resistance change layer 106b.
- the bent portion 106bt is provided along the step 105t, and is configured by a portion on the side surface of the step 105t.
- the bent portion 106bt is formed in the second resistance change layer 106b on the step 105t reflecting the step shape of the lower electrode 105, the bent portion 106bt is used as a starting point even at a low voltage. Break phenomenon can occur. Further, since the step shape is intentionally controlled, the shape of the bent portion 106bt of the second resistance change layer 106b is stabilized, and the variation in the break voltage does not increase.
- only one ring-shaped step 105t is formed, but a plurality of steps may be formed. When a plurality of layers are formed, there is an effect in that the region that is the starting point of the break can be expanded. As described above, it is possible to achieve both reduction of the break voltage and suppression of variation thereof, and it is possible to realize miniaturization and large capacity of the memory.
- FIGS. 14A to 14F are plan views of the nonvolatile memory device 40 as viewed from above, corresponding to the steps of FIGS. 13A to 13F.
- the manufacturing method of the principal part of the non-volatile memory device 40 of this Embodiment 4 is demonstrated using these. Further, the steps before FIG. 13A are the same as those in FIGS. 2A to 2F, and the description thereof will be omitted.
- the entire surface of the wafer is planarized and polished using a chemical mechanical polishing method (CMP method). Then, a conductive layer 105 ′′ (film thickness: 20 to 100 nm) to be the lower electrode 105 after patterning is formed.
- CMP method chemical mechanical polishing method
- a desired mask is used to form the subsequent resistance change element.
- a ring-shaped step 105t (height: 1 to 30 nm) is formed on the surface of the conductive layer 105 ′′ so that one ring-shaped step 105t is always included in the formation.
- an inert gas such as Ar as an etching gas.
- FIG. 15 shows a cross-sectional view of an SEM image immediately after forming a ring-shaped step 105t on the conductive layer 105 ′′ (lower electrode 105) made of tantalum nitride.
- the ring height is 20 nm. It can be seen that a ring-shaped step 105t having a diameter of 250 nm is formed.
- the oxygen content rate is the first resistance change layer on the conductive layer 105 ′′.
- a second variable resistance layer 106b ′ higher than 106a ′ is formed, in which the second variable resistance layer 106b ′ is formed by a reactive sputtering method in which a tantalum target is sputtered in an oxygen gas atmosphere. Is 67 to 71 atm%, the resistivity is 10 7 m ⁇ cm or more, and the film thickness is 2 to 10 nm, where the second resistance change depends on the height of the step 105 t (the depth of the recess).
- the thickness of the bent portion 106bt of the layer 106b ′ (the thickness on the side wall of the concave portion of the conductive layer 105 ′′) can be adjusted to be thin, and the thin film portion can be stably formed locally.
- the bent portion 106bt of the second resistance change layer 106b ′ has a tendency that the film quality is sparse compared to the flat portion, and a film that is easily broken can be realized.
- the variable resistance layer is formed by using reactive sputtering.
- a reactive sputtering method in which a tantalum oxide target is sputtered in an oxygen gas atmosphere may be used, or a variable resistance layer may be formed by using a CVD method. May be formed.
- the second variable resistance layer 106b ′ is formed of a transition metal oxide.
- the first variable resistance layer 106a ′ is formed.
- the first variable resistance layer 106a ' was formed by a so-called reactive sputtering method in which a tantalum target was sputtered in an argon and oxygen gas atmosphere.
- the oxygen content is 50 to 65 atm%
- the resistivity is 2 to 50 m ⁇ cm
- the film thickness is 20 to 100 nm.
- the upper electrode 107 after patterning is formed on the first variable resistance layer 106a ′.
- a conductive layer 107 ′ made of a noble metal platinum (Pt), iridium (Ir), palladium (Pd), etc. is formed.
- the conductive layer 105 ′′, the second resistance change layer 106b ′, The first resistance change layer 106a ′ and the conductive layer 107 ′ are patterned to form the resistance change layer 106 formed by stacking the second resistance change layer 106b and the first resistance change layer 106a as the lower electrode 105 and the upper electrode 107.
- the etching volume differs on the left and right with the step 105s as the axis, and there is a concern that the etching may be left behind or the base may be dug due to excessive etching.
- the ring-shaped step 105t is included in the variable resistance element, the volume of the conductive layer 105 ′′ that is the etching target does not change. That is, it is difficult to cause etching residue and base excavation due to excessive etching, and the manufacturing yield can be improved.
- the second interlayer insulating layer 108 (film thickness: 500 to 1000 nm) is formed so as to cover the variable resistance element, and the second contact hole 109 and the second contact hole 109 are formed.
- Contact plug 110 is formed. Thereafter, the second contact plug 110 is covered to form the second wiring 111, whereby the nonvolatile memory device 40 is completed.
- the bent portion 106bt can be stably formed in the second resistance change layer 106b on the step 105t, reflecting the step shape of the lower electrode 105, and the bent portion 106bt is formed.
- the break phenomenon can occur even at a low voltage at the starting point.
- the step shape can be intentionally controlled, the shape of the bent portion 106bt of the second resistance change layer 106b is stabilized, so that the variation in the break voltage does not increase. Therefore, it is possible to achieve both lowering of the break voltage and suppression of variation thereof, and it is possible to realize miniaturization and large capacity of the memory.
- FIG. 16A is a cross-sectional view of the nonvolatile memory device 41 according to Embodiment 5 of the present invention
- FIG. 16B is a plan view of the first resistance change layer 106a
- FIG. It is a perspective view of 1 resistance change layer 106a.
- FIG. 16 the same components as those in FIG.
- the difference between the nonvolatile memory device 41 of the fifth embodiment and the nonvolatile memory device 10 of the first embodiment is as follows. It is in the shape of a step formed in the first resistance change layer 106a. Specifically, in the nonvolatile memory device 10, the step 106 ax formed on the surface of the first resistance change layer 106 a is a single line, whereas in the nonvolatile memory device 41, A plurality of (two) line-shaped steps 106 a x 1 and 106 ax 2 are formed on the surface of the resistance change layer 106 a, and a plurality of steps intersect at the center of the element to form an intersection.
- the first resistance change layer 106a is divided into four regions around this intersection.
- the difference in level from the left front plane region of the first resistance change layer 106a is 10 nm
- the difference from the right back plane region is The difference from the planar area of 10 nm and the right front is 20 nm.
- the steps 106ax1 and 106ax2 are positioned so as to be sandwiched between the first contact plug 104 and the second contact plug 110 (the first contact hole 103 and the second contact hole 109), respectively, and the first resistance change layer 106a. This is a portion that causes a change in height at the interface between the first and second resistance change layers 106b.
- the steps 106ax1 and 106ax2 are respectively configured from side surfaces that connect a first main surface that is a boundary surface between the first resistance change layer 106a and the second resistance change layer 106b and a second main surface that is lower than the first main surface. Is done.
- the side surface is formed so as to form 90 ° with respect to one or both of the first main surface and the second main surface.
- the steps 106ax1 and 106ax2 are portions including an inflection point at which the flatness rapidly changes at the interface between the first resistance change layer 106a and the second resistance change layer 106b, in other words, a point at which the flatness continuity is interrupted. is there.
- the steps 106ax1 and 106ax2 are linear when the first variable resistance layer 106a and the second variable resistance layer 106b are viewed from above or below (when viewed from the side where the upper electrode 107 or the lower electrode 105 is provided). They are arranged and intersect in a cross shape.
- the steps 106ax1 and 106ax2 are preferably formed at substantially the center in the radial direction of the first contact hole 103 and the second contact hole 109.
- the bent portion 106bx is located so as to be sandwiched between the first contact plug 104 and the second contact plug 110 (the first contact hole 103 and the second contact hole 109). It is a part of the second resistance change layer 106b bent in the stacking direction of 106b.
- the bent portion 106bx is provided along the steps 106ax1 and 106ax2.
- the maximum bent portion 106bx of the second resistance change layer 106b is formed on the intersection of the steps 106ax1 and 106ax2 of the first resistance change layer 106a.
- a break phenomenon can occur even at a low voltage.
- the electric field tends to concentrate at the intersection, and the break location can be fixed. Therefore, by arranging the intersection at the central portion of the variable resistance element that is remote from the end of the variable resistance element, a filament can be formed in a portion where the influence of the oxidized region due to etching damage or the layer film insulating film is small.
- the variation in resistance change characteristics is extremely small, a nonvolatile memory device with a small bit variation and a good manufacturing yield can be realized.
- FIG. 17 (a) to 17 (g) are cross-sectional views illustrating a method for manufacturing the main part of the nonvolatile memory device 41 according to Embodiment 5 of the present invention.
- 18A to 18C also show perspective views of the first resistance change layer 106a ′.
- the manufacturing method of the principal part of the non-volatile memory device 41 of this Embodiment 5 is demonstrated using these. Further, since the steps before FIG. 17A are the same as those in FIGS. 2A to 2G, the description thereof will be omitted.
- the first variable resistance layer 106a ′ is formed by a so-called reactive sputtering method in which a tantalum target is sputtered in an atmosphere of argon and oxygen gas, and the oxygen content is 50%.
- the resistivity is 2 to 50 m ⁇ cm, and the film thickness is 20 to 100 nm.
- a desired mask is used to straddle adjacent resistance change elements.
- a step 106ax1 (height: 10 nm) having a line shape (a line shape running in the direction perpendicular to the paper surface of FIG. 17) is formed.
- a desired mask is used to cross the step 106ax1 (
- a line-shaped step 106ax2 (height: 10 nm) is formed in the direction parallel to the paper surface of FIG.
- two line-shaped steps 106ax1 and 106ax2 are formed on the surface of the first resistance change layer 106a ', and an intersection is formed at the center of the element by the steps.
- Four regions are formed in the first resistance change layer 106a 'around the intersection.
- the left back region of the first resistance change layer 106a ′ is used as a reference, the left front plane region and the right back plane region of the first resistance change layer 106a ′ etched once are a step of 10 nm.
- a step of 20 nm is generated with respect to the planar region on the right front side that is etched twice.
- fluorine (F) contained in the etching solution does not enter the resistance change layer and does not deteriorate the resistance change layer.
- the oxygen content is on the first resistance change layer 106a ′.
- a higher second variable resistance layer 106b ′ is formed.
- the second variable resistance layer 106b ′ was formed by a reactive sputtering method in which a tantalum target was sputtered in an oxygen gas atmosphere. Its oxygen content is 67 to 71 atm%, its resistivity is 10 7 m ⁇ cm or more, and its film thickness is 2 to 10 nm.
- a bent portion 106bx of the second resistance change layer 106b ' is formed on the steps 106ax1 and 106ax2 on the surface of the first resistance change layer 106a'.
- the film thickness of the bent portion 106bx of the second resistance change layer 106b ′ (the film thickness on the side walls of the steps 106ax1 and 106ax2) can be thinly adjusted in accordance with the height of the underlying steps 106ax1 and 106ax2. Therefore, the thin film portion can be stably formed locally.
- the bent portion 106bx of the second variable resistance layer 106b ′ tends to have a poorer film quality than the flat portion, and a film that is easy to break can be realized.
- variable resistance layer is formed by using reactive sputtering.
- a reactive sputtering method in which a tantalum oxide target is sputtered in an oxygen gas atmosphere may be used, or plasma oxidation may be performed in an atmosphere containing oxygen.
- a resistance change layer may be formed.
- a noble metal platinum (platinum)
- Pt iridium
- Ir palladium
- Pd palladium
- variable resistance element in the step of forming the variable resistance element, the conductive layer 105 ′′, the first variable resistance layer 106a ′, and the second variable resistance layer 106b are used using a desired mask.
- a second interlayer insulating layer 108 (film thickness: 500 to 1000 nm) is formed so as to cover the variable resistance element, and the second contact hole 109 and the second contact hole 109 are formed.
- Contact plug 110 is formed. Thereafter, the second contact plug 110 is covered to form the second wiring 111, whereby the nonvolatile memory device 41 is completed.
- the electric field concentration is generated in the second resistance change layer 106b formed on the intersection of the steps using the shape of the plurality of steps on the surface of the first resistance change layer 106a.
- An easy region can be intentionally formed.
- a filament can be formed in a portion that is less affected by the oxidation region due to etching damage or a layer film insulating film. Therefore, variation in resistance change characteristics is extremely small, and thus a nonvolatile memory device with little bit variation and good manufacturing yield can be realized.
- the step 106ax1 and the step 106ax2 are line-shaped, but may be ring-shaped. Further, the first variable resistance layer 106a and the second variable resistance layer 106b may be disposed upside down. That is, steps 106ax1 and 106ax2 are formed at the interface between the lower electrode 105 and the second resistance change layer 106b, the second resistance change layer 106b is formed to cover the steps 106ax1 and 106ax2, and the intersection of the steps 106ax1 and 106ax2. You may have the bending part 106bx on the top.
- FIG. 19A is a cross-sectional view of the nonvolatile memory device 42 according to Embodiment 6 of the present invention
- FIG. 19B is a plan view of the first variable resistance layer 106a.
- FIG. 19 the same components as those in FIG.
- the difference between the nonvolatile memory device 42 of the sixth embodiment and the nonvolatile memory device 20 of the second embodiment is the second resistance change layer.
- the ring-shaped step shape is devised so that the difference between the thick film portion and the thin film portion of 106b becomes larger.
- the ring-shaped step 106 ay is formed on the surface of the first resistance change layer 106 a
- the first resistance change layer 106 a and the first resistance change layer 106 a This is that a ring-shaped step 106az, in other words, a recess is formed on the surface of the laminated structure of the two resistance change layers 106b1.
- the ring-shaped step 106az is formed by removing a part of the first resistance change layer 106a and the second resistance change layer 106b1. Further, the second resistance change layer 106b2 is stacked to cover the ring-shaped step 106az. As described above, in the nonvolatile memory device 20, the local film thickness difference of the second resistance change layer 106b is small due to the step coverage of the second resistance change layer 106b generated in the ring-shaped step 106az.
- the second variable resistance layer 106b2 when the second variable resistance layer 106b2 is formed, the second variable resistance layer 106b1 remains in a region other than the ring-shaped step 106az, so that the film thickness is The difference in film thickness of the second resistance change layer 106b is large.
- the step 106az is located so as to be sandwiched between the first contact plug 104 and the second contact plug 110 (the first contact hole 103 and the second contact hole 109), and the first resistance change layer 106a and the second resistance plug 106a. This is a portion that causes a change in height at the interface with the resistance change layer 106b.
- the step 106az is composed of a side surface that connects a first main surface serving as a boundary surface between the first resistance change layer 106a and the second resistance change layer 106b and a second main surface having a lower height.
- the step 106az is formed such that the side surface forms, for example, 90 ° with respect to any one or all of the first main surface and the second main surface.
- the step 106az is a portion including an inflection point at which the flatness changes abruptly at the interface between the first resistance change layer 106a and the second resistance change layer 106b, in other words, a point at which the flatness continuity is interrupted.
- the step 106az is arranged in a ring shape when the first variable resistance layer 106a and the second variable resistance layer 106 are viewed from above or below (when viewed from the side where the upper electrode 107 or the lower electrode 105 is provided).
- the center of the ring-shaped step 106az is preferably formed at the approximate center in the radial direction of the first contact hole 103 and the second contact hole 109.
- the bent portion 106by is located so as to be sandwiched between the first contact plug 104 and the second contact plug 110 (the first contact hole 103 and the second contact hole 109).
- the second resistance change layer 106b is bent in the stacking direction of the 106a and the second resistance change layer 106b.
- the bent portion 106by is provided along the step 106az and includes a portion on the side surface of the step 106az.
- the break phenomenon can be generated even at a low voltage starting from the bent portion 106by.
- the second resistance change layer 106b1 remains in the region other than the ring-shaped step 106ay when the second resistance change layer 106b2 is formed, the thickness of the second resistance change layer 106b is increased.
- the leakage current can be greatly reduced, the voltage can be more reliably applied to the cell, and the break voltage can be further reduced. As described above, it is possible to achieve both reduction of the break voltage and suppression of variation thereof, and it is possible to realize miniaturization and large capacity of the memory.
- FIG. 20A to 20 (g) are cross-sectional views showing a method of manufacturing the main part of the nonvolatile memory device 42 according to Embodiment 6 of the present invention.
- the manufacturing method of the principal part of the non-volatile memory device 42 of this Embodiment 6 is demonstrated using this. Further, the steps before FIG. 20A are the same as those in FIGS. 2A to 2G, and the description thereof will be omitted.
- the first variable resistance layer 106a ′ made of the first transition metal oxide is formed on the conductive layer 105 ′′.
- the first variable resistance layer 106a ′ is formed by a so-called reactive sputtering method in which a tantalum target is sputtered in an atmosphere of argon and oxygen, and the oxygen content is 50 to 65 atm%.
- the resistivity is 2 to 50 m ⁇ cm and the film thickness is 20 to 100 nm.
- the oxygen content is changed to the first transition metal oxide (
- a second variable resistance layer 106b1 ′ composed of a second transition metal oxide having a higher oxygen content than the first variable resistance layer 106a ′) is formed.
- a tantalum target was formed by a reactive sputtering method in which sputtering is performed in an oxygen gas atmosphere. Its oxygen content is 67 to 71 atm%, its resistivity is 10 7 m ⁇ cm or more, and its film thickness is 2 to 10 nm.
- the resistance change layer is formed using reactive sputtering, but reactive sputtering in which a tantalum oxide target is sputtered in an oxygen gas atmosphere may be used, or plasma oxidation may be performed in an atmosphere containing oxygen.
- a resistance change layer may be formed.
- a step 106ay is formed in the stacked structure of the first resistance change layer 106a ′ and the second resistance change layer 106b1 ′ (the surface of the second resistance change layer 106b1 ′).
- a ring-shaped step 106ay is included by using a desired mask so that a single ring-shaped step 106ay is always included when a subsequent variable resistance element is formed (when the second variable resistance layer 106b2 ′ is formed).
- a step 106ay (height: 2 to 30 nm) is formed.
- the second resistance change layer 106b1 ′ is surely removed in the ring-shaped step 106ay, that is, the first resistance change layer 106a ′ is formed on the second resistance change layer 106b1 ′. Through-holes reaching up to are formed, and part of the first resistance change layer 106a ′ is removed.
- fluorine (F) or the like contained in the etching gas enters the first variable resistance layer 106a ′ and does not cause etching damage that deteriorates the film quality of the variable resistance layer, non-destructive elements such as Ar are used. It is preferable to use an active gas as an etching gas.
- fluorine (F) contained in the etching solution does not enter the resistance change layer and does not deteriorate the resistance change layer.
- the ring-shaped step 106ay between the second resistance change layer 106b1 ′ and the first resistance change layer 106a ′ A second resistance change layer 106b2 ′ composed of a second transition metal oxide having an oxygen content higher than that of the first transition metal oxide is formed thereon. That is, the second resistance change layer 106b2 'is further stacked by covering the step 106ay on the second resistance change layer 106b1' and the first resistance change layer 106a '.
- the film formation method is the same as that of the second resistance change layer 106b1 '.
- a bent portion 106by of the second resistance change layer 106b2 ' is formed on the ring-shaped step 106ay.
- the film thickness difference of the second resistance change layer 106b is increased by the film thickness of 106b1 ′.
- a noble metal platinum (platinum)
- Pt iridium
- Ir palladium
- Pd palladium
- variable resistance element in the step of forming the variable resistance element, the conductive layer 105 ′′, the first variable resistance layer 106a ′, and the second variable resistance layer 106b are used using a desired mask.
- the etching volume is different on the left and right with the step 106ax as an axis, and there is a concern that the etching may be left behind or the substrate may be dug due to excessive etching. Since the step 106ay is included in the variable resistance element, the volume of the first variable resistance layer 106a to be etched is not changed. The remaining, digging base by etching excess can improve manufacturing yield hardly occurs.
- a second interlayer insulating layer 108 (film thickness: 500 to 1000 nm) is formed so as to cover the variable resistance element, and the second contact hole 109 and the second contact hole 109 Contact plug 110 is formed. Thereafter, the second contact plug 110 is covered to form the second wiring 111, whereby the nonvolatile memory device 42 is completed.
- the bent portion 106by can be stably formed in the second resistance change layer 106b on the step 106ay, reflecting the step shape on the surface of the first resistance change layer 106a.
- the bent portion 106by as a starting point, a break phenomenon can occur even at a low voltage.
- the step shape can be intentionally controlled and formed, the shape of the bent portion 106by of the second resistance change layer 106b is stabilized, so that variations in the initial break voltage do not increase.
- the second variable resistance layer 106b1 remains in the region other than the ring-shaped step 106ay when the second variable resistance layer 106b2 is formed, the thickness of the second variable resistance layer 106b is increased, Leakage current can be significantly reduced, more reliably applied to the cell, and further reduction of the break voltage is possible. Therefore, it is possible to achieve both lowering of the break voltage and suppression of variation thereof, and it is possible to realize miniaturization and large capacity of the memory.
- the first resistance change layer 106a and the second resistance change layer 106b may be arranged upside down.
- a plurality of steps may be formed on the surface of the first resistance change layer 106a.
- Embodiment 7 When a memory cell array is configured by two-dimensionally arranging the memory cells having the nonvolatile memory elements described in Embodiments 1 to 6, the resistance of only a predetermined memory cell (selected memory cell) is changed, There are cases where it is desired not to change the resistance of other memory cells (non-selected memory cells). In such a case, a diode element is connected in series with the variable resistance element to form a memory cell, the diode element of a predetermined memory cell is turned on, and the diode elements of other memory cells are turned off. In this case, it is necessary to increase the voltage applied to the memory cell by adding the voltage distributed to the diode element. For this reason, there is a great demand for lower voltage.
- the nonvolatile memory device can lower the break voltage of the resistance change element, so that the voltage applied to the memory cell can be lowered.
- the break phenomenon of the resistance change element occurs locally, the transient current that flows during the break can be reduced. Thereby, destruction of the diode element can also be prevented.
- FIG. 21A is a cross-sectional view of the nonvolatile memory device 44 according to Embodiment 7 of the present invention
- FIG. 21B is a plan view of the first variable resistance layer 106a.
- the same components as those of FIG. 21 are identical to those of FIG. 21A.
- the difference between the nonvolatile memory device 44 according to the seventh embodiment and the nonvolatile memory device 10 according to the first embodiment is below the resistance change element.
- the lower electrode 112 of the diode element, the semiconductor layer 113, and the upper electrode 114 of the diode element, that is, the diode element is incorporated. That is, the nonvolatile memory device 44 is an element in which a resistance change element and a diode element are integrated.
- the nonvolatile memory device 44 has a structure in which the upper electrode 114 of the diode element and the lower electrode 105 of the resistance change element are shared, but these electrodes may be configured separately.
- the surface of the lower electrode 112 of the diode element is flattened, and the surface of the element film of the semiconductor layer 113 formed thereabove is formed substantially flat.
- a line-shaped step 106ax is formed on the surface of the first resistance change layer 106a.
- the lower electrode 112 of the diode element is also formed so as to enter the recessed portion generated above the first contact plug 104 in the first contact hole 103, but the lower electrode 112 of the diode element is formed.
- the surface of is formed flat. Since the semiconductor layer 113 can be formed on a planarized base, variation in film thickness can be extremely reduced, and stable rectification characteristics of an MSM diode in which the semiconductor layer 113 is sandwiched between upper and lower electrodes can be obtained. Can do.
- the bent portion 106bx of the second variable resistance layer 106b is formed on the step 106ax of the first variable resistance layer 106a, so that the electric field concentration starts from the bent portion 106bx. Even at a low voltage, the initial break phenomenon can be caused. Further, since the step shape is intentionally controlled, the shape of the bent portion 106bx of the second resistance change layer 106b is stabilized, so that the variation in the break voltage does not increase.
- the break voltage of the resistance change element can be lowered, so that the voltage applied to the memory cell can be lowered. Moreover, since the break phenomenon of the resistance change element occurs locally, the transient current that flows during the break can be reduced. Thereby, destruction of the diode element can also be prevented.
- FIG. 22 (a) to (i) are cross-sectional views illustrating a method of manufacturing the main part of the nonvolatile memory device 44 according to Embodiment 7 of the present invention.
- the manufacturing method of the principal part of the nonvolatile memory device 44 of the seventh embodiment will be described using this. Further, the steps before FIG. 22A are the same as those in FIG. 2A to FIG.
- the first contact plug 104 is covered and formed on the first interlayer insulating layer 102 later.
- a conductive layer 112 ′ (film thickness: 50 to 200 nm) made of tantalum nitride to be the lower electrode 112 of the diode element is formed by sputtering.
- a conductive layer 112 ′ is formed so as to also enter a recess portion generated above the first contact plug 104 in the first contact hole 103.
- the upper surface of the conductive layer 105 ′ on the first contact plug 104 reflects the shape of the base and has a dent.
- the entire surface of the wafer is planarized and polished using a chemical mechanical polishing method (CMP method).
- CMP method chemical mechanical polishing method
- a conductive layer 112 ′′ (film thickness: 20 to 100 nm) to be the lower electrode 112 is formed.
- the point of this process is to flatten the conductive layer 112 ′ until the above-described dent generated in FIG. Polishing and leaving the conductive layer 112 ′′ on the entire surface.
- the surface of the conductive layer 112 ′′ is not transferred with the step generated on the first contact plug 104, has a very high flatness over the entire surface of the lower electrode 112, and is continuous.
- the polishing target is always the same material and the polishing rate of the CMP method is different. This is because it can be avoided.
- the semiconductor layer 113 ′ is deposited on the conductive layer 112 ′′.
- the semiconductor layer 113 ′ is formed of silicon nitride. For example, 5 to 30 nm is deposited and formed by the sputtering method.
- the conductive layer 114 ′ serving as the upper electrode of the diode element is formed on the semiconductor layer 113 ′. accumulate.
- the conductive layer 114 'to be the upper electrode 114 of the diode element is formed by depositing, for example, 20 to 50 nm by a tantalum nitride sputtering method.
- the upper electrode 114 of the diode element also serves as the lower electrode 105 of the resistance change element.
- the first variable resistance layer 106a ′ is formed on the conductive layer 114 ′ (conductive layer 105 ′).
- the resistance change layer 106a ′ is formed.
- the first variable resistance layer 106a ' is formed by a so-called reactive sputtering method in which a tantalum target is sputtered in an argon and oxygen gas atmosphere.
- the oxygen content is 50 to 65 atm%
- the resistivity is 2 to 50 m ⁇ cm
- the film thickness is 20 to 100 nm.
- a line-shaped step 106ax is formed across adjacent resistance change elements using a desired mask. (Height: 1 to 30 nm) is formed on the surface of the first variable resistance layer 106a ′.
- an inert gas such as Ar is used in order not to cause etching damage that deteriorates the film quality of the resistance change layer by entering fluorine (F) or the like contained in the etching gas into the first resistance change layer 106a ′. Is preferably used as the etching gas.
- fluorine (F) contained in the etching solution does not enter the resistance change layer and does not deteriorate the resistance change layer.
- the oxygen content rate on the first resistance change layer 106a ′ is the first resistance change layer 106a ′.
- the second resistance change layer 106b ′ having a higher oxygen content is formed.
- the second variable resistance layer 106b ′ was formed by a reactive sputtering method in which a tantalum target was sputtered in an oxygen gas atmosphere. Its oxygen content is 67 to 71 atm%, its resistivity is 10 7 m ⁇ cm or more, and its film thickness is 2 to 10 nm.
- a bent portion 106bx of the second resistance change layer 106b ′ is formed on the step 106ax on the surface of the first resistance change layer 106a ′.
- the film thickness of the bent portion 106bx (the film thickness on the side wall of the step 106ax) of the second resistance change layer 106b ′ can be adjusted thinly according to the height of the base step 106ax. In particular, the thin film portion can be formed stably.
- the bent portion 106bx of the second variable resistance layer 106b ′ tends to have a poorer film quality than the flat portion, and a film that is easy to break can be realized.
- the variable resistance layer is formed by using reactive sputtering.
- a reactive sputtering method in which a tantalum oxide target is sputtered in an oxygen gas atmosphere may be used, or plasma oxidation may be performed in an atmosphere containing oxygen.
- a resistance change layer may be formed.
- a noble metal platinum, which becomes the upper electrode 107 after patterning is formed on the second resistance change layer 106b ′.
- the conductive layer 112 ′′, the semiconductor layer 113 ′, the conductive layer 114 ′, the first layer are formed using a desired mask.
- the variable resistance layer 106a ′, the second variable resistance layer 106b ′, and the conductive layer 107 ′ are patterned, and the diode element in which the semiconductor layer 113 is sandwiched between the electrodes and the variable resistance layer 106 that is formed of the stacked layers are sandwiched between the electrodes.
- patterning is performed in a lump using the same mask, but patterning may be performed for each process (for each different layer).
- a second interlayer insulating layer 108 (film thickness 500 to 1000 nm) is formed so as to cover the diode element, and the second interlayer insulating layer 108 (thickness 500 to 1000 nm) is formed by the same manufacturing method as in FIGS. 2B and 2C. Forming a contact hole 109 and second contact plug 110. Thereafter covers the second contact plug 110, to form a second wiring 111, the nonvolatile memory device 44 is completed.
- the above manufacturing method it is possible to realize an element capable of reducing the voltage of the break of the resistance change element in the memory cell structure in which the resistance change element and the diode element are connected in series. Since the break voltage of the variable resistance element can be lowered, the applied voltage of the entire cell can be lowered. In addition, since the break phenomenon of the resistance change element locally occurs in the bent portion 106bx, the transient current that flows during the break can be reduced. Thereby, destruction of the diode element can also be prevented.
- the step 106ax is assumed to be a line shape, but may be a ring shape as described in the second embodiment, the fourth embodiment, and the fifth embodiment.
- a plurality of steps may be formed on the surface of the first resistance change layer 106a. The above contents can be similarly applied to the modification shown in FIG.
- the first resistance change layer 106a and the second resistance change layer 106b ′ (106b1) are stacked, and then the ring-shaped step 106ax is formed.
- the second variable resistance layer 106b may be formed by covering the step 106ax and further stacking the second variable resistance layer 106b '(106b2).
- the metal oxide layer has a laminated structure of a tantalum oxide layer.
- the above-described effects of the present invention are manifested only in the case of the tantalum oxide layer.
- the present invention is not limited to this.
- the metal oxide layer may be composed of another metal oxide layer (transition metal oxide layer) such as a stacked structure of a hafnium (Hf) oxide layer or a stacked structure of a zirconium (Zr) oxide layer.
- the composition of the first hafnium oxide layer is HfO x and the composition of the second hafnium oxide layer is HfO y , 0.9 ⁇ x ⁇ It is preferably about 1.6, y is about 1.8 ⁇ y ⁇ 2.0, and the thickness of the second hafnium oxide layer is preferably 3 nm or more and 4 nm or less.
- the composition of the first zirconium oxide layer is ZrO x and the composition of the second zirconium oxide layer is ZrO y , 0.9 ⁇ x ⁇ It is preferably about 1.4, y is about 1.9 ⁇ y ⁇ 2.0, and the thickness of the second zirconium oxide layer is preferably 1 nm or more and 5 nm or less.
- the first hafnium oxide layer is formed on the lower electrode by a so-called reactive sputtering method using an Hf target and sputtering in argon gas and oxygen gas.
- the second hafnium oxide layer can be formed by exposing the surface of the first hafnium oxide layer to a plasma of argon gas and oxygen gas after forming the first hafnium oxide layer.
- the oxygen content of the first hafnium oxide layer can be easily adjusted by changing the flow rate ratio of oxygen gas to argon gas during reactive sputtering, as in the case of the tantalum oxide layer described above.
- the substrate temperature can be set to room temperature without any particular heating.
- the film thickness of the second hafnium oxide layer can be easily adjusted by the exposure time of the argon gas and oxygen gas to the plasma.
- the composition of the first hafnium oxide layer is represented as HfO x and the composition of the second hafnium oxide layer is represented as HfO y , 0.9 ⁇ x ⁇ 1.6, 1.8 ⁇ y ⁇ 2.0
- the thickness of the second hafnium oxide layer can realize stable resistance change characteristics in the range of 3 nm to 4 nm.
- the first zirconium oxide layer is formed on the lower electrode by a so-called reactive sputtering method using a Zr target and sputtering in argon gas and oxygen gas.
- the second zirconium oxide layer can be formed by exposing the surface of the first zirconium oxide layer to a plasma of argon gas and oxygen gas after forming the first zirconium oxide layer.
- the oxygen content of the first zirconium oxide layer can be easily adjusted by changing the flow ratio of oxygen gas to argon gas during reactive sputtering.
- the substrate temperature can be set to room temperature without any particular heating.
- the film thickness of the second zirconium oxide layer can be easily adjusted by the exposure time of the argon gas and oxygen gas to the plasma.
- the composition of the first zirconium oxide layer is expressed as ZrO x and the composition of the second zirconium oxide layer is expressed as ZrO y , 0.9 ⁇ x ⁇ 1.4, 1.9 ⁇ y ⁇ 2.0
- a stable resistance change characteristic can be realized when the thickness of the second zirconium oxide layer is in the range of 1 nm to 5 nm.
- the materials of the upper electrode and the lower electrode described in the first to seventh embodiments are merely examples, and other materials may be used.
- Au gold
- copper Cu
- silver etc.
- W tungsten
- TaN nickel
- Nickel (Ni) or the like may be used.
- the fact that the bent portion is provided in the second resistance change layer means that the first resistance change layer and the second resistance change layer are formed on the surface of the second resistance change layer.
- the step is transferred to a position corresponding to the step at the interface.
- the second resistance change layer may be thinner in the bent portion than the other portions of the second resistance change layer, or may be the same thickness as the other portions.
- the present invention provides a variable resistance nonvolatile memory device and a method for manufacturing the variable resistance nonvolatile memory device, and can realize a highly reliable nonvolatile memory that operates stably, so that various electronic devices using the nonvolatile memory can be realized. Useful in the equipment field.
- Nonvolatile memory device 100 Substrate 101 First wiring 102 First interlayer insulating layer 103 First contact hole 104 First contact plug 104 ′, 105 ′, 105 ′′, 107 ′, 112 ′, 112 ′′, 114 ′ Conductive layer 105, 112, 127 Lower electrode 105s, 105t, 106ax, 106ay, 106ax1, 106ax2, 106az Step 106 Resistance change layer 106a, 106a ′ First Resistance change layer (low oxygen concentration layer / low resistance layer) 106b, 106b ′, 106b1, 106b2 Second variable resistance layer (high oxygen concentration layer / high resistance layer) 106bx, 106by, 106bs, 106bt Bending portion 107, 114, 128 Upper electrode 108 Second interlayer insulating layer 109 Second contact hole 110 Second contact plug 111 Second wiring 113, 113 ′ Semiconductor layer
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Abstract
Description
[装置の構成]
図1(a)は、本発明の実施の形態1における不揮発性記憶装置10の断面図、図1(b)はそのうちの第1の抵抗変化層106aの平面図である。なお、以下で、断面図とは抵抗変化素子の積層方向と平行な線を含む面内図を示し、平面図とは抵抗変化素子の積層方向からみたときの図を示している。
図2(a)から(k)、図3(a)から(b)は本発明の実施の形態1における不揮発性記憶装置10の要部の製造方法を示す断面図である。また、図4(a)から(e)は、図2(h)から図3(a)の工程に相当した、不揮発性記憶装置10を上方から見た平面図である。これらを用いて、本実施の形態1の不揮発性記憶装置10の要部の製造方法について説明する。
[装置の構成]
図5(a)は、本発明の実施の形態2における不揮発性記憶装置20の断面図、図5(b)はそのうちの第1の抵抗変化層106aの平面図である。図5において、図1と同じ構成要素については同じ符号を用い、説明を省略する。
図6(a)から(f)は本発明の実施の形態2における不揮発性記憶装置20の要部の製造方法を示す断面図である。また、図7(a)から(e)は、図6(a)から(e)の工程に相当した、不揮発性記憶装置20を上方から見た平面図である。これらを用いて、本実施の形態2の不揮発性記憶装置20の要部の製造方法について説明する。また、図6(a)以前の工程は、図2(a)~(g)と同様であるので、説明を省略する。
[装置の構成]
図9(a)は、本発明の実施の形態3における不揮発性記憶装置30の断面図、図9(b)はそのうちの下部電極105の表面の平面図である。図9において、図1と同じ構成要素については同じ符号を用い、説明を省略する。
図10(a)から(g)は本発明の実施の形態3における不揮発性記憶装置30の要部の製造方法を示す断面図である。また、図11(a)から(f)は、図10(a)から(f)の工程に相当した、不揮発性記憶装置30を上方から見た平面図である。これらを用いて、本実施の形態3の不揮発性記憶装置30の要部の製造方法について説明する。また、図10(a)以前の工程は、図2(a)~(f)と同様であるので、説明を省略する。
[装置の構成]
図12(a)は、本発明の実施の形態4における不揮発性記憶装置40の断面図、図12(b)はそのうちの下部電極105の表面の平面図である。図12において、図9と同じ構成要素については同じ符号を用い、説明を省略する。
図13(a)から(g)は本発明の実施の形態4における不揮発性記憶装置40の要部の製造方法を示す断面図である。また、図14(a)から(f)は、図13(a)から(f)の工程に相当した、不揮発性記憶装置40を上方から見た平面図である。これらを用いて、本実施の形態4の不揮発性記憶装置40の要部の製造方法について説明する。また、図13(a)以前の工程は、図2(a)~(f)と同様であるので、説明を省略する。
[装置の構成]
図16(a)は、本発明の実施の形態5における不揮発性記憶装置41の断面図、図16(b)はそのうちの第1の抵抗変化層106aの平面図、図16(c)は第1の抵抗変化層106aの斜視図である。図16において、図1と同じ構成要素については同じ符号を用い、説明を省略する。
図17(a)から(g)は本発明の実施の形態5における不揮発性記憶装置41の要部の製造方法を示す断面図である。また、図18(a)から(c)においては、第1の抵抗変化層106a’の斜視図も示した。これらを用いて、本実施の形態5の不揮発性記憶装置41の要部の製造方法について説明する。また、図17(a)以前の工程は、図2(a)~(g)と同様であるので、説明を省略する。
[装置の構成]
図19(a)は、本発明の実施の形態6における不揮発性記憶装置42の断面図、図19(b)はそのうちの第1の抵抗変化層106aの平面図である。図19において、図1と同じ構成要素については同じ符号を用い、説明を省略する。
図20(a)から(g)は本発明の実施の形態6における不揮発性記憶装置42の要部の製造方法を示す断面図である。これを用いて、本実施の形態6の不揮発性記憶装置42の要部の製造方法について説明する。また、図20(a)以前の工程は、図2(a)~(g)と同様であるので、説明を省略する。
上述した実施の形態1乃至6にて説明した不揮発性記憶素子を有するメモリセルを二次元状に配置してメモリセルアレイを構成した場合、所定のメモリセル(選択メモリセル)のみを抵抗変化させ、それ以外のメモリセル(非選択メモリセル)については抵抗変化させないようにしたい場合がある。このような場合には、抵抗変化素子にダイオード素子を直列接続してメモリセルを構成し、所定のメモリセルのダイオード素子をONとし、それ以外のメモリセルのダイオード素子をOFFにすればよい。この場合には、ダイオード素子に分配される電圧分を追加して、メモリセルに印加される電圧を上げて与えなければならない。このため、より低電圧化の要望が大きい。
図21(a)は、本発明の実施の形態7における不揮発性記憶装置44の断面図、図21(b)はそのうちの第1の抵抗変化層106aの平面図である。図21において、図1と同じ構成要素については同じ符号を用い、説明を省略する。
図22(a)から(i)は本発明の実施の形態7における不揮発性記憶装置44の要部の製造方法を示す断面図である。これを用いて、本実施の形態7の不揮発性記憶装置44の要部の製造方法について説明する。また、図22(a)以前の工程は、図2(a)~(e)と同様であるので、説明を省略する。
上記の各実施の形態においては、金属酸化物層はタンタル酸化物層の積層構造で構成されていたが、本発明の上述した作用効果は、タンタル酸化物層の場合に限って発現されるものではなく、本発明はこれに限定されない。例えば、金属酸化物層はハフニウム(Hf)酸化物層の積層構造やジルコニウム(Zr)酸化物層の積層構造など、その他の金属酸化物層(遷移金属酸化物層)で構成されてもよい。
100 基板
101 第1の配線
102 第1の層間絶縁層
103 第1のコンタクトホール
104 第1のコンタクトプラグ
104’、105’、105”、107’、112’、112”、114’ 導電層
105、112、127 下部電極
105s、105t、106ax、106ay、106ax1、106ax2、106az 段差
106 抵抗変化層
106a、106a’ 第1の抵抗変化層(低酸素濃度層・低抵抗層)
106b、106b’、106b1、106b2 第2の抵抗変化層(高酸素濃度層・高抵抗層)
106bx、106by、106bs、106bt 屈曲部
107、114、128 上部電極
108 第2の層間絶縁層
109 第2のコンタクトホール
110 第2のコンタクトプラグ
111 第2の配線
113、113’ 半導体層
Claims (11)
- 基板と、
前記基板上に形成された下部電極と、
前記下部電極上に形成され、第1の遷移金属酸化物で構成される第1の抵抗変化層と、
前記第1の抵抗変化層上に形成され、酸素含有率が前記第1の遷移金属酸化物の酸素含有率より高い第2の遷移金属酸化物で構成される第2の抵抗変化層と、
前記第2の抵抗変化層上に形成された上部電極とを備え、
前記第1の抵抗変化層と前記第2の抵抗変化層との界面には段差があり、
前記第2の抵抗変化層は、前記段差を被覆して形成されかつ前記段差の上方に屈曲部を有する
不揮発性記憶装置。 - 基板と、
前記基板上に形成された下部電極と、
前記下部電極上に形成され、第2の遷移金属酸化物で構成される第2の抵抗変化層と、
前記第2の抵抗変化層上に形成され、酸素含有率が前記第2の遷移金属酸化物の酸素含有率より低い第1の遷移金属酸化物で構成される第1の抵抗変化層と、
前記第1の抵抗変化層上に形成された上部電極とを備え、
前記下部電極と前記第2の抵抗変化層との界面には段差があり、
前記第2の抵抗変化層は、前記段差を被覆して形成されかつ前記段差の上方に屈曲部を有する
不揮発性記憶装置。 - 前記不揮発性記憶装置は、さらに、前記下部電極の下方にコンタクトプラグを有し、
前記下部電極と前記第1の抵抗変化層との界面は平坦である
請求項1記載の不揮発性記憶装置。 - 前記第2の抵抗変化層の屈曲部が前記第2の抵抗変化層を上方からみたときライン状である
請求項1または2に記載の不揮発性記憶装置。 - 前記第2の抵抗変化層の屈曲部が前記第2の抵抗変化層を上方からみたときリング状である
請求項1または2に記載の不揮発性記憶装置。 - 前記段差は複数の段差からなり、該複数の段差が交わった交点が存在する
請求項1または2に記載の不揮発性記憶装置。 - 前記第1の遷移金属酸化物及び前記第2の遷移金属酸化物は、タンタル、ハフニウムまたはジルコニウムの酸化物から構成される
請求項1または2に記載の不揮発性記憶装置。 - 前記下部電極もしくは前記上部電極に接して、ダイオード素子が形成されている
請求項1または2に記載の不揮発性記憶装置。 - 基板上に下部電極を形成する工程と、
前記下部電極上に第1の遷移金属酸化物で構成される第1の抵抗変化層を形成する工程と、
前記第1の抵抗変化層の表面に段差を形成する工程と、
前記第1の抵抗変化層の前記段差を被覆して、酸素含有率が前記第1の遷移金属酸化物の酸素含有率より高い第2の遷移金属酸化物で構成され、かつ前記段差の上方に屈曲部を有する第2の抵抗変化層を形成する工程と、
前記第2の抵抗変化層上に上部電極を形成する工程とを有する
不揮発性記憶装置の製造方法。 - 基板上に下部電極を形成する工程と、
前記下部電極の表面に段差を形成する工程と、
前記下部電極の前記段差を被覆して、第2の遷移金属酸化物で構成され、かつ前記段差の上方に屈曲部を有する第2の抵抗変化層を形成する工程と、
前記第2の抵抗変化層上に、酸素含有率が前記第2の遷移金属酸化物の酸素含有率より低い第1の遷移金属酸化物で構成される第1の抵抗変化層を形成する工程と、
前記第1の抵抗変化層上に上部電極を形成する工程とを有する
不揮発性記憶装置の製造方法。 - 基板上に下部電極を形成する工程と、
前記下部電極上に第1の遷移金属酸化物で構成される第1の抵抗変化層を形成する工程と、
前記第1の抵抗変化層上に、酸素含有率が前記第1の遷移金属酸化物の酸素含有率より高い第2の遷移金属酸化物で構成される第2の抵抗変化層を形成する工程と、
前記第2の抵抗変化層に段差を形成した後、該段差を被覆して前記第2の抵抗変化層を更に積み増す工程と、
積み増された前記第2の抵抗変化層上に上部電極を形成する工程とを有する
不揮発性記憶装置の製造方法。
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JP2011503298A JP4722236B2 (ja) | 2009-09-14 | 2010-09-13 | 不揮発性記憶装置及びその製造方法 |
CN201080003184.7A CN102217067B (zh) | 2009-09-14 | 2010-09-13 | 非易失性存储装置及其制造方法 |
US13/129,215 US8389972B2 (en) | 2009-09-14 | 2010-09-13 | Nonvolatile memory device and method of manufacturing the same |
US13/752,601 US8492743B2 (en) | 2009-09-14 | 2013-01-29 | Nonvolatile memory device and method of manufacturing the same |
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Also Published As
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US8492743B2 (en) | 2013-07-23 |
CN102217067A (zh) | 2011-10-12 |
US20130140514A1 (en) | 2013-06-06 |
JPWO2011030559A1 (ja) | 2013-02-04 |
US20110220863A1 (en) | 2011-09-15 |
US8389972B2 (en) | 2013-03-05 |
CN102217067B (zh) | 2014-07-30 |
JP4722236B2 (ja) | 2011-07-13 |
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