WO2010100949A1 - Iii族窒化物半導体発光素子及びその製造方法、並びにランプ - Google Patents
Iii族窒化物半導体発光素子及びその製造方法、並びにランプ Download PDFInfo
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- WO2010100949A1 WO2010100949A1 PCT/JP2010/001567 JP2010001567W WO2010100949A1 WO 2010100949 A1 WO2010100949 A1 WO 2010100949A1 JP 2010001567 W JP2010001567 W JP 2010001567W WO 2010100949 A1 WO2010100949 A1 WO 2010100949A1
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- type semiconductor
- translucent electrode
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 353
- 150000004767 nitrides Chemical class 0.000 title claims abstract description 114
- 238000000034 method Methods 0.000 title claims description 111
- 238000004519 manufacturing process Methods 0.000 title claims description 29
- 239000000758 substrate Substances 0.000 claims abstract description 83
- 239000013078 crystal Substances 0.000 claims abstract description 49
- 239000000463 material Substances 0.000 claims description 43
- 230000008569 process Effects 0.000 claims description 25
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 8
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 claims description 8
- 229910001195 gallium oxide Inorganic materials 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052738 indium Inorganic materials 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 claims description 6
- UPGUYPUREGXCCQ-UHFFFAOYSA-N cerium(3+) indium(3+) oxygen(2-) Chemical compound [O--].[O--].[O--].[In+3].[Ce+3] UPGUYPUREGXCCQ-UHFFFAOYSA-N 0.000 claims description 5
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 5
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 5
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- 230000004888 barrier function Effects 0.000 description 12
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 11
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- 239000010980 sapphire Substances 0.000 description 11
- 238000000926 separation method Methods 0.000 description 11
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- 230000000052 comparative effect Effects 0.000 description 10
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 9
- 239000011777 magnesium Substances 0.000 description 9
- 238000005546 reactive sputtering Methods 0.000 description 9
- 238000000137 annealing Methods 0.000 description 7
- 229910052732 germanium Inorganic materials 0.000 description 7
- 238000001451 molecular beam epitaxy Methods 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 6
- 239000000969 carrier Substances 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 6
- 239000010931 gold Substances 0.000 description 6
- 238000010030 laminating Methods 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 6
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- 230000009471 action Effects 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 239000002019 doping agent Substances 0.000 description 5
- 229910052757 nitrogen Inorganic materials 0.000 description 5
- 239000002994 raw material Substances 0.000 description 5
- 229910010413 TiO 2 Inorganic materials 0.000 description 4
- 229910021529 ammonia Inorganic materials 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
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- 230000031700 light absorption Effects 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 4
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- 238000006243 chemical reaction Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
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- -1 gallium nitride compound Chemical class 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 238000002834 transmittance Methods 0.000 description 3
- 239000011787 zinc oxide Substances 0.000 description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 2
- 229910005191 Ga 2 O 3 Inorganic materials 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
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- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- AMWRITDGCCNYAT-UHFFFAOYSA-L hydroxy(oxo)manganese;manganese Chemical compound [Mn].O[Mn]=O.O[Mn]=O AMWRITDGCCNYAT-UHFFFAOYSA-L 0.000 description 2
- 238000005286 illumination Methods 0.000 description 2
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- 229910052718 tin Inorganic materials 0.000 description 2
- VOITXYVAKOUIBA-UHFFFAOYSA-N triethylaluminium Chemical compound CC[Al](CC)CC VOITXYVAKOUIBA-UHFFFAOYSA-N 0.000 description 2
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- OTRPZROOJRIMKW-UHFFFAOYSA-N triethylindigane Chemical compound CC[In](CC)CC OTRPZROOJRIMKW-UHFFFAOYSA-N 0.000 description 2
- IBEFSUTVZWZJEL-UHFFFAOYSA-N trimethylindium Chemical compound C[In](C)C IBEFSUTVZWZJEL-UHFFFAOYSA-N 0.000 description 2
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- 229910006404 SnO 2 Inorganic materials 0.000 description 1
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- LNRYQGINUXUWLV-UHFFFAOYSA-N [Mn].[Fe].[Zn] Chemical compound [Mn].[Fe].[Zn] LNRYQGINUXUWLV-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- GSWGDDYIUCWADU-UHFFFAOYSA-N aluminum magnesium oxygen(2-) Chemical compound [O--].[Mg++].[Al+3] GSWGDDYIUCWADU-UHFFFAOYSA-N 0.000 description 1
- HZMPWQGNGPZWRV-UHFFFAOYSA-N aluminum strontium lanthanum(3+) oxygen(2-) tantalum(5+) Chemical compound [O-2].[Ta+5].[Al+3].[Sr+2].[La+3] HZMPWQGNGPZWRV-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
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- 229910052791 calcium Inorganic materials 0.000 description 1
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- 229910000420 cerium oxide Inorganic materials 0.000 description 1
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- 238000010586 diagram Methods 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
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- 238000000227 grinding Methods 0.000 description 1
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- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
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- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
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- QBJCZLXULXFYCK-UHFFFAOYSA-N magnesium;cyclopenta-1,3-diene Chemical compound [Mg+2].C1C=CC=[C-]1.C1C=CC=[C-]1 QBJCZLXULXFYCK-UHFFFAOYSA-N 0.000 description 1
- AXZKOIWUVFPNLO-UHFFFAOYSA-N magnesium;oxygen(2-) Chemical compound [O-2].[Mg+2] AXZKOIWUVFPNLO-UHFFFAOYSA-N 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
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- QEFYFXOXNSNQGX-UHFFFAOYSA-N neodymium atom Chemical compound [Nd] QEFYFXOXNSNQGX-UHFFFAOYSA-N 0.000 description 1
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
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- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 1
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- 229910052726 zirconium Inorganic materials 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
- H01L33/145—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/025—Physical imperfections, e.g. particular concentration or distribution of impurities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
- H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/40—Materials therefor
- H01L33/42—Transparent materials
Definitions
- the present invention relates to a group III nitride semiconductor light-emitting device having a light-emitting diode (LED) structure, a method for manufacturing the same, and a lamp.
- LED light-emitting diode
- Group III nitride semiconductors have attracted attention as semiconductor materials for light-emitting elements that emit light of short wavelengths.
- MOCVD method metal organic chemical vapor deposition method
- MBE method molecular beam epitaxy method
- an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer made of a group III nitride semiconductor are stacked in this order on a sapphire single crystal substrate.
- the sapphire substrate is an insulator, its element structure generally has a structure in which the positive electrode formed on the p-type semiconductor layer and the negative electrode formed on the n-type semiconductor layer exist on the same plane.
- a sapphire substrate using a translucent electrode as a positive electrode to extract light from the p-type semiconductor side and a highly reflective film such as Ag as a positive electrode there are two types of flip chip methods that extract light from the side.
- External quantum efficiency is used as an index of the output of such a light emitting element. If the external quantum efficiency is high, it can be said that the light-emitting element has a high output.
- the external quantum efficiency is expressed as a product of the internal quantum efficiency and the light extraction efficiency.
- the internal quantum efficiency is a rate at which the energy of current injected into the device is converted into light in the light emitting layer.
- the light extraction efficiency is a ratio of light that can be extracted outside the light emitting element in the light generated in the light emitting layer. Therefore, in order to improve the external quantum efficiency, it is necessary to improve the light extraction efficiency in addition to the light emission efficiency in the light emitting layer.
- the gallium nitride compound semiconductor device having the above composition As a characteristic of the gallium nitride compound semiconductor device having the above composition, there is a small current diffusion in the lateral direction. For this reason, current is injected only into the semiconductor directly under the electrode, and light emitted from the light emitting layer is blocked by the electrode and is not extracted outside. Therefore, in such a light emitting element, a translucent electrode is usually used, and light is extracted through the translucent electrode.
- a known conductive material such as a layer structure in which an oxide such as Ni or Co and Au as a contact metal are combined is used for the translucent electrode.
- the entire light emitting layer (semiconductor layer) emits light uniformly as well as directly under the electrode.
- a translucent electrode is provided on a semiconductor layer and a bonding pad electrode is provided thereon
- current concentration is generated immediately below the bonding pad electrode as described above. For this reason, the light emitting action by the light emitting layer is concentrated just under the bonding pad electrode as described above, and there is a possibility that the light emission efficiency is lowered and the luminance is lowered.
- Patent Documents 1 and 2 According to the light-emitting elements described in Patent Literatures 1 and 2, by providing the insulating layer having the above-described configuration, it is possible to effectively promote current diffusion in the lateral direction of the translucent electrode and to increase the light emission efficiency. Has been. However, Patent Documents 1 and 2 have a problem in that light emission is strong in the vicinity of the n-side bonding pad electrode, and it is difficult to obtain good electrical characteristics, and the light emission efficiency is not necessarily improved.
- the present invention has been made in view of the above problems, and current concentration in the translucent electrode and the semiconductor layer directly under the n-side bonding pad electrode is suppressed, so that the light emission efficiency is excellent, and light absorption and multiplexing by the electrodes are improved. It is an object of the present invention to provide a group III nitride semiconductor light-emitting device that suppresses loss due to reflection, has excellent light extraction efficiency, and has high external quantum efficiency and electrical characteristics. Another object of the present invention is to provide a method for producing a group III nitride semiconductor light-emitting device capable of producing a light-emitting device having excellent light emission efficiency and light extraction efficiency as described above. Furthermore, an object of the present invention is to provide a lamp that uses the above-mentioned group III nitride semiconductor light emitting device and has excellent light emission characteristics.
- the present inventor has intensively studied to solve the above problem, and in the conventional light emitting device, the sheet resistance of the n-side layer and the p-side layer is set to be approximately the same, and the current is uniformly diffused in terms of luminous efficiency.
- the sheet resistance of the n-type semiconductor layer on the n side is lower than the sheet resistance of the translucent electrode on the p side. It has been found that light extraction efficiency is improved by reducing light emission. At this time, it is clear that light absorption and multiple reflection by the p-side bonding pad electrode can be prevented by providing an insulating layer immediately below.
- the present inventors have found that the sheet resistance of the n-side layer is dominant in the driving voltage of the light-emitting element, and by reducing the sheet resistance of the n-side layer, in particular, 30 to The inventors have found that the electrical characteristics are greatly improved when a large driving current of about 100 mA is applied to the light emitting element, and thus completed the present invention. That is, the present invention relates to the following.
- a semiconductor layer in which an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer are sequentially stacked is formed on a single crystal group III nitride semiconductor layer formed on a substrate, and the p-type semiconductor
- a positive electrode bonding pad is provided on the surface of the translucent electrode above the insulating layer provided on the p-type semiconductor layer, and a sheet resistance of the n-type semiconductor layer However, it is lower than the sheet resistance of the said translucent electrode,
- the group III nitride semiconductor light-emitting device characterized by the above-mentioned.
- the translucent electrode includes indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium cerium oxide (ICO: Indium Tin Oxide).
- a method of manufacturing a group III nitride semiconductor light-emitting device comprising: a semiconductor layer forming step of forming a transparent electrode; and a transparent electrode forming step of forming a transparent electrode on the p-type semiconductor layer,
- the translucent electrode forming step an insulating layer is formed on at least a part of the p-type semiconductor layer, and then the translucent electrode is formed on the p-type semiconductor layer so as to cover the insulating layer,
- a positive electrode forming step of forming a positive electrode bonding pad above the insulating layer formed on the p-type semiconductor layer on the surface of the translucent electrode is provided,
- the semiconductor layer forming step is the n-type
- the n-type semiconductor layer is formed to have a sheet resistance of 15 ⁇ / ⁇ or less, and in the translucent electrode forming step, the translucent electrode is set to 30 ⁇ / ⁇ or less.
- the translucent electrode forming step includes indium tin oxide (ITO), indium zinc oxide (IZO), and indium gallium oxide (IGO) as materials for forming the translucent electrode. Any one of the above [6] to [8], wherein at least one selected from the group consisting of Indium Gallium Oxide), Indium Cerium Oxide (ICO) and Conductive Titanium Oxide (TiO 2 ) is used.
- the III according to any one of [6] to [9], wherein the translucent electrode forming step uses silicon oxide (SiO 2 ) as a material for forming the insulating layer.
- a lamp comprising the group III nitride semiconductor light-emitting device according to any one of [1] to [5] above.
- a transparent electrode is formed on the p-type semiconductor layer, and an insulating layer is provided on at least a part of the p-type semiconductor layer, and the transparent electrode covers the insulating layer. Since the positive electrode bonding pad is provided above the insulating layer provided on the p-type semiconductor layer on the surface of the translucent electrode, at a position corresponding to the positive electrode bonding pad in the translucent electrode and the semiconductor layer.
- an epitaxial process for forming a single crystal group III nitride semiconductor layer on a substrate, and an n-type semiconductor layer on the group III nitride semiconductor layer A semiconductor layer forming step of forming a semiconductor layer by sequentially laminating a light emitting layer and a p-type semiconductor layer, and a translucent electrode forming step of forming a translucent electrode on the p-type semiconductor layer.
- the conductive electrode forming step an insulating layer is formed on at least a part of the p-type semiconductor layer, and then a translucent electrode is formed on the p-type semiconductor layer so as to cover the insulating layer.
- a positive electrode forming step of forming a positive electrode bonding pad on the surface of the translucent electrode and above the insulating layer formed on the p-type semiconductor layer is provided.
- Sheet resistance is higher than sheet resistance of translucent electrode Since the n-type semiconductor layer is formed so as to be low, the above-described group III nitride semiconductor light-emitting device having excellent light emission efficiency and light extraction efficiency, high external quantum efficiency, and excellent electrical characteristics Can be manufactured.
- the lamp according to the present invention uses the group III nitride semiconductor light-emitting device of the present invention, the lamp has excellent light emission characteristics.
- FIG. 4 is a diagram schematically illustrating another example of the group III nitride semiconductor light-emitting device according to the present invention, and is a perspective view illustrating a main part of FIG. 3.
- a group III nitride semiconductor light-emitting device (hereinafter sometimes abbreviated as a light-emitting device) according to the present invention, a manufacturing method thereof, and an embodiment of a lamp will be described with reference to FIGS. 1 to 6 as appropriate. .
- the light emitting device 1 includes a single crystal underlayer (group III nitride semiconductor layer) 3 formed on the main surface 11a of the substrate 11 as shown in FIG. 1 and FIG.
- a semiconductor layer 20 in which a p-type semiconductor layer 4, a light emitting layer 5, and a p-type semiconductor layer 6 are sequentially stacked is formed, and a translucent electrode 7 is formed on the p-type semiconductor layer 6.
- An insulating layer 15 is provided on at least a part of the transparent electrode 7, and the translucent electrode 7 is formed so as to cover the insulating layer 15.
- the light emitting element 1 of the illustrated example has a planar shape in the direction in which the positive electrode bonding pad 8 and the negative electrode bonding pad 9 are separated, that is, the chip length dimension (L) in FIG. 2 is the chip width dimension (W). It is longer than that and is configured as a substantially rectangular shape.
- the light emitting element 1 of the example demonstrated by this embodiment is comprised as a light emitting diode (LED) like an example of illustration with the said structure.
- LED light emitting diode
- the material that can be used for the substrate 11 as described above is not particularly limited as long as it is a substrate material on which a group III nitride semiconductor crystal is epitaxially grown, and various materials are selected.
- a substrate material on which a group III nitride semiconductor crystal is epitaxially grown can be used.
- sapphire is particularly preferably used, and the buffer layer 2 described in detail later is formed on the main surface 11a made of the c-plane of the substrate 11 made of sapphire. desirable.
- the buffer layer 2 is formed without using ammonia.
- the buffer layer 2 also functions as a coat layer, which is effective in preventing chemical alteration of the substrate 11.
- the temperature of the substrate 11 can be kept low. Therefore, even when the substrate 11 made of a material that decomposes at a high temperature is used, the substrate 11 is damaged.
- Each layer can be formed on the substrate without giving.
- Buffer layer In the present invention, it is preferable to form the buffer layer 2 on the main surface 11a of the substrate 11 and form the underlayer 3 thereon.
- Buffer layer 2 for example, is laminated on the substrate 11 by Al X Ga 1-X N ( 0 ⁇ x ⁇ 1) having a composition, for example, activated by plasma and a gas and metal material including a V group element reactions It can be formed by the reactive sputtering method.
- a film formed by a method using a plasma metal raw material as in this embodiment has an effect that alignment is easily obtained.
- the buffer layer 2 serves to alleviate the difference in lattice constant between the substrate 11 and the base layer 3 and facilitate the formation of a C-axis oriented single crystal layer on the C surface of the substrate 11. Therefore, when a single crystal group III nitride semiconductor layer (underlying layer 3) is laminated on the buffer layer 2, the underlayer 3 having better crystallinity can be formed.
- the buffer layer 2 may be omitted.
- the buffer layer 2 is preferably composed of the composition Al X Ga 1-X N (0 ⁇ x ⁇ 1), and more preferably AlN.
- the buffer layer to be laminated on the substrate preferably has a composition containing Al, and the group III nitride compound represented by the general formula Al X Ga 1-X N (0 ⁇ x ⁇ 1) Any material can be used, and a composition containing As or P as the group V can also be used.
- the buffer layer 2 has a composition containing Al, it is preferably GaAlN.
- the Al composition is more preferably 50% or more.
- the buffer layer 2 is most preferably configured with AlN.
- the material constituting the buffer layer 2 a material having the same crystal structure as that of the group III nitride semiconductor can be used, but the length of the lattice is close to that of the group III nitride semiconductor constituting the underlayer described later. And nitrides of group IIIa elements of the periodic table are particularly preferred.
- the group III nitride crystal forming the buffer layer 2 has a hexagonal crystal structure, and can be formed into a single crystal film by controlling the film forming conditions. Further, the group III nitride crystal can be formed into a columnar crystal (polycrystal) having a texture based on a hexagonal column by controlling the film forming conditions. Note that the columnar crystal described here is a crystal which is separated by forming a crystal grain boundary between adjacent crystal grains, and is itself a columnar shape as a longitudinal sectional shape.
- the buffer layer 2 preferably has a single crystal structure from the viewpoint of the buffer function.
- the group III nitride crystal has a hexagonal crystal and forms a structure based on a hexagonal column.
- Group III nitride crystals can be grown not only in the upward direction but also in the in-plane direction by controlling the film formation conditions and the like.
- the buffer layer 2 having such a single crystal structure is formed on the substrate 11, the buffer function of the buffer layer 2 works effectively, so that the group III nitride semiconductor layer formed thereon is A crystal film having good orientation and crystallinity is obtained.
- the thickness of the buffer layer 2 is preferably in the range of 0.01 to 0.5 ⁇ m. By setting the film thickness of the buffer layer 2 within this range, the buffer has good orientation and effectively functions as a coat layer when each layer made of a group III nitride semiconductor is formed on the buffer layer 2. Layer 2 is obtained. When the thickness of the buffer layer 2 is less than 0.01 ⁇ m, a sufficient function as the above-described coat layer cannot be obtained, and a buffer function that relaxes the difference in lattice constant between the substrate 11 and the base layer 3 can be obtained. It may not be obtained sufficiently.
- the buffer layer 2 when the buffer layer 2 is formed with a film thickness exceeding 0.5 ⁇ m, the film forming process time becomes long despite the fact that the buffer function and the function as the coat layer are not changed, and the productivity may be reduced. There is.
- the thickness of the buffer layer 2 is more preferably in the range of 0.02 to 0.1 ⁇ m.
- the underlayer (group III nitride semiconductor layer) 3 provided in the light emitting device 1 of the present invention is made of a group III nitride semiconductor as described above, and is laminated on the buffer layer 2 by a conventionally known MOCVD method. can do.
- the use of the 1-y N layer (0 ⁇ y ⁇ 1, preferably 0 ⁇ y ⁇ 0.5, more preferably 0 ⁇ y ⁇ 0.1) allows formation of the underlayer 3 with good crystallinity. And more preferable.
- a material different from that of the buffer layer 2 may be used as the material of the base layer 3, but the same material as that of the buffer layer 2 may be used.
- the underlayer 3 may have a configuration in which n-type impurities are doped within the range of 1 ⁇ 10 17 to 1 ⁇ 10 19 atoms / cm 3 as necessary, but may be undoped ( ⁇ 1 ⁇ 10 17 elements). / Cm 3 ), and undoped is preferable in that good crystallinity can be maintained.
- the substrate 11 is conductive, electrodes can be formed above and below the light emitting element by doping the base layer 3 with a dopant to make it conductive.
- an insulating material is used for the substrate 11, a chip structure is provided in which the positive electrode and the negative electrode are provided on the same surface of the light emitting element.
- the n-type impurity doped in the underlayer 3 is not particularly limited, and examples thereof include Si, Ge, and Sn, and preferably Si and Ge.
- the thickness of the underlayer 3 is preferably in the range of 1 to 8 ⁇ m from the viewpoint of obtaining an underlayer with good crystallinity, and in the range of 2 to 5 ⁇ m shortens the process time required for film formation. This is more preferable in terms of productivity.
- the semiconductor layer 20 formed on the base layer 3 includes an n-type semiconductor layer 4, a light emitting layer 5, and a p-type semiconductor layer each made of a group III nitride semiconductor. Each layer of such a semiconductor layer 20 is formed by MOCVD, so that higher crystallinity can be obtained.
- the n-type semiconductor layer 4 is usually composed of an n-type contact layer 4a and an n-type cladding layer 4b.
- the n-type contact layer 4a can also serve as the n-type cladding layer 4b.
- the n-type contact layer 4a is a layer for providing a negative electrode.
- the n-type contact layer 4a is composed of an Al x Ga 1-x N layer (0 ⁇ x ⁇ 1, preferably 0 ⁇ x ⁇ 0.5, more preferably 0 ⁇ x ⁇ 0.1). preferable.
- the n-type contact layer 4a is preferably doped with an n-type impurity, and the n-type impurity is preferably 1.5 ⁇ 10 17 to 1.5 ⁇ 10 20 / cm 3 , preferably 1.5 ⁇ 10 18.
- n-type semiconductor layer 4 When contained at a concentration of ⁇ 1.5 ⁇ 10 19 / cm 3 , it is preferable in terms of maintaining good ohmic contact with the negative electrode and effectively reducing the sheet resistance Rs2 of the n-type semiconductor layer 4.
- an n-type impurity For example, Si, Ge, Sn, etc. are mentioned, Preferably Si and Ge are mentioned.
- the film thickness of the n-type contact layer 4a is preferably 0.5 to 5 ⁇ m, and more preferably set to a range of 1 to 3 ⁇ m. When the film thickness of the n-type contact layer 4a is in the above range, the crystallinity of the semiconductor is favorably maintained.
- the n-type cladding layer 4b is a layer that injects carriers into the light emitting layer 5 and confines carriers.
- the n-type cladding layer 4b can be formed of AlGaN, GaN, GaInN, or the like. Alternatively, a heterojunction of these structures or a superlattice structure in which a plurality of layers are stacked may be used. Needless to say, when the n-type cladding layer 4b is formed of GaInN, it is preferably larger than the GaInN band gap of the light emitting layer 5.
- the film thickness of the n-type cladding layer 4b is not particularly limited, but is preferably 0.005 to 0.5 ⁇ m, and more preferably 0.005 to 0.1 ⁇ m.
- the n-type doping concentration of the n-type cladding layer 4b is preferably 1.5 ⁇ 10 17 to 1.5 ⁇ 10 20 / cm 3 , more preferably 1.5 ⁇ 10 18 to 1.5 ⁇ 10 19 / cm 3 . is there. A doping concentration within this range is preferable from the standpoint that it is possible to effectively reduce the sheet resistance Rs2 of the n-type semiconductor layer 4 in addition to maintaining good crystallinity and reducing the operating voltage of the element.
- the sheet resistance Rs2 of the n-type semiconductor layer 4 is lower than the sheet resistance Rs1 of the translucent electrode 7 to be described in detail later.
- the sheet resistance Rs2 of the n-type semiconductor layer 4 is preferably 15 ⁇ / ⁇ or less, and the sheet resistance Rs1 of the translucent electrode 7 is more preferably 30 ⁇ / ⁇ or less.
- the sheet resistance Rs2 of the n-type semiconductor layer 4 is as described above, it is preferable that the thickness of the entire n-type semiconductor layer 4 is 2 ⁇ m or more.
- a method of controlling the sheet resistance Rs2 of the n-type semiconductor layer 4 a method of controlling the doping amount of n-type impurities such as Si can also be performed.
- the sheet resistance Rs2 of the n-type semiconductor layer 4 has a characteristic lower than that of the sheet resistance Rs1 of the translucent electrode 7, a conventional light emitting device is provided with a doping amount of an n-type impurity such as Si.
- it is preferably about 1.5 times the standard doping amount of the n-type semiconductor layer.
- the sheet resistance Rs2 can be controlled within the desired range described above, and specifically, the dope amount is preferably set within the above range.
- the sheet resistance of the n-type semiconductor layer 4 and the p-side translucent electrode 7 is set to be approximately the same, whereby a current is uniformly supplied to the translucent electrode 7 and the semiconductor layer 20. It has been considered preferable to diffuse in view of luminous efficiency. However, such a configuration has a problem that the light emission efficiency and the light extraction efficiency are lowered.
- an insulating layer 15 (to be described in detail later) is provided on the p-type semiconductor layer 6 and the sheet resistance (Rs2) of the n-type semiconductor layer 4 is transparent.
- the sheet resistance (Rs1) of the photoelectrode 7 By controlling to be lower than the sheet resistance (Rs1) of the photoelectrode 7, light emission near the negative electrode bonding pad 9 provided on the n-type semiconductor layer 4 is suppressed, while the light emitting layer 15 is removed. It has been found that the light extraction efficiency is improved in the vicinity of the positive electrode bonding pad 8 that is not formed because the area of the portion with high emission intensity is increased.
- the present inventors have found that the sheet resistance Rs2 of the n-type semiconductor layer 4 works dominantly on the driving voltage (Vf) of the light emitting element 1, and this sheet resistance Rs2 is used as the sheet of the translucent electrode 7. It has been found that the electrical characteristics are greatly improved by lowering the resistance (Rs1). Thereby, the light extraction efficiency is improved, the external quantum efficiency is excellent, and the light emitting device 1 having high light emission output and electrical characteristics is obtained.
- the n-type cladding layer 4b is a layer including a superlattice structure, a detailed illustration is omitted, but an n-side first layer made of a group III nitride semiconductor having a thickness of 100 angstroms or less. And an n-side second layer made of a group III nitride semiconductor having a composition different from that of the n-side first layer and having a film thickness of 100 angstroms or less may be included.
- the n-type cladding layer 4b may include a structure in which n-side first layers and n-side second layers are alternately and repeatedly stacked. Preferably, either the n-side first layer or the n-side second layer is in contact with the light emitting layer 5).
- the n-side first layer and the n-side second layer as described above include, for example, AlGaN-based Al (sometimes simply referred to as AlGaN), GaInN-based (including simply InGaN), and In.
- the composition can be GaN.
- the n-side first layer and the n-side second layer are composed of an alternate structure of GaInN / GaN, an alternate structure of AlGaN / GaN, an alternate structure of GaInN / AlGaN, and an alternate structure of GaInN / GaInN having different compositions (“The description of “differing composition” means that each elemental composition ratio is different, and the same applies hereinafter), and may be an AlGaN / AlGaN alternating structure having a different composition.
- the n-side first layer and the n-side second layer are preferably GaInN / GaInN having different GaInN / GaN structures or different compositions.
- the superlattice layers of the n-side first layer and the n-side second layer are each preferably 60 angstroms or less, more preferably 40 angstroms or less, and each in the range of 10 angstroms to 40 angstroms. Most preferred. If the film thickness of the n-side first layer and the n-side second layer forming the superlattice layer is more than 100 angstroms, crystal defects are likely to occur, which is not preferable.
- the n-side first layer and the n-side second layer may each have a doped structure, or a combination of a doped structure and an undoped structure.
- the impurity to be doped conventionally known impurities can be applied to the material composition without any limitation.
- Si is suitable as an impurity.
- the n-side superlattice multilayer film as described above may be manufactured while doping is appropriately turned ON / OFF, even if the composition represented by GaInN, AlGaN, or GaN is the same.
- the n-type cladding layer 4b has a layer structure including a superlattice structure, the light emission output is remarkably improved and the light emitting device 1 having excellent electric characteristics can be obtained.
- Light emitting layer Examples of the light emitting layer stacked on the n-type semiconductor layer include the light emitting layer 5 having a structure such as a single quantum well structure or a multiple quantum well structure.
- the well layer having a quantum well structure as shown in FIG. 1 is generally a group III nitride having a composition of Ga 1-y In y N (0 ⁇ y ⁇ 0.4) in the case of a structure emitting blue light.
- a material semiconductor is used, such as Ga 1-y In y N0.07 ⁇ y ⁇ 0.20. Used.
- the Ga 1-y In y N is used as the well layer 5b, and Al x Ga 1-x N (0 ⁇ 5) having a larger band gap energy than the well layer 5b. z ⁇ 0.3) is preferably the barrier layer 5a. Further, the well layer 5b and the barrier layer 5a may or may not be doped with impurities.
- the film thickness of the well layer 5b can be set to a film thickness that can provide a quantum effect, for example, 1 to 10 nm, and more preferably 2 to 6 nm, from the viewpoint of light emission output.
- the p-type semiconductor layer 6 is generally composed of a p-type cladding layer 6a and a p-type contact layer 6b.
- the p-type contact layer 6b can also serve as the p-type cladding layer 6a.
- the p-type cladding layer 6a is a layer for confining carriers in the light emitting layer 5 and injecting carriers.
- the composition of the p-type cladding layer 6a is not particularly limited as long as it is larger than the band gap energy of the light-emitting layer 5 and can confine carriers in the light-emitting layer 5, but is preferably Al x Ga 1-1. xN (0 ⁇ x ⁇ 0.4).
- the p-type cladding layer 6a is made of such AlGaN, it is preferable in terms of confining carriers in the light emitting layer.
- the film thickness of the p-type cladding layer 6a is not particularly limited, but is preferably 1 to 400 nm, more preferably 5 to 100 nm.
- the p-type doping concentration of the p-type cladding layer 6a is preferably 1 ⁇ 10 18 to 1 ⁇ 10 21 / cm 3 , more preferably 1 ⁇ 10 19 to 1 ⁇ 10 20 / cm 3 .
- the p-type dope concentration is in the above range, a good p-type crystal can be obtained without reducing the crystallinity.
- the p-type cladding layer 6a may have a superlattice structure in which a plurality of layers are stacked.
- the p-type cladding layer 6a is a layer including a superlattice structure
- a detailed illustration is omitted, but a p-side first layer made of a group III nitride semiconductor having a thickness of 100 angstroms or less and A structure in which a p-side second layer made of a group III nitride semiconductor having a composition different from that of the p-side first layer and having a film thickness of 100 angstroms or less is stacked may be included. Further, it may include a structure in which p-side first layers and p-side second layers are alternately and repeatedly stacked.
- the p-side first layer and the p-side second layer as described above may have different compositions, for example, any composition of AlGaN, GaInN, or GaN.
- the GaInN / GaN alternating structure AlGaN.
- An alternating structure of / GaN or an alternating structure of GaInN / AlGaN may be used.
- the p-side first layer and the p-side second layer preferably have an AlGaN / AlGaN or AlGaN / GaN alternating structure.
- the superlattice layers of the p-side first layer and the p-side second layer are each preferably 60 angstroms or less, more preferably 40 angstroms or less, and each in the range of 10 angstroms to 40 angstroms. Is most preferred. If the thickness of the p-side first layer and the p-side second layer forming the superlattice layer exceeds 100 angstroms, it becomes a layer containing many crystal defects and the like, which is not preferable.
- the p-side first layer and the p-side second layer may each have a doped structure, or a combination of a doped structure and an undoped structure.
- the impurity to be doped conventionally known impurities can be applied to the material composition without any limitation.
- Mg is suitable as an impurity.
- the p-side superlattice multilayer film as described above may be manufactured while doping is appropriately turned on and off even if the composition represented by GaInN, AlGaN, and GaN is the same.
- the p-type cladding layer 6a has a layer structure including a superlattice structure, the light emission output is remarkably improved and the light emitting device 1 having excellent electric characteristics can be obtained.
- the p-type contact layer 6b is a layer for providing a positive electrode.
- the p-type contact layer 6b is preferably Al x Ga 1-x N (0 ⁇ x ⁇ 0.4).
- Al composition is in the above range, it is preferable in terms of maintaining good crystallinity and good ohmic contact with the p ohmic electrode.
- a p-type impurity (dopant) is contained at a concentration of 1 ⁇ 10 18 to 1 ⁇ 10 21 / cm 3 , preferably 5 ⁇ 10 19 to 5 ⁇ 10 20 / cm 3 , good ohmic contact can be obtained. It is preferable in terms of maintenance, prevention of crack generation, and good crystallinity.
- the thickness of the p-type contact layer 6b is not particularly limited, but is preferably 0.01 to 0.5 ⁇ m, and more preferably 0.05 to 0.2 ⁇ m. When the film thickness of the p-type contact layer 6b is within this range, it is preferable in terms of light emission output.
- an insulating layer 15 made of an insulating material is provided at least partly on the p-type semiconductor layer 6, in the light emitting device 1 of the example shown in FIGS.
- the insulating layer 15 is formed so as to be covered with the translucent electrode 7.
- the material of the insulating layer 15 is not particularly limited, and a conventionally known insulating oxide film or the like can be used without any limitation, but silicon oxide (SiO 2 ) is particularly preferable.
- the conductive thin film forming the translucent electrode 7 that is not provided with the insulating layer 15 made of an insulating material is formed in the lateral direction rather than the current diffusion in the vertical direction (semiconductor layer direction). Since current diffusion in the (in-film direction) is small, current concentration tends to occur immediately below the bonding pad electrode (positive electrode bonding pad 8) formed thereon. For this reason, the region where the light emitting action is obtained in the light emitting layer 5 is only directly below the bonding pad electrode, and there is a problem that the light emission efficiency of the light extracted from the light emitting element is lowered and a desired luminance cannot be obtained.
- the insulating layer 15 having the above-described structure covered with the translucent electrode 7 is provided on the p-type semiconductor layer 6, thereby allowing the translucent electrode 7 to be within the film.
- Current diffusion at is promoted. That is, in the translucent electrode 8 and the semiconductor layer 20, the current is diffused mainly in the periphery of the position corresponding to the insulating layer 15 and the positive electrode bonding pad 8.
- the light emitting action is suppressed at a position immediately below the insulating layer 15 in the light emitting layer 5, and a good light emitting action is obtained in the peripheral part and the peripheral part of the negative electrode bonding pad 9, so that the light extracted from the light emitting element can be obtained.
- Luminous efficiency is improved. Therefore, the light emitting device 1 having excellent internal quantum efficiency and enhanced emission luminance can be realized.
- FIG. 5 is a graph showing the relationship between the forward current (I) of the light emitting element and the light emission output (Po).
- curves (a), (b), and (c) are provided with an insulating layer.
- the characteristics of the light emitting device according to the present invention are also shown.
- curves (d) and (e) indicate characteristics of a light-emitting element that does not include an insulating layer.
- the light emitting device according to the present invention in which an insulating layer is provided and current is diffused to the periphery of the insulating layer and the positive electrode bonding pad is compared with the light emitting device in which the insulating layer is not provided.
- a high light emission output (Po) can be obtained even when the forward current (I) is the same.
- the insulating layer 15 is provided on the p-type semiconductor layer 6, so that a current flows in the periphery of the position A corresponding to the insulating layer 15 and the positive electrode bonding pad 8 in the translucent electrode 7 and the semiconductor layer 20. This is considered to be because the light is diffused and the peripheral portion emits light effectively.
- the thickness of the insulating layer 15 is preferably in the range of 50 to 500 nm, and more preferably in the range of 100 to 300 nm. If the thickness of the insulating layer 15 is in the above range, the effect of suppressing the current concentration as described above can be obtained more effectively.
- the shape of the insulating layer 15 in plan view is not particularly limited, and for example, a substantially circular shape or a substantially square shape can be selected and adopted as appropriate. Is a substantially circular shape.
- the diameter is preferably larger than the diameter of the positive electrode bonding pad 8 within a range of 30 ⁇ m or less, and is 10 ⁇ m or less. It is more preferable to form large within the range.
- the translucent electrode 7 is a translucent electrode made of a conductive oxide film or the like, and a translucent material usually used in this technical field can be used without any limitation.
- a translucent material for example, ITO (In 2 O 3 —SnO 2 ), AZO (ZnO—Al 2 O 3 ), IZO (In 2 O 3 —ZnO: indium zinc oxide), GZO (Indium Zinc Oxide), GZO ( ZnO—Ga 2 O 3 ), IGO (In 2 O 3 —Ga 2 O 3 ), ICO (In 2 O 3 —Ce 2 O 3 ), titanium oxide doped with any impurity element (TiO 2 ), etc.
- the material to include is mentioned.
- reduced TiO 2 -X obtained by partially reducing TiO 2 may be used as titanium oxide, as long as it is conductive.
- examples of the material doped into titanium oxide include Nb. In the present invention, it is more preferable to use at least one of ITO, IZO, IGO, ICO, and conductive titanium oxide.
- the method of forming the translucent electrode 7 is not particularly limited, and can be provided by conventional means well known in this technical field.
- the structure of the translucent electrode 7 can also be used without any limitation including any conventionally known structure.
- the translucent electrode 7 may be formed so as to cover the entire surface of the insulating layer 15 and to cover almost the entire surface of the p-type semiconductor layer 6, or may be formed in a lattice shape or a tree shape with a gap. It is also possible.
- thermal annealing for the purpose of alloying or transparency may or may not be performed.
- the sheet resistance Rs2 of the n-type semiconductor layer 4 is lower than the sheet resistance Rs1 of the translucent electrode 7 on the p side.
- the light emitting layer 5 at the position around the positive electrode bonding pad 8 mainly emits light, so that light emission near the negative electrode bonding pad 9 provided on the n-type semiconductor layer 4 is suppressed, while the light emitting layer 15 In the vicinity of the positive electrode bonding pad 8 that has not been removed, the area of the portion with high emission intensity is increased, so that the light extraction efficiency is improved.
- the film thickness of the translucent electrode 7 can be made thin, the light transmittance can be improved and the light extraction efficiency can be further improved. Thereby, the light emitting element 1 which is excellent in light emission efficiency and light extraction efficiency, and has high light emission intensity and electrical characteristics can be realized.
- the sheet resistance Rs1 of the translucent electrode 7 is 30 ⁇ / ⁇ or less.
- the sheet resistance Rs2 of the n-type semiconductor layer 4 is lower than the sheet resistance Rs1 of the translucent electrode 7 on the p side, and the sheet resistance Rs2 of the n-type semiconductor layer 4 is 15 ⁇ / ⁇ .
- the method for controlling the sheet resistance Rs1 of the translucent electrode 7 is not particularly limited.
- a method of controlling the film resistance by adjusting the film thickness or annealing may be employed.
- the sheet resistance Rs1 of the translucent electrode 7 is made higher than the sheet resistance Rs2 of the n-type semiconductor layer 4 and the sheet resistance Rs1 is 30 ⁇ / ⁇ or less as in the present embodiment, for example, It is possible to control to a desired characteristic by reducing the film thickness.
- the thickness of the translucent electrode 7 is preferably 100 nm or less. By setting the thickness of the translucent electrode 7 as described above, the sheet resistance Rs1 can be controlled to 30 ⁇ / ⁇ or less. Further, the maximum thickness of the translucent electrode 7 is preferably set to 600 nm or less in consideration of productivity.
- the light emitting element 1 which concerns on this invention, it is more preferable to set it as the structure by which the unevenness
- FIG. Thereby, the light extraction efficiency from the translucent electrode 7 is improved, and the sheet resistance Rs1 of the translucent electrode 7 can be controlled by optimizing the shape and size of the unevenness.
- the positive electrode bonding pad 8 is provided on the translucent electrode 7, and the negative electrode bonding pad 9 is provided so as to be in contact with the n-type contact layer provided in the n-type semiconductor layer 4. .
- the positive electrode bonding pad 8 is provided on a part of the translucent electrode 7 made of a translucent conductive oxide film layer in contact with the p-type semiconductor layer 6 and the insulating layer 15. . Further, the positive electrode bonding pad 8 in the illustrated example is provided at a position A corresponding to the insulating layer 15 on the surface 7 a of the translucent electrode 7.
- the positive electrode bonding pad 8 is provided for electrical connection with a circuit board, a lead frame or the like.
- various structures using Au, Al, Ni, Cu and the like are well known, and these known materials and structures can be used without any limitation.
- the thickness of the positive electrode bonding pad 8 is preferably in the range of 100 to 1500 nm. In addition, in view of the characteristics of the bonding pad, the larger the thickness, the higher the bondability. Therefore, the thickness of the positive electrode bonding pad 8 is more preferably 300 nm or more.
- the positive electrode bonding pad 8 is preferably provided at the position A corresponding to the insulating layer 15 on the surface 7a of the translucent electrode 7.
- a through hole (not shown) is provided at a position A corresponding to the insulating layer 15 on the surface 7a of the translucent electrode 7, and the positive electrode bonding pad 8 is in contact with the insulating layer 15 through the through hole. It is also possible to have a configuration provided. With such a configuration, an effect that the bonding strength of the positive electrode bonding pad 8 is improved can be obtained.
- the negative electrode bonding pad 9 is formed in contact with the n-type semiconductor layer 4 of the semiconductor layer 20. For this reason, when forming the negative electrode bonding pad 9, a part of the light emitting layer 5 and the p-type semiconductor layer 6 is removed to expose the n-type contact layer of the n-type semiconductor layer 4, and the negative electrode bonding pad is formed thereon. 9 is formed.
- compositions and structures are known, and these known compositions and structures can be used without any limitation, and can be provided by conventional means well known in this technical field.
- the formation position on the light emitting element 1 and the distance between electrode centers of the positive electrode bonding pad 8 and the negative electrode bonding pad 9 described above are not particularly limited. However, in order to obtain more excellent light emission efficiency and light extraction efficiency, it is preferable to appropriately adjust the formation position of each bonding pad and the distance between the electrode centers.
- the light emitting element 1 having a substantially rectangular shape in plan view as in the example shown in FIGS. 1 and 2 is configured, first, the negative electrode bonding pad 9 is disposed near one end side in the longitudinal direction of the light emitting element 1 to emit light.
- a configuration in which the positive electrode bonding pad 8 is disposed in the vicinity of the approximate center of the element 1 or in the vicinity of the other end side in the longitudinal direction is preferable from the viewpoint of easily obtaining the high light emission efficiency and the light extraction efficiency as described above.
- the sheet resistance Rs2 of the n-type semiconductor layer 4 provided in the semiconductor layer 20 is lower than the sheet resistance Rs1 of the translucent electrode 7. This suppresses current concentration when current flows from the negative electrode bonding pad 9 through the n-type semiconductor layer 4 through the light-emitting layer 5 and the p-type semiconductor layer 6 and flows through the translucent electrode 7.
- the light emitting device 1 excellent in the above can be obtained.
- the chip size of the light emitting element 1 in plan view that is, the electrode separation direction dimension (chip length dimension) L in the direction in which the positive electrode bonding pad 8 and the negative electrode bonding pad 9 are separated, and the electrode separation direction.
- the chip width dimension W in the direction orthogonal to is not particularly limited.
- the electrode separation direction dimension L and the chip width dimension W may be a dimensional ratio in which the chip shape in plan view is a square shape, or may be a dimensional ratio in which the chip shape is a rectangular shape.
- the effect of improving the luminous efficiency according to the present invention can be obtained. However, in order to make the effect of improving the light emission efficiency obtained by the above configuration even more remarkable, as shown in the example of FIG. It is more preferable to make it long and have a substantially rectangular shape.
- the light-emitting element includes the insulating layer 15 having the above-described configuration, and the sheet resistance Rs2 of the n-type semiconductor layer 4 is lower than the sheet resistance Rs1 of the translucent electrode 7.
- the drive current (forward current) IF is preferably used in the range of about 30 to 100 mA.
- the light emitting element driven under such conditions is used for illumination using a reflector or the like, for headlamp applications, and the like.
- the light emitting element 1 is driven with a relatively large current to obtain a high light emission intensity, and is suitable for the above-described illumination application. A more preferable chip size when the light emitting element 1 is driven under the above conditions will be described in detail below.
- the dimension L in the electrode separation direction in a plan view is 400 ⁇ m or more, more preferably 400 to 550 ⁇ m
- the chip width dimension W is 180 ⁇ m or more, more preferably 180 to 260 ⁇ m.
- the chip size (W ⁇ L) in plan view can be a combination of 260 ⁇ 550 ⁇ m, 240 ⁇ 400 ⁇ m, 180 ⁇ 400 ⁇ m, and the like.
- the semiconductor layer 20 (light emission) immediately below the positive electrode bonding pad 8 is formed by adopting the above chip size and shape.
- the action of suppressing light emission in the layer 5) and suppressing light emission in the vicinity of the negative electrode bonding pad 9 becomes more remarkable.
- the light emitting layer 5 located mainly in the periphery of the positive electrode bonding pad 8 emits light effectively, while light emission near the negative electrode bonding pad 9 provided on the n-type semiconductor layer 4 is further suppressed. Therefore, in the periphery of the positive electrode bonding pad 8 from which the light emitting layer 15 has not been removed, the area of the portion with high light emission intensity is further increased, so that the light emission efficiency is further improved.
- the horizontal and vertical dimensions of the light-emitting element 1, that is, the electrode separation direction dimension L ⁇ the chip width dimension W are within the above range, and the area in plan view is about 180,000 ⁇ m 2 or less. It is preferable from the point that the above-mentioned effect of improving the luminous efficiency becomes remarkable.
- the planar view area is 154,000 ⁇ m 2
- the chip size (W ⁇ L) is 280 ⁇ 550 ⁇ m
- the planar view area is 143 If it is 2,000 ⁇ m 2 and 240 ⁇ 400 ⁇ m, it is 96,000 ⁇ m 2 , and if it is 180 ⁇ 400 ⁇ m, it is 72,000 ⁇ m 2 .
- the sheet resistance Rs2 on the n-type semiconductor layer 4 side is lower as the planar view area of the light emitting element is larger.
- the sheet resistance Rs2 on the n-type semiconductor layer 4 side is a translucent electrode particularly when the light emitting element is driven by applying a large current and has a large area in plan view, that is, a light emitting area. 7, the light emission efficiency improvement effect as described above can be obtained more remarkably.
- the electrode separation direction dimension L ⁇ chip width dimension W of the light emitting element 1 and the planar view area are within the above ranges, and the horizontal / vertical dimension ratio in the planar view, that is, (electrode separation) It is preferable that the direction dimension L) / (chip width dimension W) is in the range of 1.5 to 2.7 from the viewpoint that the above-described effect of improving the light emission efficiency becomes remarkable. For example, when the chip size (L ⁇ W) is 280 ⁇ 550 ⁇ m, the horizontal / vertical dimension ratio (L / W) is 2.0.
- the distance between the electrode centers of the positive electrode bonding pad 8 and the negative electrode bonding pad 9 described above is limited by the electrode separation direction dimension L of the light emitting element 1.
- the distance between the electrode centers is expressed by the following expression ⁇ dimension L dimension of the light emitting element L ⁇ 0.5 to 0.75 ⁇ with the planar view size and shape of the light emitting element 1 as the above conditions.
- the range is preferable because the effects of the present invention become remarkable and higher luminous efficiency can be obtained without causing uneven light emission.
- the sheet resistance Rs2 of the n-type semiconductor layer 4 is configured to be lower than the sheet resistance Rs1 of the translucent electrode 7, so that the light emitting device used by applying a large forward current IF. Even so, there is an effect that the occurrence of uneven light emission is suppressed.
- the n-type semiconductor layer 4, the light-emitting layer 5, and the p-type semiconductor layer 6 are sequentially formed on the single crystal base layer 3 formed on the substrate 11.
- a stacked semiconductor layer 20 is formed, a translucent electrode 7 is formed on the p-type semiconductor layer 6, and an insulating layer 15 is provided on at least a part of the p-type semiconductor layer 6 and the translucent light is transmitted.
- the conductive electrode 7 is formed so as to cover the insulating layer 15, and the positive electrode bonding pad 8 is provided on the surface 7 a of the translucent electrode 7 at a position A above the insulating layer 15 provided on the p-type semiconductor layer 6.
- the substrate 100 has a principal surface 110 composed of a plane 111 composed of a (0001) C plane and a plurality of convex portions 112.
- the base layer 103 may be formed by epitaxially growing a group III nitride semiconductor on the main surface 110 so as to cover the flat surface 111 and the convex portion 112.
- a plurality of convex portions 112 are formed on the substrate 11A in the example shown in FIGS. And the part in which the convex part 112 is not formed in the main surface 110 of the board
- substrate 100 is made into the plane 111 which consists of a (0001) C surface. Therefore, as in the example shown in FIGS. 3 and 4, the main surface 110 of the substrate 100 is composed of a flat surface 111 formed of a C surface and a plurality of convex portions 112.
- the convex portion 112 is composed of a surface 112c that is not parallel to the C-plane, and the C-plane does not appear on the surface 112c.
- the planar shape of the base 112a is substantially circular, the outer shape gradually decreases toward the top, and the side surface 112b has a bowl-like (hemispherical) shape curved outward. ing.
- a convex part is comprised from oxides or nitrides other than sapphire so that a detail may mention later, it is good also as a column shape.
- the planar arrangement of the convex portions 112 is arranged in a grid pattern at equal intervals.
- the protrusion 112 has a base width d 1 in the range of 0.05 to 1.5 ⁇ m, a height h in the range of 0.05 to 1 ⁇ m, and is not less than 1 ⁇ 4 of the base width d 1.
- the interval d 2 is 0.3 to 5 times the base width d 1 .
- the base width d 1 of the convex portion 112 refers to the length of the maximum width on the bottom side (base portion 12 a) of the convex portion 112.
- the distance d 2 between adjacent convex portions 112 refers to the distance between the edge of the base portion 112a of the protrusion 112 in closest proximity.
- the distance d 2 between the adjacent convex portions 112 is preferably 0.5 to 5 times the base width d 1 .
- the distance d 2 between the protrusions 112 is less than 0.3 times the base width d 1 , the plane formed by the C plane when epitaxially growing the base layer 103 constituting the n-type semiconductor layer 4 (semiconductor layer 20). It becomes difficult for crystal growth from above 111 to be promoted, and it becomes difficult to completely fill the protrusion 112 with the base layer 103, and the flatness of the surface 103a of the base layer 103 may not be sufficiently obtained.
- the crystal of the semiconductor layer forming the LED structure is formed on the base layer 103 by filling the protrusion 112, this crystal naturally has a lot of pits, and the III-nitride semiconductor light-emitting element formed is formed. It will lead to deterioration of output and electrical characteristics.
- the distance d 2 between the protrusions 112 exceeds 5 times the base width d 1 , the substrate 100 and the substrate 100 are formed when the group 100 nitride semiconductor light-emitting device is formed using the substrate 100.
- the chance of irregular reflection of light at the interface with the group III nitride semiconductor layer may be reduced, and the light extraction efficiency may not be sufficiently improved.
- the base width d 1 is preferably 0.05 to 1.5 ⁇ m. If the base width d 1 is less than 0.05 ⁇ m, when a group III nitride semiconductor light emitting device is formed using the substrate 100, the effect of irregularly reflecting light may not be obtained sufficiently. On the other hand, when the base width d 1 exceeds 1.5 ⁇ m, it is difficult to epitaxially grow the base layer 1033 by filling the convex portions 112. Even if an underlayer with good flatness and crystallinity can be formed, the strain between the underlayer and the light emitting layer increases, leading to a decrease in internal quantum efficiency. Further, if the base width d 1 is smaller in the above range, the light output of the light emitting element can be further improved.
- the base width d 1 is more preferably 0.05 to 1 ⁇ m.
- the height h of the convex 112 is preferably 0.05 to 1 ⁇ m. If the height h of the protrusion 112 is less than 0.05 ⁇ m, when a group III nitride semiconductor light emitting device is formed using the substrate 100, the effect of irregular reflection of light may not be obtained sufficiently. If the height h of the convex portion 112 exceeds 1 ⁇ m, it may be difficult to epitaxially grow the base layer 103 by filling the convex portion 112, and the surface flatness of the base layer 103 may not be sufficiently obtained. .
- the height h of the convex portion 112 is preferably 1/4 or more of the base width d 1.
- the effect of irregularly reflecting light when the substrate 100 is used to form a group III nitride semiconductor light-emitting device and the light extraction efficiency are improved. There is a possibility that the effect of improving cannot be obtained sufficiently.
- the shape of the convex part 112 is not limited to the example shown in FIG.3 and FIG.4, What kind of shape may be sufficient if it consists of a surface non-parallel to C surface.
- the planar shape of the base portion may be a substantially polygonal shape, the outer shape gradually decreases toward the top, and the side surface 111 may be curved outward.
- the side surface may have a substantially conical shape or a substantially polygonal pyramid shape including a slope whose outer shape gradually decreases toward the top.
- the shape which the inclination angle of a side surface changes in two steps may be sufficient.
- planar arrangement of the convex portions 112 is not limited to the illustrated example, and may be equally spaced or not equally spaced. Further, the planar arrangement of the convex portions 112 may be a quadrangular shape, a triangular shape, or a random shape.
- substrate 100 can be formed by etching the board
- the convex portion may be formed by depositing another material forming the convex portion on the C surface of the substrate 100 on the substrate.
- a method for depositing another material for forming the convex portion on the substrate for example, a sputtering method, a vapor deposition method, a CVD method, or the like can be used.
- the material forming the convex portion it is preferable to use a material having a refractive index substantially equal to the material of the substrate, such as oxide or nitride.
- the substrate is a sapphire substrate, for example, SiO 2 , Al 2 O 3 , SiN, ZnO, or the like can be used.
- the interface between the substrate 100 and the underlayer 103 is a buffer layer. Since the projections and depressions are formed through 102, light confinement inside the light emitting element is reduced by diffused reflection of light, and a light emitting element with excellent light extraction efficiency can be realized.
- the manufacturing method of the group III nitride semiconductor light emitting device includes an epitaxial process for forming a single crystal underlayer (group III nitride semiconductor layer) 3 on the main surface 11 a of the substrate 11, A semiconductor layer forming step in which the n-type semiconductor layer 4, the light emitting layer 5, and the p-type semiconductor layer 6 are sequentially stacked to form the semiconductor layer 20, and the translucent electrode 7 is formed on the p-type semiconductor layer 6.
- An electrode forming step, and the transparent electrode forming step covers the insulating layer 15 on the p-type semiconductor layer 6 after forming the insulating layer 15 on at least a part of the p-type semiconductor layer 6.
- positive electrode bonding is performed on the surface A of the translucent electrode 7 at a position A above the insulating layer 15 formed on the p-type semiconductor layer 6.
- a positive electrode forming step for forming the pad 8 is provided.
- Process is a method of the sheet resistance of the n-type semiconductor layer 4 to form a n-type semiconductor layer 4 to be lower than the sheet resistance of the transparent electrode 7.
- buffer layer formation process In the manufacturing method according to the present invention, it is preferable that a buffer layer forming step of forming the buffer layer 2 on the main surface 11a of the substrate 11 is provided before the epitaxial step. In the present invention, the buffer layer may be omitted. In this case, the buffer layer forming step may not be performed.
- Pretreatment of substrate In this embodiment, after introducing the substrate 11 into the chamber of the sputtering apparatus and before forming the buffer layer 2, it is desirable to perform pretreatment using a method such as reverse sputtering by plasma treatment.
- “Deposition of buffer layer” After performing the pretreatment to the substrate 11, on the main surface 11a of the substrate 11, by a reactive sputtering method, forming an Al X Ga 1-X N ( 0 ⁇ X ⁇ 1) comprising a buffer layer 2 of the composition.
- the ratio of the nitrogen flow rate with respect to the flow rate of the nitrogen source and the inert gas in the chamber of the sputtering apparatus is in the range of 50 to 100%. It is preferable to control so that it is about 75%.
- the ratio of the nitrogen flow rate to the flow rate of the nitrogen source and the inert gas in the chamber of the sputtering apparatus is set so that the nitrogen source is 1 to 50%. It is preferable to control to be within the range, and more preferably about 25%.
- the buffer layer is not limited to the reactive sputtering method described above, and can be formed using, for example, the MOCVD method. However, the buffer layer is formed using the reactive sputtering method from the viewpoint of simplification of the process. It is preferable.
- the growth method of the gallium nitride-based compound semiconductor (group III nitride semiconductor) when forming the underlayer 3, the n-type semiconductor layer 4, the light emitting layer 5, and the p-type semiconductor layer 6 is not particularly limited. All methods known to grow nitride semiconductors such as reactive sputtering, MOCVD (metal organic chemical vapor deposition), HVPE (hydride vapor deposition), MBE (molecular beam epitaxy) are applied. it can.
- n-type monosilane (SiH 4 ) or disilane (Si 2 H 6 ) is used as a Si raw material
- organic germanium compounds such as tetraethylgermanium ((C 2 H 5 ) 4 Ge) can be used.
- elemental germanium can also be used as a doping source.
- p-type for example, biscyclopentadienyl magnesium (Cp 2 Mg) or bisethylcyclopentadienyl magnesium (EtCp 2 Mg) is used as the Mg raw material.
- the gallium nitride-based compound semiconductor as described above can contain other group III elements in addition to Al, Ga, and In. If necessary, such as Ge, Si, Mg, Ca, Zn, and Be can be used. A dopant element can be contained. Furthermore, it is not limited to the element added intentionally, but may include impurities that are inevitably included depending on the film forming conditions and the like, as well as trace impurities that are included in the raw materials and reaction tube materials.
- the MOCVD method is preferably used because a film having good crystallinity can be obtained.
- an example using the MOCVD method in the epitaxial step and the semiconductor layer forming step is used. explain.
- a base layer 3 is formed on the buffer layer 2 formed on the substrate 11 by using a conventionally known MOCVD method.
- MOCVD method the method of forming the underlayer 3 using the MOCVD method is described.
- the method of laminating the underlayer 3 is not particularly limited, and crystal growth that can cause dislocation looping is produced. Any method can be used without any limitation.
- the MOCVD method, the MBE method, the VPE method, and the like are preferable in that a film with favorable crystallinity can be formed because migration can occur.
- the MOCVD method can be used more suitably in that a film having particularly good crystallinity can be obtained.
- the temperature of the substrate 11 when the underlayer 3 is formed is preferably 800 ° C. or higher. This is because atom migration tends to occur by increasing the temperature of the substrate 11 when forming the underlayer 3, and dislocation looping easily proceeds, more preferably 900 ° C. or more. 1000 ° C. or higher is most preferable.
- the temperature of the substrate 11 when forming the base layer 3 needs to be lower than the temperature at which the crystals decompose, and is preferably less than 1200 ° C. If the temperature of the substrate 11 when forming the underlayer 3 is within the above range, the underlayer 3 with good crystallinity can be obtained.
- the underlayer 3 can be formed by doping with impurities as necessary, but undoped is preferable from the viewpoint of improving crystallinity. It is also possible to form a base layer made of a group III nitride semiconductor using a reactive sputtering method. When the sputtering method is used, the apparatus can have a simple configuration as compared with the MOCVD method, the MBE method, or the like.
- semiconductor layer formation process Next, in the semiconductor layer forming step, after the epitaxial step, as shown in FIG. 1, a semiconductor composed of an n-type semiconductor layer 4, a light emitting layer 5, and a p-type semiconductor layer 6 on the base layer 3.
- the layer 20 is laminated using a conventionally known MOCVD method.
- the n-type semiconductor layer 4 is formed by sequentially laminating the n-type contact layer 4a and the n-type clad layer 4b on the base layer 3 formed by the epitaxial process using a conventionally known MOCVD method.
- a film forming apparatus for forming the n-type contact layer 4a and the n-type clad layer 4b the MOCVD apparatus used for forming the above-described underlayer 3 and the light-emitting layer 5 described later may be used by appropriately changing various conditions. Is possible.
- the n-type contact layer 4a and the n-type cladding layer 4b can be formed by a reactive sputtering method.
- n-type semiconductor layer 4 has a sheet resistance Rs2 that is lower than sheet resistance Rs1 of translucent electrode 7 formed in the subsequent translucent electrode formation step.
- a type semiconductor layer 4 is formed.
- the n-type semiconductor layer 4 is formed so that the sheet resistance Rs2 is, for example, 15 ⁇ / ⁇ or less.
- the method for adjusting the film thickness and the method for controlling the doping amount of n-type impurities such as Si are appropriately employed. Is possible.
- the n-type semiconductor layer 4 is formed so that the sheet resistance Rs2 is reduced.
- the doping amount of n-type impurities such as Si is compared with the doping amount in the conventional light emitting device. About 1.5 times.
- the n-type semiconductor layer 4 can be formed while controlling the sheet resistance Rs2 to be, for example, 15 ⁇ / ⁇ or less.
- the light emitting layer 5 is formed on the n-type cladding layer 4b (n-type semiconductor layer 4) by a conventionally known MOCVD method.
- the light emitting layer 5 formed in the present embodiment has a stacked structure starting with a GaN barrier layer and ending with the GaN barrier layer, and includes a seven-layer barrier layer 5 a made of GaN, and a non-doped layer.
- Six well layers 5b made of Ga 0.8 In 0.2 N are alternately stacked.
- the light emitting layer 5 can be formed using the same film forming apparatus (MOCVD apparatus) used for forming the n-type semiconductor layer 4 described above.
- the p-type semiconductor layer 6 composed of the p-type cladding layer 6a and the p-type contact layer 6b is formed on the light-emitting layer 5, that is, on the barrier layer 5a that is the uppermost layer of the light-emitting layer 5, by a conventionally known MOCVD method.
- MOCVD method a conventionally known MOCVD method.
- the p-type cladding layer 6a and the p-type contact layer 6b constituting the p-type semiconductor layer 6 can be formed by using a reactive sputtering method.
- a p-type cladding layer 6a made of Mg-doped Al 0.1 Ga 0.9 N is formed on the light emitting layer 5 (the uppermost barrier layer 5a), and further, Mg A p-type contact layer 6b made of Al 0.02 Ga 0.98 N doped with is formed.
- the same MOCVD apparatus can be used for stacking the p-type cladding layer 6a and the p-type contact layer 6b.
- not only Mg but also zinc (Zn), for example, can be used as the p-type impurity.
- the insulating layer 15 is formed on at least a part of the p-type semiconductor layer 6, and then the insulating layer 15 is covered on the p-type semiconductor layer 6.
- a translucent electrode 7 is formed on the substrate.
- the insulating layer 15 made of an insulating material is formed on at least a part of the p-type semiconductor layer 6, in the example shown in FIGS.
- the material used for forming the insulating layer 15 is not particularly limited, and a conventionally known insulating oxide film or the like can be used without any limitation.
- silicon oxide (SiO 2 ) can be used.
- a conventionally known method such as a sputtering method can be used without any limitation.
- the transparent electrode 7 is formed by laminating IZO on the p-type semiconductor layer 6 formed by the above method so as to cover the insulating layer 15.
- the method for forming the translucent electrode 7 is not particularly limited, and can be provided by conventional means well known in this technical field. In addition, any structure including a conventionally known structure can be used without any limitation.
- the translucent electrode 7 can be formed using a material such as ITO, ITO, IGO, ICO, AZO, GZO, or conductive titanium oxide (for example, TiO 2 doped with Nb) in addition to IZO. . Moreover, after forming the translucent electrode 7, you may perform the thermal annealing for the purpose of alloying and transparency.
- the translucent electrode forming step of the present embodiment it is more preferable to form irregularities on the surface 7 a of the translucent electrode 7. Thereby, the light extraction efficiency from the translucent electrode 7 is improved, and the sheet resistance Rs1 of the translucent electrode 7 can be controlled by appropriately adjusting the shape and size of the unevenness.
- the sheet resistance Rs2 of the n-type semiconductor layer 4 is formed to be lower than the sheet resistance Rs1 of the translucent electrode 7.
- the sheet resistance Rs2 of the n-type semiconductor layer 4 is translucent while the translucent electrode 7 is controlled so that the sheet resistance Rs1 is, for example, 30 ⁇ / ⁇ or less. It is necessary to form the conductive electrode 7 so as to be lower than the sheet resistance Rs1. For this reason, by forming the film thickness of the translucent electrode 7 to be, for example, 100 nm or more and 600 nm or less, the sheet resistance Rs1 of the translucent electrode 7 can be controlled to be 30 ⁇ / ⁇ or less. .
- a method of controlling the sheet resistance Rs1 of the translucent electrode 7 there is a method of reducing the resistance value by performing an annealing treatment in addition to the method of optimizing the film thickness as described above.
- the annealing process to the translucent electrode 7 it is preferable to carry out on the conditions made into the temperature range of 500 degreeC or more and 900 degrees C or less in nitrogen atmosphere.
- the crystal structure of the translucent electrode 7 becomes a hexagonal crystal, and the sheet resistance Rs1 can be effectively reduced and controlled to a desired resistance value.
- the annealing temperature exceeds 900 ° C.
- the crystal structure of the translucent electrode made of IZO becomes cubic, and it becomes difficult to control the sheet resistance Rs1 appropriately.
- the sheet resistance Rs1 of the translucent electrode 7 is, for example, 30 ⁇ / ⁇ or less, and the relationship between the translucent electrode 7 and the sheet resistances Rs1 and Rs2 of the n-type semiconductor layer 4 is as follows. Thus, it becomes easy to control the relationship represented by the following formula (Rs1> Rs2).
- the positive electrode bonding pad 8 is formed on the surface 7 a of the translucent electrode 7 at the position A corresponding to the insulating layer 15 formed on the p-type semiconductor layer 6.
- the positive electrode bonding pad 8 can be formed, for example, by laminating Ti, Al, and Au materials in order from the surface side of the translucent electrode 7 by a conventionally known method.
- Formation of negative electrode bonding pads When forming the negative electrode bonding pad 9, first, a part of the p-type semiconductor layer 6, the light emitting layer 5 and the n-type semiconductor layer 4 formed on the substrate 11 is removed by a method such as dry etching, whereby n A part of the mold contact layer 4a is exposed. Then, on this exposed region, for example, each material of Ni, Al, Ti, and Au is laminated in order from the surface side of the exposed region by a conventionally known method, so that the detailed illustration is omitted. A negative electrode bonding pad 9 can be formed.
- the planar view shape is as shown in FIG. More preferably, it is formed as a long, substantially rectangular shape. Thereby, it becomes possible to manufacture the light emitting element 1 which is more excellent in luminous efficiency.
- an epitaxial layer for forming a single crystal underlayer (group III nitride semiconductor layer) 3 on the main surface 11a of the substrate 11 is formed.
- a step of forming a semiconductor layer 20 by sequentially stacking an n-type semiconductor layer 4, a light emitting layer 5, and a p-type semiconductor layer 6 on the base layer 3; and a light-transmitting property on the p-type semiconductor layer 6.
- the translucent electrode forming step includes forming the insulating layer 15 on at least part of the p-type semiconductor layer 6, and then forming the insulating layer 15 on the p-type semiconductor layer 6.
- the translucent electrode 7 is formed so as to cover the insulating layer 15, and after the translucent electrode forming step, on the surface 7 a of the translucent electrode 7, above the insulating layer 15 formed on the p-type semiconductor layer 6.
- a positive electrode forming step of forming a positive electrode bonding pad 8 at position A The semiconductor layer forming step is a method of forming the n-type semiconductor layer 4 so that the sheet resistance Rs2 of the n-type semiconductor layer 4 is lower than the sheet resistance Rs1 of the translucent electrode 7.
- the light emitting device 1 having excellent light emission efficiency and light extraction efficiency, high external quantum efficiency, and excellent electrical characteristics can be manufactured.
- the lamp of the present invention uses the group III nitride semiconductor light-emitting device of the present invention.
- Examples of the lamp of the present invention include a combination of the group III nitride semiconductor light emitting device of the present invention and a phosphor.
- a lamp in which a group III nitride semiconductor light-emitting device and a phosphor are combined can have a configuration well known to those skilled in the art by means well known to those skilled in the art.
- Conventionally, a technique for changing the emission color by combining a group III nitride semiconductor light-emitting element and a phosphor is known, and such a technique should be adopted in the lamp of the present invention without any limitation. Is possible.
- FIG. 6 is a schematic view schematically showing an example of a lamp configured using the group III nitride semiconductor light emitting device according to the present invention.
- the lamp 80 shown in FIG. 5 is a cannonball type, and the light emitting element 1 shown in FIGS. 1 and 2 is used.
- the positive electrode bonding pad 8 of the light emitting element 1 is bonded to one of the two frames 81 and 82 (the frame 81 in FIG. 6) with a wire 83, and the negative electrode bonding pad 9 of the light emitting element 1 is
- the light emitting element 1 is mounted by being joined to the other frame 82 by the wire 84. Further, the periphery of the light emitting element 1 is sealed with a mold 85 made of a transparent resin.
- the lamp of the present invention uses the light-emitting element 1 of the present invention, the lamp has excellent light emission characteristics.
- the lamp of the present invention can be used for any purpose such as a bullet type for general use, a side view type for portable backlight use, and a top view type used for a display.
- Example 1 a sample of a light-emitting element was manufactured by the procedure described below (see FIGS. 1 to 4, FIG. 7, etc.).
- substrate 11 which has the main surface 11a which consists of a (0001) C surface of a sapphire substrate was prepared.
- the substrate 11 having a plurality of convex portions (not shown) formed on the main surface 11a is used (the protrusions formed on the main surface 110 in FIGS. 3 and 4). Part 112).
- the base width d 1 of the convex portion formed on the main surface 11a is 1.3 .mu.m
- the height h was used 0.7 [mu] m
- a substrate spacing d 2 is set to the 0.7 [mu] m.
- a 50 nm thick buffer layer 2 made of AlN having a single crystal structure was formed on the main surface 11a of the substrate 11 using RF sputtering.
- the sputtering film forming apparatus an apparatus having a high-frequency power source and having a mechanism capable of moving the position of the magnet in the target was used.
- an underlayer 3 made of a group III nitride semiconductor was formed by using the low pressure MOCVD method described below (epitaxial process).
- the substrate 11 on which the buffer layer 2 was formed taken out from the sputter deposition apparatus, was introduced into a reaction furnace for growing a group III nitride semiconductor layer by MOCVD.
- the temperature of the substrate 11 is raised to 1120 ° C. in a hydrogen atmosphere, and supply of trimethylgallium (TMG) into the vapor phase growth reactor is started.
- TMG trimethylgallium
- Undoped GaN was epitaxially grown to a thickness of 3 ⁇ m.
- an initial layer of the n-type contact layer 4a made of GaN was formed by the same MOCVD apparatus (semiconductor layer forming step). At this time, the n-type contact layer 4a was doped with Si. Crystal growth was performed under the same conditions as the underlayer except that SiH 4 was circulated as a Si dopant material.
- the n-type cladding layer 4b was laminated on the n-type contact layer 4a produced by the above procedure using the same MOCVD apparatus. Further, when the n-type semiconductor layer 4 was formed, the sheet resistance was appropriately adjusted within the range shown in Table 1 below by appropriately adjusting the Si doping amount.
- the light emitting layer 5 formed in the present example has a multiple quantum well structure including a barrier layer 5a made of GaN and a well layer 5b made of Ga 0.85 In 0.15 N.
- a barrier layer 5a is first formed on an n-type cladding layer 4b having a superlattice structure of Si-doped GaInN and GaN, and Ga 0.85 In is formed on the barrier layer 5a.
- a well layer 5b made of 0.15 N was formed.
- the seventh barrier layer 5a is formed on the sixth well layer 5b, and the barrier layers 5a are arranged on both sides of the light emitting layer 5 having the multiple quantum well structure.
- the structure was as follows.
- the light emitting layer 5 having a multiple quantum well structure was formed by the above procedure.
- a p-type cladding layer 6a having a superlattice structure made of GaN doped with four layers of non-doped Al 0.06 Ga 0.94 N and three layers of Mg is formed.
- a film was formed.
- a p-type contact layer 6b made of Mg-doped GaN having a thickness of 200 nm was formed thereon to form a p-type semiconductor layer 6.
- the n-type semiconductor layer 4, the light emitting layer 5, and the p-type semiconductor layer p were stacked in this order on the base layer 3 to form the semiconductor layer 20.
- a light-emitting diode which is a kind of semiconductor light-emitting element, was produced by the following procedure using the wafer obtained by the above procedure (see FIGS. 1 and 2).
- an insulating layer 15 made of SiO 2 was formed at one place on the p-type semiconductor layer 6 using a known sputtering method. At this time, the insulating layer 15 was formed to a thickness of 200 nm and a circular shape having a diameter of 100 ⁇ m.
- a translucent electrode 7 was formed by depositing a layer made of an IZO material on the p-type semiconductor layer 6 so as to cover the insulating layer 15 by using a known photolithography technique. Electrode forming step). At this time, the film resistance was adjusted to 250 nm and the sheet resistance of the translucent electrode 7 was appropriately adjusted with the numerical values shown in Table 1 below by annealing in a nitrogen atmosphere.
- a positive electrode bonding pad having a three-layer structure is formed by sequentially stacking Ti, Al, and Au on the surface 7a of the translucent electrode 7 at a position corresponding to the underlying insulating layer 15 by a known photolithography technique. 8 was formed (positive electrode forming step). At this time, the positive electrode bonding pad 8 was formed in a circular shape having a diameter of 90 ⁇ m. Then, a part of the semiconductor layer 20 and the translucent positive electrode 7 is removed by dry etching to provide an exposed region where the n-type contact layer 4a is exposed, and then Ni, Al, Ti, and Au are formed thereon. By sequentially laminating these layers, a negative electrode bonding pad 9 as shown in FIGS. 1 and 2 was formed. At this time, the distance between the centers of the positive electrode bonding pad 8 and the negative electrode bonding pad 9 in a plan view of the wafer was set to 440 ⁇ m.
- the wafer is 240 ⁇ m (chip width dimension W) ⁇ 600 ⁇ m (electrode separation direction dimension L) square.
- An LED (light emitting diode) chip (light emitting element 1) was cut into rectangular chips. Then, this chip was placed on the lead frame 81 so that the positive electrode bonding pad 8 and the negative electrode bonding pad 9 were on top, and connected to the lead frame with a gold wire to produce a lamp 80 (see FIG. 6). .
- Examples 2 and 3 and Comparative Examples 1 and 2 In Examples 2 and 3 and Comparative Examples 1 and 2, the presence / absence of an insulating layer, the film thickness of the translucent electrode, and the distance between the centers of the positive electrode bonding pad and the negative electrode bonding pad in the wafer plan view are shown in Table 1 below. In the same manner as in Example 1 except that the sheet resistance is adjusted so that the relationship between the sheet resistances is as shown in Table 1 below, a rectangle of 240 ⁇ m ⁇ 600 ⁇ m square is formed. A chip of a group nitride semiconductor light emitting device was fabricated. In the same manner as described above, a lamp was manufactured using this chip.
- Table 1 below shows the measurement results of sheet resistance, translucent electrode thickness, light emission output (Po), and drive voltage (Vf) in Examples 1 to 3 and Comparative Examples 1 and 2.
- Example 4 to 6 the relationship between the film thickness of the translucent electrode and each sheet resistance was set as shown in Table 2 below, and the electrode separation direction dimension (L: chip length dimension) in wafer plan view and A group III nitride semiconductor light emitting device chip was fabricated in the same manner as in Example 1 except that the chip width dimension (W) in the direction orthogonal to the above was adjusted as appropriate so as to have the relationship shown in Table 2 below. did. In the same manner as described above, a lamp was manufactured using this chip.
- the light emission output Po (when a forward current IF of 30 mA is passed between the electrodes on the p side (positive electrode bonding pad) and n side (negative electrode bonding pad) of the lamp and if necessary, 100 mA is flowed. mW) was measured.
- the sample of Example 1 having the configuration of the light emitting device according to the present invention has a light emission output (Po) of 20.8 mW at a forward current (IF) of 20 mA, and a high light emission output is obtained.
- the driving voltage (Vf) at this time was also greatly reduced to 3.15 mV, and it was revealed that the device had excellent electrical characteristics.
- the light emission output is as high as 19.6 mW or more. It was confirmed that it had a light emission output.
- the sheet resistance of the n-type semiconductor layer is higher than the sheet resistance of the translucent electrode, and each sample of Comparative Examples 1 and 2 that does not satisfy the relationship defined in the present invention has a light emission output of 18.6. ⁇ 18.9 mW, which is a lower output than the samples of the above examples.
- the sample of Comparative Example 1 in which no insulating layer is provided has the lowest light output of 18.6 mW.
- the samples of Comparative Examples 1 and 2 are manufactured as a configuration in which the sheet resistance of the n-type semiconductor layer is higher than the sheet resistance of the translucent electrode, and in Comparative Example 1, no insulating layer is provided. For this reason, in the samples of Comparative Examples 1 and 2, the semiconductor layer at the position corresponding to the negative electrode bonding pad on the n side emitted light mainly, so that the area of the portion with high emission intensity was reduced and the light extraction rate was reduced. it is conceivable that.
- the light emission output when the forward current (IF) is 30 mA is 31. The output is as high as 5 mW.
- the light emission output is 31.8 mW. , 28.1 mW.
- the group III nitride semiconductor light-emitting device of the present invention has excellent light emission efficiency by suppressing current concentration directly under the electrode, and light extraction by the electrode and suppression of loss due to multiple reflection are suppressed. It is clear that it is excellent in efficiency and has high emission intensity and electrical characteristics.
- SYMBOLS 1 Group III nitride semiconductor light emitting element (light emitting element), 11, 100 ... Substrate, 11a, 110 ... Main surface, 4 ... N-type semiconductor layer, 5 ... Light emitting layer, 6 ... P-type semiconductor layer, 7 ... Translucent , 7a ... surface (translucent electrode), 8 ... positive electrode bonding pad, 15 ... insulating layer, 20 ... semiconductor layer, 80 ... lamp, A ... position (position corresponding to the insulating layer on the surface of the translucent electrode) ), Rs1... Sheet resistance (translucent electrode), Rs2... Sheet resistance (n-type semiconductor layer)
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Abstract
Description
本願は、2009年3月6日に、日本に出願された特願2009-054204号、およびに2010年3月3日に、日本に出願された特願2010-46812号に基づき優先権を主張し、その内容をここに援用する。
また、内部量子効率とは、素子に注入した電流のエネルギーが発光層で光に変換される割合である。一方、光取り出し効率とは、発光層で発生した光のうち発光素子の外部に取り出すことができる光の割合である。
従って、外部量子効率を向上させるには、発光層における発光効率の他、光取り出し効率を改善する必要がある。
また、本発明は、上述のような発光効率並びに光取り出し効率に優れた発光素子を製造することが可能なIII族窒化物半導体発光素子の製造方法を提供することを目的とする。
さらに、本発明は、上記III族窒化物半導体発光素子が用いられてなり、発光特性に優れたランプを提供することを目的とする。
またさらに、本発明者等は、発光素子の駆動電圧にはn側の層のシート抵抗が支配的に働くことを知見し、n側の層のシート抵抗を低くすることにより、特に、30~100mA程度の大きな駆動電流を発光素子に印加する場合に、電気的特性が大きく向上することを見出し、本発明を完成した。
即ち、本発明は以下に関する。
[2] 前記n型半導体層のシート抵抗が15Ω/□以下であり、前記透光性電極のシート抵抗が30Ω/□以下であることを特徴とする上記[1]に記載のIII族窒化物半導体発光素子。
[3] 前記透光性電極の表面の少なくとも一部が凹凸形状とされていることを特徴とする上記[1]又は[2]に記載のIII族窒化物半導体発光素子。
[4] 前記透光性電極が、酸化インジウム錫(ITO:Indium Tin Oxide)、酸化インジウム亜鉛(IZO:Indium Zinc Oxide)、酸化インジウムガリウム(IGO:Indium Gallium Oxide)、酸化インジウムセリウム(ICO:Indium Cerium Oxide)及び導電性酸化チタン(TiO2)からなる群から選ばれる少なくとも1種が用いられてなることを特徴とする上記[1]~[3]の何れか1項に記載のIII族窒化物半導体発光素子。
[5] 前記絶縁層が、酸化シリコン(SiO2)からなることを特徴とする上記[1]~[4]の何れか1項に記載のIII族窒化物半導体発光素子。
[7] 前記半導体層形成工程は、前記n型半導体層を15Ω/□以下のシート抵抗となるように形成し、前記透光性電極形成工程は、前記透光性電極を30Ω/□以下のシート抵抗となるように形成することを特徴とする上記[6]に記載のIII族窒化物半導体発光素子の製造方法。
[8] 前記透光性電極形成工程は、前記透光性電極の表面の少なくとも一部に凹凸形状を形成することを特徴とする上記[6]又は[7]に記載のIII族窒化物半導体発光素子の製造方法。
[9] 前記透光性電極形成工程は、前記透光性電極を形成する材料として酸化インジウム錫(ITO:Indium Tin Oxide)、酸化インジウム亜鉛(IZO:Indium Zinc Oxide)、酸化インジウムガリウム(IGO:Indium Gallium Oxide)、酸化インジウムセリウム(ICO:Indium Cerium Oxide)及び導電性酸化チタン(TiO2)からなる群から選ばれる少なくとも1種を用いることを特徴とする上記[6]~[8]の何れか1項に記載のIII族窒化物半導体発光素子の製造方法。
[10] 前記透光性電極形成工程は、前記絶縁層を形成する材料として酸化シリコン(SiO2)を用いることを特徴とする上記[6]~[9]の何れか1項に記載のIII族窒化物半導体発光素子の製造方法。
本発明に係る発光素子1は、図1及び図2に示す一例のように、基板11の主面11a上に形成された単結晶の下地層(III族窒化物半導体層)3上に、n型半導体層4、発光層5及びp型半導体層6が順次積層された半導体層20が形成され、p型半導体層6上に透光性電極7が形成されてなり、p型半導体層6上の少なくとも一部に絶縁層15が備えられるとともに、透光性電極7が絶縁層15を覆って形成され、概略構成されている。また、図1及び図2に示す例の発光素子1は、n型半導体層4のシート抵抗Rs2が、透光性電極7のシート抵抗Rs1よりも低い構成とされたものである。また、図示例においては、基板11と下地層3との間にバッファ層2が設けられているとともに、透光性電極7上に正極ボンディングパッド8が備えられ、半導体層20の一部が除去されて露出したn型半導体層4に負極ボンディングパッド9が備えられている。また、図示例の発光素子1は、その平面形状が、正極ボンディングパッド8と負極ボンディングパッド9とが離間する方向、即ち、図2中におけるチップ長さ寸法(L)がチップ幅寸法(W)よりも長尺とされ、略長方形状として構成されている。また、本発明においては、図2中に示す平面形状において、チップ幅寸法W:チップ長さ寸法Lを、1:1(L/W=1)~1:2.7(L/W=2.7)の範囲として、正方形状チップ又は長方形状チップとして構成することができる。
本実施形態で説明する例の発光素子1は、上記構成により、図示例のような発光ダイオード(LED)として構成される。
以下、発光素子1の積層構造について詳しく説明する。
(基板の材料)
本実施形態の発光素子において、上述したような基板11に用いることができる材料としては、III族窒化物半導体結晶が表面にエピタキシャル成長される基板材料であれば特に限定されず、各種材料を選択して用いることができる。例えば、サファイア、SiC、シリコン、酸化亜鉛、酸化マグネシウム、酸化マンガン、酸化ジルコニウム、酸化マンガン亜鉛鉄、酸化マグネシウムアルミニウム、ホウ化ジルコニウム、酸化ガリウム、酸化インジウム、酸化リチウムガリウム、酸化リチウムアルミニウム、酸化ネオジウムガリウム、酸化ランタンストロンチウムアルミニウムタンタル、酸化ストロンチウムチタン、酸化チタン、ハフニウム、タングステン、モリブデン等が挙げられる。また、上記各基板材料の中でも、特に、サファイアを用いることが好ましく、また、サファイアからなる基板11のc面からなる主面11a上に、詳細を後述するバッファ層2が形成されていることが望ましい。
また、バッファ層2をスパッタ法により形成した場合、基板11の温度を低く抑えることが可能なので、高温で分解してしまう性質を持つ材料からなる基板11を用いた場合でも、基板11にダメージを与えることなく基板上への各層の成膜が可能である。
本発明では、基板11の主面11a上にバッファ層2を形成し、その上に下地層3を形成することが好ましい。バッファ層2は、例えば、AlXGa1-XN(0≦x≦1)なる組成で基板11上に積層され、例えば、V族元素を含むガスと金属材料とをプラズマで活性化して反応させる反応性スパッタ法によって形成することができる。本実施形態のような、プラズマ化した金属原料を用いた方法で成膜された膜は、配向が得られ易いという作用がある。
本発明の発光素子1に備えられる下地層(III族窒化物半導体層)3は、上述したようにIII族窒化物半導体からなり、従来公知のMOCVD法によってバッファ層2上に積層して成膜することができる。
基板11が導電性である場合には、下地層3にドーパントをドープして導電性とすることにより、発光素子の上下に電極を形成することができる。一方、基板11に絶縁性の材料を用いる場合には、発光素子の同じ面に正極及び負極の各電極が設けられたチップ構造をとることになるので、下地層3はドープしない結晶とした方が、結晶性が良好となるので好ましい。下地層3にドープされるn型不純物としては、特に限定されないが、例えば、Si、GeおよびSn等が挙げられ、好ましくはSiおよびGeが挙げられる。
下地層3上に形成される半導体層20は、III族窒化物半導体から各々なるn型半導体層4、発光層5及びp型半導体層を有する。このような半導体層20の各層は、MOCVD法で形成することにより、より結晶性の高いものが得られる。
n型半導体層4は、通常、n型コンタクト層4aとn型クラッド層4bとから構成される。また、n型コンタクト層4aはn型クラッド層4bを兼ねることも可能である。
上述のように、n型クラッド層4bを、超格子構造を含む層構成とすることで、発光出力が格段に向上し、電気特性に優れた発光素子1とすることが可能となる。
n型半導体層の上に積層される発光層としては、単一量子井戸構造あるいは多重量子井戸構造等の構造を有する発光層5が挙げられる。図1に示すような量子井戸構造の井戸層としては、青色発光を呈する構成とする場合には、通常、Ga1-yInyN(0<y<0.4)なる組成のIII族窒化物半導体が用いられるが、本発明のような緑色発光を呈する井戸層5bの場合には、Ga1-yInyN0.07<y<0.20等、インジウムの組成が高められたものが用いられる。
p型半導体層6は、通常、p型クラッド層6aおよびp型コンタクト層6bから構成される。また、p型コンタクト層6bがp型クラッド層6aを兼ねることも可能である。
また、p型クラッド層6aは、複数回積層した超格子構造としてもよい。
上述のように、p型クラッド層6aを、超格子構造を含む層構成とすることで、発光出力が格段に向上し、電気特性に優れた発光素子1とすることが可能となる。
本発明の発光素子においては、p型半導体層6上の少なくとも一部、図1及び図2に示す例の発光素子1では略中央付近に、絶縁材料からなる絶縁層15が備えられている。また、図示例では、絶縁層15が透光性電極7に覆われるように形成されている。
絶縁層15の材料としては特に限定されず、従来公知の絶縁性酸化膜等を何ら制限無く用いることができるが、中でも酸化シリコン(SiO2)を用いることが好ましい。
透光性電極7は、導電性を備えた酸化膜等からなる透光性の電極であり、この技術分野で通常用いられる透光性材料を何ら制限無く用いることができる。このような材料としては、例えば、ITO(In2O3-SnO2)、AZO(ZnO-Al2O3)、IZO(In2O3-ZnO:酸化インジウム亜鉛;Indium Zinc Oxide)、GZO(ZnO-Ga2O3)、IGO(In2O3-Ga2O3)、ICO(In2O3-Ce2O3)、任意の不純物元素がドープされた酸化チタン(TiO2)等を含む材料が挙げられる。また、これらの材料の内、酸化チタンには、TiO2を一部還元した還元型TiO2-Xを用いてもよく、導電性のものであれば良い。また、酸化チタンにドープする材料としては、例えば、Nb等が挙げられる。
また、本発明においては、ITO、IZO、IGO、ICO及び導電性酸化チタンの内の、少なくとも何れか1種を用いることがより好ましい。
本発明に係る発光素子1においては、透光性電極7上に正極ボンディングパッド8が設けられ、n型半導体層4に備えられるn型コンタクト層に接するように負極ボンディングパッド9が設けられている。
正極ボンディングパッド8は、図1及び図2に示すように、p型半導体層6及び絶縁層15と接する透光性導電酸化膜層からなる透光性電極7上の一部に設けられている。また、図示例の正極ボンディングパッド8は、透光性電極7の表面7aにおいて、絶縁層15に対応する位置Aに設けられている。
負極ボンディングパッド9は、半導体層20のn型半導体層4に接するように形成される。このため、負極ボンディングパッド9を形成する際には、発光層5およびp型半導体層6の一部を除去してn型半導体層4のn型コンタクト層を露出させ、この上に負極ボンディングパッド9を形成する。
本発明においては、発光素子1の平面視におけるチップサイズ、即ち、正極ボンディングパッド8と負極ボンディングパッド9とが離間する方向の電極離間方向寸法(チップ長さ寸法)L、及び、この電極離間方向に直交する方向でのチップ幅寸法Wについては、特に限定されない。例えば、電極離間方向寸法L及びチップ幅寸法Wを、平面視におけるチップ形状が正方形状となる寸法比としても良いし、あるいは、長方形状となる寸法比としても良く、何れの場合であっても、本発明による発光効率の向上効果が得られる。
しかしながら、上記構成によって得られる発光効率向上の効果をさらに顕著なものとするためには、図2に示す例のように、その平面視形状を、電極離間方向寸法Lをチップ幅寸法Wよりも長くし、略長方形状とすることがより好ましい。
発光素子1を上記条件で駆動する場合の、より好ましいチップサイズについて、以下に詳述する。
本発明に係る発光素子においては、n型半導体層4のシート抵抗Rs2を、透光性電極7のシート抵抗Rs1よりも低く構成しているので、大きな順方向電流IFを印加して用いる発光素子であっても、発光ムラが生じるのが抑制されるという効果がある。
本発明に係るIII族窒化物半導体発光素子の製造方法は、基板11の主面11a上に単結晶の下地層(III族窒化物半導体層)3を形成するエピタキシャル工程と、下地層3上にn型半導体層4、発光層5及びp型半導体層6を順次積層して半導体層20を形成する半導体層形成工程と、p型半導体層6上に透光性電極7を形成する透光性電極形成工程とが備えられてなり、透光性電極形成工程が、p型半導体層6上の少なくとも一部に絶縁層15を形成した後、p型半導体層6上に絶縁層15を覆うように透光性電極7を形成し、透光性電極形成工程の後、透光性電極7の表面7aにおいて、p型半導体層6上に形成された絶縁層15の上方の位置Aに正極ボンディングパッド8を形成する正極形成工程が備えられており、半導体層形成工程は、n型半導体層4のシート抵抗が透光性電極7のシート抵抗よりも低くなるようにn型半導体層4を形成する方法である。
以下、本発明の製造方法に備えられる各工程について詳しく説明する。
本発明に係る製造方法では、エピタキシャル工程の前に、基板11の主面11a上にバッファ層2を形成するバッファ層形成工程が備えられていることが好ましい。また、本発明においては、バッファ層を省略した構成とすることも可能なので、この場合にはバッファ層形成工程を行なわなくても良い。
本実施形態では、基板11をスパッタ装置のチャンバ内に導入した後、バッファ層2を形成する前に、プラズマ処理による逆スパッタ等の方法を用いて前処理を行うことが望ましい。
基板11に前処理を行なった後、基板11の主面11a上に、反応性スパッタ法により、AlXGa1-XN(0≦X≦1)なる組成のバッファ層2を成膜する。反応性スパッタ法によって単結晶構造を有するバッファ層2を形成する場合、スパッタ装置のチャンバ内の窒素原料と不活性ガスの流量に対する窒素流量の比を、窒素原料が50~100%の範囲となるように制御することが好ましく、75%程度とすることがより好ましい。また、柱状結晶(多結晶)構造を有するバッファ層2を形成する場合には、スパッタ装置のチャンバ内の窒素原料と不活性ガスの流量に対する窒素流量の比を、窒素原料が1~50%の範囲となるように制御することが好ましく、25%程度とすることがより好ましい。
次に、エピタキシャル工程では、上記バッファ層形成工程の後、図1に示すように、基板11の主面11a上に形成されたバッファ層2の上に、単結晶のIII族窒化物半導体をエピタキシャル成長させて、主面11aを覆うように下地層(III族窒化物半導体層)103を形成する。
また、本発明においては、エピタキシャル工程においてIII族窒化物半導体からなる下地層3を形成した後、半導体層形成工程において、下地層3上に、n型半導体層4、発光層5及びp型半導体層6の各層からなる半導体層20を形成する。
なお、本実施形態においては、それぞれIII族窒化物半導体を用いて各層を成膜するエピタキシャル工程及び半導体層形成工程において、両工程に共通する構成については、一部、説明を省略することがある。
エピタキシャル工程では、図1に示すように、基板11上に形成されたバッファ層2の上に、下地層3を、従来公知のMOCVD法を用いて形成する。
本実施形態では、MOCVD法を用いて下地層3を形成する方法を説明しているが、下地層3を積層する方法としては特に限定されず、転位のループ化を生じさせることができる結晶成長方法であれば、何ら制限なく用いることができる。特に、MOCVD法やMBE法、VPE法等は、マイグレーションを生じさせることができるため、結晶性の良好な膜を形成することが可能となる点で好適である。中でも、MOCVD法は、特に結晶性の良好な膜を得ることができる点で、より好適に用いることができる。
また、反応性スパッタ法を用いてIII族窒化物半導体からなる下地層を成膜することも可能である。スパッタ法を用いる場合には、MOCVD法やMBE法等と比較して、装置を簡便な構成とすることが可能となる。
次に、半導体層形成工程においては、上記エピタキシャル工程の後、図1に示すように、下地層3の上に、n型半導体層4、発光層5及びp型半導体層6の各層からなる半導体層20を、従来公知のMOCVD法を用いて積層する。
上記エピタキシャル工程で形成された下地層3の上に、従来公知のMOCVD法を用いて、n型コンタクト層4a及びn型クラッド層4bを順次積層することにより、n型半導体層4を形成する。n型コンタクト層4a及びn型クラッド層4bを形成する成膜装置としては、上述の下地層3や後述の発光層5の成膜に用いるMOCVD装置を、各種条件を適宜変更して用いることが可能である。また、n型コンタクト層4a及びn型クラッド層4bを反応性スパッタ法で形成することも可能である。
このように、n型半導体層4のシート抵抗Rs2を制御する方法としては、上述したように、膜厚の適性化による方法や、Si等のn型不純物のドープ量を制御する方法を適宜採用することが可能である。本発明においては、n型半導体層4を、シート抵抗Rs2が低減されるように形成するので、上述したように、Si等のn型不純物のドープ量を、従来の発光素子におけるドープ量に比べて1.5倍程度とすることが好ましい。n型不純物のドープ量を増量することにより、シート抵抗Rs2が、例えば、15Ω/□以下となるように制御しながら、n型半導体層4を形成することができる。
次いで、n型クラッド層4b(n型半導体層4)上に、発光層5を、従来公知のMOCVD法によって形成する。本実施形態で形成する発光層5は、図4に例示するように、GaN障壁層に始まりGaN障壁層に終わる積層構造を有しており、GaNからなる7層の障壁層5aと、ノンドープのGa0.8In0.2Nからなる6層の井戸層5bとを交互に積層して形成する。また、本実施形態の製造方法では、上述したn型半導体層4の成膜に用いる成膜装置(MOCVD装置)と同じものを使用して発光層5を成膜することができる。
次いで、発光層5上、つまり、発光層5の最上層となる障壁層5aの上に、p型クラッド層6a及びp型コンタクト層6bからなるp型半導体層6を、従来公知のMOCVD法を用いて形成する。p型半導体層6の形成には、n型半導体層4及び発光層5の形成に用いるMOCVD装置と同じ装置を、各種条件を適宜変更して用いることが可能である。また、p型半導体層6を構成するp型クラッド層6a及びp型コンタクト層6bを、反応性スパッタ法を用いて形成することも可能である。
次に、透光性電極形成工程では、図1に示すように、p型半導体層6上の少なくとも一部に絶縁層15を形成した後、p型半導体層6上に絶縁層15を覆うように透光性電極7を形成する。
まず、p型半導体層6上の少なくとも一部、図1及び図2に示す例では略中央付近に、絶縁材料からなる絶縁層15を形成する。
絶縁層15の形成に用いる材料としては特に限定されず、従来公知の絶縁性酸化膜等を何ら制限無く用いることができ、例えば、酸化シリコン(SiO2)を用いることができる。
また、絶縁層15する方法としては、例えば、スパッタ法等の従来公知の方法を何ら制限無く用いることができる。
次に、上記方法によって形成されたp型半導体層6の上に、絶縁層15を覆うようにIZOを積層することにより、透光性電極7を形成する。
透光性電極7の形成方法としては、特に限定されず、この技術分野でよく知られた慣用の手段で設けることができる。また、その構造も、従来公知の構造を含めて如何なる構造のものも何ら制限なく用いることができる。
次に、本実施形態の製造方法では、透光性電極形成工程の後、透光性電極7の表面7aにおいてp型半導体層6上に形成された絶縁層15に対応する位置Aに正極ボンディングパッド8を形成する正極形成工程が備えられている。また、本実施形態では、半導体層20の所定の位置をエッチング除去することにより、n型半導体層4を露出させて露出領域を形成し、この露出領域に負極ボンディングパッド9を形成する。
まず、透光性電極7の表面7aに、p型半導体層6上に形成された絶縁層15に対応する位置Aで、正極ボンディングパッド8を形成する。この正極ボンディングパッド8は、例えば、透光性電極7の表面側から順に、Ti、Al、Auの各材料を、従来公知の方法で積層することによって形成することができる。
負極ボンディングパッド9を形成する際は、まず、基板11上に形成されたp型半導体層6、発光層5及びn型半導体層4の一部をドライエッチング等の方法によって除去することにより、n型コンタクト層4aの一部を露出させる。そして、この露出領域上に、例えば、露出領域の表面側から順に、Ni、Al、Ti、及びAuの各材料を従来公知の方法で積層することにより、詳細な図示を省略する4層構造の負極ボンディングパッド9を形成することができる。
本発明のランプは、本発明のIII族窒化物半導体発光素子が用いられてなるものである。
本発明のランプとしては、例えば、本発明のIII族窒化物半導体発光素子と蛍光体とを組み合わせてなるものを挙げることができる。III族窒化物半導体発光素子と蛍光体とを組み合わせたランプは、当業者周知の手段によって当業者周知の構成とすることができる。また、従来より、III族窒化物半導体発光素子と蛍光体と組み合わせることによって発光色を変える技術が知られており、本発明のランプにおいてもこのような技術を何ら制限されることなく採用することが可能である。
なお、本発明のランプは、一般用途の砲弾型、携帯のバックライト用途のサイドビュー型、表示器に用いられるトップビュー型等いかなる用途にも用いることができる。
本実施例においては、以下に説明するような手順により、発光素子のサンプルを作製した(図1~図4、図7等を参照)。
まず、サファイア基板の(0001)C面からなる主面11aを有する基板11を準備した。ここで、本実施例においては、基板11として、主面11a上に、図示略の複数の凸部が形成されているものを用いた(図3、4において主面110上に形成された凸部112を参照)。また、本実施例では、主面11aに形成された凸部の基部幅d1が1.3μm、高さhが0.7μm、間隔d2が0.7μmとされた基板を用いた。
まず、スパッタ成膜装置から取り出した、バッファ層2が形成された基板11を、MOCVD法によるIII族窒化物半導体層の成長のための反応炉内に導入した。そして、アンモニアガスの流通を続けながら水素雰囲気中で、基板11の温度を1120℃に昇温させ、トリメチルガリウム(TMG)の気相成長反応炉内への供給を開始し、バッファ層2上にアンドープのGaNを3μmの膜厚までエピタキシャル成長させた。
また、n型半導体層4の形成時、Siドープ量を適宜調整することにより、そのシート抵抗を下記表1に示す範囲で適宜調整した。
本実施例で形成した発光層5は、GaNからなる障壁層5aと、Ga0.85In0.15Nからなる井戸層5bとから構成される多重量子井戸構造を有する。この発光層5の形成にあたっては、SiドープのGaInNとGaNの超格子構造からなるn型クラッド層4b上に、まず、障壁層5aを形成し、この障壁層5a上に、Ga0.85In0.15Nからなる井戸層5bを形成した。このような積層手順を6回繰り返した後、6番目に積層した井戸層5b上に、7番目の障壁層5aを形成し、多重量子井戸構造を有する発光層5の両側に障壁層5aを配した構造とした。
以上の手順にて、多重量子井戸構造の発光層5を形成した。
このようにして、下地層3上に、n型半導体層4、発光層5及びp型半導体層pの各層をこの順で積層し、半導体層20を形成した。
まず、p型半導体層6上の1箇所に、公知のスパッタ法を用いて、SiO2からなる絶縁層15を形成した。この際、絶縁層15を200nmの膜厚で形成するとともに、直径が100μmの円形状とした。
次いで、公知のフォトリソグラフィー技術を用いて、絶縁層15を覆うように、p型半導体層6上にIZO材料からなる層を成膜することにより、透光性電極7を形成した(透光性電極形成工程)。この際、膜厚を250nmとするとともに、窒素雰囲気下でアニールを施すことにより、透光性電極7のシート抵抗を、下記表1に示す数値で適宜調整した。
そして、半導体層20及び透光性正極7の一部にドライエッチングを施して除去することにより、n型コンタクト層4aが露出した露出領域を設けた後、この上にNi、Al、Ti及びAuの各層を順次積層することにより、図1及び図2に示すような負極ボンディングパッド9を形成した。また、この際、ウェーハの平面視における正極ボンディングパッド8と負極ボンディングパッド9の中心間距離を440μmとした。
そして、このチップを、正極ボンディングパッド8及び負極ボンディングパッド9が上になるようにリードフレーム81上に載置し、金線でリードフレームに結線することによってランプ80(図6参照)を作製した。
実施例2、3、並びに比較例1、2においては、絶縁層の有無、透光性電極の膜厚、及び、ウェーハ平面視での正極ボンディングパッドと負極ボンディングパッドの中心間距離を下記表1に示す条件とし、また、各シート抵抗の関係が下記表1に示す関係となるように適宜調整した点を除き、上記実施例1と同様の方法で、240μm×600μm角の長方形とされたIII族窒化物半導体発光素子のチップを作製した。そして、上記同様、このチップを用いてランプを作製した。
実施例4~6においては、透光性電極の膜厚及び各シート抵抗の関係を下記表2に示す条件とし、また、ウェーハ平面視における電極離間方向寸法(L:チップ長さ寸法)及びこれに直交する方向でのチップ幅寸法(W)が下記表2に示す関係となるように適宜調整した点を除き、上記実施例1と同様の方法でIII族窒化物半導体発光素子のチップを作製した。そして、上記同様、このチップを用いてランプを作製した。
表1に示すように、本発明に係る発光素子の構成を備えた実施例1のサンプルは、順方向電流(IF)20mAにおける発光出力(Po)が20.8mWとなり、高い発光出力が得られるとともに、この際の駆動電圧(Vf)も3.15mVと非常に低減されたものとなり、優れた電気的特性を備えていることが明らかとなった。また、n型半導体層4のシート抵抗Rs2が透光性電極7のシート抵抗Rs1よりも低く調整された実施例2、3の各々のサンプルにおいても、何れも発光出力が19.6mW以上と高い発光出力を備えていることが確認できた。
また、n型半導体層のシート抵抗が透光性電極のシート抵抗よりも低い実施例1~3は、下記比較例1、2の発光素子に比べて、n側の負極ボンディングパッド付近での発光が低減され、発光強度の高い部分の面積が大きくなっていることが確認できた。
例えば、実施例4は、チップサイズをL=550μm、W=280μmとし、横縦比=2.0とした例であるが、順方向電流(IF)を30mAとした際の発光出力が31.5mWと高出力となっている。
また、n型半導体層のシート抵抗Rs2、透光性電極のシート抵抗Rs1を実施例4と同一としたうえで、平面視寸法を変化させた実施例5、6では、発光出力が31.8mW、28.1mWに変化していることがわかる。
即ち、本発明では、n型半導体層のシート抵抗を透光性電極のシート抵抗よりも低くすることで上記効果が得られ、さらに好ましくは、チップ幅寸法W:チップ長さ寸法Lを、1:1(L/W=1)~1:2.7(L/W=2.7)の範囲の比とし、正方形状チップ及び長尺形状チップに構成することで、順方向電流IFが30~100mAの条件において、特に効果的に発光効率が向上することがわかる。
Claims (11)
- 基板上に形成された単結晶のIII族窒化物半導体層上に、n型半導体層、発光層及びp型半導体層が順次積層された半導体層が形成されており、前記p型半導体層上に透光性電極が形成されてなるIII族窒化物半導体発光素子であって、
前記p型半導体層上の少なくとも一部に絶縁層が備えられるとともに、前記透光性電極が前記絶縁層を覆って形成されており、
前記透光性電極の表面において、前記p型半導体層上に備えられた前記絶縁層の上方に正極ボンディングパッドが設けられており、
前記n型半導体層のシート抵抗が、前記透光性電極のシート抵抗よりも低いことを特徴とするIII族窒化物半導体発光素子。 - 前記n型半導体層のシート抵抗が15Ω/□以下であり、前記透光性電極のシート抵抗が30Ω/□以下であることを特徴とする請求項1に記載のIII族窒化物半導体発光素子。
- 前記透光性電極の表面の少なくとも一部が凹凸形状とされていることを特徴とする請求項1に記載のIII族窒化物半導体発光素子。
- 前記透光性電極が、酸化インジウム錫(ITO:Indium Tin Oxide)、酸化インジウム亜鉛(IZO:Indium Zinc Oxide)、酸化インジウムガリウム(IGO:Indium Gallium Oxide)、酸化インジウムセリウム(ICO:Indium Cerium Oxide)及び導電性酸化チタン(TiO2)からなる群から選ばれる少なくとも1種が用いられてなることを特徴とする請求項1に記載のIII族窒化物半導体発光素子。
- 前記絶縁層が、酸化シリコン(SiO2)からなることを特徴とする請求項1~請求項4の何れか1項に記載のIII族窒化物半導体発光素子。
- 基板上に単結晶のIII族窒化物半導体層を形成するエピタキシャル工程と、前記III族窒化物半導体層上にn型半導体層、発光層及びp型半導体層を順次積層して半導体層を形成する半導体層形成工程と、前記p型半導体層上に透光性電極を形成する透光性電極形成工程とが備えられてなるIII族窒化物半導体発光素子の製造方法であって、
前記透光性電極形成工程は、前記p型半導体層上の少なくとも一部に絶縁層を形成した後、前記p型半導体層上に前記絶縁層を覆うように前記透光性電極を形成し、
前記透光性電極形成工程の後、前記透光性電極の表面において、前記p型半導体層上に形成された前記絶縁層の上方に正極ボンディングパッドを形成する正極形成工程が備えられており、
前記半導体層形成工程は、前記n型半導体層のシート抵抗が前記透光性電極のシート抵抗よりも低くなるように前記n型半導体層を形成することを特徴とするIII族窒化物半導体発光素子の製造方法。 - 前記半導体層形成工程は、前記n型半導体層を15Ω/□以下のシート抵抗となるように形成し、前記透光性電極形成工程は、前記透光性電極を30Ω/□以下のシート抵抗となるように形成することを特徴とする請求項6に記載のIII族窒化物半導体発光素子の製造方法。
- 前記透光性電極形成工程は、前記透光性電極の表面の少なくとも一部に凹凸形状を形成することを特徴とする請求項6に記載のIII族窒化物半導体発光素子の製造方法。
- 前記透光性電極形成工程は、前記透光性電極を形成する材料として、酸化インジウム錫(ITO:Indium Tin Oxide)、酸化インジウム亜鉛(IZO:Indium Zinc Oxide)、酸化インジウムガリウム(IGO:Indium Gallium Oxide)、酸化インジウムセリウム(ICO:Indium Cerium Oxide)及び導電性酸化チタン(TiO2)からなる群から選ばれる少なくとも1種を用いることを特徴とする請求項6に記載のIII族窒化物半導体発光素子の製造方法。
- 前記透光性電極形成工程は、前記絶縁層を形成する材料として酸化シリコン(SiO2)を用いることを特徴とする請求項6に記載のIII族窒化物半導体発光素子の製造方法。
- 請求項1~請求項5の何れか1項に記載のIII族窒化物半導体発光素子が用いられてなることを特徴とするランプ。
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