WO2010027231A2 - 리드 프레임 및 그 제조방법 - Google Patents
리드 프레임 및 그 제조방법 Download PDFInfo
- Publication number
- WO2010027231A2 WO2010027231A2 PCT/KR2009/005057 KR2009005057W WO2010027231A2 WO 2010027231 A2 WO2010027231 A2 WO 2010027231A2 KR 2009005057 W KR2009005057 W KR 2009005057W WO 2010027231 A2 WO2010027231 A2 WO 2010027231A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- copper
- lead frame
- rough
- substrate
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/85439—Silver (Ag) as principal constituent
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
Definitions
- An embodiment relates to a lead frame and a method of manufacturing the same.
- the lead frame is one of the components constituting the semiconductor package together with the semiconductor chip.
- the lead frame may simultaneously serve as a conductor connecting the inside and the outside of the semiconductor package and a support for supporting the semiconductor chip.
- the conventional lead frame was used by plating a release metal layer or an alloy layer on a substrate used as the base material of the lead frame.
- the release metal layer or the alloy layer may prevent impurities from diffusing or oxidizing the substrate and may improve adhesion with an epoxy mold compound (EMC) resin during a packaging process.
- EMC epoxy mold compound
- An embodiment provides a lead frame and a method of manufacturing the same.
- the embodiment provides a lead frame and a method of manufacturing the same, which can improve characteristics with a simple process and low cost.
- Lead frame according to the embodiment is a copper substrate; And a rough copper layer having a surface roughness of 110-300 nm on the surface of the copper substrate.
- Lead frame according to the embodiment is a copper substrate; A rough copper layer on the copper substrate; A nickel layer on the rough copper layer; A palladium layer on the nickel layer; And a gold layer on the palladium layer.
- Lead frame manufacturing method is a step of preparing a copper substrate; And electroplating the copper substrate in a copper sulfate solution to form a rough copper layer.
- the embodiment can provide a lead frame and a method of manufacturing the same.
- the embodiment can provide a lead frame and a method of manufacturing the same that can improve characteristics at a simple process and at low cost.
- FIG. 1 is a cross-sectional view showing a lead frame according to the first embodiment.
- FIG. 4 is a view for explaining a lead frame manufacturing method according to the first embodiment.
- FIG. 5 is a view for explaining a lead frame according to the second embodiment
- FIG. 6 is an enlarged view of a surface of a gold layer according to a second embodiment
- each layer (film), region, pattern or structure is “on” or “under” the substrate, each layer (film), region, pad or patterns.
- “on” and “under” include both “directly” or “indirectly” formed.
- the criteria for the top or bottom of each layer will be described with reference to the drawings.
- each layer is exaggerated, omitted, or schematically illustrated for convenience and clarity of description.
- the size of each component does not necessarily reflect the actual size.
- FIG. 1 is a cross-sectional view showing a lead frame according to a first embodiment.
- the lead frame according to the first embodiment includes a copper substrate 10 and a rough copper layer 20 formed on the surface of the copper substrate 10.
- the silver plating layer 30 may be locally formed on the surface of the rough copper layer 20.
- the copper substrate 10 may be formed of copper (Cu) or may be formed of an alloy containing copper as a main component.
- the copper substrate 10 may include various impurities to improve mechanical and electrical properties of the copper material.
- the copper substrate 10 may be manufactured by including at least one impurity of nickel (Ni), magnesium (Mg), and silicon (Si) in copper (Cu).
- the rough copper layer 20 may have an average thickness of 0.3-0.6 ⁇ m and a surface roughness of 110-300 nm.
- the rough copper layer 20 is formed on the surface of the copper substrate 10. Therefore, the bonding force of the copper substrate 10 and the rough copper layer 20 is stronger than the plating layer of the release material.
- the rough copper layer 20 may block diffusion of impurities of the copper substrate 10 to the outside by heat generated during the process, and prevent the copper substrate 10 from being oxidized by moisture in the air. Can be.
- the resin and the adhesive force for the epoxy mold compound (EMC) may be enhanced during the packaging process.
- the rough copper layer 20 has a very large surface roughness of 110-300 nm, adhesion to the resin is increased by an anchoring effect.
- the silver plating layer 30 may be formed to improve weldability and electrical conductivity with an electronic device such as a semiconductor chip.
- the silver plating layer 30 may be formed to a thickness of 3-5 ⁇ m.
- FIG. 4 is a view for explaining a lead frame manufacturing method according to the first embodiment.
- the manufacturing method of the lead frame may be a reel-to-reel process or a separate unit of strip unit, and may be manufactured in an in-line process. Can be.
- a copper substrate 10 is prepared (S100).
- the copper substrate 10 includes copper as a main material and may include various impurities to improve mechanical and electrical properties.
- the copper substrate 10 may be manufactured by including at least one impurity of nickel (Ni), magnesium (Mg), and silicon (Si) in copper (Cu).
- the washing step may proceed to a degreasing step, a washing step, a pickling step and a washing step.
- a rough copper layer 20 is formed on the surface of the copper substrate 10 (S120).
- the rough copper layer 20 is formed by electroplating in a copper sulfate (CuSO 4 ⁇ 5H 2 O) solution. It may proceed for 10 to 40 seconds, thereby forming a rough copper layer 20 having a thickness of 0.3-0.6 ⁇ m of surface roughness 110-300 nm.
- the copper sulfate solution may contain various additives as necessary.
- the concentration of copper ions is less than 5g / L, the amount of grains formed by plating is small, so that the effect of improving adhesion is small, and when the concentration of copper ions is greater than 70g / L, grains are formed as a whole and surface roughness The effect of increasing is small.
- the surface roughness of the rough copper layer 20 is formed to be small, and when the current density is greater than 7ASD, the rough copper layer 20 is overplated to form the rough copper layer 20.
- the grain size of the portion is formed relatively large and the grain size of the portion is formed relatively small so that a uniform surface roughness cannot be obtained.
- the surface roughness of the rough copper layer 20 is formed to be small, and when the plating time is greater than 40 seconds, the rough copper layer 20 is overplated to provide the rough copper layer 20.
- the grain size of the portion of the c) is formed relatively large and the grain size of the portion is formed relatively small to obtain a uniform surface roughness.
- the surface roughness of the rough copper layer 20 is less than 110nm, the effect of improving adhesion is less, and if the surface roughness of the rough copper layer 20 is greater than 300nm, uniform surface roughness may not be obtained.
- the copper sulfate (CuSO 4 ⁇ 5H 2 O) solution may form a plating layer having a higher surface roughness than other copper plating solutions, for example, blue copper (CuCN).
- CuCN blue copper
- a rough copper layer 20 having a thickness of 0.3 ⁇ m to 0.6 ⁇ m may be formed.
- the thickness of the rough copper layer 20 is less than 0.3 ⁇ m the surface roughness is formed small and when larger than 0.6 ⁇ m the rough copper layer 20 is overplated so that the grain size of a portion of the rough copper layer 20 It is formed relatively large and the grain size of a part is formed relatively small so that a uniform surface roughness cannot be obtained.
- the copper substrate 10 has a copper ion concentration of 40 g / L and a current density of 5 ASD (current amount per unit area) for 30 seconds.
- the rough copper layer 20 of thickness was formed.
- the copper substrate 10 on which the rough copper layer 20 is formed is cleaned (S130).
- the washing process may proceed to a washing process.
- a silver plating layer 30 is locally formed on the rough copper layer 20 (S140).
- the post-treatment process may include an electrolytic peeling process, an pickling process, a defecation process, a water washing process, and a drying process for the unnecessary silver plating layer.
- a lead frame as shown in FIG. 1 can be manufactured.
- the lead frame manufacturing method forms the rough copper layer 20 on the copper substrate 10 through an electroplating process.
- the electroplating process may increase the surface roughness of the rough copper layer 20 by appropriately controlling the concentration of copper ions, current density, time, and additives.
- the embodiment can improve the characteristics of the lead frame without forming a plating layer of the release material.
- FIG 5 is a view for explaining a lead frame according to the second embodiment.
- the silver plating layer 30 is locally formed on the rough copper layer 20, but in the second embodiment, the silver copper layer 20 is formed on the rough copper layer 20.
- the nickel (Ni) layer 40, the palladium (Pd) layer 50, and the gold (Au) layer 60 may be sequentially plated.
- the nickel layer 40 is plated on the rough copper layer 20
- the palladium layer 50 is plated on the nickel layer 40
- the gold layer 60 is formed on the palladium layer 50. It can be plated.
- the nickel layer 40 may be formed to a thickness of 0.5-2.5 ⁇ m
- the palladium layer 50 may be formed to a thickness of 0.02-0.15 ⁇ m
- the gold layer 60 is 0.003- It may be formed to a thickness of 0.015 ⁇ m.
- the gold layer 60 may have a surface roughness of 90-270 nm.
- the lead frame according to the second embodiment has the advantage that the soldering characteristics are improved by forming the rough copper layer 20, the nickel layer 40, the palladium layer 50, and the gold layer 60 on the copper substrate 10. .
- FIG. 6 is an enlarged view of a surface of a gold layer according to a second embodiment.
- the surface of the gold layer 60 is formed to be very rough according to the surface roughness of the rough copper layer 20.
- the embodiment may be applied to a lead frame and a method of manufacturing the same.
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Electroplating Methods And Accessories (AREA)
Abstract
Description
Claims (15)
- 구리 기판; 및상기 구리 기판의 표면에 표면 조도가 110-300nm인 러프 구리층을 포함하는 리드 프레임.
- 제 1항에 있어서,상기 러프 구리층 상에 국부적으로 형성된 은 도금층을 포함하는 리드 프레임.
- 제 1항에 있어서,상기 러프 구리층은 0.3-0.6㎛의 두께로 형성된 리프 프레임.
- 제 1항에 있어서,상기 러프 구리층 상에 형성된 니켈층, 팔라듐층 및 금층을 포함하는 리드 프레임.
- 제 1항에 있어서,상기 구리 기판은 니켈(Ni), 마그네슘(Mg) 및 실리콘(Si) 중 적어도 하나의 불순물을 포함하는 리드 프레임.
- 구리 기판;상기 구리 기판 상에 러프 구리층;상기 러프 구리층 상에 니켈층;상기 니켈층 상에 팔라듐층; 및상기 팔라듐층 상에 금층을 포함하는 리드 프레임.
- 제 6항에 있어서,상기 금층은 표면 조도가 90-270nm인 리드 프레임.
- 제 6항에 있어서,상기 니켈층은 상기 팔라듐층보다 두껍게 형성되고, 상기 팔라듐층은 상기 금층보다 두껍게 형성되는 리드 프레임.
- 구리 기판이 준비되는 단계; 및상기 구리 기판을 황산동 용액에서 전기 도금하여 러프 구리층을 형성하는 단계를 포함하는 리드 프레임 제조방법.
- 제 9항에 있어서,상기 러프 구리층을 형성하는 단계는.황산동 용액의 구리 이온의 농도를 5-70g/L로 하고 전류밀도를 3-7ASD로 하여 10~40초 동안 진행하는 리드 프레임 제조방법.
- 제 9항에 있어서,상기 러프 구리층은 표면 조도가 110-300nm인 리드 프레임 제조방법.
- 제 9항에 있어서,상기 러프 구리층은 두께가 0.3-0.6㎛인 리드 프레임 제조방법.
- 제 9항에 있어서,상기 러프 구리층 상에 국부적으로 은 도금층을 형성하는 단계를 포함하는 리드 프레임 제조방법.
- 제 9항에 있어서,상기 러프 구리층 상에 니켈층, 팔라듐층 및 금층을 형성하는 단계를 포함하는 리드 프레임 제조방법.
- 제 14항에 있어서,상기 금층은 표면 조도가 90-270nm인 리드 프레임 제조방법.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011525988A JP2012502462A (ja) | 2008-09-05 | 2009-09-07 | リードフレーム及びその製造方法 |
US13/062,245 US8945951B2 (en) | 2008-09-05 | 2009-09-07 | Lead frame and manufacturing method thereof |
CN2009801394703A CN102171820A (zh) | 2008-09-05 | 2009-09-07 | 引线框及其制造方法 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2008-0087689 | 2008-09-05 | ||
KR1020080087689A KR101241735B1 (ko) | 2008-09-05 | 2008-09-05 | 리드 프레임 및 그 제조방법 |
Publications (2)
Publication Number | Publication Date |
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WO2010027231A2 true WO2010027231A2 (ko) | 2010-03-11 |
WO2010027231A3 WO2010027231A3 (ko) | 2010-06-24 |
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ID=41797680
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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PCT/KR2009/005057 WO2010027231A2 (ko) | 2008-09-05 | 2009-09-07 | 리드 프레임 및 그 제조방법 |
Country Status (6)
Country | Link |
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US (1) | US8945951B2 (ko) |
JP (1) | JP2012502462A (ko) |
KR (1) | KR101241735B1 (ko) |
CN (1) | CN102171820A (ko) |
TW (1) | TW201011885A (ko) |
WO (1) | WO2010027231A2 (ko) |
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WO2013089376A1 (en) * | 2011-12-12 | 2013-06-20 | Samsung Techwin Co., Ltd | Lead frame and semiconductor package manufactured by using the same |
KR101646094B1 (ko) | 2011-12-12 | 2016-08-05 | 해성디에스 주식회사 | 리드 프레임 및 이를 이용하여 제조된 반도체 패키지 |
CN107154392B (zh) * | 2016-03-02 | 2019-11-26 | 顺德工业股份有限公司 | 导线架 |
US11000915B2 (en) * | 2016-03-31 | 2021-05-11 | Texas Instruments Incorporated | Stabilized transient liquid phase metal bonding material for hermetic wafer level packaging of MEMS devices |
WO2017179447A1 (ja) * | 2016-04-12 | 2017-10-19 | 古河電気工業株式会社 | リードフレーム材およびその製造方法 |
US9653385B1 (en) * | 2016-05-26 | 2017-05-16 | Sdi Corporation | Lead frame |
CN107447237B (zh) * | 2016-05-30 | 2021-04-20 | 史莱福灵有限公司 | 具有降低的接触噪声的滑环 |
WO2018074035A1 (ja) * | 2016-10-18 | 2018-04-26 | 株式会社デンソー | 電子装置及びその製造方法 |
JP6479265B2 (ja) * | 2016-12-27 | 2019-03-06 | 古河電気工業株式会社 | リードフレーム材およびその製造方法ならびに半導体パッケージ |
TWI613768B (zh) * | 2017-03-20 | 2018-02-01 | 矽品精密工業股份有限公司 | 電子封裝件及其製法 |
JP7016677B2 (ja) * | 2017-11-21 | 2022-02-07 | 新光電気工業株式会社 | リードフレーム、半導体装置、リードフレームの製造方法 |
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KR20100103015A (ko) * | 2009-03-12 | 2010-09-27 | 엘지이노텍 주식회사 | 리드 프레임 및 그 제조방법 |
-
2008
- 2008-09-05 KR KR1020080087689A patent/KR101241735B1/ko active IP Right Grant
-
2009
- 2009-09-04 TW TW098129899A patent/TW201011885A/zh unknown
- 2009-09-07 JP JP2011525988A patent/JP2012502462A/ja active Pending
- 2009-09-07 WO PCT/KR2009/005057 patent/WO2010027231A2/ko active Application Filing
- 2009-09-07 CN CN2009801394703A patent/CN102171820A/zh active Pending
- 2009-09-07 US US13/062,245 patent/US8945951B2/en active Active
Patent Citations (4)
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KR19990016567A (ko) * | 1997-08-18 | 1999-03-15 | 윤종용 | 반도체 칩 패키지의 리드 프레임 표면 처리 방법 및 그 리드프레임 |
KR20000007350A (ko) * | 1998-07-02 | 2000-02-07 | 유무성 | 다중 도금층을 가지는 반도체 리이드프레임 |
KR100819800B1 (ko) * | 2005-04-15 | 2008-04-07 | 삼성테크윈 주식회사 | 반도체 패키지용 리드 프레임 |
KR20080048526A (ko) * | 2005-09-06 | 2008-06-02 | 유니셈 (모리셔스) 홀딩스 리미티드 | 반도체 패키지들을 위한 다이 패드 |
Also Published As
Publication number | Publication date |
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KR20100028791A (ko) | 2010-03-15 |
JP2012502462A (ja) | 2012-01-26 |
CN102171820A (zh) | 2011-08-31 |
KR101241735B1 (ko) | 2013-03-08 |
WO2010027231A3 (ko) | 2010-06-24 |
US8945951B2 (en) | 2015-02-03 |
TW201011885A (en) | 2010-03-16 |
US20110272184A1 (en) | 2011-11-10 |
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