WO2009139070A1 - 製造方法および試験用ウエハユニット - Google Patents
製造方法および試験用ウエハユニット Download PDFInfo
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- WO2009139070A1 WO2009139070A1 PCT/JP2008/059085 JP2008059085W WO2009139070A1 WO 2009139070 A1 WO2009139070 A1 WO 2009139070A1 JP 2008059085 W JP2008059085 W JP 2008059085W WO 2009139070 A1 WO2009139070 A1 WO 2009139070A1
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- wafer
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- test
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/073—Multiple probes
- G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
- G01R1/07364—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card with provisions for altering position, number or connection of probe tips; Adapting to differences in pitch
- G01R1/07378—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card with provisions for altering position, number or connection of probe tips; Adapting to differences in pitch using an intermediate adapter, e.g. space transformers
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates to a test wafer unit and a manufacturing method thereof.
- the present invention relates to a test wafer unit provided with a plurality of test circuits for testing a plurality of semiconductor chips formed on a semiconductor wafer, and a method for manufacturing the same.
- the apparatus includes a probe card that can be electrically connected to a plurality of semiconductor chips at once.
- the BOST circuit can be formed with high density by a semiconductor process, and a large number of BOST circuits can be provided in the probe card.
- a via hole that electrically connects the front and back surfaces of the semiconductor wafer is formed.
- the BOST circuit is formed in the probe card, it is preferable to shorten the time for forming the via hole in order to reduce damage to the BOST circuit when forming the via hole. For example, by reducing the thickness of the semiconductor wafer used as the probe card substrate as much as possible, the time for forming the via hole penetrating the semiconductor wafer can be shortened.
- the strength of the semiconductor wafer is reduced.
- the probe card since the probe card contacts the chip under test with a constant pressing force, it is not preferable to reduce the strength of the semiconductor wafer used for the probe card.
- the probe card has a large area, and the problem due to a decrease in the strength of the semiconductor wafer becomes significant.
- an object of the present invention is to provide a manufacturing method and a test wafer unit that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims.
- the dependent claims define further advantageous specific examples of the present invention.
- the first aspect of the present invention is a manufacturing method for manufacturing a test wafer unit provided with a plurality of test circuits for testing a plurality of semiconductor chips formed on a semiconductor wafer. Then, a plurality of test circuits are formed on the circuit wafer, and a plurality of circuit side pads to be electrically connected to the plurality of test circuits are formed on a predetermined surface of the connection wafer having a wafer thickness larger than that of the circuit wafer.
- a plurality of wafer-side pads to be electrically connected to the plurality of semiconductor chips on the back surface of the predetermined surface, and a plurality of lengths for electrically connecting the plurality of circuit-side pads and the plurality of wafer-side pads.
- a test wafer unit provided with a plurality of test circuits for testing a plurality of semiconductor chips formed on a semiconductor wafer, wherein the circuit wafer has a plurality of test circuits formed thereon. And a plurality of circuit-side pads to be electrically connected to the plurality of test circuits are formed on the predetermined surface, and a plurality of wafers to be electrically connected to the plurality of semiconductor chips on the back surface of the predetermined surface.
- a test wafer unit comprising a connection wafer having a wafer thickness larger than a circuit wafer, wherein a side pad is formed and a plurality of long via holes are formed to electrically connect the plurality of circuit side pads and the plurality of wafer side pads. I will provide a.
- FIG. 5 is a diagram showing an example of a method for manufacturing a test wafer unit 600.
- FIG. FIG. 2A shows a circuit wafer 610 and a connection wafer 630 to be prepared.
- FIG. 2B shows pads and the like formed on the circuit wafer 610 and the connection wafer 630.
- FIG. 2C shows an example of the test wafer unit 600.
- 5 is a diagram illustrating a detailed configuration example of a test wafer unit 600.
- FIG. FIG. 6 is a view showing another example of a test wafer unit 600.
- FIG. 11 is a diagram showing another example of a connection wafer 630.
- FIG. 11 is a diagram showing another example of a connection wafer 630.
- 3 is a block diagram illustrating a functional configuration example of a test circuit 616.
- FIG. 1 is a diagram for explaining an outline of a test using the test wafer unit 600.
- each semiconductor chip 310 of the semiconductor wafer 300 is tested using the test wafer unit 600.
- the test wafer unit 600 may include a wafer formed of the same semiconductor material as the substrate of the semiconductor wafer 300 to be tested. Further, the test wafer unit 600 may include a wafer having substantially the same diameter as the substrate of the semiconductor wafer 300 to be tested. The wafer of the test wafer unit 600 is disposed so as to overlap the semiconductor wafer 300, thereby being electrically connected to the inspection pads in the plurality of semiconductor chips 310 in a lump. A plurality of wafer-side pads 636 corresponding to the pads of the semiconductor chip 310 may be formed on the surface of the test wafer unit 600 that faces the semiconductor wafer 300.
- the test wafer unit 600 includes a plurality of test circuits 616 corresponding to the plurality of semiconductor chips 310.
- the test wafer unit 600 may include a plurality of test circuits 616 corresponding to the plurality of semiconductor chips 310 on a one-to-one basis.
- Each test circuit 616 may test the corresponding semiconductor chip 310 based on test data given in advance.
- each test circuit 616 may generate a test signal to be supplied to the corresponding semiconductor chip 310, and determine whether the semiconductor chip 310 is good or bad based on a response signal output from the corresponding semiconductor chip 310. Good.
- the control device 10 may supply test data, power supply power, a control signal, and the like to each test circuit 616.
- the control device 10 may write the same test data in parallel to each test circuit 616.
- the test wafer unit 600 tests the plurality of semiconductor chips 310 in parallel by being electrically connected together with the plurality of semiconductor chips 310 of the semiconductor wafer 300 to be tested.
- the test circuit 616 and the wafer-side pad 636 are shown on the same wafer of the test wafer unit 600. However, the test circuit 616 and the wafer-side pad 636 are provided on different wafers in the test wafer unit 600. It is done.
- FIG. 2 is a diagram illustrating an example of a method for manufacturing the test wafer unit 600.
- FIG. 2A shows a circuit wafer 610 and a connection wafer 630 to be prepared.
- FIG. 2B shows pads and the like formed on the circuit wafer 610 and the connection wafer 630.
- FIG. 2C shows an example of the test wafer unit 600.
- a circuit wafer 610 and a connection wafer 630 are prepared.
- a wafer having a wafer thickness h 2 larger than the wafer thickness h 1 of the circuit wafer 610 is prepared as the connection wafer 630.
- circuit wafer 610 and the connection wafer 630 may be formed of the same substrate material.
- the circuit wafer 610 and the connection wafer 630 may be formed of the same substrate material as the semiconductor wafer 300 to be tested.
- the circuit wafer 610 and the connection wafer 630 may be silicon wafers.
- circuit wafer 610 and the connection wafer 630 may be wafers having substantially the same diameter.
- the circuit wafer 610 and the connection wafer 630 may have the same diameter as the semiconductor wafer 300 to be tested.
- elements such as pads, wirings, and circuits are formed on the circuit wafer 610 and the connection wafer 630.
- these elements may be formed by a semiconductor process such as exposure.
- element formation for the circuit wafer 610 and the connection wafer 630 is performed for each wafer.
- a plurality of test circuits 616 are formed on the surface of the wafer.
- the test circuit 616 is formed corresponding to the plurality of semiconductor chips 310 to be tested, and tests the corresponding semiconductor chips 310, respectively.
- the test circuit 616 may include a circuit that generates a test signal supplied to the semiconductor chip 310. Further, a circuit for determining whether the semiconductor chip 310 is good or bad based on a signal output from the semiconductor chip 310 may be provided.
- a plurality of front surface pads 612, a plurality of back surface pads 620, a plurality of wirings 614, and a plurality of short via holes 618 are further formed corresponding to the plurality of test circuits 616.
- Each surface pad 612 is formed on the same surface as the test circuit 616 in the circuit wafer 610.
- Each wiring 614 electrically connects the corresponding test circuit 616 and the surface pad 612.
- Each back pad 620 is formed on the back surface of the surface on which the test circuit 616 is provided in the circuit wafer 610.
- Each short via hole 618 is formed through the circuit wafer 610 so as to electrically connect the corresponding test circuit 616 and back surface pad 620 via the front surface pad 612.
- the short via hole 618 is formed by forming a through hole in the circuit wafer 610 by etching or the like and applying a conductive material to the surface of the through hole by vapor deposition or the like.
- the front surface pad 612 and the back surface pad 620 are formed at both ends of the short via hole 618.
- the test circuit 616 when the conductive material for the short via hole 618 is applied, the test circuit 616 that has already been formed may be damaged because the processing such as heating and charging is performed.
- the damage given to the test circuit 616 depends on the time length of the step of applying the conductive material of the short via hole 618. Further, the time length of the step of applying the conductive material for the short via hole 618 depends on the length of the short via hole 618, the surface area, and the like. For this reason, it is preferable that the wafer thickness h1 of the circuit wafer 610 be thin enough to ignore damage to the test circuit 616 when the conductive material for the short via hole 618 is applied. For example, the wafer thickness h1 of the circuit wafer 610 may be about several tens of ⁇ m.
- a plurality of circuit side pads 632, a plurality of wafer side pads 636, and a plurality of long via holes 634 are formed in the connection wafer 630.
- the plurality of circuit-side pads 632 are formed on a predetermined surface of the connection wafer 630 that should be disposed to face the circuit wafer 610 so as to be electrically connected to the plurality of test circuits 616.
- the plurality of circuit side pads 632 are formed in one-to-one correspondence with the plurality of back surface pads 620.
- the wafer-side pad 636 is formed on the back surface of the predetermined surface described above so as to be electrically connected to the plurality of semiconductor chips 310.
- the plurality of wafer side pads 636 are formed in one-to-one correspondence with the plurality of circuit side pads 632.
- the long via hole 634 is formed through the connection wafer 630 so as to electrically connect the corresponding circuit side pad 632 and wafer side pad 636.
- the long via hole 634 is formed by forming a through hole in the connection wafer 630 by etching or the like and applying a conductive material to the surface of the through hole by electrolytic plating or the like.
- the circuit side pad 632 and the wafer side pad 636 are formed at both ends of the long via hole 634.
- the long via hole 634 may be formed by the same method as the short via hole 618, or may be formed by a method suitable for forming a via hole having a larger area. Since a circuit that generates a signal is not formed in the connection wafer 630, the long via hole 634 may be formed over a longer time than the short via hole 618. For example, the time for forming the conductive material in the short via hole 618 may be shorter than the time for forming the conductive material in the long via hole 634.
- the circuit wafer 610 and the connection wafer 630 are overlapped so that the combination of the corresponding back surface pad 620 and circuit side pad 632 is electrically connected, A test wafer unit 600 is formed.
- the plurality of test circuits 616 are electrically connected to the plurality of wafer side pads 636 via the plurality of circuit side pads 632.
- test wafer unit 600 of this example forms the test circuit 616 on the relatively thin circuit wafer 610
- damage to the test circuit 616 when the short via hole 618 is formed on the circuit wafer 610. Can be reduced.
- the relatively thick connection wafer 630 is superimposed on the circuit wafer 610, the strength of the test wafer unit 600 can be improved. For this reason, even if it is a case where the semiconductor wafer 300 of a large area is tested, it can prevent that the wafer unit 600 for a test is damaged.
- the circuit wafer 610 and the connection wafer 630 may be fixed in a superposed state. For example, it may be attached via an anisotropic conductive sheet having adhesiveness. Moreover, you may bond together by another method.
- FIG. 3 is a diagram showing a detailed configuration example of the test wafer unit 600.
- the test wafer unit 600 of this example stores a circuit wafer 610 and a connection wafer 630 between the wiring board 202 and the membrane 222.
- the wiring board 202 may be a printed board on which wiring for electrically connecting the test circuit 616 of the circuit wafer 610 and the control device 10 is provided.
- the circuit wafer 610 is electrically connected to the wiring substrate 202 via the apparatus-side anisotropic conductive sheet 212.
- the connection wafer 630 is electrically connected to the circuit wafer 610 via the intermediate anisotropic conductive sheet 252.
- the connection wafer 630 is electrically connected to the membrane 222 via the wafer side anisotropic conductive sheet 218.
- the support unit 204 supports the membrane 222 with respect to the wiring substrate 202, so that the apparatus-side anisotropic conductive sheet 212, the circuit wafer 610, the intermediate anisotropic conductive sheet 252, the connection wafer 630, and the wafer side
- the anisotropic conductive sheet 218 is fixed to the wiring board 202.
- the support portion 204 may include an extending portion 205 provided by extending in the vertical direction from the back surface of the wiring board 202, and a locking portion 209 that locks the fixing ring 220 at the lower end of the extending portion 205. That is, the support unit 204 may indicate the membrane 222 fixed to the fixing ring 220 by supporting the fixing ring 220.
- the support unit 204 supports the lower end of the fixing ring 220 at a position away from the lower surface of the wiring substrate 202 by a predetermined distance so that the lower end of the fixing ring 220 cannot be more than a predetermined distance from the lower surface of the wiring substrate 202. It's okay. Further, the support part 204 may be fixed to the wiring board 202 by inserting screws into the screw holes 208 provided in the wiring board 202 and the screw holes 206 provided in the support part 204. The diameter of the screw hole 206 may be larger than the diameter of the screw hole 208.
- the device-side seal 214 is provided along the peripheral edge of the surface of the membrane 222 on the wiring board 202 side, and seals between the peripheral edge of the surface of the membrane 222 on the wiring board 202 side and the wiring board 202.
- the apparatus side seal part 214 may be formed of an elastic material having elasticity.
- the membrane 222 is provided between the wafer side anisotropic conductive sheet 218 and the semiconductor wafer 300.
- the membrane 222 may have bump terminals that electrically connect the terminals of the semiconductor wafer 300 and the wafer-side pads 636 of the connection wafer 630.
- the fixing ring 220 fixes the membrane 222 to the apparatus side seal part 214. As shown in FIG. 3, a gap may be provided between each anisotropic conductive sheet and each wafer and the apparatus-side seal portion 214.
- the fixing ring 220 may be provided in an annular shape along the peripheral edge of the surface of the membrane 222 on the semiconductor wafer 300 side.
- the membrane 222 has a circular shape with substantially the same diameter as the fixing ring 220, and the end portion is fixed to the fixing ring 220.
- the membrane 222 of the test wafer unit 600 is electrically connected to the semiconductor wafer 300 placed on the wafer tray 226.
- the wafer tray 226 is moved to a predetermined position by the wafer stage 228.
- the wafer tray 226 is provided so as to form a sealed space with the wiring board 202.
- the wafer tray 226 of this example forms a sealed space with the wiring substrate 202, the device-side seal portion 214, and the wafer-side seal portion 224.
- the wafer tray 226 places the semiconductor wafer 300 on the surface of the sealed space side.
- the wafer side seal part 224 is provided along the region corresponding to the peripheral part of the membrane 222 on the surface of the wafer tray 226, and seals between the peripheral part of the wafer tray side surface of the membrane 222 and the wafer tray 226.
- the wafer side seal portion 224 may be formed in an annular shape on the surface of the wafer tray 226.
- the wafer side seal portion 224 may be formed in a lip shape in which the annular diameter increases as the distance from the surface of the wafer tray 226 increases.
- the tip of the wafer-side seal portion 224 bends according to the pressing force, thereby bringing the distance between the membrane 222 and the semiconductor wafer 300 closer.
- the wafer-side seal portion 224 is formed such that the height from the surface of the wafer tray 226 when not pressed against the membrane 222 is higher than the height of the semiconductor wafer 300.
- the decompression unit 234 decompresses the sealed space between the wiring substrate 202 and the wafer tray 226 formed by the wiring substrate 202, the wafer tray 226, the apparatus side seal unit 214, and the wafer side seal unit 224. As a result, the decompression unit 234 brings the wafer tray 226 closer to the wiring board 202 to a predetermined position.
- the wafer tray 226 is disposed at the predetermined position so as to apply a pressing force to each anisotropic conductive sheet, and the wiring substrate 202, the circuit wafer 610, the connection wafer 630, the membrane 222, and the semiconductor.
- the wafer 300 is electrically connected.
- the wafer side seal portion 224 may contact the membrane 222 inside the fixing ring 220.
- the sealed space is divided by the membrane 222 into a space on the wiring substrate 202 side and a space on the wafer tray 226 side.
- the membrane 222 is provided with a through hole 242 connecting these spaces.
- the device side anisotropic conductive sheet 212, the circuit wafer 610, the connection wafer 630, and the wafer side anisotropic conductive sheet 218 may be similarly provided with a through hole 213, a through hole 240, and a through hole 219. .
- through holes are also provided in the device-side anisotropic conductive sheet 212, the circuit wafer 610, the intermediate anisotropic conductive sheet 252, the connection wafer 630, and the wafer-side anisotropic conductive sheet 218. .
- These through-holes are preferably distributed substantially uniformly in each plane. With such a configuration, the air sucked in the process of depressurizing the sealed space flows in a dispersed manner through the many through holes.
- the pressing force applied to the anisotropic conductive sheet is distributed almost uniformly in each plane, and the stress strain in the depressurization process can be greatly reduced. For this reason, the crack of a wafer, the distortion of an anisotropic conductive sheet, etc. can be prevented. Further, by providing the through-hole 242 in the membrane 222, it is possible to decompress the space on the wiring substrate 202 side and the space on the semiconductor wafer 300 side with one decompression unit 234, and electrically connect them. Can do.
- the decompression unit 234 sucks the semiconductor wafer 300 onto the wafer tray 226.
- the decompression unit 234 of this example includes a decompressor 236 for a sealed space and a decompressor 238 for a semiconductor wafer.
- an air intake path 232 for a sealed space and an air intake path 230 for a semiconductor wafer are formed in the wafer tray 226.
- connection wafer 630 fixed to the wiring board 202 and the semiconductor wafer 300 can be electrically connected. Then, in a state where the connection wafer 630 and the semiconductor wafer 300 are electrically connected, the connection space 630 and the semiconductor are sealed by sealing the air intake path 232 for the sealed space and the air intake path 230 for the semiconductor wafer. The wafer 300 is fixed.
- FIG. 4 is a diagram showing another example of the test wafer unit 600.
- a plurality of wafer-side pads 636 are formed with a pad interval different from that of the plurality of circuit-side pads 632. That is, the connection wafer 630 of this example also functions as a pitch conversion substrate.
- the plurality of circuit side pads 632 are formed at positions corresponding to the back surface pads 620 of the circuit wafer 610.
- the plurality of wafer side pads 636 are formed at positions corresponding to the pads 312 of the semiconductor wafer 300. With such a configuration, the circuit wafer 610 having different pad intervals and the semiconductor wafer 300 can be electrically connected.
- one end of the long via hole 634 in this example is connected to the corresponding wafer-side pad 636.
- a plurality of pitch conversion wirings 638 and a plurality of intermediate pads 640 are further formed on the connection wafer 630.
- the plurality of intermediate pads 640 are formed at positions where they are connected to the other end of the long via hole 634.
- Each pitch conversion wiring 638 electrically connects the other end of the corresponding long via hole 634 to the corresponding circuit side pad 632 through the intermediate pad 640.
- FIG. 5 is a view showing another structure example of the connection wafer 630.
- a plurality of switches 642 are further formed in addition to the structure of the connection wafer 630 described with reference to FIGS.
- the plurality of switches 642 may be provided in one-to-one correspondence with the plurality of wafer-side pads 636.
- Each switch 642 switches whether or not to electrically connect the corresponding wafer side pad 636 and the corresponding test circuit 616.
- the switch 642 may include a transistor provided between the circuit side pad 632 and the intermediate pad 640.
- FIG. 6 is a diagram showing another example of the structure of the connection wafer 630.
- a switch portion 644 is further formed on the connection wafer 630 in this example.
- the switch unit 644 switches which test circuit 616 is electrically connected to each wafer-side pad 636.
- the switch unit 644 of this example may switch the connection relationship between the wafer-side pad 636 and the test circuit 616 by switching to which intermediate pad 640 each circuit-side pad 632 is connected.
- FIG. 7 is a block diagram illustrating a functional configuration example of the test circuit 616.
- the test circuit 616 includes a pattern generation unit 122, a waveform shaping unit 130, a driver 132, a comparator 134, a timing generation unit 136, a logic comparison unit 138, a characteristic measurement unit 140, and a power supply unit 142. Note that the test circuit 616 may have the configuration shown in FIG. 7 for each input / output pin of the semiconductor chip 310 to be connected. These structures may be formed on the circuit wafer 610 by a semiconductor process such as exposure.
- the pattern generator 122 generates a logic pattern of the test signal.
- the pattern generation unit 122 of this example includes a pattern memory 124, an expected value memory 126, and a fail memory 128.
- the pattern generator 122 may output a logical pattern stored in advance in the pattern memory 124.
- the pattern memory 124 may store a logical pattern given from the control device 10 before starting the test.
- the pattern generator 122 may generate the logical pattern based on an algorithm given in advance.
- the waveform shaping unit 130 shapes the waveform of the test signal based on the logical pattern given from the pattern generation unit 122.
- the waveform shaping unit 130 may shape the waveform of the test signal by outputting a voltage corresponding to each logic value of the logic pattern for each predetermined bit period.
- the driver 132 outputs a test signal corresponding to the waveform given from the waveform shaping unit 130.
- the driver 132 may output a test signal in accordance with the timing signal given from the timing generator 136.
- the driver 132 may output a test signal having the same cycle as the timing signal.
- the driver 132 supplies the test signal to the corresponding semiconductor chip 310.
- the comparator 134 measures the response signal output from the semiconductor chip 310.
- the comparator 134 may measure the logical pattern of the response signal by sequentially detecting the logical value of the response signal in accordance with the strobe signal supplied from the timing generator 136.
- the logic comparison unit 138 functions as a determination unit that determines the quality of the corresponding semiconductor chip 310 based on the logic pattern of the response signal measured by the comparator 134. For example, the logic comparison unit 138 may determine the quality of the semiconductor chip 310 based on whether or not the expected value pattern given from the pattern generation unit 122 matches the logic pattern detected by the comparator 134.
- the pattern generation unit 122 may supply the expected value pattern stored in advance in the expected value memory 126 to the logic comparison unit 138.
- the expected value memory 126 may store a logic pattern given from the control device 10 before the test is started.
- the pattern generation unit 122 may generate the expected value pattern based on an algorithm given in advance.
- the fail memory 128 stores the comparison result in the logical comparison unit 138.
- the fail memory 128 may store the pass / fail judgment result in the logic comparison unit 138 for each address of the semiconductor chip 310.
- the control device 10 may read the pass / fail judgment result stored in the fail memory 128.
- the test circuit 616 may output the pass / fail judgment result stored in the fail memory 128 to the control device 10 outside the test wafer unit 600.
- the characteristic measurement unit 140 measures the voltage or current waveform output by the driver 132.
- the characteristic measurement unit 140 may function as a determination unit that determines whether the semiconductor chip 310 is good or not based on whether a waveform of a current or voltage supplied from the driver 132 to the semiconductor chip 310 satisfies a predetermined specification. .
- the power supply unit 142 supplies power for driving the semiconductor chip 310.
- the power supply unit 142 may supply power to the semiconductor chip 310 according to the power supplied from the control device 10 during the test. Further, the power supply unit 142 may supply drive power to each component of the test circuit 616.
- test circuit 616 Since the test circuit 616 has such a configuration, a test system in which the scale of the control device 10 is reduced can be realized.
- a general-purpose personal computer or the like can be used as the control device 10.
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Abstract
Description
Claims (9)
- 半導体ウエハに形成される複数の半導体チップを試験する複数の試験回路が設けられた試験用ウエハユニットを製造する製造方法であって、
回路用ウエハに前記複数の試験回路を形成し、
前記回路用ウエハよりウエハ厚が厚い接続用ウエハにおいて所定の面に、前記複数の試験回路と電気的に接続されるべき複数の回路側パッドを形成し、前記所定の面の裏面に、前記複数の半導体チップと電気的に接続されるべき複数のウエハ側パッドを形成し、前記複数の回路側パッドおよび前記複数のウエハ側パッドを電気的に接続する複数の長ビアホールを形成し、
前記回路用ウエハおよび前記接続用ウエハを重ねあわせることで、前記複数の試験回路と、前記複数の回路側パッドとを電気的に接続させて、前記試験用ウエハユニットを形成する製造方法。 - 前記接続用ウエハの前記複数のウエハ側パッドを、前記複数の回路側パッドとは異なるパッド間隔で形成し、
それぞれの前記長ビアホールを、一端が対応する前記ウエハ側パッドに接続するように形成し、
それぞれの前記長ビアホールの他端を、対応する前記回路側パッドに電気的に接続するピッチ変換配線を、前記接続用ウエハに更に形成する
請求項1に記載の製造方法。 - それぞれの前記ウエハ側パッドと、対応する前記試験回路とを電気的に接続するか否かを切り替えるスイッチを、前記接続用ウエハに更に形成する
請求項1に記載の製造方法。 - それぞれの前記ウエハ側パッドに、いずれの前記試験回路を電気的に接続するかを切り替えるスイッチを、前記接続用ウエハに更に形成する
請求項1に記載の製造方法。 - 前記複数の試験回路を、前記回路用ウエハの所定の面に形成し、
前記所定の面の裏面に設けられた複数のパッドと、前記複数の試験回路とを電気的に接続する複数の短ビアホールを、前記回路用ウエハに更に形成する
請求項1に記載の製造方法。 - 前記短ビアホールに導電材料を成膜する時間は、前記長ビアホールに導電材料を成膜する時間よりも短い
請求項5に記載の製造方法。 - 前記回路用ウエハおよび前記接続用ウエハとして、基板材料が同一のウエハを用いる
請求項1に記載の製造方法。 - 前記回路用ウエハおよび前記接続用ウエハとして、直径が略同一のウエハを用いる
請求項1に記載の製造方法。 - 半導体ウエハに形成される複数の半導体チップを試験する複数の試験回路が設けられた試験用ウエハユニットであって、
前記複数の試験回路が形成された回路用ウエハと、
所定の面に、前記複数の試験回路と電気的に接続されるべき複数の回路側パッドが形成され、前記所定の面の裏面に、前記複数の半導体チップと電気的に接続されるべき複数のウエハ側パッドが形成され、前記複数の回路側パッドおよび前記複数のウエハ側パッドを電気的に接続する複数の長ビアホールが形成される、前記回路用ウエハよりウエハ厚が厚い接続用ウエハと
を備える試験用ウエハユニット。
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PCT/JP2008/059085 WO2009139070A1 (ja) | 2008-05-16 | 2008-05-16 | 製造方法および試験用ウエハユニット |
JP2010511830A JP5208208B2 (ja) | 2008-05-16 | 2008-05-16 | 製造方法および試験用ウエハユニット |
TW098116152A TWI382486B (zh) | 2008-05-16 | 2009-05-15 | 製造方法以及測試用晶圓單元 |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110254000A1 (en) * | 2010-04-15 | 2011-10-20 | Hynix Semiconductor Inc. | Semiconductor chip embedded with a test circuit |
JP2013088288A (ja) * | 2011-10-18 | 2013-05-13 | Fujitsu Semiconductor Ltd | 検査装置及び検査システム |
CN113687206A (zh) * | 2021-10-21 | 2021-11-23 | 常州欣盛半导体技术股份有限公司 | 晶片测试板、晶片测试系统和晶片测试方法 |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2010044143A1 (ja) * | 2008-10-14 | 2010-04-22 | 株式会社アドバンテスト | 試験装置および製造方法 |
US20120286818A1 (en) * | 2011-05-11 | 2012-11-15 | Qualcomm Incorporated | Assembly for optical backside failure analysis of wire-bonded device during electrical testing |
US9817029B2 (en) | 2011-12-07 | 2017-11-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Test probing structure |
KR101977699B1 (ko) * | 2012-08-20 | 2019-08-28 | 에스케이하이닉스 주식회사 | 멀티 칩 반도체 장치 및 그것의 테스트 방법 |
JP6374642B2 (ja) * | 2012-11-28 | 2018-08-15 | 株式会社日本マイクロニクス | プローブカード及び検査装置 |
CN110911301A (zh) * | 2019-12-26 | 2020-03-24 | 苏州科阳光电科技有限公司 | 一种晶圆级封装检测结构及方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001210685A (ja) * | 1999-11-19 | 2001-08-03 | Hitachi Ltd | テストシステムおよび半導体集積回路装置の製造方法 |
JP2001338953A (ja) * | 2000-05-29 | 2001-12-07 | Mitsubishi Electric Corp | 半導体試験装置、半導体試験方法および半導体装置 |
JP2003084047A (ja) * | 2001-06-29 | 2003-03-19 | Sony Corp | 半導体装置の測定用治具 |
JP2007134048A (ja) * | 2001-08-07 | 2007-05-31 | Shinozaki Seisakusho:Kk | バンプ付き薄膜シートの製造方法及びバンプ付き薄膜シート |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63293934A (ja) * | 1987-05-27 | 1988-11-30 | Hitachi Ltd | 半導体素子検査装置 |
JPH0286147A (ja) * | 1988-09-22 | 1990-03-27 | Hitachi Ltd | 半導体装置 |
JPH04188863A (ja) | 1990-11-22 | 1992-07-07 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
JP2948018B2 (ja) | 1992-03-17 | 1999-09-13 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
JPH07231021A (ja) * | 1994-02-21 | 1995-08-29 | Aging Tesuta Kaihatsu Kyodo Kumiai | ウエハーバーンイン装置 |
JP2679684B2 (ja) * | 1995-05-12 | 1997-11-19 | 日本電気株式会社 | 異方導電フィルム及び異方導電フィルムを用いた半導体ウェハ測定治具 |
JPH08335610A (ja) | 1995-06-08 | 1996-12-17 | Advantest Corp | 半導体デバイス解析装置 |
US6400173B1 (en) * | 1999-11-19 | 2002-06-04 | Hitachi, Ltd. | Test system and manufacturing of semiconductor device |
JP2001153886A (ja) * | 1999-11-26 | 2001-06-08 | Mitsubishi Electric Corp | プローブカード、及びこれを備えたテスト装置 |
JP2002222839A (ja) * | 2001-01-29 | 2002-08-09 | Advantest Corp | プローブカード |
JP2003133538A (ja) | 2001-10-26 | 2003-05-09 | Nippon Hoso Kyokai <Nhk> | 半導体装置およびその製造方法 |
KR20030086042A (ko) * | 2002-05-03 | 2003-11-07 | 주식회사 하이닉스반도체 | 반도체소자의 테스트 장치 |
KR101104287B1 (ko) * | 2004-02-27 | 2012-01-13 | 가부시키가이샤 아드반테스트 | 프로브 카드 |
JP2006194620A (ja) * | 2005-01-11 | 2006-07-27 | Tokyo Electron Ltd | プローブカード及び検査用接触構造体 |
JP2007171140A (ja) * | 2005-12-26 | 2007-07-05 | Apex Inc | プローブカード、インターポーザおよびインターポーザの製造方法 |
JP4946110B2 (ja) | 2006-03-17 | 2012-06-06 | 富士通セミコンダクター株式会社 | 半導体装置試験方法、半導体装置試験装置および半導体装置試験プログラム |
JP4708269B2 (ja) * | 2006-06-22 | 2011-06-22 | シャープ株式会社 | 半導体装置、及び半導体装置の検査方法 |
JP2008089461A (ja) * | 2006-10-03 | 2008-04-17 | Tohoku Univ | 半導体集積回路検査用プローバ |
US7733102B2 (en) * | 2007-07-10 | 2010-06-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Ultra-fine area array pitch probe card |
-
2008
- 2008-05-16 KR KR1020107018692A patent/KR101148917B1/ko not_active IP Right Cessation
- 2008-05-16 WO PCT/JP2008/059085 patent/WO2009139070A1/ja active Application Filing
- 2008-05-16 JP JP2010511830A patent/JP5208208B2/ja not_active Expired - Fee Related
-
2009
- 2009-05-15 TW TW098116152A patent/TWI382486B/zh not_active IP Right Cessation
-
2010
- 2010-11-12 US US12/945,742 patent/US8441274B2/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001210685A (ja) * | 1999-11-19 | 2001-08-03 | Hitachi Ltd | テストシステムおよび半導体集積回路装置の製造方法 |
JP2001338953A (ja) * | 2000-05-29 | 2001-12-07 | Mitsubishi Electric Corp | 半導体試験装置、半導体試験方法および半導体装置 |
JP2003084047A (ja) * | 2001-06-29 | 2003-03-19 | Sony Corp | 半導体装置の測定用治具 |
JP2007134048A (ja) * | 2001-08-07 | 2007-05-31 | Shinozaki Seisakusho:Kk | バンプ付き薄膜シートの製造方法及びバンプ付き薄膜シート |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110254000A1 (en) * | 2010-04-15 | 2011-10-20 | Hynix Semiconductor Inc. | Semiconductor chip embedded with a test circuit |
KR101123802B1 (ko) | 2010-04-15 | 2012-03-12 | 주식회사 하이닉스반도체 | 반도체 칩 |
US8586983B2 (en) | 2010-04-15 | 2013-11-19 | Kwon Whan Han | Semiconductor chip embedded with a test circuit |
JP2013088288A (ja) * | 2011-10-18 | 2013-05-13 | Fujitsu Semiconductor Ltd | 検査装置及び検査システム |
CN113687206A (zh) * | 2021-10-21 | 2021-11-23 | 常州欣盛半导体技术股份有限公司 | 晶片测试板、晶片测试系统和晶片测试方法 |
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