WO2010044143A1 - 試験装置および製造方法 - Google Patents
試験装置および製造方法 Download PDFInfo
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- WO2010044143A1 WO2010044143A1 PCT/JP2008/068603 JP2008068603W WO2010044143A1 WO 2010044143 A1 WO2010044143 A1 WO 2010044143A1 JP 2008068603 W JP2008068603 W JP 2008068603W WO 2010044143 A1 WO2010044143 A1 WO 2010044143A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's
- G01R31/318511—Wafer Test
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
- G01R31/31926—Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing
Definitions
- the present invention relates to a test apparatus and a manufacturing apparatus.
- a test apparatus for testing a device under test such as a semiconductor circuit is based on whether or not a predetermined characteristic of the device under test satisfies a specification when a predetermined signal is input to the device under test. Judge the quality. Therefore, the test apparatus has a function corresponding to the type of device under test, the test item to be performed, and the like.
- the test apparatus is provided with a test circuit that realizes these functions (see, for example, Patent Document 1 and FIG. 5). JP 2002-139551 A
- test circuit described above has a unique function. Therefore, when a device under test is tested using other functions, a test circuit must be added or replaced. If the test circuit cannot be added or exchanged in the test apparatus, the device under test must be tested using another test apparatus.
- an object of the present invention is to provide a test apparatus and a manufacturing method that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims.
- the dependent claims define further advantageous specific examples of the present invention.
- a test apparatus for testing a plurality of devices under test formed on a wafer under test.
- a test board that is electrically connected to the device under test, a programmable device that is provided on the test board and that changes the logical relationship of the output logic data to the input logic data according to the given program data, and for testing Provided in correspondence with a plurality of devices under test on the substrate, and a plurality of input / output circuits that supply test signals corresponding to the output logic data of the programmable devices to the corresponding devices under test, respectively,
- a test apparatus including a determination unit that determines the quality of each device under test based on the operation result of the device under test. .
- a manufacturing method for manufacturing a test substrate that is electrically connected to a plurality of devices under test formed on a wafer under test and tests the plurality of devices under test.
- a programmable device that generates a digital test signal corresponding to given program data, a test circuit that generates an analog test signal, and a plurality of terminals of the device under test are provided on the circuit board and correspond to each other.
- a plurality of input / output circuits electrically connected to the terminals are formed by optical exposure, wiring for connecting the programmable device and the input / output circuit to the test substrate, and wiring for connecting the test circuit and the input / output circuit
- a manufacturing method in which at least a part is formed by electron beam exposure according to the type of device under test to be tested.
- FIG. 2 is a diagram for explaining an outline of a test apparatus 200.
- FIG. 2 is a diagram illustrating a configuration example of a circuit block 110.
- FIG. 3 is a block diagram illustrating a functional configuration example of a programmable device 120.
- FIG. FIG. 5 is a diagram illustrating another configuration example of the circuit block 110.
- FIG. 5 is a diagram illustrating another configuration example of the circuit block 110.
- FIG. 5 is a diagram illustrating another configuration example of the circuit block 110. It is a figure which shows the other structural example of the board
- substrate 100 for a test. 5 is a flowchart showing an example of a method for manufacturing the test substrate 100.
- FIG. 1 is a diagram for explaining the outline of the test apparatus 200.
- the test apparatus 200 is an apparatus for testing a plurality of devices under test 310 formed on a wafer under test 300, and includes a test substrate 100 and a control unit 10.
- the wafer under test 300 may be a disk-shaped semiconductor substrate, for example. More specifically, the wafer under test 300 may be silicon, a compound semiconductor, or another semiconductor substrate.
- the device under test 310 may be formed on the wafer under test 300 using a semiconductor process such as exposure.
- the test substrate 100 is electrically connected to the wafer under test 300. More specifically, the test substrate 100 is electrically connected to each of the plurality of devices under test 310 formed on the wafer under test 300 in a lump.
- the test substrate 100 has a plurality of circuit blocks 110.
- the test substrate 100 may be a wafer formed of the same semiconductor material as the wafer under test 300.
- the test substrate 100 may be a silicon substrate.
- the test substrate 100 may be formed of a semiconductor material having substantially the same coefficient of thermal expansion as the substrate of the wafer under test 300.
- the test substrate 100 may be a printed circuit board.
- the plurality of circuit blocks 110 are provided corresponding to the plurality of devices under test 310.
- the plurality of circuit blocks 110 are provided in one-to-one correspondence with the plurality of devices under test 310.
- Each circuit block 110 is electrically connected to a corresponding device under test 310 and tests the device under test 310.
- test substrate 100 of this example has substantially the same diameter as the wafer under test 300.
- Each circuit block 110 may be formed in a region of the test substrate 100 corresponding to a region in which a plurality of devices under test 310 are formed in the wafer under test 300.
- each circuit block 110 is formed such that the area where the circuit block 110 is formed overlaps the area where the device under test 310 is formed. May be.
- each circuit block 110 may be electrically connected to a corresponding device under test 310 via a via hole formed in the test substrate 100.
- electrically connecting may refer to a state in which an electrical signal can be transmitted between two members.
- the input / output pads of the circuit block 110 and the device under test 310 may be electrically connected by direct contact or indirectly through other conductors.
- the test apparatus 200 may include a probe member such as a membrane sheet having substantially the same diameter as the wafer under test 300 and the test substrate 100.
- the membrane sheet has bumps that electrically connect corresponding input / output pads of the circuit block 110 and the device under test 310.
- the test apparatus 200 may include an anisotropic conductive sheet between the membrane sheet and the test substrate 100.
- the circuit block 110 and the input / output pads of the device under test 310 are electrically connected in a non-contact state, such as capacitive coupling (also referred to as electrostatic coupling) or inductive coupling (also referred to as magnetic coupling). Also good. Further, a part of the transmission line between the input / output pads in the circuit block 110 and the device under test 310 may be an optical transmission line.
- test substrate 100 of this example is formed of the same semiconductor material as the wafer under test 300, even if the ambient temperature fluctuates, the test substrate 100 and the wafer under test 300 are not connected. Good electrical connection can be maintained. Therefore, for example, even when the test wafer 300 is heated and tested, the test wafer 300 can be accurately tested.
- the high-density circuit block 110 can be easily formed on the test substrate 100.
- the high-density circuit block 110 can be easily formed on the test substrate 100 by a semiconductor process using exposure or the like. Therefore, a large number of circuit blocks 110 corresponding to a large number of devices under test 310 can be formed on the test substrate 100 relatively easily.
- the scale of the control unit 10 can be reduced.
- the control unit 10 has a function of notifying the circuit block 110 of timing such as the start of a test, a function of reading a test result in the circuit block 110, and a function of supplying driving power to the circuit block 110 and the device under test 310. It only needs to have a function.
- the circuit block 110 can be arranged in the vicinity of the device under test 310. Therefore, transmission loss between the circuit block 110 and the device under test 310 can be reduced, and signals can be transmitted with high accuracy without providing an output driver or the like in the circuit block 110.
- FIG. 2 is a diagram illustrating a configuration example of the circuit block 110.
- the circuit block 110 includes a programmable device 120, a plurality of input / output circuits 130, and a plurality of wirings 112.
- the programmable device 120 is provided on the test substrate 100, and the logical relationship of the output logic data with respect to the input logic data changes according to the program data given from the control unit 10.
- the programmable device 120 may be a device whose connection between internal logic circuits is changed according to program data.
- the programmable device 120 may be a PLD, FPGA, or the like. Since the programmable device 120 of this example is provided for each circuit block 110, a plurality of programmable devices 120 are provided corresponding to the plurality of devices under test 310.
- the programmable device 120 functions as a test circuit that tests the corresponding device under test 310.
- the programmable device 120 may generate a digital signal having a pattern obtained by performing a logical operation according to program data on the given pattern data.
- the programmable device 120 may output the generated digital signal to the device under test 310 via a pin specified by the program data.
- the programmable device 120 may fetch a signal output from the device under test 310 from a pin corresponding to the program data.
- the programmable device 120 may determine pass / fail of the device under test 310 by performing a logical operation according to the program data on the captured signal.
- the programmable device 120 may be capable of functioning as a known logic circuit mounted on a conventional test circuit. Thereby, the versatility of the test apparatus 200 can be improved by changing the program data given to the programmable device 120 according to the type of the device under test 310 and the test item to be executed.
- the programmable device 120 may include a memory that stores program data to be given in a rewritable manner.
- the control unit 10 may function as a program control unit that changes program data to be given to the programmable device 120.
- the input / output circuit 130 is provided corresponding to each terminal of the plurality of devices under test 310 on the test substrate 100. Each input / output circuit 130 is electrically connected to one of the pins of the programmable device 120 via the wiring 112. The input / output circuit 130 transmits a signal between the pin of the corresponding programmable device 120 and the terminal of the corresponding device under test 310.
- the input / output circuit 130 may include a pad that contacts the terminal of the device under test 310 and an input / output buffer circuit that transmits a signal. As described above, since the circuit block 110 is disposed in the vicinity of the device under test 310, it is possible to accurately transmit a signal between the programmable device 120 and the device under test 310 without providing a driver circuit or the like. Can do.
- FIG. 3 is a block diagram illustrating a functional configuration example of the programmable device 120.
- the programmable device 120 of this example is programmed as a circuit that performs a function test of the device under test 310.
- the function test may be a test for determining whether or not the logic circuit operates normally when a predetermined logic pattern is input to the logic circuit of the device under test 310.
- the programmable device 120 functions as the pattern generation unit 122 and the logic comparison unit 124.
- the pattern generator 122 generates a digital signal having a predetermined logic pattern.
- the pattern generation unit 122 may generate a plurality of digital signals whose logical patterns sequentially change in a pseudo random bit sequence (PRBS).
- PRBS pseudo random bit sequence
- at least a part of the programmable device 120 functions as a circuit that generates a pseudo-random bit sequence.
- the pattern generation unit 122 may generate a digital signal having a logical pattern corresponding to the pattern data given from the control unit 10.
- the pattern generator 122 may function as an algorithm pattern generator (ALPG) that generates a logical pattern according to an algorithm defined by program data.
- APG algorithm pattern generator
- the method by which the pattern generation unit 122 generates the logical pattern can be set by program data supplied to the programmable device 120.
- the logic comparison unit 124 may function as a determination unit that determines the quality of the device under test 310 based on the operation result of the device under test 310 to which the above-described digital signal is applied.
- the logic comparison unit 124 may receive the response signal of the device under test 310 via the input / output circuit 130 and determine whether or not the logical value pattern of the response signal matches a predetermined expected value pattern.
- the expected value pattern may be given from the pattern generator 122.
- the programmable device 120 may measure the logic pattern of the response signal of the device under test 310 and output it to the control unit 10.
- the control unit 10 may function as a determination unit that compares the logical pattern with the expected value pattern.
- a function test of the device under test 310 can be performed.
- various tests can be performed by changing the program data given to the programmable device 120.
- the programmable device 120 may be set by program data so as to perform a DC test, an analog test, or the like of the device under test 310.
- the DC test may be a test for measuring a current or voltage supplied to the device under test 310 when a constant voltage or current is applied to the device under test 310. Thereby, the internal resistance or the like at the pin of the device under test 310 can be measured.
- the analog test may be a test for measuring a waveform of a signal output from the device under test 310 when a predetermined analog signal is applied to the device under test 310.
- the programmable device 120 may generate a test signal and measure a response signal in cooperation with another analog circuit.
- the circuit block 110 may include an analog circuit that modulates the amplitude, phase, and the like of a digital signal generated by the programmable device 120.
- the circuit block 110 may include a circuit that converts the response signal of the device under test 310 into a digital signal and inputs the digital signal to the programmable device 120.
- control unit 10 may change program data to be given to the programmable device 120 based on the comparison determination result in the logic comparison unit 124. That is, the control unit 10 may determine the content of the next test to be performed based on the test result of the device under test 310 and provide the programmable device 120 with program data corresponding to the test content. Thereby, various tests can be performed consistently by the single test apparatus 200. That is, during the test of the device under test 310, the functional configuration, application, etc. of the circuit block 110 can be changed in real time for each test item.
- each programmable device 120 may change the logical relationship between the inputs and outputs of its own programmable device 120 based on the determination result of the corresponding device under test 310.
- each programmable device 120 may include a microcomputer that controls the logical relationship between the input and output of the programmable device 120.
- the microcomputer may be provided with a microcode indicating that the functional configuration of the programmable device 120 is changed in accordance with the test result of the corresponding device under test 310 in the initial command from the control unit 10.
- the microcomputer may change the functional configuration of the programmable device 120 based on the self-diagnosis result in each test item started in response to the initial command.
- FIG. 4 is a diagram illustrating another configuration example of the circuit block 110.
- the circuit block 110 of this example includes a plurality of analog circuits in addition to the configuration of the circuit block 110 described with reference to FIG.
- the circuit block 110 of this example includes a level variable circuit 132 and a delay circuit 134 as analog circuits.
- analog circuits may generate analog test signals corresponding to the input / output signals of the programmable device 120.
- the level variable circuit 132 may adjust the signal level of the output logic data of the programmable device 120.
- the signal level may be a concept including both the amplitude and offset (for example, DC level) of the signal.
- the delay circuit 134 may delay the output logic data of the programmable device 120. Characteristics such as an amplification factor and a delay amount in the analog circuit may be controlled by a control signal supplied from the control unit 10.
- an analog signal corresponding to the output logic data of the programmable device 120 can be generated.
- the analog circuit may be provided corresponding to some pins of the programmable device 120.
- the circuit block 110 can input and output both an analog signal and a digital signal.
- the level variable circuit 132 may be provided between the device under test 310 and the input / output circuit 130 that receives a signal from the device under test 310.
- the analog output signal of the device under test 310 can be converted into a signal level corresponding to the characteristics of the programmable device 120. Therefore, the device under test 310 in which analog terminals and digital terminals are mixed can be tested.
- the level variable circuit 132 may be included in the input / output circuit 130.
- some of the input / output circuits 130 may include the level variable circuit 132, and all of the input / output circuits 130 may include the level variable circuit 132.
- FIG. 5 is a diagram illustrating another configuration example of the circuit block 110.
- the circuit block 110 of this example further includes a test circuit 140 that generates or measures an analog signal in addition to the configuration of the circuit block 110 shown in FIG.
- the test circuit 140 is connected to the input / output circuit 130 corresponding to the analog terminal of the device under test 310.
- the programmable device 120 is connected to an input / output circuit 130 corresponding to the digital terminal of the device under test 310.
- the device under test 310 in which analog terminals and digital terminals are mixed can be tested.
- the test circuit 140 and the programmable device 120 may operate in synchronization. These circuits may be provided with a common operation clock from the control unit 10.
- FIG. 6 is a diagram illustrating another configuration example of the circuit block 110.
- the circuit block 110 of this example further includes a plurality of test circuits 140 in addition to the configuration of the circuit block 110 shown in FIG.
- the test circuit 140 of this example may be a circuit that performs the same test as a conventional test circuit.
- the test circuit 140 may be a circuit that performs an analog test, a logic test (function test), an RF test (high frequency test), a memory test, and the like.
- the plurality of test circuits 140 are electrically connected to the common programmable device 120 via the wiring 114.
- the programmable device 120 changes the connection relationship between the plurality of test circuits 140 and the plurality of input / output circuits 130 according to the given program data. By changing the setting of the programmable device 120, the devices under test 310 having different pin arrangements can be tested with the same test apparatus 200.
- FIG. 7 is a diagram showing another configuration example of the test substrate 100. 1 to 6, the example in which the programmable device 120 is provided for each device under test 310 has been described. However, the test substrate 100 of this example is common to a plurality of devices under test 310. The programmable device 120 is provided.
- the programmable device 120 may not be provided.
- the programmable device 120 is provided in a region different from the circuit block 110.
- the programmable device 120 may be provided at the center of the test substrate 100 or may be provided at an end portion of the test substrate 100.
- the programmable device 120 may be provided on the back surface of the test substrate 100.
- one programmable device 120 may be provided for each region obtained by dividing the test substrate 100 into a plurality of regions.
- the programmable device 120 is electrically connected to each circuit block 110 via the wiring 116 and supplies a common signal.
- the programmable device 120 may generate a logical pattern of test signals that the circuit block 110 should generate.
- the signal output from the programmable device 120 can be changed by program data. Thereby, various tests can be performed.
- FIG. 8 is a flowchart showing an example of a method for manufacturing the test substrate 100.
- the programmable device 120, the test circuit 140, and the input / output circuit 130 described with reference to FIGS. 1 to 7 are formed by optical exposure.
- at least a part of the wirings 112, 114, 116 described with reference to FIGS. 1 to 7 is formed by electron beam exposure.
- test resources such as the programmable device 120 by optical exposure using a mask
- a plurality of test substrates 100 having these test resources can be easily manufactured.
- the test substrate corresponding to the type of the device under test 310 can be manufactured by forming the wiring between them with an electron beam.
- the programmable device 120 when the test substrate 100 described with reference to FIG. 6 is manufactured, the programmable device 120, the test circuit 140 that generates an analog test signal, and the plurality of terminals of the device under test 310 are provided.
- a plurality of input / output circuits 130 that are electrically connected to corresponding terminals are formed by optical exposure (S500, S502, S504). These circuits may be formed in any order.
- the manufacturing method since it is not necessary to create a mask for optical exposure for each type of device under test 310, the manufacturing cost can be reduced. Further, the manufacturing period can be shortened as compared with the case where all the circuits of the circuit block 110 are formed by electron beam exposure for each type of device under test 310.
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Abstract
Description
Claims (14)
- 被試験ウエハに形成された複数の被試験デバイスを試験する試験装置であって、
前記被試験ウエハと対向して設けられ、複数の前記被試験デバイスと電気的に接続される試験用基板と、
前記試験用基板に設けられ、与えられるプログラムデータに応じて、入力論理データに対する出力論理データの論理関係が変化するプログラマブルデバイスと、
前記試験用基板において複数の前記被試験デバイスと対応して設けられ、前記プログラマブルデバイスの出力論理データに応じた試験信号を、それぞれ対応する前記被試験デバイスに供給する複数の入出力回路と、
前記試験信号に応じたそれぞれの前記被試験デバイスの動作結果に基づいて、それぞれの前記被試験デバイスの良否を判定する判定部と
を備える試験装置。 - 前記試験用基板において複数の前記被試験デバイスと対応して設けられ、前記プログラマブルデバイスの出力論理データに応じたアナログの前記試験信号を生成する複数のアナログ回路を更に備える
請求項1に記載の試験装置。 - 前記アナログ回路は、前記プログラマブルデバイスの入出力信号の信号レベルを調整するレベル可変回路を有する
請求項2に記載の試験装置。 - 前記アナログ回路は、前記プログラマブルデバイスの入出力信号を遅延させる遅延回路を有する
請求項2または3に記載の試験装置。 - 前記入出力回路は、前記被試験デバイスが出力する応答信号を受け取り、前記応答信号の論理値パターンを前記プログラマブルデバイスに入力し、
前記プログラマブルデバイスは、前記判定部として更に機能する
請求項1から4のいずれかに記載の試験装置。 - 前記プログラマブルデバイスに与える前記プログラムデータを変更するプログラム制御部を更に備える
請求項5に記載の試験装置。 - 前記プログラム制御部は、前記判定部における判定結果に基づいて、前記プログラマブルデバイスに与える前記プログラムデータを変更する
請求項6に記載の試験装置。 - 前記プログラマブルデバイスは、複数の前記被試験デバイスに対して共通に設けられる
請求項1から7のいずれかに記載の試験装置。 - 前記プログラマブルデバイスは、複数の前記被試験デバイスに対応して複数設けられる
請求項1から7のいずれかに記載の試験装置。 - 共通の前記プログラマブルデバイスに電気的に接続される複数の試験回路を更に備え、
前記プログラマブルデバイスは、与えられる前記プログラムデータに応じて、前記試験回路と、前記入出力回路との間の接続関係を変更する
請求項1に記載の試験装置。 - 前記プログラマブルデバイスは、前記判定部における判定結果に基づいて、前記プログラマブルデバイスの入出力間の前記論理関係を変化させる
請求項1に記載の試験装置。 - それぞれの前記プログラマブルデバイスは、対応する前記被試験デバイスの試験結果に基づいて、当該プログラマブルデバイスの入出力間の前記論理関係を変化させるマイクロコンピュータを有する
請求項1に記載の試験装置。 - それぞれの前記マイクロコンピュータは、他の前記プログラマブルデバイスにおける前記マイクロコンピュータとは独立して、自己の前記プログラマブルデバイスの前記論理関係を制御する
請求項12に記載の試験装置。 - 被試験ウエハに形成された複数の被試験デバイスと電気的に接続し、複数の前記被試験デバイスを試験する試験用基板を製造する製造方法であって、
前記試験用基板に、
与えられるプログラムデータに応じたデジタルの試験信号を生成するプログラマブルデバイスと、
アナログの試験信号を生成する試験回路と、
前記被試験デバイスの複数の端子と対応して設けられ、それぞれ対応する前記端子と電気的に接続される複数の入出力回路と
を光学露光により形成し、
前記試験用基板に、前記プログラマブルデバイスおよび前記入出力回路を接続する配線、ならびに、前記試験回路および前記入出力回路を接続する配線の少なくとも一部を、試験すべき前記被試験デバイスの種類に応じて電子ビーム露光により形成する製造方法。
Priority Applications (8)
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KR1020117004021A KR101254280B1 (ko) | 2008-10-14 | 2008-10-14 | 시험 장치 및 제조 방법 |
PCT/JP2008/068603 WO2010044143A1 (ja) | 2008-10-14 | 2008-10-14 | 試験装置および製造方法 |
JP2010533743A JP5475674B2 (ja) | 2008-10-14 | 2008-10-14 | 試験装置 |
TW098134505A TWI405986B (zh) | 2008-10-14 | 2009-10-12 | 測試裝置以及製造方法 |
JP2010533825A JP4704514B2 (ja) | 2008-10-14 | 2009-10-13 | 試験装置 |
PCT/JP2009/005328 WO2010044251A1 (ja) | 2008-10-14 | 2009-10-13 | 試験装置 |
US12/949,718 US20110099443A1 (en) | 2008-10-14 | 2010-11-18 | Test apparatus |
US13/044,320 US8892381B2 (en) | 2008-10-14 | 2011-03-09 | Test apparatus and manufacturing method |
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US13/044,320 Continuation US8892381B2 (en) | 2008-10-14 | 2011-03-09 | Test apparatus and manufacturing method |
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PCT/JP2008/068603 WO2010044143A1 (ja) | 2008-10-14 | 2008-10-14 | 試験装置および製造方法 |
PCT/JP2009/005328 WO2010044251A1 (ja) | 2008-10-14 | 2009-10-13 | 試験装置 |
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JP (1) | JP5475674B2 (ja) |
KR (1) | KR101254280B1 (ja) |
TW (1) | TWI405986B (ja) |
WO (2) | WO2010044143A1 (ja) |
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KR20150021785A (ko) * | 2013-08-21 | 2015-03-03 | 삼성전자주식회사 | 반도체 메모리 테스트 방법 |
US20150153405A1 (en) * | 2013-12-04 | 2015-06-04 | Princeton Technology Corporation | Automatic testing system and method |
CN104678292B (zh) * | 2015-03-09 | 2018-10-09 | 新华三技术有限公司 | 一种复杂可编程逻辑器件cpld测试方法和装置 |
KR102374712B1 (ko) | 2017-07-03 | 2022-03-17 | 삼성전자주식회사 | 신호들을 병합하는 전송 선로를 갖는 테스트 인터페이스 보드, 이를 이용하는 테스트 방법, 및 테스트 시스템 |
RU195541U1 (ru) * | 2019-10-31 | 2020-01-30 | Акционерное общество "Научно-производственное предприятие "Пульсар" | Стенд для испытаний изделий электронной техники |
Citations (1)
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JP2001210685A (ja) * | 1999-11-19 | 2001-08-03 | Hitachi Ltd | テストシステムおよび半導体集積回路装置の製造方法 |
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JP3195790B2 (ja) * | 1990-05-31 | 2001-08-06 | アジレント・テクノロジー株式会社 | 電子部品試験装置 |
US5289116A (en) * | 1990-05-31 | 1994-02-22 | Hewlett Packard Company | Apparatus and method for testing electronic devices |
DE69133311T2 (de) * | 1990-10-15 | 2004-06-24 | Aptix Corp., San Jose | Verbindungssubstrat mit integrierter Schaltung zur programmierbaren Verbindung und Probenuntersuchung |
JP3172003B2 (ja) * | 1992-09-22 | 2001-06-04 | 株式会社東芝 | 集積回路試験装置 |
JPH10239392A (ja) * | 1997-02-28 | 1998-09-11 | Nec Corp | 試験装置 |
US6400173B1 (en) * | 1999-11-19 | 2002-06-04 | Hitachi, Ltd. | Test system and manufacturing of semiconductor device |
US6445208B1 (en) * | 2000-04-06 | 2002-09-03 | Advantest Corp. | Power source current measurement unit for semiconductor test system |
JP2002139551A (ja) | 2000-11-02 | 2002-05-17 | Advantest Corp | 半導体試験装置 |
JP2002184948A (ja) * | 2000-12-12 | 2002-06-28 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
JP2002296329A (ja) * | 2001-03-30 | 2002-10-09 | Agilent Technologies Japan Ltd | 集積回路の試験装置 |
US7313740B2 (en) * | 2002-07-25 | 2007-12-25 | Inapac Technology, Inc. | Internally generating patterns for testing in an integrated circuit device |
EP1662569A4 (de) * | 2003-08-22 | 2010-05-05 | New Ind Res Organization | Schaltung zum feststellen und messen von geräuschen in integrierten halbleiterschaltungen |
US7307433B2 (en) * | 2004-04-21 | 2007-12-11 | Formfactor, Inc. | Intelligent probe card architecture |
US7362089B2 (en) * | 2004-05-21 | 2008-04-22 | Advantest Corporation | Carrier module for adapting non-standard instrument cards to test systems |
WO2006012503A2 (en) * | 2004-07-22 | 2006-02-02 | Auburn University | Automatic analog test & compensation with built-in pattern generator & analyzer |
US7272764B2 (en) * | 2004-11-04 | 2007-09-18 | International Business Machines Corporation | Method, system, and program product for boundary I/O testing employing a logic built-in self-test of an integrated circuit |
US7480882B1 (en) * | 2008-03-16 | 2009-01-20 | International Business Machines Corporation | Measuring and predicting VLSI chip reliability and failure |
JP5208208B2 (ja) * | 2008-05-16 | 2013-06-12 | 株式会社アドバンテスト | 製造方法および試験用ウエハユニット |
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2008
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- 2008-10-14 JP JP2010533743A patent/JP5475674B2/ja active Active
- 2008-10-14 KR KR1020117004021A patent/KR101254280B1/ko active IP Right Grant
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2009
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- 2009-10-13 WO PCT/JP2009/005328 patent/WO2010044251A1/ja active Application Filing
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2010
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2011
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Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001210685A (ja) * | 1999-11-19 | 2001-08-03 | Hitachi Ltd | テストシステムおよび半導体集積回路装置の製造方法 |
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TW201018934A (en) | 2010-05-16 |
US8892381B2 (en) | 2014-11-18 |
US20110099443A1 (en) | 2011-04-28 |
TWI405986B (zh) | 2013-08-21 |
JPWO2010044143A1 (ja) | 2012-03-08 |
JP5475674B2 (ja) | 2014-04-16 |
WO2010044251A1 (ja) | 2010-04-22 |
US20110218752A1 (en) | 2011-09-08 |
KR20110043708A (ko) | 2011-04-27 |
KR101254280B1 (ko) | 2013-04-12 |
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