Classifications

• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/0213—Electrical arrangements not otherwise provided for
  • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
  • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
  • H05K1/0219—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
  • H05K1/0221—Coaxially shielded signal lines comprising a continuous shielding layer partially or wholly surrounding the signal lines
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K9/00—Screening of apparatus or components against electric or magnetic fields
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/03—Use of materials for the substrate
  • H05K1/0393—Flexible materials
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/09—Shape and layout
  • H05K2201/09209—Shape and layout details of conductors
  • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
  • H05K2201/09809—Coaxial layout
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
  • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
  • H05K2203/0703—Plating
  • H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/46—Manufacturing multilayer circuits
  • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
  • Y10T29/00—Metal working
  • Y10T29/49—Method of mechanical manufacture
  • Y10T29/49002—Electrical device making
  • Y10T29/49117—Conductor or circuit manufacturing
  • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
  • Y10T29/00—Metal working
  • Y10T29/49—Method of mechanical manufacture
  • Y10T29/49002—Electrical device making
  • Y10T29/49117—Conductor or circuit manufacturing
  • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
  • Y10T29/49155—Manufacturing circuit on or in base
  • Y10T29/49162—Manufacturing circuit on or in base by using wire as conductive path

Definitions

• This application relates generally to the field of flexible electronic circuits, and more particularly to methods and apparatuses for shielded electronic circuits supported on a flexible member.
• EMI electromagnetic interference
• EMI has many deleterious effects on the operation of mobile communication devices. For example, EMI may cause the distortion of transmitted data and even the complete loss of data.
• Coaxial cables comprise a pair of conductors disposed around a common axis.
• a first conductor is positioned along the central axis of the cable and carries the transmitted signal.
• a second conductor connected to an electrical ground, is cylindrically disposed around the first conductor by an insulative or dielectric material.
• the apparatuses and methods disclosed herein for a shielded flexible circuit advantageously enable high data transmission rates along closely spaced conductors on a flexible circuit.
• the apparatuses and methods are suitable for use in flip phones and slider phones. Additionally, they are capable of shielding conductive traces against EMI when data transmission rates exceed 1 GHz.
• cell phones are able to transmit data at rates needed for streaming video and other high-rate applications without substantial signal loss or distortion.
• shielded flexible circuits are capable of transmitting data at rates between 2 and 4 GHz.
• an apparatus comprises a flexible support member; a first conductor and a second conductor in contact with said flexible support member; said first and second conductors electrically insulated from the other; a first conductive material co-axially disposed around said first conductor, said first conductive material electrically insulated from said first conductor; and a second conductive material co-axially disposed around said second conductor, said second conductive material electrically insulated from said second conductor.
• a method of shielding a flexible circuit comprises forming a first conductor and a second conductor from a first conductive material adhered to a top side of a flexible support member, said first and second conductors electrically insulated from one another; forming a second conductive material co-axially disposed around said first conductor, said second conductive material electrically insulated from said first conductor; forming a third conductive material co-axially disposed around said second conductor, said third conductive material electrically insulated from said second conductor.
• FIG. IA is a top perspective view of one embodiment of a flexible circuit with one conductive layer.
• FIG. 1 B is a top perspective view of the flexible circuit of FlG. IA with etched traces.
• FIG. 1C is a top perspective view of the flexible circuit of FIG. IB with a dielectric layer insulating the etched traces.
• FIG. ID is a top perspective view of the flexible circuit of FIG. 1C with channels exposing alternate grounded traces on a top side of the flexible circuit.
• FIG. IE is a top perspective view of the flexible circuit of FIG. ID with a conductive shielding layer on the top side in communication with the alternate grounded traces.
• FIG. IF is a top perspective view of the flexible circuit of FIG. IE with channels exposing the alternate grounded traces on a bottom side of the flexible circuit.
• FIG. IG is a top perspective view of the flexible circuit of FIG. IF with a conductive shielding layer on the bottom side in communication with the alternate grounded traces.
• FIG. IH is a cross-sectional view of the single copper layer shielded flexible circuit of FIG. IG with alternate grounded traces.
• FIG. 2 is a process diagram illustrating one embodiment of a method for manufacturing the single copper layer shielded flexible circuit of FIG. IH with alternate grounded traces.
• FIG. 3 is a cross-sectional view of one embodiment of a single copper layer flexible circuit with all traces shielded.
• FIG. 4 is a process diagram illustrating one embodiment of the method for manufacturing a single copper layer flexible circuit of FIG. 3 with all traces shielded.
• FIG. 5A is a top perspective view of one embodiment of a flexible circuit with two conductive layers.
• FIG. 5B is a top perspective view of the flexible circuit of FIG. 5A with etched traces.
• FIG. 5C is a top perspective view of the flexible circuit of FIG. 5B with a dielectric layer on a top side of the flexible circuit.
• FIG. 5D is a top perspective view of the flexible circuit of FIG. 5C with channels between the etched traces on the top side.
• FIG. 5E is a top perspective view of the flexible circuit of FIG. 5D with a conductive shielding layer on the top side in communication with a copper layer on a bottom side.
• FIG. 5F is a cross-sectional view of the two copper layer shielded flexible circuit of FlG. 5E.
• FIG. 6 is a process diagram illustrating one embodiment of a method for manufacturing the two copper layer shielded flexible circuit of FIG. 5F.
• FIG. 7 A is a top perspective view of one embodiment of a flexible circuit with two conductive layers.
• FIG. 7B is a top perspective view of the flexible circuit of FIG. 7A with etched traces.
• FIG. 7C is a top perspective view of the flexible circuit of FIG. 7B with a dielectric layer and a conductive shielding layer on a top side.
• FIG. 7D is a top perspective view of the flexible circuit of FIG. 7C with channels between the etched traces
• FIG. 7E is a top perspective view of the flexible circuit of FIG. 7D with plated channels.
• FIG. 7F is a top perspective view of the flexible circuit of FIG. 7E with a dielectric layer on the top side.
• FIG. 7G is a cross-sectional view of the three layer shielded flexible circuit of FIG. 7F.
• FIG. 8 is a process diagram illustrating one embodiment of the method for manufacturing the three copper layer shielded flexible circuit of FlG. 7G.
• FlG. 9A illustrates one type of a mobile communication device with a hinge.
• FIG. 9B illustrates a flexible circuit that provides electrical communication between the screen of the mobile communication device and the body of the mobile communication device.
• the apparatuses and methods disclosed herein pertain to shielding active signal traces on a flexible support mer ⁇ ber.
• a shielded flexible circuit is constructed using a base flexible material that comprises a flexible non-conductive substrate on a top side and a copper layer on a bottom side.
• alternate traces are grounded to the copper layer and used to shield the traces between them.
• embodiments of this type will hereinafter be referred to as a "Single-Copper Layer Shielding With Alternate Grounded Traces" embodiment.
• a shielded flexible circuit is constructed using a base material that comprises a flexible substrate on a top side and a copper layer on a bottom side.
• substantially every trace may be used as an active signal trace.
• embodiments of this type will hereinafter be referred to as a "Single Copper Layer With All Traces Shielded" embodiment.
• a shielded flexible circuit is constructed using a base material that comprises a flexible substrate with a copper layer on a top side and a copper layer on a bottom side of the flexible substrate.
• a base material that comprises a flexible substrate with a copper layer on a top side and a copper layer on a bottom side of the flexible substrate.
• a shielded flexible circuit is constructed using a base material that comprises a flexible substrate with a copper layer on a top side and a copper layer on a bottom side of the flexible substrate.
• copper may be used to shield the copper traces on all sides.
• embodiments of this type will hereinafter be referred to as a "Three Copper Layer" embodiment.
• Fig. IH illustrates one embodiment of a single copper layer shielding with alternate grounded traces.
• Fig. 2 illustrates a process diagram, including steps 501-508, for manufacturing a shielded flexible circuit
• Figs. IA-H illustrate the structure of the shielded flexible circuit as each step of the method is practiced.
• the figures associated with the structure of the circuit at each step of the method will be expressly referenced.
• each step of the method of Fig. 2 will be referred to using the reference numbers of Fig. 2 only.
• the method for manufacturing a shielded flexible circuit begins with the flexible support member 100 illustrated in Fig. IA.
• the flexible support member 100 is comprised of two layers, a flexible substrate 102 and a base conductive layer 101. It is known to one with ordinary skill in the art that the flexible support member 100 is commercially manufactured and readily available for purchase. In other embodiments, the method may begin by applying the base conductive layer 101 to the flexible substrate 102 using plating, lamination, vapor deposition or other known techniques.
• the flexible substrate 102 is made of a polyimide material.
• the flexible substrate 102 may be any of the commonly used “Flex” or printed circuit board (“PCB”) materials such as FR4, PET/PEN, Teflon / High speed materials, and so forth.
• PCB printed circuit board
• the base conductive layer 101 is a copper layer.
• the base conductive layer 101 may be any electrically conductive material such as gold or silver. Though it is contemplated that other materials may be used, the base conductive layer 101 will be referred to herein as a copper base conductive layer 101.
• Traditional PCB manufacturing methods may be used to create tooling holes or vias in the flexible support member 100.
• Fig. IB illustrates the copper traces 11 1 , 112, 113, 114 formed after completion of step 501.
• the copper traces 1 1 1 , 112, 113, 1 14 are printed and etched using photolithography techniques well known to those skilled in the art.
• One photolithography technique requires laminating a dry film etch resist to the base conductive layer 101 using a hot roll laminator or a vacuum lamination process.
• Many dry film etch resist layers are commercially available and are produced by companies such as Dupont®.
• the thickness of the dry film etch resist layer is between 0.0007" to 0.0020".
• a circuit image is then transferred to the etch resist layer using Ultraviolet ("UV") energy and an appropriate tool such as a photo tool, a Mylar® film, or a Mylai ⁇ 8> glass.
• UV Ultraviolet
• an appropriate tool such as a photo tool, a Mylar® film, or a Mylai ⁇ 8> glass.
• the areas of etch resist which were not exposed to UV energy are then chemically washed off of the panel.
• a solution containing Potassium Carbonate may be used to wash off the undeveloped (that is, not exposed to UV energy) etch resist.
• the copper which is exposed through the developed etch resist is chemically removed.
• an aqueous wash of cupric chloride etchant may be used to remove the copper.
• other types of copper etchants may be used, such as alkaline-based etchants and ferric chloride-based etchants.
• Fig. 1C illustrates the insulative or dielectric layer 121 applied to the top side of the flexible circuit 100 with the traces 111, 112, 1 13, 1 14.
• This layer is formed by step 502 to insulate the etched traces 111, 112, 113, 1 14 from the grounded shielding that is created later in the method so as to prevent an electrical short and to protect the traces 11 1, 112, 1 13, 114 from contamination.
• Any number of dielectric or non-conductive insulative materials may be used.
• the dielectric layer 121 is comprised of a polyirnide film with a thermal set adhesive on one side of the film.
• the polyimide film may range in thickness from 0.0005 " to 0.0010", and the thermal set adhesive may range in thickness from 0.0005" to 0.0015".
• the film 121 is placed on top of the etched traces 111, 112, 1 13, 1 14 with the adhesive layer contacting the etched traces 1 11, 112, 1 13, 114. Then, using an autoclave or a vacuum press, the film is laminated to the flexible circuit 100. For example, lamination parameters such as 210 psi at 385 degrees Fahrenheit for 60 minutes may be used. It is recognized that other known techniques may be used to adhere the dielectric layer 121 to the flexible circuit 100.
• Fig. ID illustrates the channels 131, 133 in the dielectric layer 121 created by step 503.
• the channels 131 , 133 are created in locations corresponding to alternate traces 1 1 1, 1 13 and form discontinuities that will later form the shielding for the trace(s) 1 12 between them.
• the channels 131, 133 expose the alternate grounded traces 1 1 1, 1 13 along the length of each trace by removing the dielectric layer 121 above them.
• the channels are created using laser ablation techniques. In other embodiments, other processing techniques, such as plasma etching and chemical milling, may be used.
• channels may be created in locations corresponding to more or less than every other trace.
• the traces between the created channels are shielded.
• the exposed alternate grounded traces 1 1 1, 1 13 are metalized to protect the traces 1 1 1 , 1 13 from oxidation.
• a Nickel and Gold compound may be used to metalize the traces 1 11, 1 13.
• Figs. IE and IF illustrate a conductive shielding layer 141 and a dielectric layer 171 formed on the top side of the flexible circuit 100 by steps 504 and 505.
• the conductive layer 141 is applied to the flexible circuit 100 such that it is in electrical communication with the alternate grounded traces 111, 1 13.
• the conductive layer 141 may be comprised of any conductive material capable of adhering to the alternate grounded traces 111, 1 13 and the dielectric layer 121. Suitable conductive layer 141 materials include, but are not limited to, a silver based film and silver ink.
• the conductive layer 141 may be applied to the flexible circuit 100 using techniques similar to those used for adhering the dielectric layer 121 to the flexible circuit 100 (for example, lamination).
• a dielectric layer 171 is applied to the flexible circuit 100 such that it is on top of the conductive layer 141. Techniques such as lamination may be used to adhere the dielectric layer 171 to the conductive layer 141.
• a suitable dielectric layer 171 material includes, but is not limited to, the material used for dielectric layer 121.
• the conductive layer 141 and the dielectric layer 171 may be adhered to the flexible circuit 100 separately, as described above, or concurrently (that is, steps 504 and 505 may be performed as one step).
• concurrent application of the conductive layer 141 and the dielectric layer 171 may be performed using a pre-made material comprising a conductive layer and a dielectric layer. Examples of such materials can be found in Tatsuta's® PC series of materials. These materials comprise a conductive layer of silver foil, sandwiched between a conductive adhesive layer and a dielectric layer. The material is placed on the flexible circuit 100 such that the conductive adhesive is in contact with the dielectric layer 121. Then, the material may be laminated or otherwise adhered to the flexible circuit 100.
• Fig. IF illustrates channels 151 , 152 formed by step 506 in the flexible substrate 102, on the bottom side of the flexible circuit 100, below the alternate grounded traces 1 1 1 , 1 13.
• the channels 151 , 152 may be created using techniques similar to those employed in step 503 (for example, laser ablation).
• the channels are created in the flexible substrate 102 such that the alternate grounded traces 1 1 1 , 1 13 are exposed along the length of the trace.
• the exposed copper traces 1 1 1 , 1 13 are metalized using a Nickel/Gold compound in order to prevent oxidation.
• Fig. IG illustrates the conductive shielding layer 161 applied by step 507 to the side of the flexible circuit 100 below the flexible substrate 102.
• This conductive shielding layer 161 is applied such that it is in electrical communication with the alternate grounded traces 1 1 1 , 1 13.
• the conductive shielding layer 161 may be laminated to the flexible circuit 100 and further, may be comprised of any conductive material such as copper or silver.
• Fig. IH illustrates a dielectric layer 172 applied by step 508 to the conductive shielding layer 161.
• This dielectric layer 172 shields the exposed conductive shielding layer from electrical interference and contamination.
• the dielectric layer 172 may be adhered to the flexible circuit 100 using techniques such as lamination and may be comprised of materials similar to those used in step 502 (for example, a polyimide film).
• the conductive shielding layer 161 and the dielectric layer 172 may be applied to the flexible circuit 100 in one step using materials such as those included in the Tatsuta® PC series.
• the center copper trace 1 12 is shielded on all sides. It is first shielded by non-conductive dielectric materials and then the non-conductive materials are surrounded by conductive materials.
• the trace 112 is electrically insulated from the ground plane 1 1 1, 1 13, 141 on the top and sides by dielectric layer 121 and electrically insulated from the ground plane 161 on the bottom by the flexible substrate 102.
• the conductive shielding comprises the conductive layer 141 on the top side of the trace 1 12, the conductive layer 161 on the bottom side of the trace 1 12, and the alternate grounded traces 1 1 1 and 1 13 on the sides of the trace 112.
• dielectric layers 171 and 172 are not required to shield the circuit from EMI. In some embodiments, neither or only one of the layers 171, 172 may be employed.
• Fig. 3 illustrates one embodiment of a single copper layer with all traces shielded.
• Fig. 4 illustrates a process diagram, including steps 601-608, for one method of manufacturing the shielded flexible circuit 900 shown in Figure 3. As described herein, the steps of the method of Fig. 4 will be referred to using the reference numbers provided in Fig. 4.
• the apparatus and method for manufacturing the apparatus of Figs. 3 and 4 share characteristics with the embodiment depicted in Figs. IA-H and Fig. 2. That is, many of the possible materials and techniques suggested and/or employed with respect the single copper layer shielding with alternate grounded traces embodiments may be used in connection with the single copper layer with all traces shielded embodiments. However, differences between the two sets of embodiments are noted below.
• every trace 1 1 1, 112 need not be shielded. Rather, with these embodiments, it may be possible to shield every trace 1 1 1 , 112.
• the method for manufacturing a shielded flexible circuit 900 begins with a flexible support member such as the member 100 depicted in Fig. IA.
• a flexible support member such as the member 100 depicted in Fig. IA.
• active signal traces 1 11, 1 12 are formed from the base conductive layer 101 using print and etch techniques 601.
• a dielectric layer 121 is then applied to the top of the traces 111, 1 12 so as to electrically insulate the traces 1 1 1 , 1 12 from the conductive portion of the shielding 141 that is applied in step 604.
• channels 182, 383, 184 are created between the active signal traces 1 1 1, 1 12.
• the channels 182, 183, 184 may be created using laser ablation techniques to remove portions of the dielectric layer 121 located between the traces 1 1 1 , 112. In the embodiment depicted in Fig. 3, the traces 1 1 1 , 1 12 are not exposed to the channels.
• a conductive shielded layer 141 is placed on top of the dielectric layer 121 and in the channels 182, 183, 184 in step 604.
• the conductive shielding layer 141 is adhered 604 to the top side of the flexible circuit 900 such that it is in contact with the flexible substrate 102.
• an insulative layer 171 is adhered 605 to the top of the conductive shielding layer. It is recognized that in addition to performing steps 604 and 605 sequentially steps 604 and 605 may be performed as one step using a Tatsuta® PC series material.
• a second set of channels 185, 186, 187 are created 606 on the bottom side of the flexible circuit 900.
• the channels 1 85, 186, 187 are located between the traces 1 1 1 , 1 12 and positioned such that they expose the conductive shielding layer 141 located between the first set of channels 182, 183, 184.
• the second set of channels 185, 186, 187 may be created by employing laser ablation techniques to remove portions of the flexible substrate 102 in these locations.
• a conductive shielded layer 161 is then adhered in step 607 to the bottom side of the flexible circuit 900 using, for example, lamination techniques.
• This conductive shielding layer 161 is applied in the channels 185, 186, 187 and is in electrical communication with conductive shielding layer 141.
• a dielectric layer 199 may be adhered in step 608 to the conductive shielding layer 161 also using lamination techniques. As stated with respect to steps 604 and 605, it is recognized that steps 607 and 608 may be performed sequentially or as one step.
• step 606 of the method laser ablating channels 185, 186, 187 on the bottom side of the flexible circuit 900 may be omitted. Omitting step 606 requires that in step 603, laser ablation of channels 182, 183, 184 on the top side of the flexible support member, both the portions of the dielectric layer 121 and the polyimide layer 102 located between the traces 111 , 1 12 be removed.
• the traces 1 11, 112 are each shielded in 360 degrees, first by a dielectric shielding and next by a conductive shielding.
• Each trace 1 11 , 1 12 is insulated in all directions from the conductive shielding material and the other traces 1 1 1, 1 12.
• Dielectric layer 121 electrically insulates the top and sides of the traces 1 1 1, 1 12 from the ground plane 182, and the flexible substrate 102 electrically insulates the bottom of the traces 1 1 1 , 1 12 from the ground plane 161. Accordingly, each trace 11 1 , 1 12 is surrounded by grounded, conductive shielding materials.
• Conductive layer 141 provides conductive shielding on the top and sides of the traces 111, 112 and the bottom conductive layer 161 provides conductive shielding on the bottom of the traces 1 1 1, 112, 113. rv. "TWO Copper Layer" Embodiments
• Fig. 5F illustrates one embodiment of a two copper layer shielded flexible circuit.
• Fig. 6 illustrates a process diagram, including steps 701-706, for manufacturing the shielded flexible circuit of FIG. 5F, and Figs. 5A-F illustrate the structure of the shielded flexible circuit as each step of the method is practiced.
• the figures associated with the structure of the circuit at each step of the method will be expressly referenced.
• each step of the process diagram of Fig. 6 will be referred to using the reference numbers of Fig. 6.
• the method for manufacturing a shielded flexible circuit begins with the flexible support member 200 illustrated in Fig. 5A.
• the flexible support member 200 is comprised of three layers, a flexible substrate 202 sandwiched between a top conductive layer 203 and a bottom conductive layer 201. It is known to one with ordinary skill in the art that flexible support member 200 is commercially manufactured and readily available for purchase.
• the method may begin by applying the top and bottom base conductive layers 201, 203 to the flexible substrate 202 using plating, lamination, vapor deposition or other known techniques. Though the embodiments described herein are not limited to a top and bottom conductive layer 201 , 203 comprised of copper, the embodiment depicted utilizes copper top and bottom conductive layers 201, 203.
• Fig. 5B illustrates the traces 211, 212, 213, 214 after they have been printed and etched in step 701 from the top copper layer 203.
• traces 21 1 , 212, 213, 214 are not in electrical communication with one another because the design requirements of the illustrated embodiment requires that the traces 211 , 212, 213, 214 be electrically isolated from one another.
• Fig. 5C illustrates an insulative or dielectric layer 221 applied in step 702 to the top side of the flexible circuit 200.
• the dielectric layer 221 is adhered to the flexible substrate 202 and the traces 21 1 , 212, 213, 214.
• Fig. 5D illustrates channels 231 , 232, 233, 234 formed in step 703 between the active signal traces 211 , 212, 213, 214.
• the channels 231, 232, 233, 234 are created by employing laser ablation or other known techniques to remove portions of the dielectric layer 221 and the flexible substrate 202 located between the traces 21 1 , 212, 213, 214.
• the channels 231, 232, 233, 234 expose the top portion of the bottom copper layer 201 but do not expose the traces 211 , 212, 2] 3, 214 (that is, the traces 21 1 , 212, 213, 214 remain insulated).
• Fig. 5E illustrates a conductive shielded layer 241 applied in step 704 to the top side of the flexible circuit 200.
• the conductive shielding layer 241 is applied to the flexible circuit 240 such that it is in the channels 231 , 232, 233, 234 and is in electrical communication with the bottom conductive layer 201.
• the conductive shielding layer 241 is a silver filled ink.
• Dupont's® CB208 product is a silver ink that is commercially available and known to those skilled in the art.
• the silver ink is screen printed onto the surface of the dielectric layer 221 that was previously laser processed to expose the bottom conductive layer 201.
• other conductive materials with the requisite flow characteristics may be used.
• 5F illustrates insulative or dielectric layers 251 , 252 applied in steps 705 and 706 to the top and bottom sides of the flexible circuit 200.
• a dielectric film 251 , 252 is laminated to the flexible circuit 200.
• the dielectric layers 251 , 252 may serve to protect the flexible circuit 250 from external shorting.
• step 704 is carried out by laminating or otherwise adhering a conductive film to the dielectric layer and the channels 231, 232, 233, 234.
• an insulative layer 252 may be then adhered to the top of the conductive shielding layer 251 in order to prevent external shorting.
• the conductive shielding layer 241 and the dielectric layer 252 are applied concurrently to the flexible circuit 250 by adhering materials such as those in the Tatsuta® PC series.
• each trace 21 1 , 212, 213 is shielded in 360 degrees.
• Each trace 21 1 , 212, 213 is insulated in all directions from the conductive shielding material and the other traces 21 1 , 212, 213.
• Dielectric layer 221 electrically insulates the top and sides of the traces 21 1 from the grounded plane 241, 212, 213, and the flexible substrate 202 electrically insulates the bottom of the traces 21 1 , 212, 213 from the grounded plane 201 . Accordingly, each trace 21 1 , 212, 213 is surrounded by grounded shielding materials.
• Conductive layer 241 provides conductive shielding on the top and sides of the traces 21 1 , 212, 213, and the bottom conductive layer 201 provides conductive shielding on the bottom of the traces 21 1, 212, 213.
• Fig. 7G illustrates one embodiment of a three copper layer shielded flexible circuit.
• Fig. 8 illustrates a process diagram, including steps 801-808, for one embodiment of a method for manufacturing a shielded flexible circuit, and Figs. 7A-G illustrate the structure of the shielded flexible circuit as each step of the method is practiced.
• the figures associated with the structure of the circuit at each step of the method will be expressly referenced.
• each step of the process diagram of Fig. 8 will be referred to using the reference numbers of Fig. 8 only.
• the method for manufacturing a shielded flexible circuit begins with the flexible support member 300 illustrated in Fig. 7A.
• the flexible support member 300 is comprised of three layers, a flexible substrate 302 sandwiched between a top conductive layer 303 and a bottom conductive layer 301. It is known to one with ordinary skill in the art that flexible support member 300 is commercially manufactured and readily available for purchase.
• the method may begin by applying the top and bottom base conductive layer to the flexible substrate using plating, lamination, vapor deposition or other known techniques.
• the top and bottom conductive layers may comprise any conductive material such as copper, silver, or gold.
• Fig. 7B depicts the traces 311, 312, 313, 314 used to carry electrical signals after they have been printed and etched in step 801.
• the traces 31 1, 312, 313, 314 are etched from the top conductive layer 303.
• Fig. 7C depicts the flexible circuit 300 after steps 802 and 803 are complete.
• Step 802 requires applying a dielectric material 321 to the top side of the flexible circuit 300.
• the dielectric layer 322 may be comprised of any of the electrically insulative materials disclosed above and may be adhered to the flexible circuit using any of the techniques described above (for example, lamination).
• Step 803 requires applying a conductive shielding layer 322 on top of the dielectric layer 321.
• the conductive shielding layer 322 is a copper foil. The copper foil is adhered to the flexible circuit 300 using lamination techniques or other techniques known in the art.
• steps 802 and 803 can be carried out simultaneously by using a material comprised of a conductive layer and a dielectric layer. The material is adhered to the flexible circuit 300 with the dielectric layer in physical contact with the traces 311, 312, 313, 314.
• steps 802 and 803 can be carried out simultaneously by using a conductive material which adheres to the flexible circuit 300 via a dielectric adhesive.
• the conductive material is a copper foil
• dielectric foil bonding adhesives such as ADH/PI/ADH may be used.
• Fig. 7D illustrates channels 331, 332, 333, 334 formed between the traces 311, 312, 313, 314 by step 804.
• the channels 331, 332, 333, 334 are created by removing portions of the flexible substrate 302, the dielectric layer 321, and the conductive layer 322 located between the traces 31 1, 312, 313, 314.
• the channels 331, 332, 333, 334 are sufficiently deep so as to expose the bottom conductive layer 301.
• techniques such as laser ablation may be employed to create the channels 331 , 332, 333, 334.
• Fig. 7E illustrates the copper plating 341, 342, 343, 344 applied to the channels 331, 332, 333, 334 in step 805.
• the copper plating provides an electrical connection between the conductive shielding layer 322 and the bottom conductive layer 301.
• conventional processes such as the SHADOW® process may be used.
• SHADOW® is a graphite based direct metallization process that facilitates the copper plating process.
• techniques and materials other than those used in copper plating are used to electrically connect the conductive shielding layer 322 and the bottom conductive layer 301.
• Such techniques and materials may include applying silver ink using screening techniques.
• step 806 unwanted copper is removed from the flexible circuit 300 using commonly known techniques such as photolithography in step 806. For example, copper that was inadvertently plated on the top of conductive shielding layer 322 is removed in step 806.
• Fig. 7F illustrates a dielectric layer 351 applied to the top of the conductive shielding layer 322 and the plated channels 341, 342, 343, 344 in step 807.
• Fig. 7G illustrates a dielectric layer 352 applied to the bottom of the bottom conductive layer 301 in step 808.
• the dielectric layers 351, 352 may protect the flexible circuit 350 from external shorting. However, as noted above, some embodiments employ only one or no dielectric layers 351, 352.
• each trace 31 1, 312, 313 is insulated in all directions from the conductive shielding material and the other traces 31 1, 312, 313.
• Dielectric layer 321 electrically insulates the top and sides of the traces 31 1, 312, 313 from the grounded plane 322, 341, 342, 343, 344, and the flexible substrate 302 electrically insulates the bottom of the traces 31 1 , 312, 313 from the grounded plane set. Accordingly, each trace 311, 312, 313 is surrounded by grounded shielding materials.
• Conductive layer 322 is the top grounded shielding material, and the bottom conductive layer 301 is the bottom shielding material.
• the plated channels 341 , 342, 343, 344 shield the sides of the traces 311, 312, 313 and electrically connect conductive layer 322 and the bottom conductive layer 301.
• FIG. 9A depicts one type of flip phone 400.
• a typical flip phone 400 comprises a body 420, a screen 430, and an antenna 410.
• the body 420 is mechanically connected to the screen 430 via a hinge 450.
• the body 420 comprises circuitry which processes data transmitted and received by the antenna 410. Accordingly, images corresponding to the transmitted and received data are displayed on the screen 430.
• Fig. 9B depicts the flip phone 400 after the body 420 has been physically separated from the screen 430.
• a shielded flexible circuit 440 according to the apparatuses and methods for manufacturing disclosed herein provides an electrical connection between the body 420 and the screen 430.
• the shielded flexible circuit 440 must be mechanically flexible along the hinge's 450 axis of rotation. Such flexibility is required in order for the flip phone 400 to open and close.
• the traces on the shielded flexible circuit 440 must be capable of shielding each trace from EMI created by external sources and the other traces on the flexible circuit 440. Therefore, the shielded flexibly circuit 440 advantageously provides an electrical connection between the body 420 and the screen 430 in flip phone 400 applications.
• one embodiment of the shielded flexible circuit 440 can accommodate data transmission rates between 2 to 4 GHz without substantial signal loss or distortion due to EMI.
• the distance between the centers of proximate traces may be as small as 20 thousandths of an inch.

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Physics & Mathematics (AREA)
• Electromagnetism (AREA)
• Structure Of Printed Boards (AREA)
• Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
• Insulated Conductors (AREA)
• Communication Cables (AREA)
• Manufacturing Of Printed Circuit Boards (AREA)

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• 2007
  • 2007-04-24 US US11/739,550 patent/US7645941B2/en active Active
  • 2007-04-26 WO PCT/US2007/010009 patent/WO2007133405A2/en not_active Ceased
  • 2007-04-26 JP JP2009509606A patent/JP2009535848A/ja active Pending
  • 2007-04-26 KR KR1020087028721A patent/KR20090008405A/ko not_active Withdrawn
• 2009
  • 2009-12-04 US US12/631,532 patent/US20100071935A1/en not_active Abandoned

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