Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
  • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B81—MICROSTRUCTURAL TECHNOLOGY
  • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
  • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
  • B81C1/00865—Multistep processes for the separation of wafers into individual elements
  • B81C1/00888—Multistep processes involving only mechanical separation, e.g. grooving followed by cleaving
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
  • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support

Definitions

• the present invention relates to a semiconductor chip cutting method and a semiconductor chip, for example, a semiconductor chip cutting method and a semiconductor chip for cutting a semiconductor chip having a structure on a surface from a wafer.
• FIG. 4A and FIG. 4B are cross-sectional views schematically showing the chip structure of a GaAsFET described in JP-A-6-112236.
• a GaAs substrate 23 is formed on the heat radiation electrodes 21, 22, and a gate electrode 24, a source electrode 25, and a drain electrode 26 are formed on the GaAs substrate 23.
• Via holes 27 are also formed in the GaAs substrate 23 by etching on the substrate surface side, and cavities 28 are formed in the heat dissipation electrode 21 by etching corresponding to the via holes 27.
• the chip is divided by cutting the heat radiation electrode 22 sandwiched between the via hole 27 and the cavity 28 with the blade 30 of the dicer.
• Japanese Patent Application Laid-Open No. 2000-346648 discloses a method of manufacturing a regular octagonal plate-shaped semiconductor device by previously removing a shape corresponding to the shape of an excess portion of a wafer, and cutting along vertical and horizontal dicing lines. It is written on the screen.
• FIG. 5A and FIG. 5B are diagrams showing a method for manufacturing a semiconductor device described in Japanese Patent Laid-Open No. 2000-346648, and show the upper surface of a wafer.
• a regular octagonal device in which a through hole 30 is formed is cut out by dicing.
• vertical and horizontal dicing lines 31 and 32 are set on the wafer.
• the diamond-shaped portion 33 corresponding to the shape of the surplus portion at the time of dicing is previously removed by blasting or ultrasonic waves.
• a regular octagonal device by dicing with a blade in the direction of the arrow as shown in Figure 5B 35 is formed.
• the shape is limited to a semiconductor chip having a rectangular shape, and when the wafer is cut, chips are generated and an impact is applied to the semiconductor chip.
• semiconductor devices such as MEMS (Micro Electoro Mechanical System)
• thin membrane structures and comb electrodes are often formed on the chip surface. When impact is applied to thin membrane structures when cutting wafers. Otherwise, the semiconductor chip may be damaged. In the case of a comb electrode, the electrode may collapse due to impact during cutting.
• an object of the present invention is to prevent each chip from being scattered when a semiconductor chip having an arbitrary shape is cut out from the wafer, to reduce generation of chips, and to give an impact to the semiconductor chip. There is no semiconductor chip cutting method and semiconductor chip.
• the present invention relates to a semiconductor chip cutting method for cutting a semiconductor chip from a semiconductor wafer, the step of forming a structure on one surface of the semiconductor substrate of the semiconductor wafer, and the structure on the structure side of the semiconductor substrate. Forming a holding film for holding the semiconductor chip on the surface of the semiconductor substrate, and etching the cutting line surrounding the structure from the other surface side of the semiconductor substrate to cut out the semiconductor chip.
• the step of forming the holding film includes a step of attaching a transport member on the holding film after forming the holding film on the surface of the structure. By sticking the transfer member, the mechanical strength of the entire structure of the semiconductor chip can be increased, and the handling of the semiconductor wafer becomes easy.
• the method includes a step of fixing the other surface side of the semiconductor substrate structure to the holding member after etching the cut line.
• the method further includes a step of removing the semiconductor chip force holding film fixed to the holding member. Even if the holding film is removed, the semiconductor chip is fixed by the holding member, so that the semiconductor chip does not fall apart.
• the cut line draws an arbitrary line. It is possible to cut semiconductor chips of various shapes. Specifically, the cut line draws a circle.
• the semiconductor chip extends from the other surface side of the semiconductor substrate to the structure on the one surface side, and has a through hole that forms a part of the structure. And a step of dry etching the holes simultaneously. Etching at the same time can simplify the process.
• the step of cutting out the semiconductor chip includes a step of applying a resist to the other surface side of the semiconductor substrate excluding a region corresponding to the through hole and the cutting line and performing dry etching.
• the cutting line can be formed into an arbitrary shape, so that not only rectangular chips but also various shapes such as circular chips can be cut out.
• the structure includes at least one of a movable part and a thin film.
• a semiconductor chip of the structure can be configured.
• a semiconductor chip is formed by any one of the processes.
• the structure can be protected by the holding film, and the dicing process can be eliminated by etching the cut line, so that the process can be simplified. Further, since the dicing process can be omitted, the structure of the semiconductor chip is broken. In addition, since the structure can be held by the holding film, it is possible to prevent the semiconductor chips from being scattered after the cutting line etching, and the generation of chips can be extremely reduced. Because it depends It becomes possible to cut into shapes.
• FIG. 2A is an enlarged view of the semiconductor chip shown in FIG.
• FIG. 2B is a cross-sectional view taken along line ⁇ - ⁇ in FIG. 2A.
• FIG. 3A is a diagram for explaining a process of a semiconductor chip cutting method according to an embodiment of the present invention.
• FIG. 3B is a diagram for explaining a process of the semiconductor chip cutting-out method according to the embodiment of the present invention.
• FIG. 3C is a diagram for explaining a process of the semiconductor chip cutting method according to the embodiment of the present invention.
• FIG. 3D is a diagram for explaining a process of the semiconductor chip cutting method according to the embodiment of the present invention.
• FIG. 3E is a diagram for explaining a process of the semiconductor chip cutting-out method in one embodiment of the present invention.
• FIG. 3F A diagram for explaining a process of the semiconductor chip cutting-out method in one embodiment of the present invention.
• FIG. 3G is a diagram for explaining a process of the semiconductor chip cutting-out method in one embodiment of the present invention.
• FIG. 3H is a diagram for describing a process of a semiconductor chip cutting-out method in one embodiment of the present invention.
• FIG. 4A is a cross-sectional view schematically showing a GaAsFET for explaining a conventional chip structure cutting method.
• FIG. 4B is a cross-sectional view schematically showing a GaAsFET for explaining a conventional chip structure cutting method.
• FIG. 5A is a diagram showing a top surface of a semiconductor device wafer in order to explain a conventional semiconductor device wafer dicing method.
• FIG. 5B is a diagram showing a top surface of a semiconductor device wafer for explaining a conventional semiconductor device wafer dicing method.
• FIG. 1 is a plan view showing a semiconductor wafer on which a semiconductor chip to be cut out by the semiconductor chip cutting method of one embodiment of the present invention is formed
• FIG. 2A is a semiconductor chip shown in FIG. 2B is an enlarged plan view
• FIG. 2B is a cross-sectional view taken along line ⁇ - ⁇ in FIG. 2A.
• a disk-shaped semiconductor wafer 1 has a large number of semiconductor chips 2 formed thereon.
• the semiconductor chip 2 has a disk shape as shown in FIG. 2A, and a scribe region 3 as a cutting line is formed so as to surround the periphery thereof.
• the semiconductor chip 2 has a structure in which a through hole 5 is formed in a silicon substrate 4 and a structure material 6 is formed so as to cover the opening of the through hole 5.
• the surroundings of the structural material 6 are supported by the silicon substrate 4, but the structure material 6 may be cantilevered by the silicon substrate 4.
• the semiconductor chip 2 is, for example, an acceleration sensor or an acoustic sensor, and the structural material 6 may be a thin film or a movable part.
• the semiconductor chip 2 is held on a holding material 12 such as a tape.
• the through hole 5 is etched into the silicon substrate 4 and simultaneously etched along the scribe region 3 to form a chip, thereby simplifying the process, and other than the rectangular shape.
• the semiconductor chip 2 having various shapes can be cut out, the dicing process is avoided, and the structural material 6 is less damaged.
• the present invention is directed to a method for cutting out a semiconductor chip having a structure having a through hole 5, etching is performed along the scribe region 3 even for a semiconductor chip having no through hole. It can also be applied to things. Also, the etching for forming the through hole 5 and the etching along the scribe region 3 may be performed in separate processes!
• FIGS. 3A to 3H are diagrams for explaining each step of the semiconductor chip cutting method according to the embodiment of the present invention.
• the structure material 6 is formed on the surface (one surface) of the silicon substrate 4 by, for example, thermal diffusion or CVD using SiO, SiN, PolySi or the like.
• the structure material 6 may be an active layer of an SOI wafer. Subsequently, the structural material 6 is Processing is performed by otolitho, etching, etc., for example, a membrane is formed. At this time, the region 7 corresponding to the scribe region 3 is also etched.
• a holding film 8 is formed so as to cover the silicon substrate 4 and the structural material 6.
• This holding film 8 has mechanical strength to give a chip holding effect, and in particular, considering that the protective region can be a membrane shape, it has a ductility that easily absorbs a light impact. Is preferred. Further, it preferably has a characteristic that it can be easily selectively removed from other materials. That is, it is required that the holding material 12 such as a tape described later is not peeled off when the holding film 8 that cannot be removed at the time of resist removal is removed. In addition, the thermal conductivity is high so that the etching characteristics are maintained when performing the Si dry etching described later. Especially when considering the case where the chip is a thin film, it is a low stress film so that distortion due to stress can be suppressed. preferable. In addition, it is desirable that film formation and film thickness control be easy in consideration of process convenience.
• a metal material such as Ti, Cu, Ni, or A1 as the holding film 8 because the thermal conductivity is good.
• resin materials such as polyimide and resist, and UV tapes such as dicing-extended tape can also be used.
• a resin material it is necessary to use a different type from the etching mask resist and to have a selection ratio.
• the holding film 8 is a metal film, it can be formed by sputtering, CVD, plating, or the like.
• a thickness of 1 ⁇ m is sufficient.
• the through pattern corresponding to the through hole 5 and the pattern corresponding to the scribe region 3 are removed, and the resist 9 is patterned. Then, the silicon substrate 4 is attached to a carrier wafer 11 as a conveying member using the bonding material 10 with the surface side of the silicon substrate 4 facing down. Since the scribe region 3 can draw an arbitrary line, the present invention can be applied to cut out not only a rectangular semiconductor chip but also a circular semiconductor chip.
• a penetration process is performed by Si dry etching using the resist 9 as a mask material to form the through hole 5 shown in FIG. 2B.
• the semiconductor chip 2 can be cut out simultaneously.
• the holding film 8 keeps each semiconductor chip 2 connected to the outer periphery of the wafer.
• the semiconductor chip 2 is peeled off from the carrier wafer 11 shown in FIG. 3D, and the resist 9 is removed. As shown in FIG. 3E, the through-hole 5 side of the semiconductor chip 1 is turned down and fixed on the holding material 12 shown in FIG. 3F.
• the holding material 12 is a force that uses a tape or the like. A material that is resistant to the holding film removing material that removes the holding film 8 in the process of FIG.
• the semiconductor chip 2 shown in FIG. 2B can be formed.
• the retention film removing material for example, when Ti is used as the retention film 8, dilute hydrofluoric acid is used.
• the semiconductor chip 2 Since the semiconductor chip 2 is fixed by the holding material 12 such as a tape, the semiconductor chip 2 can be separated from the holding material 12 as shown in FIG. , Can be easily removed individually as needed.
• the scribe region 3 is also etched at the same time, so that the process can be simplified.
• the dicing process can be eliminated, the chip structure is damaged and the generation of chips can be reduced.
• the holding film 8 it is possible to prevent the chips from being separated.
• the shape of the scribe region 3 depends on the photo process of the through etching, it can be cut into various shapes such as a circle other than a rectangle.
• the semiconductor chip cutting method of the present invention can be used for scribing a semiconductor chip having a thin membrane structure on the surface.

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• Engineering & Computer Science (AREA)
• Manufacturing & Machinery (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Power Engineering (AREA)
• Dicing (AREA)
• Mechanical Treatment Of Semiconductor (AREA)
• Micromachines (AREA)

Applications Claiming Priority (2)

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Citations (6)

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• 2005
  • 2005-10-03 JP JP2005290229A patent/JP2007103595A/ja active Pending
• 2006
  • 2006-10-02 WO PCT/JP2006/319667 patent/WO2007040190A1/ja active Application Filing
  • 2006-10-03 TW TW095136785A patent/TW200731373A/zh unknown

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