WO2007040190A1 - Semiconductor chip cutting method and semiconductor chip - Google Patents

Semiconductor chip cutting method and semiconductor chip Download PDF

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Publication number
WO2007040190A1
WO2007040190A1 PCT/JP2006/319667 JP2006319667W WO2007040190A1 WO 2007040190 A1 WO2007040190 A1 WO 2007040190A1 JP 2006319667 W JP2006319667 W JP 2006319667W WO 2007040190 A1 WO2007040190 A1 WO 2007040190A1
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Prior art keywords
semiconductor chip
cutting
semiconductor
cutting method
holding
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PCT/JP2006/319667
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French (fr)
Japanese (ja)
Inventor
Tomofumi Kiyomoto
Katsuyuki Ono
Muneo Harada
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Tokyo Electron Limited
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Publication of WO2007040190A1 publication Critical patent/WO2007040190A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00865—Multistep processes for the separation of wafers into individual elements
    • B81C1/00888—Multistep processes involving only mechanical separation, e.g. grooving followed by cleaving
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support

Definitions

  • the present invention relates to a semiconductor chip cutting method and a semiconductor chip, for example, a semiconductor chip cutting method and a semiconductor chip for cutting a semiconductor chip having a structure on a surface from a wafer.
  • FIG. 4A and FIG. 4B are cross-sectional views schematically showing the chip structure of a GaAsFET described in JP-A-6-112236.
  • a GaAs substrate 23 is formed on the heat radiation electrodes 21, 22, and a gate electrode 24, a source electrode 25, and a drain electrode 26 are formed on the GaAs substrate 23.
  • Via holes 27 are also formed in the GaAs substrate 23 by etching on the substrate surface side, and cavities 28 are formed in the heat dissipation electrode 21 by etching corresponding to the via holes 27.
  • the chip is divided by cutting the heat radiation electrode 22 sandwiched between the via hole 27 and the cavity 28 with the blade 30 of the dicer.
  • Japanese Patent Application Laid-Open No. 2000-346648 discloses a method of manufacturing a regular octagonal plate-shaped semiconductor device by previously removing a shape corresponding to the shape of an excess portion of a wafer, and cutting along vertical and horizontal dicing lines. It is written on the screen.
  • FIG. 5A and FIG. 5B are diagrams showing a method for manufacturing a semiconductor device described in Japanese Patent Laid-Open No. 2000-346648, and show the upper surface of a wafer.
  • a regular octagonal device in which a through hole 30 is formed is cut out by dicing.
  • vertical and horizontal dicing lines 31 and 32 are set on the wafer.
  • the diamond-shaped portion 33 corresponding to the shape of the surplus portion at the time of dicing is previously removed by blasting or ultrasonic waves.
  • a regular octagonal device by dicing with a blade in the direction of the arrow as shown in Figure 5B 35 is formed.
  • the shape is limited to a semiconductor chip having a rectangular shape, and when the wafer is cut, chips are generated and an impact is applied to the semiconductor chip.
  • semiconductor devices such as MEMS (Micro Electoro Mechanical System)
  • thin membrane structures and comb electrodes are often formed on the chip surface. When impact is applied to thin membrane structures when cutting wafers. Otherwise, the semiconductor chip may be damaged. In the case of a comb electrode, the electrode may collapse due to impact during cutting.
  • an object of the present invention is to prevent each chip from being scattered when a semiconductor chip having an arbitrary shape is cut out from the wafer, to reduce generation of chips, and to give an impact to the semiconductor chip. There is no semiconductor chip cutting method and semiconductor chip.
  • the present invention relates to a semiconductor chip cutting method for cutting a semiconductor chip from a semiconductor wafer, the step of forming a structure on one surface of the semiconductor substrate of the semiconductor wafer, and the structure on the structure side of the semiconductor substrate. Forming a holding film for holding the semiconductor chip on the surface of the semiconductor substrate, and etching the cutting line surrounding the structure from the other surface side of the semiconductor substrate to cut out the semiconductor chip.
  • the step of forming the holding film includes a step of attaching a transport member on the holding film after forming the holding film on the surface of the structure. By sticking the transfer member, the mechanical strength of the entire structure of the semiconductor chip can be increased, and the handling of the semiconductor wafer becomes easy.
  • the method includes a step of fixing the other surface side of the semiconductor substrate structure to the holding member after etching the cut line.
  • the method further includes a step of removing the semiconductor chip force holding film fixed to the holding member. Even if the holding film is removed, the semiconductor chip is fixed by the holding member, so that the semiconductor chip does not fall apart.
  • the cut line draws an arbitrary line. It is possible to cut semiconductor chips of various shapes. Specifically, the cut line draws a circle.
  • the semiconductor chip extends from the other surface side of the semiconductor substrate to the structure on the one surface side, and has a through hole that forms a part of the structure. And a step of dry etching the holes simultaneously. Etching at the same time can simplify the process.
  • the step of cutting out the semiconductor chip includes a step of applying a resist to the other surface side of the semiconductor substrate excluding a region corresponding to the through hole and the cutting line and performing dry etching.
  • the cutting line can be formed into an arbitrary shape, so that not only rectangular chips but also various shapes such as circular chips can be cut out.
  • the structure includes at least one of a movable part and a thin film.
  • a semiconductor chip of the structure can be configured.
  • a semiconductor chip is formed by any one of the processes.
  • the structure can be protected by the holding film, and the dicing process can be eliminated by etching the cut line, so that the process can be simplified. Further, since the dicing process can be omitted, the structure of the semiconductor chip is broken. In addition, since the structure can be held by the holding film, it is possible to prevent the semiconductor chips from being scattered after the cutting line etching, and the generation of chips can be extremely reduced. Because it depends It becomes possible to cut into shapes.
  • FIG. 2A is an enlarged view of the semiconductor chip shown in FIG.
  • FIG. 2B is a cross-sectional view taken along line ⁇ - ⁇ in FIG. 2A.
  • FIG. 3A is a diagram for explaining a process of a semiconductor chip cutting method according to an embodiment of the present invention.
  • FIG. 3B is a diagram for explaining a process of the semiconductor chip cutting-out method according to the embodiment of the present invention.
  • FIG. 3C is a diagram for explaining a process of the semiconductor chip cutting method according to the embodiment of the present invention.
  • FIG. 3D is a diagram for explaining a process of the semiconductor chip cutting method according to the embodiment of the present invention.
  • FIG. 3E is a diagram for explaining a process of the semiconductor chip cutting-out method in one embodiment of the present invention.
  • FIG. 3F A diagram for explaining a process of the semiconductor chip cutting-out method in one embodiment of the present invention.
  • FIG. 3G is a diagram for explaining a process of the semiconductor chip cutting-out method in one embodiment of the present invention.
  • FIG. 3H is a diagram for describing a process of a semiconductor chip cutting-out method in one embodiment of the present invention.
  • FIG. 4A is a cross-sectional view schematically showing a GaAsFET for explaining a conventional chip structure cutting method.
  • FIG. 4B is a cross-sectional view schematically showing a GaAsFET for explaining a conventional chip structure cutting method.
  • FIG. 5A is a diagram showing a top surface of a semiconductor device wafer in order to explain a conventional semiconductor device wafer dicing method.
  • FIG. 5B is a diagram showing a top surface of a semiconductor device wafer for explaining a conventional semiconductor device wafer dicing method.
  • FIG. 1 is a plan view showing a semiconductor wafer on which a semiconductor chip to be cut out by the semiconductor chip cutting method of one embodiment of the present invention is formed
  • FIG. 2A is a semiconductor chip shown in FIG. 2B is an enlarged plan view
  • FIG. 2B is a cross-sectional view taken along line ⁇ - ⁇ in FIG. 2A.
  • a disk-shaped semiconductor wafer 1 has a large number of semiconductor chips 2 formed thereon.
  • the semiconductor chip 2 has a disk shape as shown in FIG. 2A, and a scribe region 3 as a cutting line is formed so as to surround the periphery thereof.
  • the semiconductor chip 2 has a structure in which a through hole 5 is formed in a silicon substrate 4 and a structure material 6 is formed so as to cover the opening of the through hole 5.
  • the surroundings of the structural material 6 are supported by the silicon substrate 4, but the structure material 6 may be cantilevered by the silicon substrate 4.
  • the semiconductor chip 2 is, for example, an acceleration sensor or an acoustic sensor, and the structural material 6 may be a thin film or a movable part.
  • the semiconductor chip 2 is held on a holding material 12 such as a tape.
  • the through hole 5 is etched into the silicon substrate 4 and simultaneously etched along the scribe region 3 to form a chip, thereby simplifying the process, and other than the rectangular shape.
  • the semiconductor chip 2 having various shapes can be cut out, the dicing process is avoided, and the structural material 6 is less damaged.
  • the present invention is directed to a method for cutting out a semiconductor chip having a structure having a through hole 5, etching is performed along the scribe region 3 even for a semiconductor chip having no through hole. It can also be applied to things. Also, the etching for forming the through hole 5 and the etching along the scribe region 3 may be performed in separate processes!
  • FIGS. 3A to 3H are diagrams for explaining each step of the semiconductor chip cutting method according to the embodiment of the present invention.
  • the structure material 6 is formed on the surface (one surface) of the silicon substrate 4 by, for example, thermal diffusion or CVD using SiO, SiN, PolySi or the like.
  • the structure material 6 may be an active layer of an SOI wafer. Subsequently, the structural material 6 is Processing is performed by otolitho, etching, etc., for example, a membrane is formed. At this time, the region 7 corresponding to the scribe region 3 is also etched.
  • a holding film 8 is formed so as to cover the silicon substrate 4 and the structural material 6.
  • This holding film 8 has mechanical strength to give a chip holding effect, and in particular, considering that the protective region can be a membrane shape, it has a ductility that easily absorbs a light impact. Is preferred. Further, it preferably has a characteristic that it can be easily selectively removed from other materials. That is, it is required that the holding material 12 such as a tape described later is not peeled off when the holding film 8 that cannot be removed at the time of resist removal is removed. In addition, the thermal conductivity is high so that the etching characteristics are maintained when performing the Si dry etching described later. Especially when considering the case where the chip is a thin film, it is a low stress film so that distortion due to stress can be suppressed. preferable. In addition, it is desirable that film formation and film thickness control be easy in consideration of process convenience.
  • a metal material such as Ti, Cu, Ni, or A1 as the holding film 8 because the thermal conductivity is good.
  • resin materials such as polyimide and resist, and UV tapes such as dicing-extended tape can also be used.
  • a resin material it is necessary to use a different type from the etching mask resist and to have a selection ratio.
  • the holding film 8 is a metal film, it can be formed by sputtering, CVD, plating, or the like.
  • a thickness of 1 ⁇ m is sufficient.
  • the through pattern corresponding to the through hole 5 and the pattern corresponding to the scribe region 3 are removed, and the resist 9 is patterned. Then, the silicon substrate 4 is attached to a carrier wafer 11 as a conveying member using the bonding material 10 with the surface side of the silicon substrate 4 facing down. Since the scribe region 3 can draw an arbitrary line, the present invention can be applied to cut out not only a rectangular semiconductor chip but also a circular semiconductor chip.
  • a penetration process is performed by Si dry etching using the resist 9 as a mask material to form the through hole 5 shown in FIG. 2B.
  • the semiconductor chip 2 can be cut out simultaneously.
  • the holding film 8 keeps each semiconductor chip 2 connected to the outer periphery of the wafer.
  • the semiconductor chip 2 is peeled off from the carrier wafer 11 shown in FIG. 3D, and the resist 9 is removed. As shown in FIG. 3E, the through-hole 5 side of the semiconductor chip 1 is turned down and fixed on the holding material 12 shown in FIG. 3F.
  • the holding material 12 is a force that uses a tape or the like. A material that is resistant to the holding film removing material that removes the holding film 8 in the process of FIG.
  • the semiconductor chip 2 shown in FIG. 2B can be formed.
  • the retention film removing material for example, when Ti is used as the retention film 8, dilute hydrofluoric acid is used.
  • the semiconductor chip 2 Since the semiconductor chip 2 is fixed by the holding material 12 such as a tape, the semiconductor chip 2 can be separated from the holding material 12 as shown in FIG. , Can be easily removed individually as needed.
  • the scribe region 3 is also etched at the same time, so that the process can be simplified.
  • the dicing process can be eliminated, the chip structure is damaged and the generation of chips can be reduced.
  • the holding film 8 it is possible to prevent the chips from being separated.
  • the shape of the scribe region 3 depends on the photo process of the through etching, it can be cut into various shapes such as a circle other than a rectangle.
  • the semiconductor chip cutting method of the present invention can be used for scribing a semiconductor chip having a thin membrane structure on the surface.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Dicing (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Micromachines (AREA)

Abstract

A structure material (6) is formed on a silicon substrate (4), and a holding film (8) is formed on a side of the structure material (6) on the silicon substrate (4). A through hole (5) reaching the structure material (6) on one side of the silicon substrate (4) from the other side and a scribe region (3) surrounding the circumference of the structure material (6) are etched at the same time to cut out a semiconductor chip (2).

Description

明 細 書  Specification
半導体チップ切出し方法および半導体チップ  Semiconductor chip cutting method and semiconductor chip
技術分野  Technical field
[0001] この発明は、半導体チップ切出し方法および半導体チップに関し、例えば、表面に 構造体を有する半導体チップをウェハから切出す半導体チップ切出し方法および半 導体チップに関する。  The present invention relates to a semiconductor chip cutting method and a semiconductor chip, for example, a semiconductor chip cutting method and a semiconductor chip for cutting a semiconductor chip having a structure on a surface from a wafer.
背景技術  Background art
[0002] 半導体ウェハから半導体チップを切出すときは、ブレードによるダイシング工程によ つて行われている。また、エッチング工程とブレードによるダイシング工程とを併用し た例が特開平 6 - 112236号公報に記載されて 、る。  When a semiconductor chip is cut out from a semiconductor wafer, it is performed by a dicing process using a blade. An example in which an etching step and a blade dicing step are used together is described in Japanese Patent Laid-Open No. 6-112236.
[0003] 図 4Aおよび図 4Bは、特開平 6— 112236号公報に記載された GaAsFETのチッ プ構造を模式的に示す断面図である。図 4Aにおいて、放熱電極 21, 22上に GaAs 基板 23が形成されており、 GaAs基板 23上にゲート電極 24,ソース電極 25, ドレイ ン電極 26が形成されている。 GaAs基板 23には基板表面側力もバイァホール 27が エッチングによって形成されており、放熱電極 21にはノィァホール 27に対応して空 洞 28がエッチングにより形成されている。図 4Bに示すように、バイァホール 27と空洞 28とに挟まれた放熱電極 22をダイサ一の刃 30でカッティングすることにより、チップ を分割する。  FIG. 4A and FIG. 4B are cross-sectional views schematically showing the chip structure of a GaAsFET described in JP-A-6-112236. In FIG. 4A, a GaAs substrate 23 is formed on the heat radiation electrodes 21, 22, and a gate electrode 24, a source electrode 25, and a drain electrode 26 are formed on the GaAs substrate 23. Via holes 27 are also formed in the GaAs substrate 23 by etching on the substrate surface side, and cavities 28 are formed in the heat dissipation electrode 21 by etching corresponding to the via holes 27. As shown in FIG. 4B, the chip is divided by cutting the heat radiation electrode 22 sandwiched between the via hole 27 and the cavity 28 with the blade 30 of the dicer.
[0004] また、特開 2000— 346648号公報には、ウェハの余剰部形状に相当する形状を 予め除去しておき、縦横のダイシングラインによる切断で正八角形板状の半導体デ バイスを製造する方法にっ ヽて記載されて ヽる。  [0004] Also, Japanese Patent Application Laid-Open No. 2000-346648 discloses a method of manufacturing a regular octagonal plate-shaped semiconductor device by previously removing a shape corresponding to the shape of an excess portion of a wafer, and cutting along vertical and horizontal dicing lines. It is written on the screen.
[0005] 図 5Aおよび図 5Bは、特開 2000— 346648号公報に記載された半導体デバイス の製造方法を示す図であり、ウェハの上面を示している。この例は貫通穴 30が形成 された正八角形のデバイスをダイシングにより切出すものであり、図 5Aにおいてゥヱ ハ上には縦横のダイシングライン 31, 32が設定されている。ダイシング時の余剰部 形状に相当する菱形部分 33を予めブラストや超音波などにより貫通除去しておく。 図 5Bに示すようにブレードで矢印方向にダイシングすることで、正八角形のデバイス 35を形成する。 FIG. 5A and FIG. 5B are diagrams showing a method for manufacturing a semiconductor device described in Japanese Patent Laid-Open No. 2000-346648, and show the upper surface of a wafer. In this example, a regular octagonal device in which a through hole 30 is formed is cut out by dicing. In FIG. 5A, vertical and horizontal dicing lines 31 and 32 are set on the wafer. The diamond-shaped portion 33 corresponding to the shape of the surplus portion at the time of dicing is previously removed by blasting or ultrasonic waves. A regular octagonal device by dicing with a blade in the direction of the arrow as shown in Figure 5B 35 is formed.
[0006] ブレードによるダイシング工程では、形状が矩形状の半導体チップに限られており 、し力もウェハを切断するときに切屑が発生するば力りでなぐ半導体チップに衝撃が 加わってしまう。半導体チップとして、 MEMS (Micro Electoro Mechanical Sy stem)などでは、薄 ヽメンプレン構造体や櫛歯電極がチップ表面に形成されることが 多ぐウェハを切断するときの衝撃が薄いメンブレン構造体に加わると、半導体チップ が破損してしまうおそれがある。また、櫛歯電極の場合には、切断時の衝撃で、電極 が崩れたりすることがある。  [0006] In the dicing process using a blade, the shape is limited to a semiconductor chip having a rectangular shape, and when the wafer is cut, chips are generated and an impact is applied to the semiconductor chip. In semiconductor devices such as MEMS (Micro Electoro Mechanical System), thin membrane structures and comb electrodes are often formed on the chip surface. When impact is applied to thin membrane structures when cutting wafers. Otherwise, the semiconductor chip may be damaged. In the case of a comb electrode, the electrode may collapse due to impact during cutting.
[0007] 特開平 6— 112236号公報および特開 2000— 346648号公報に記載された方法 においても、一部不要な部分をエッチングやその他の方法により予め削除して 、るも のの、これらの工程は補助的なものに過ぎず、最終的にはブレードによるダイシング を用いており、切屑が発生し、半導体チップに衝撃が加わることに変わりはない。しか も、ブレードによるダイシングでは矩形形状の半導体チップを切出すことができても、 外形が曲線を持つような半導体チップに対応することができな!/、。  [0007] In the methods described in JP-A-6-112236 and JP-A-2000-346648, some unnecessary portions are deleted in advance by etching or other methods. The process is only an auxiliary process, and finally dicing with a blade is used, chips are generated, and an impact is still applied to the semiconductor chip. However, even if a rectangular semiconductor chip can be cut out by blade dicing, it cannot handle a semiconductor chip with a curved outer shape! /.
発明の開示  Disclosure of the invention
[0008] そこで、この発明の目的は、任意の形状の半導体チップをウェハから切出すときに 、各チップがバラけないようにし、しかも切屑の発生を少なくし、半導体チップに衝撃 を与えることがない半導体チップ切出し方法および半導体チップを提供することであ る。  [0008] Therefore, an object of the present invention is to prevent each chip from being scattered when a semiconductor chip having an arbitrary shape is cut out from the wafer, to reduce generation of chips, and to give an impact to the semiconductor chip. There is no semiconductor chip cutting method and semiconductor chip.
[0009] この発明は、半導体チップを半導体ウェハから切出す半導体チップ切出し方法で あって、半導体ウェハの半導体基板の一方面上に構造体を形成する工程と、半導体 基板の構造体側に、構造体の表面に半導体チップを保持する保持膜を形成するェ 程と、半導体基板の他方面側から構造体の周囲を囲む切出しラインをエッチングして 半導体チップを切出す工程とを備える。  [0009] The present invention relates to a semiconductor chip cutting method for cutting a semiconductor chip from a semiconductor wafer, the step of forming a structure on one surface of the semiconductor substrate of the semiconductor wafer, and the structure on the structure side of the semiconductor substrate. Forming a holding film for holding the semiconductor chip on the surface of the semiconductor substrate, and etching the cutting line surrounding the structure from the other surface side of the semiconductor substrate to cut out the semiconductor chip.
[0010] 切出しラインをエッチングして半導体チップを切出すようにしたので、切出しライン 形成時に切屑が発生しないかあるいは発生してもわずかであり、切出し時の衝撃も 低減できる。また、保持膜により半導体チップを保持できるので、切出しラインをエツ チングした後、半導体チップがバラけるのを防ぐことができる。 [0011] 好ましくは、保持膜を形成する工程は、保持膜を構造体表面に形成した後、保持 膜上に搬送部材を貼り付ける工程を含む。搬送部材を貼り付けることで半導体チップ の全体構造の機械的強度を高めることができ、半導体ウェハのハンドリングが容易に なる。 [0010] Since the semiconductor chip is cut out by etching the cutting line, no or no chips are generated when the cutting line is formed, and the impact during cutting can be reduced. In addition, since the semiconductor chip can be held by the holding film, it is possible to prevent the semiconductor chip from being scattered after the cutting line is etched. [0011] Preferably, the step of forming the holding film includes a step of attaching a transport member on the holding film after forming the holding film on the surface of the structure. By sticking the transfer member, the mechanical strength of the entire structure of the semiconductor chip can be increased, and the handling of the semiconductor wafer becomes easy.
[0012] さらに、切出しラインをエッチング後、半導体基板の構造体とは他方面側を保持部 材に固定する工程を含む。  [0012] Further, the method includes a step of fixing the other surface side of the semiconductor substrate structure to the holding member after etching the cut line.
[0013] さらに、保持部材に固定した半導体チップ力 保持膜を除去する工程を含む。保持 膜を除去しても半導体チップを保持部材で固定しているので、半導体チップがばら ばらになつてしまうことがない。 [0013] The method further includes a step of removing the semiconductor chip force holding film fixed to the holding member. Even if the holding film is removed, the semiconductor chip is fixed by the holding member, so that the semiconductor chip does not fall apart.
[0014] 切出しラインは任意のラインを描く。多様な形状の半導体チップを切出すのが可能 になる。具体的には切出しラインは円形を描く。 [0014] The cut line draws an arbitrary line. It is possible to cut semiconductor chips of various shapes. Specifically, the cut line draws a circle.
[0015] 半導体チップは、半導体基板の他方面側から一方面側の構造体に至り、構造体の 一部を成す貫通穴を有していて、半導体チップを切出す工程は、切出しラインと貫通 穴とを同時にドライエッチングする工程を含む。同時にエッチングすることで工程を簡 略化できる。 [0015] The semiconductor chip extends from the other surface side of the semiconductor substrate to the structure on the one surface side, and has a through hole that forms a part of the structure. And a step of dry etching the holes simultaneously. Etching at the same time can simplify the process.
[0016] 好ましくは、半導体チップを切出す工程は、貫通穴と切出しラインに対応する領域 を除く半導体基板の他方面側にレジストを塗布し、ドライエッチングする工程を含む。 これにより切出しラインを任意の形状にできるので、矩形チップに限らず円形チップ などの多様な形状の切出しも可能になる。  [0016] Preferably, the step of cutting out the semiconductor chip includes a step of applying a resist to the other surface side of the semiconductor substrate excluding a region corresponding to the through hole and the cutting line and performing dry etching. As a result, the cutting line can be formed into an arbitrary shape, so that not only rectangular chips but also various shapes such as circular chips can be cut out.
[0017] 好ましくは、構造体は、少なくとも可動部および薄膜のいずれかを有する。これによ り構造体の半導体チップを構成できる。 [0017] Preferably, the structure includes at least one of a movable part and a thin film. Thereby, a semiconductor chip of the structure can be configured.
[0018] この発明の他の局面は、いずれかの各工程により半導体チップを形成する。 In another aspect of the present invention, a semiconductor chip is formed by any one of the processes.
[0019] この発明によれば、保持膜により構造体を保護でき、切出しラインをエッチングする ことにより、ダイシング工程を不要にできるので、工程の簡略ィ匕が可能になる。また、 ダイシング工程を不要にできるので、半導体チップの構造体破損が起こりに《なる。 さらに、保持膜により構造体を保持できるので切出しラインエッチング後、半導体チッ プがバラけるのを防ぐことができ、また切屑の発生を極めて少なくでき、半導体チップ の切出しラインの形状は、フォト工程に依存するため、矩形以外の円形などの多様な 形状に切出すのが可能になる。 According to the present invention, the structure can be protected by the holding film, and the dicing process can be eliminated by etching the cut line, so that the process can be simplified. Further, since the dicing process can be omitted, the structure of the semiconductor chip is broken. In addition, since the structure can be held by the holding film, it is possible to prevent the semiconductor chips from being scattered after the cutting line etching, and the generation of chips can be extremely reduced. Because it depends It becomes possible to cut into shapes.
図面の簡単な説明 Brief Description of Drawings
圆 1]この発明の一実施形態の半導体チップ切出し方法によって切出される半導体 チップが形成されたウェハを示す平面図である。 1] A plan view showing a wafer on which a semiconductor chip cut out by a semiconductor chip cutting method according to an embodiment of the present invention is formed.
[図 2A]図 1に示す半導体チップを拡大して示した図である。  FIG. 2A is an enlarged view of the semiconductor chip shown in FIG.
[図 2B]図 2Aの線 ΠΒ— ΠΒに沿う断面図である。 2B is a cross-sectional view taken along line ΠΒ-ΠΒ in FIG. 2A.
圆 3A]この発明の一実施形態における半導体チップ切出し方法の工程を説明する ための図である。 FIG. 3A is a diagram for explaining a process of a semiconductor chip cutting method according to an embodiment of the present invention.
圆 3B]この発明の一実施形態における半導体チップ切出し方法の工程を説明する ための図である。 FIG. 3B is a diagram for explaining a process of the semiconductor chip cutting-out method according to the embodiment of the present invention.
圆 3C]この発明の一実施形態における半導体チップ切出し方法の工程を説明する ための図である。 FIG. 3C is a diagram for explaining a process of the semiconductor chip cutting method according to the embodiment of the present invention.
圆 3D]この発明の一実施形態における半導体チップ切出し方法の工程を説明する ための図である。 FIG. 3D is a diagram for explaining a process of the semiconductor chip cutting method according to the embodiment of the present invention.
圆 3E]この発明の一実施形態における半導体チップ切出し方法の工程を説明する ための図である。 FIG. 3E is a diagram for explaining a process of the semiconductor chip cutting-out method in one embodiment of the present invention.
圆 3F]この発明の一実施形態における半導体チップ切出し方法の工程を説明する ための図である。 FIG. 3F] A diagram for explaining a process of the semiconductor chip cutting-out method in one embodiment of the present invention.
圆 3G]この発明の一実施形態における半導体チップ切出し方法の工程を説明する ための図である。 FIG. 3G is a diagram for explaining a process of the semiconductor chip cutting-out method in one embodiment of the present invention.
圆 3H]この発明の一実施形態における半導体チップ切出し方法の工程を説明する ための図である。 [3H] FIG. 3H is a diagram for describing a process of a semiconductor chip cutting-out method in one embodiment of the present invention.
[図 4A]従来のチップ構造カッティング方法を説明するために GaAsFETを模式的に 示した断面図である。  FIG. 4A is a cross-sectional view schematically showing a GaAsFET for explaining a conventional chip structure cutting method.
[図 4B]従来のチップ構造カッティング方法を説明するために GaAsFETを模式的に 示した断面図である。  FIG. 4B is a cross-sectional view schematically showing a GaAsFET for explaining a conventional chip structure cutting method.
圆 5A]従来の半導体デバイスウェハダイシング方法を説明するために半導体デバイ スのウェハの上面を示した図である。 [図 5B]従来の半導体デバイスウェハダイシング方法を説明するために半導体デバイ スのウェハの上面を示した図である。 [5A] FIG. 5A is a diagram showing a top surface of a semiconductor device wafer in order to explain a conventional semiconductor device wafer dicing method. FIG. 5B is a diagram showing a top surface of a semiconductor device wafer for explaining a conventional semiconductor device wafer dicing method.
発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION
[0021] 図 1はこの発明の一実施形態の半導体チップ切出し方法によって切出される半導 体チップが形成された半導体ウェハを示す平面図であり、図 2Aは、図 1に示す半導 体チップを拡大して示した平面図であり、図 2Bは図 2Aの線 ΠΒ— ΠΒに沿う断面図 である。 FIG. 1 is a plan view showing a semiconductor wafer on which a semiconductor chip to be cut out by the semiconductor chip cutting method of one embodiment of the present invention is formed, and FIG. 2A is a semiconductor chip shown in FIG. 2B is an enlarged plan view, and FIG. 2B is a cross-sectional view taken along line ΠΒ-ΠΒ in FIG. 2A.
[0022] 図 1において、円盤状の半導体ウェハ 1には、多数の半導体チップ 2が形成されて いる。半導体チップ 2は図 2Aに示すように円盤状であって、その周囲を囲むように切 出しラインとしてのスクライブ領域 3が形成されている。半導体チップ 2は、図 2Bに示 すようにシリコン基板 4に貫通穴 5が形成され、貫通穴 5の開口部を覆うように構造体 材料 6が形成されて構成されている。構造体材料 6は周囲がシリコン基板 4によって 支持されているが、シリコン基板 4に片持ち支持されるものであってもよい。半導体チ ップ 2は、例えば加速度センサや音響センサなどであって、構造体材料 6は薄膜や可 動部などを構成して ヽる。半導体チップ 2はテープなどの保持材 12上に保持されて いる。  In FIG. 1, a disk-shaped semiconductor wafer 1 has a large number of semiconductor chips 2 formed thereon. The semiconductor chip 2 has a disk shape as shown in FIG. 2A, and a scribe region 3 as a cutting line is formed so as to surround the periphery thereof. As shown in FIG. 2B, the semiconductor chip 2 has a structure in which a through hole 5 is formed in a silicon substrate 4 and a structure material 6 is formed so as to cover the opening of the through hole 5. The surroundings of the structural material 6 are supported by the silicon substrate 4, but the structure material 6 may be cantilevered by the silicon substrate 4. The semiconductor chip 2 is, for example, an acceleration sensor or an acoustic sensor, and the structural material 6 may be a thin film or a movable part. The semiconductor chip 2 is held on a holding material 12 such as a tape.
[0023] この発明の一実施形態では、シリコン基板 4に貫通穴 5をエッチングすると同時にス クライブ領域 3に沿ってエッチングしてチップィ匕することで、工程の簡略ィ匕を図り、矩 形以外の多様な形状の半導体チップ 2の切出しを可能にし、ダイシング工程を回避 して構造体材料 6の破損を少なくする。  In one embodiment of the present invention, the through hole 5 is etched into the silicon substrate 4 and simultaneously etched along the scribe region 3 to form a chip, thereby simplifying the process, and other than the rectangular shape. The semiconductor chip 2 having various shapes can be cut out, the dicing process is avoided, and the structural material 6 is less damaged.
[0024] なお、この発明は、貫通穴 5を有する構造体の半導体チップの切出し方法に向けら れるが、特に貫通穴を有しない半導体チップであっても、スクライブ領域 3に沿ってェ ツチングするものにも適用できる。また、貫通穴 5を形成するエッチングと、スクライブ 領域 3に沿うエッチングは、別工程で行ってもよ!、。  Although the present invention is directed to a method for cutting out a semiconductor chip having a structure having a through hole 5, etching is performed along the scribe region 3 even for a semiconductor chip having no through hole. It can also be applied to things. Also, the etching for forming the through hole 5 and the etching along the scribe region 3 may be performed in separate processes!
[0025] 図 3A〜図 3Hは、この発明の一実施形態における半導体チップ切出し方法の各ェ 程を説明するための図である。図 3Aに示すように、シリコン基板 4の表面（一方面）に 構造体材料 6を、例えば SiO , SiN, PolySiなどを熱拡散もしくは CVDにより形成す  [0025] FIGS. 3A to 3H are diagrams for explaining each step of the semiconductor chip cutting method according to the embodiment of the present invention. As shown in FIG. 3A, the structure material 6 is formed on the surface (one surface) of the silicon substrate 4 by, for example, thermal diffusion or CVD using SiO, SiN, PolySi or the like.
2  2
る。構造体材料 6は SOIウェハの活性層を用いてもよい。続いて、構造体材料 6をフ オトリソ，エッチングなどにより加工し、例えばメンブレンを形成する。このとき、スクライ ブ領域 3に対応する領域 7もエッチングしておく。 The The structure material 6 may be an active layer of an SOI wafer. Subsequently, the structural material 6 is Processing is performed by otolitho, etching, etc., for example, a membrane is formed. At this time, the region 7 corresponding to the scribe region 3 is also etched.
[0026] 図 3Bに示すように、シリコン基板 4上および構造体材料 6上を覆うように保持膜 8を 形成する。この保持膜 8は、チップ保持効果を持たせるため、機械的強度を有してお り、特に、保護領域がメンブレン状と成り得ることを考えると、軽い衝撃を吸収しやす い延性があるのが好ましい。さらに、他の材料との選択的除去が容易な特性を有して いるのが好ましい。すなわち、レジスト除去時に除去されることがなぐ保持膜 8を除 去するときに後述のテープなどの保持材 12が剥がれないことが要求される。また、後 述の Siドライエッチングするときにエッチング特性を保つように熱伝導率が高ぐ特に チップが薄膜の場合を考えると、応力による歪を抑えることができるよう、低応力膜で あるのが好ましい。さらに、工程の利便性を考えて成膜、膜厚制御が容易であるとよ い。 As shown in FIG. 3B, a holding film 8 is formed so as to cover the silicon substrate 4 and the structural material 6. This holding film 8 has mechanical strength to give a chip holding effect, and in particular, considering that the protective region can be a membrane shape, it has a ductility that easily absorbs a light impact. Is preferred. Further, it preferably has a characteristic that it can be easily selectively removed from other materials. That is, it is required that the holding material 12 such as a tape described later is not peeled off when the holding film 8 that cannot be removed at the time of resist removal is removed. In addition, the thermal conductivity is high so that the etching characteristics are maintained when performing the Si dry etching described later. Especially when considering the case where the chip is a thin film, it is a low stress film so that distortion due to stress can be suppressed. preferable. In addition, it is desirable that film formation and film thickness control be easy in consideration of process convenience.
[0027] このような保持膜 8として、 Ti, Cu, Ni, A1などの金属系材料を用いると、熱伝導性 が良好であるので好ましい。ただし、多少熱伝導性は劣るがポリイミド，レジストなどの 榭脂系材料や、ダイシングエキスバンドテープなどの UVテープも使用可能である。 榭脂系材料を使用した場合には、エッチングマスク用レジストとは異なる種類を用い 、選択比を持たせる必要がある。  [0027] It is preferable to use a metal material such as Ti, Cu, Ni, or A1 as the holding film 8 because the thermal conductivity is good. However, although heat conductivity is somewhat inferior, resin materials such as polyimide and resist, and UV tapes such as dicing-extended tape can also be used. When a resin material is used, it is necessary to use a different type from the etching mask resist and to have a selection ratio.
[0028] 保持膜 8が金属膜の場合は、スパッタ， CVD,メツキなどにより成膜できる。膜厚は 例えば Tiの場合、 1 μ mの厚みがあれば充分である。  When the holding film 8 is a metal film, it can be formed by sputtering, CVD, plating, or the like. For example, in the case of Ti, a thickness of 1 μm is sufficient.
[0029] 図 3Cに示すように、シリコン基板 4の裏面 (他方面)側に、貫通穴 5に対応する貫通 パターンと、スクライブ領域 3に対応するパターンとを除!、てレジスト 9でパターユング して、シリコン基板 4の表面側を下にして、張り合わせ材料 10を用いて搬送部材とし てのキャリアウェハ 11に張り合わせる。スクライブ領域 3は任意のラインを描くことがで きるので、この発明は矩形の半導体チップのみならず円形の半導体チップを切出す のに適用できる。  [0029] As shown in FIG. 3C, on the back surface (other surface) side of the silicon substrate 4, the through pattern corresponding to the through hole 5 and the pattern corresponding to the scribe region 3 are removed, and the resist 9 is patterned. Then, the silicon substrate 4 is attached to a carrier wafer 11 as a conveying member using the bonding material 10 with the surface side of the silicon substrate 4 facing down. Since the scribe region 3 can draw an arbitrary line, the present invention can be applied to cut out not only a rectangular semiconductor chip but also a circular semiconductor chip.
[0030] 図 3Dに示すように、レジスト 9をマスク材として Siドライエッチングにより貫通処理を 行い、図 2Bに示した貫通穴 5を形成する。このとき、同時にスクライブ領域 3もエッチ ングされるので、半導体チップ 2の切出しを同時に行うことが可能になる。ただし、この 時点では保持膜 8により、各半導体チップ 2はウェハの外周とつながった状態を保つ ている。 [0030] As shown in FIG. 3D, a penetration process is performed by Si dry etching using the resist 9 as a mask material to form the through hole 5 shown in FIG. 2B. At this time, since the scribe region 3 is also etched, the semiconductor chip 2 can be cut out simultaneously. However, this At that time, the holding film 8 keeps each semiconductor chip 2 connected to the outer periphery of the wafer.
[0031] 図 3Dに示すキャリアウェハ 11から半導体チップ 2を剥がすとともに、レジスト 9を除 去する。図 3Eに示すように半導体チップ 1の貫通穴 5側を下にし、図 3Fに示す保持 材 12上に固定する。保持材 12としてはテープなどが用いられる力 図 3Gの工程で 保持膜 8を除去する保持膜除去材に耐性のある材料を選択する。  [0031] The semiconductor chip 2 is peeled off from the carrier wafer 11 shown in FIG. 3D, and the resist 9 is removed. As shown in FIG. 3E, the through-hole 5 side of the semiconductor chip 1 is turned down and fixed on the holding material 12 shown in FIG. 3F. The holding material 12 is a force that uses a tape or the like. A material that is resistant to the holding film removing material that removes the holding film 8 in the process of FIG.
[0032] 図 3Gに示すように、保持材 12で固定された半導体チップ 2から保持膜除去材を用 いて保持膜 8を除去することにより、図 2Bに示した半導体チップ 2を形成できる。保持 膜除去材としては、保持膜 8として、例えば Tiを用いた場合には、希フッ酸を使用す る。  As shown in FIG. 3G, by removing the holding film 8 from the semiconductor chip 2 fixed by the holding material 12 using the holding film removing material, the semiconductor chip 2 shown in FIG. 2B can be formed. As the retention film removing material, for example, when Ti is used as the retention film 8, dilute hydrofluoric acid is used.
[0033] 半導体チップ 2はテープなどの保持材 12により固定されているので、半導体チップ 2がばらばらになることがなぐ図 3Hに示すように、半導体チップ 2を保持材 12から剥 がすことで、必要に応じて容易に個々に取り出すことができる。  [0033] Since the semiconductor chip 2 is fixed by the holding material 12 such as a tape, the semiconductor chip 2 can be separated from the holding material 12 as shown in FIG. , Can be easily removed individually as needed.
[0034] 上述のごとくこの実施形態によれば、シリコン基板 4に貫通穴 5を形成するときに、ス クライブ領域 3も同時にエッチングするようにしたので、工程の簡略ィ匕が可能になる。 また、ダイシング工程を不要にできるので、チップの構造体破損が起こりに《なり、 切屑の発生も少なくできる。し力も、保持膜 8を形成することにより、各チップがバラけ ないようにすることができる。さらに、スクライブ領域 3の形状は、貫通エッチングのフ オト工程に依存するために矩形以外の円形などの多様な形状に切出すのが可能に なる。  As described above, according to this embodiment, when the through hole 5 is formed in the silicon substrate 4, the scribe region 3 is also etched at the same time, so that the process can be simplified. In addition, since the dicing process can be eliminated, the chip structure is damaged and the generation of chips can be reduced. Also, by forming the holding film 8, it is possible to prevent the chips from being separated. Further, since the shape of the scribe region 3 depends on the photo process of the through etching, it can be cut into various shapes such as a circle other than a rectangle.
[0035] 以上、図面を参照してこの発明の実施形態を説明した力 この発明は、図示した実 施形態のものに限定されない。図示された実施形態に対して、この発明と同一の範 囲内において、あるいは均等の範囲内において、種々の修正や変形をカ卩えることが 可能である。  [0035] The power of the embodiment of the present invention described above with reference to the drawings. The present invention is not limited to the illustrated embodiment. Various modifications and variations can be made to the illustrated embodiment within the same scope or equivalent scope as the present invention.
産業上の利用可能性  Industrial applicability
[0036] この発明の半導体チップ切出し方法は、表面に薄いメンブレン構造体を有する半 導体チップをスクライブするのに利用できる。 The semiconductor chip cutting method of the present invention can be used for scribing a semiconductor chip having a thin membrane structure on the surface.

Claims

請求の範囲 The scope of the claims
[1] 半導体チップを半導体ウェハから切出す半導体チップ切出し方法であって、 前記半導体ゥ ハの半導体基板の一方面上に構造体を形成する工程と、 前記半導体基板の構造体側に、該構造体の表面に前記半導体チップを保持する 保持膜を形成する工程と、  [1] A semiconductor chip cutting method for cutting a semiconductor chip from a semiconductor wafer, the step of forming a structure on one surface of a semiconductor substrate of the semiconductor wafer, and the structure on the structure side of the semiconductor substrate Forming a holding film for holding the semiconductor chip on the surface of
前記半導体基板の他方面側から前記構造体の周囲を囲む切出しラインをエツチン グして前記半導体チップを切出す工程とを備える、半導体チップ切出し方法。  Cutting the semiconductor chip by etching a cutting line surrounding the structure from the other surface side of the semiconductor substrate.
[2] さらに、前記切出しラインをエッチング後、前記半導体基板の構造体とは他方面側 を保持部材に固定する工程を含む、請求項 1に記載の半導体チップ切出し方法。  2. The semiconductor chip cutting method according to claim 1, further comprising a step of fixing the other surface side of the semiconductor substrate structure to the holding member after etching the cutting line.
[3] さらに、前記保持部材に固定した半導体チップ力 前記保持膜を除去する工程を 含む、請求項 2に記載の半導体チップ切出し方法。 [3] The semiconductor chip cutting method according to [2], further comprising a step of removing the holding film force of the semiconductor chip fixed to the holding member.
[4] 前記保持膜を形成する工程は、前記保持膜を前記構造体表面に形成した後、前 記保持膜上に搬送部材を貼り付ける工程を含む、請求項 1に記載の半導体チップ切 出し方法。 [4] The semiconductor chip cutout according to [1], wherein the step of forming the holding film includes a step of attaching a transport member on the holding film after the holding film is formed on the surface of the structure. Method.
[5] 前記切出しラインは任意のラインを描ぐ請求項 1に記載の半導体チップ切出し方 法。  5. The semiconductor chip cutting method according to claim 1, wherein the cutting line draws an arbitrary line.
[6] 前記切出しラインは円形を描ぐ請求項 1に記載の半導体チップ切出し方法。  6. The semiconductor chip cutting method according to claim 1, wherein the cutting line draws a circle.
[7] 前記半導体チップは、前記半導体基板の他方面側から一方面側の前記構造体に 至り、前記構造体の一部を成す貫通穴を有していて、  [7] The semiconductor chip has a through hole that extends from the other surface side of the semiconductor substrate to the structure body on one surface side and forms a part of the structure body.
前記半導体チップを切出す工程は、前記切出しラインと前記貫通穴とを同時にドラ ィエッチングする工程を含む、請求項 1に記載の半導体チップ切出し方法。  2. The semiconductor chip cutting method according to claim 1, wherein the step of cutting the semiconductor chip includes a step of dry etching the cutting line and the through hole simultaneously.
[8] 前記半導体チップを切出す工程は、前記貫通穴と前記切出しラインに対応する領 域を除く半導体基板の他方面側にレジストを塗布し、ドライエッチングする工程を含 む、請求項 7に記載の半導体チップ切出し方法。 [8] The process according to claim 7, wherein the step of cutting out the semiconductor chip includes a step of applying a resist to the other side of the semiconductor substrate excluding a region corresponding to the through-hole and the cut-out line, and dry etching. The semiconductor chip cutting method as described.
[9] 前記構造体は、少なくとも可動部および薄膜のいずれかを有する、請求項 1に記載 の半導体チップ切出し方法。 9. The semiconductor chip cutting method according to claim 1, wherein the structure includes at least one of a movable part and a thin film.
[10] 請求項 1から 9のいずれかに記載の各工程により形成された、半導体チップ。 [10] A semiconductor chip formed by each process according to any one of [1] to [9].
PCT/JP2006/319667 2005-10-03 2006-10-02 Semiconductor chip cutting method and semiconductor chip WO2007040190A1 (en)

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