Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
  • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
  • H01L33/145—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
  • H01L2933/0008—Processes
  • H01L2933/0016—Processes relating to electrodes
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L33/005—Processes
  • H01L33/0093—Wafer bonding; Removal of the growth substrate
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
  • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape

Definitions

• the present invention relates to the design of semiconductor light-emitting devices. More specifically, the present invention relates to novel device structures which facilitate more efficient light emission.
• HB-LEDs High- brightness light-emitting diodes
• An LED typically produces light from an active region which is situated between a positively-doped cladding layer (p-type cladding layer) and negatively-doped cladding layer (n-type cladding layer).
• the carriers which include holes from the p-type cladding layer and electrons from the n-type cladding layer, recombine in the active region.
• this recombination process releases energy in the form of photons, or light, whose wavelength corresponds to the energy band-gap of the material in the active region.
• the electrodes When a significant overlap exists between the upper and lower electrodes, the electrodes can obstruct a substantial amount of vertically emitted light. In addition, more carriers recombine in the active region which coincides with the overlapped area, since this region typically is part of a low- resistance path between the electrodes. The concentration of carriers in this undesirable location further exacerbates the vertical-light obstruction problem.
• One embodiment of the present invention provides a semiconductor light- emitting device, which comprises: an upper cladding layer; a lower cladding layer; an active layer between the upper and lower cladding layers; an upper ohmic-contact layer forming a conductive path to the upper cladding layer; and a lower ohmic-contact layer forming a conductive path the lower cladding layer.
• the lower ohmic-contact layer has a shape substantially different from the shape of the upper ohmic-contact layer, thereby diverting a carrier flow away from a portion of the active layer which is substantially below the upper ohmic-contact layer when a voltage is applied to the upper and lower ohmic-contact layers.
• the shape of the lower ohmic-contact layer is substantially complementary to the shape of the upper ohmic-contact layer, thereby allowing the carrier flow to be concentrated in the portion of the active layer where light emitted upward is not substantially obstructed by the upper ohmic-contact layer.
• a portion of the lower ohmic-contact layer is not present at a region substantially below the upper ohmic-contact layer. The region where the lower ohmic- contact layer is not present contains a high-resistance material or a material that can form a Schottky or high-resistance contact with the lower cladding layer.
• the material contained in the region where the lower ohmic-contact layer is not present comprises one of: SiO 2 , Au, Al, and Ag.
• the material contained in the region where the lower ohmic-contact layer is not present is reflective with regard to the wavelength of the light emitted by the active layer.
• the device further includes a layer of high- resistance material situated between the lower cladding layer and the lower ohmic-contact layer. The high-resistance material is confined to a region substantially below the upper ohmic- contact layer, thereby reducing carrier recombination occurring below the upper ohmic-contact layer which can obstruct light emitted upward.
• the device further includes a bonding-material layer below the lower ohmic-contact layer and a low-resistance substrate below the bonding- material layer, wherein the low-resistance substrate comprises Si, and the upper and lower cladding layers comprise n-type GaN and p-type GaN, respectively.
• the active layer comprises an InGaN/GaN multi-quantum- well structure, and the bonding-material layer comprises Au.
• a further embodiment of the present invention provides a semiconductor light- emitting device, which comprises: an upper cladding layer, a lower cladding layer, an active layer between the upper and lower cladding layers, an upper ohmic-contact layer forming a conductive path to the upper cladding layer, and a lower ohmic-contact layer forming a conductive path to the lower cladding layer. Furthermore, a portion of the lower cladding layer, or a portion of the active layer, or both, is not present at a region substantially below the upper ohmic-contact layer, thereby reducing carrier recombination below the upper ohmic-contact layer which causes light emitted upward to be obstructed by the upper ohmic-contact layer. [0015] In a variation of this embodiment, the region where the portion of the lower cladding layer, or the portion of the active layer, is not present contains a high-resistance material.
• the shape of the lower cladding layer or the active layer is substantially complementary to the shape of the upper ohmic-contact layer.
• One embodiment of the present invention provides a method for fabricating a semiconductor light-emitting device. The method comprises forming a layered semiconductor structure on a growth substrate, wherein the layered semiconductor structure comprises an n- type semiconductor layer, an active layer, and a p-type semiconductor layer.
• the method further comprises: forming a first ohmic-contact layer with a conductive path to a first side of the layered structure, removing a portion of the first ohmic-contact layer, form a bonding- material layer over the first ohmic-contact layer, bonding a low-resistance substrate onto the bonding-material layer, removing the growth substrate to expose a second side of the layered structure, and forming a second ohmic-contact layer with a conductive path to the second side of the layered structure.
• the second ohmic-contact layer is confined within a region which substantially corresponds to the region where the portion of the first ohmic-contact layer is removed, thereby diverting carrier flow away from a portion within the active layer where vertically emitted light can be substantially obstructed by the second ohmic-contact layer.
• the shape of the second ohmic-contact layer is substantially complementary to the shape of the first ohmic-contact layer.
• the method further comprises filling the region where the portion of the first ohmic-contact layer is removed with a high-resistance material or a material that can form a Schottky or high-resistance contact with the layered structure.
• the material used to fill the region where the portion of the first ohmic-contact layer is removed comprises one of: SiO 2 , Au, Al, and Ag.
• the first ohmic-contact layer comprises a material that is reflective with regard to the wavelength of the light emitted by the active layer.
• One embodiment of the present invention provides a method for fabricating a semiconductor light-emitting device. The method comprises forming a layered semiconductor structure on a growth substrate, wherein the layered semiconductor structure comprises an n- type semiconductor layer, an active layer; and a p-type semiconductor layer.
• the method further comprises forming a high-resistance-material region which is confined to an area on a first side of the layered structure, forming a first ohmic-contact layer with a conductive path to the first side of the layered structure, wherein the first ohmic-contact layer covers the high- resistance-material region, forming a bonding-material layer over the first ohmic-contact layer, bonding a low-resistance substrate onto the bonding-material layer, removing the growth substrate to expose a second side of the layered structure, and forming a second ohmic-contact layer with a conductive path to the second side of the layered structure.
• the second ohmic- contact layer is confined within a region which substantially corresponds to the high-resistance- material region, thereby diverting carrier flow away from a portion within the active layer where emitted light can be substantially obstructed by the second ohmic-contact layer.
• the shape of the second ohmic-contact layer is substantially the same as the shape of the high-resistance-material region.
• One embodiment of the present invention provides a method for fabricating a semiconductor light-emitting device. The method comprises forming a layered semiconductor structure above a growth substrate, wherein the layered semiconductor structure comprising an n-type semiconductor layer, an active layer, and a p-type semiconductor layer.
• the method further comprises removing a portion of the p-type layer, filling the region where the p-type layer is removed with a high-resistance material, forming a first ohmic-contact layer with a conductive path to the first side of the layered structure, wherein the first ohmic-contact layer covers the high-resistance-material region, forming a bonding-material layer over the first ohmic-contact layer, bonding a low-resistance substrate onto the bonding-material layer, removing the growth substrate to expose a second side of the layered structure, and forming a second ohmic-contact layer with a conductive path to the second side of the layered structure.
• the second ohmic-contact layer is confined within a region which substantially corresponds to the high-resistance-material region, thereby diverting carrier flow away from a portion within the active layer where vertically emitted light can be substantially obstructed by the second ohmic-contact layer.
• the shape of the second ohmic-contact layer is substantially complementary to the shape of the high-resistance-material region.
• the high-resistance-material region penetrates the p-type layer.
• the method further comprises removing a portion of the active layer and filling the region where the active layer is removed with a high- resistance material.
• FIG. 1 illustrates an LED structure with vertical electrodes which obstruct vertically emitted light.
• FIG. 2 illustrates an LED structure with substantially complementary vertical electrodes in accordance with one embodiment of the present invention.
• FIG. 3 illustrates an LED structure with a high-resistance layer situated between the lower cladding layer and lower ohmic-contact layer in accordance with one embodiment of the present invention.
• FIG. 4 illustrates an LED structure wherein a portion of the lower cladding layer and active layer is removed and replaced by a high-resistance material in accordance with one embodiment of the present invention.
• FIGs. 5-12 illustrate examples of complementary upper and lower electrodes in accordance with embodiments of the present invention.
• FIG. 13 illustrates a process for fabricating an LED with complementary electrodes in accordance with one embodiment of the present invention.
• FIG. 14 illustrates a process for fabricating an LED with a buried high-resistance layer between an electrode and the p-type cladding layer in accordance with one embodiment of the present invention.
• FIG. 15 illustrates a process for fabricating an LED with a buried high-resistance region which penetrates the p-type cladding layer and the active layer in accordance with one embodiment of the present invention.
• the two electrode of an LED can be placed on the same side of the substrate (lateral electrodes) or on different sides of the substrate (vertical electrodes).
• Vertical- electrode configuration is a preferred design due to its ease of packaging and better reliability.
• FIG. 1 illustrates a typical LED structure with vertical electrodes.
• An active layer 106 is "sandwiched" between an upper layer 104 and a lower layer 108.
• upper layer 102 or lower layer 108 can include additional layers, such as an n-type or p-type cladding layer, a substrate layer, or a buffer layer.
• a cladding layer can include one or more layers of material, although "cladding layer” as used in some literature refers only to a doped layer immediately adjacent to the active layer.
• upper layer 104 is an upper electrode 102, which is a layer of conductive or low-resistance material.
• lower layer 108 is a lower electrode 110, which is also a layer of conductive or low-resistance material.
• upper electrode 102 and lower electrode 110 are both ohmic-contact layers. Note that an ohmic-contact layer can form an ohmic contact with an adjacent layer and typically exhibit a low resistance.
• An ohmic- contact layer can be based on one or more metal, alloy, or compound materials, such as Pt, Ni, NiO, and ITO (indium tin oxide).
• upper layer 104 includes a negatively doped layer, or n-type layer, and lower layer 108 includes a positively doped layer, or p-type layer.
• lower electrode 110 also obstructs downward-propagating light. However, it is possible to use reflective materials for lower electrode 110 so that lower electrode 110 can reflect a significant portion of the light.
• Embodiments of the present invention mitigate the vertical-light obstruction problem by manipulating the carrier flow in a device so that majority of the carrier recombination occurs in an active-layer region where vertically emitted light is not obstructed by the upper electrode. Such manipulation is achieved by modifying the resistance distribution across the metal, cladding, and/or the active layer.
• One embodiment of the present invention modifies the effective resistance distribution across the LED's layered structure by using specially shaped electrodes.
• the upper and lower electrodes have substantially complementary shapes, so that the overlapped area between the vertical projections of the electrodes on a horizontal projection plane is significantly reduced. In this way, majority of the carrier recombination can occur in active-layer regions where upward-propagating light is not obstructed by the upper electrode.
• FIG. 2 illustrates an LED structure with substantially complementary vertical electrodes in accordance with one embodiment of the present invention.
• an upper electrode 202 is of the shape of a ring
• a lower electrode 210 is an ohmic-contact layer with a portion removed, wherein the removed portion corresponds to the shape of upper electrode 202.
• FIG. 5 presents a top view of the these electrodes. The removed portion in ohmic-contact layer 210 is then filled with a high-resistance material.
• high- resistance material can include insulating materials, materials with a resistivity that is substantially higher than that of a metal or the cladding layer, or materials which can form a high-resistance contact with a metal or cladding layer.
• the high- resistance material can be an insulator material, such as SiO 2 , SiN, or Al 2 O 3 .
• the high-resistance material can be a conductive metal, such as Au or Cr, which can form a Schottky contact with a cladding layer.
• substantially complementary shapes means having substantial upper and lower electrode areas whose vertical projections do not overlap.
• the overlapped area is less than 100%, preferably less than 50%, of the area of the upper electrode.
• the upper and lower electrodes can have shapes whose vertical projections do not overlap at all, so long as the electrodes can retain sufficient connection with wires or do not impair the LED's luminescence efficiency.
• the un-overlapped area between the upper and lower electrodes does not exceed five times the area of the upper electrode.
• a layer of high-resistance material 310 is first placed between the lower cladding layer and the lower electrode. A portion of high- resistance layer 310 is then removed, so that its shape is substantially complementary to the shape of an upper electrode 302.
• a lower electrode 312 which in one embodiment is a layer of metal, is deposited or epitaxially grown, only part of this ohmic-contact layer can form a conductive path to a lower layer 308 due to high-resistance material layer 310.
• the carrier flow through the region of an active layer 306 which is in the "shadow," or the vertical projection, of the upper electrode is reduced, and the carrier flow through other regions of active layer 306 is increased.
• a significant amount of light emitted upward can propagate to and leave the upper surface of the device without being obstructed by upper electrode 302.
• upper electrode 302 is of a circular shape
• high-resistance layer 310 is of a similar circular shape with a slightly larger area. Note further that the shape of high-resistance layer 310 does not need to match exactly the shape of upper electrode 302. A smaller or larger high- resistance layer is also possible.
• a portion of a cladding and/or active layer is removed and replaced by a high-resistance material to divert carrier flow to non-obstructed regions. As is shown in FIG. 4, a portion of a lower layer 408 and an active layer 406 is removed and replaced by a high-resistance material 412.
• high-resistance material 412 substantially overlaps with the vertical projection of upper electrode 402. Note that in one embodiment, only a portion of lower layer 408 is removed and replaced by high-resistance material, whereas active layer 406 remains intact. In a further embodiment, high-resistance material 412 can penetrate both lower layer 408 and active layer 406. In yet a further embodiment, only a portion of active layer 406, but not lower layer 408, is removed and replaced by high-resistance material. Other configurations are also possible, so long as the placement of high-resistance material 412 can reduce carrier flow below upper electrode 402.
• FIGs. 5-12 illustrate examples of complementary upper and lower electrodes in accordance with embodiments of the present invention. Note that these shapes can also reflect the shapes of effective low-resistance conductive regions on the upper and lower electrodes in devices with buried high-resistance layers, such as those illustrated in FIGs. 3 and 4.
• FIG.5 illustrates an upper electrode 502 which is of a ring shape, and a lower electrode 504 with a portion removed.
• the removed portion of lower electrode 504 substantially corresponds to upper electrode 502, and is replaced with a high-resistance material. Note that the area defined by the dashed line represents the top view of an upper layer below the upper electrode, or a lower layer above the lower electrode.
• FIG. 6 illustrates an upper electrode 602 which is of a circular shape, and a lower electrode 604 with a portion removed.
• the removed portion of lower electrode 604 substantially corresponds to upper electrode 602, and is replaced with a high-resistance material.
• FIG. 7 illustrates an upper electrode 702 which is of a star shape, and a lower electrode 704 with a portion removed.
• the removed portion of lower electrode 704 substantially corresponds to upper electrode 702, and is replaced with a high-resistance material.
• FIG. 8 illustrates an upper electrode 804 which is of an irregular shape, and a lower electrode 804 which a portion removed.
• the removed portion of lower electrode 804 substantially corresponds to upper electrode 804, and is replace with a high-resistance material.
• FIG. 9 illustrates an upper electrode 902 which is of a triangular shape, and a lower electrode 904 with a substantially different shape.
• the area around lower electrode 904 is filled with a high-resistance material.
• FIG. 10 illustrates an upper electrode 1002 which is of the shape of a strip, and a lower electrode 1004 which is of the shape of a square. Note that the vertical projections of upper electrode 1002 and lower electrode 1004 do not overlap at all. The area around lower electrode 1004 is filled with a high-resistance material.
• FIG. 11 illustrates an upper electrode 1104 which includes two strip-shaped metal parts, and a lower electrode 1104 which is of a rectangular shape.
• the vertical projection of lower electrode 1104 falls between the vertical projections of the two strips of upper electrode 1102.
• upper electrode 1102 does not overlap with lower electrode 1104.
• the area around lower electrode 1104 is filled with a high-resistance material.
• FIG. 12 illustrates an upper electrode 1202 which is of an oval shape, and a lower electrode 1204 with a portion removed.
• the removed portion of lower electrode 1204 substantially corresponds to upper electrode 1202, and is replaced with a high-resistance material.
• the exemplary fabrication processes described below use GaN light-emitting devices as examples. However, the general device structures described herein are applicable to a wide range of semiconductor light-emitting devices.
• an GaN-based layered structure is fabricated on a Si substrate.
• a buffer layer is present between the GaN-based device and the Si substrate to resolve lattice and thermal mismatch. Commonly used compounds for the buffer layer include In x Ga y Ali.
• x- yN (0 ⁇ x ⁇ 1; 0 ⁇ y ⁇ 1)
• In x GayAli. ⁇ .yP (0 ⁇ x ⁇ 1; 0 ⁇ y ⁇ 1); and In x Ga y Al 1-x-y As (O ⁇ x ⁇ lj O ⁇ y ⁇ l).
• the devise structures described herein are applicable to a wide range of semiconductor or metal substrate materials, such as Si, GaAs, GaP, Cu, and Cr.
• FIG. 13 illustrates a process for fabricating an LED with complementary electrodes, wherein the upper electrode has a ring shape.
• a GaN light-emitting layered structure is first fabricated on a growth Si substrate 1302 in Step A.
• a buffer layer 1304 is grown on substrate 1302.
• An n-type GaN layer 1306 is then grown on buffer layer 1304.
• an InGaN/GaN multi-quantum-well active layer 1307 and a p-type GaN layer 1308 are formed on n-type GaN layer 1306.
• Chemical vapor deposition CVD can be used to fabricate these layers.
• the layered structure is placed in a 760 0 C N 2 environment for approximately 20 minutes for the purpose of annealing.
• an ohmic-contact layer 1310 is formed on the p-type GaN layer.
• this fabrication step uses physical vapor deposition methods, such as electron- beam evaporation, filament evaporation, or sputter deposition.
• Ohmic-contact layer 1310 can also be a reflective material.
• ohmic-contact layer 1310 has a reflectivity not less than 30%.
• ohmic-contact layer 1310 comprises Pt.
• Step C of the fabrication process removes portion of the ohmic-contact layer using photo lithography to produce a patterned ohmic-contact layer 1311.
• the removed portion corresponds to the shape of a ring.
• ohmic-contact layer 1311 becomes the lower electrode after the structure is flipped upside down in subsequent steps.
• Step D a bonding metal material 1312 is deposited over ohmic-contact layer 134.
• Bonding metal material 1312 although being a conductive material, can form a high-resistance contact with the p-type layer.
• bonding metal material 1312 comprises Au, because Au can form a Schottky barrier with p-type GaN.
• Step E the entire layered structure 1314 obtained in Step D is flipped upside down and bonded to a second Si substrate 1318, which is of low resistance.
• the bonding side of substrate 1318 is coated with a bonding metal material 1316 which is the same as bonding material 1312.
• a layer of protective material 1320 which protects substrate 1318 from subsequent etching.
• protective layer 1320 also comprises Au. Note that protective layer 1320 is generally a conductive material, so that a conductive path can form from the p-type GaN layer through bonding layer 1316, substrate 1318, and protective layer 1320.
• Step F a layered structure 1322 which includes two substrates is formed in Step F.
• Step G growth Si substrate 1302 is removed using, for example, wet etching based on KOH or HNA. Note that the resulting structure 1324 includes substrate 1318, because protective layer 1320 protects substrate 1318 from being attacked by the etchant.
• Step H another ohmic-contact layer 1326 is deposited on the top surface of structure 1324. Portions of ohmic-contact layer 1326 are then removed in Step I using photo lithography to produce a shaped upper ohmic-contact layer 1328.
• Ohmic-contact layer 1328 has a ring shape and substantially corresponds to the removed portion of lower ohmic-contact layer 1311.
• the fabrication process illustrated in FIG. 13 can produce any substantially complementary electrode shapes, such as those illustrated in FIGs. 5-12.
• the same process can be used to produce a star-shaped upper electrode and the corresponding lower electrode, as is illustrated in FIG. 7.
• the area of the removed portion of the lower electrode can be larger than the area of the upper electrode. In one embodiment, the area of the removed portion of the lower electrode is 1.5 times the area of the upper electrode.
• a high-resistance material can fill the region where the lower ohmic-contact layer is removed.
• a layer of SiO 2 can fill the void where ohmic- contact layer 1311 is removed.
• the SiO 2 layer can then be patterned and etched to expose ohmic-contact layer 1311 which has not been removed. Bonding ohmic-contact layer 1312 is then deposited over ohmic-contact layer 1311 and the SiO 2 layer in Step D.
• FIG. 14 illustrates a process for fabricating an LED with a buried high-resistance layer between an electrode and the p-type cladding layer, wherein the upper electrode is of a ring shape, in accordance with one embodiment.
• a GaN device is fabricated on a growth Si substrate 1402.
• an InGaAlN buffer layer 1404 is grown on substrate 1402.
• An InGaN/GaN multi-quantum-well active layer 1407 and a p-type GaN layer 1408 are subsequently grown on n-type GaN layer 1406
• Step B a layer of high-resistance material, such as SiO 2 , is deposited using, for example, Plasma Enhanced Chemical Vapor Deposition (PECVD).
• PECVD Plasma Enhanced Chemical Vapor Deposition
• the SiO 2 layer is then patterned and etched to form a ring-shaped insulator layer 1409. Insulator layer 1409 is later used to prevent a p-side electrode from forming a conductive path in certain regions with p-type
• Step C a reflective ohmic-contact layer 1411 is deposited over insulator layer 1409 and p-type GaN layer 1408.
• the region of ohmic-contact layer 1411 which is in ohmic contact with p-type GaN layer 1408 is of a shape that is substantially complementary to the shape of insulator layer 1409.
• Step D a bonding-ohmic-contact layer 1412 is further deposited over ohmic- contact layer 1411.
• the resulting layered structure 1414 is then flipped upside down and bonded with a low-resistance Si wafer 1418.
• the bonding side of Si wafer 1418 is coated with a bonding-metal layer 1416.
• the other side of Si wafer 1418 is coated with a protective layer 1420.
• the bonding process occurs under high temperature and high pressure.
• Step F a layered structure 1422 is formed which includes two substrates.
• Step G growth substrate 1402 is removed using wet etching, resulting in structure 1424.
• Low-resistance Si wafer 1418 is intact because protection layer 1420 protects wafer 1418 from being attacked by the etchant.
• Step H InGaAlN buffer layer 1404 is etched away to expose n-type GaN layer 1406. Subsequently, an ohmic-contact layer 1426 is deposited over n-type GaN layer 1406. In Step I 5 ohmic-contact layer 1426 is etched into a ring-shaped upper electrode 1428 using photo lithography.
• FIG. 15 illustrates a process for fabricating an LED with a buried insulator which penetrates the p-type cladding layer and the active layer in accordance with one embodiment of the present invention.
• the upper electrode is of a circular shape, and the shape of a buried insulator substantially coincides with the shape of the upper electrode.
• Step A a GaN-based light-emitting device, which includes a buffer layer 1504, an n-type GaN layer 1506, a multi-quantum-well active layer 1507, and a p-type GaN layer 1508, is grown on a growth Si substrate 1502. Subsequently, a portion of p-type GaN layer 1508 and active layer 1507 is etched away to create a void 1509 in Step B.
• An insulator material such as SiO 2 is then deposited to fill void 1509 in Step C. Further patterning and etching are applied to remove the excessive insulator material in Step D.
• Step E an ohmic-contact layer is deposited over p-type GaN layer 1508 and insulator 1511.
• a bonding layer 1513 is deposited over ohmic-contact layer 1512.
• the resulting layered structure 1514 is then flipped upside down and bonded with a low-resistance substrate 1518.
• On the bonding side of low-resistance substrate 1518 is a bonding layer 1516, which in one embodiment comprises the same metal as bonding layer 1513.
• a conductive protective layer 1520 On the other side of low-resistance substrate 1518.
• Growth substrate 1502 is then removed by wet etching in Step G, resulting in structure 1524.
• Buffer layer 1504 is further removed in Step H, exposing n-type GaN layer 1506.
• An ohmic-contact layer 1526 is then deposited, forming an ohmic contact with n-type GaN layer 1506.
• Step I ohmic-contact layer 1526 is patterned and etched to form a circular- shaped upper electrode 1526. Note that the shape of insulator 1511 substantially coincides with the shape of upper electrode 1526.

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