WO2006046403A1 - 半導体ウエーハの製造方法及び半導体ウエーハ - Google Patents
半導体ウエーハの製造方法及び半導体ウエーハ Download PDFInfo
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- WO2006046403A1 WO2006046403A1 PCT/JP2005/018745 JP2005018745W WO2006046403A1 WO 2006046403 A1 WO2006046403 A1 WO 2006046403A1 JP 2005018745 W JP2005018745 W JP 2005018745W WO 2006046403 A1 WO2006046403 A1 WO 2006046403A1
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- polishing
- chamfered portion
- wafer
- chamfered
- polished
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 35
- 238000005498 polishing Methods 0.000 claims abstract description 232
- 239000004744 fabric Substances 0.000 claims abstract description 55
- 238000000034 method Methods 0.000 claims description 38
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 18
- 229910052710 silicon Inorganic materials 0.000 claims description 18
- 239000010703 silicon Substances 0.000 claims description 18
- 238000007517 polishing process Methods 0.000 abstract description 12
- 235000012431 wafers Nutrition 0.000 description 138
- 230000002093 peripheral effect Effects 0.000 description 12
- 230000000052 comparative effect Effects 0.000 description 8
- 238000005530 etching Methods 0.000 description 8
- 238000000227 grinding Methods 0.000 description 8
- 239000002002 slurry Substances 0.000 description 7
- 238000003825 pressing Methods 0.000 description 5
- 238000005259 measurement Methods 0.000 description 4
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 3
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000007717 exclusion Effects 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000011156 evaluation Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- JOYRKODLDBILNP-UHFFFAOYSA-N Ethyl urethane Chemical compound CCOC(N)=O JOYRKODLDBILNP-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000008119 colloidal silica Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 239000007888 film coating Substances 0.000 description 1
- 238000009501 film coating Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
- B24B37/07—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool
- B24B37/08—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool for double side lapping
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B9/00—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor
- B24B9/02—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground
- B24B9/06—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground of non-metallic inorganic material, e.g. stone, ceramics, porcelain
- B24B9/065—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground of non-metallic inorganic material, e.g. stone, ceramics, porcelain of thin, brittle parts, e.g. semiconductors, wafers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02021—Edge treatment, chamfering
Definitions
- the present invention relates to a method of manufacturing a semiconductor wafer. For example, when a large-diameter silicon wafer having a diameter of 300 mm or more is manufactured through a double-side polishing process or the like, high flatness can be achieved even at the outer periphery of the wafer.
- the present invention relates to a method for manufacturing a semiconductor wafer and a semiconductor wafer. Background art
- Semiconductor wafers used in the manufacture of semiconductor devices are obtained by slicing a silicon single crystal ingot grown by, for example, the Chiyoklarsky method and processing it into a wafer shape, then chamfering (grinding), lapping, etching, one side Manufactured through various processes such as polishing and chamfering (mirror chamfering).
- the manufacturing process of 300 mm large diameter silicon wafers is performed simultaneously on the front and back surfaces to obtain more accurate wafer flatness quality and nanotopography quality.
- a double-side polishing step for polishing is generally employed. In this case, for example, as shown in FIG. 15, mirror-like silicon wafers are processed through slicing, chamfering, lapping (double-side polishing, surface grinding), etching, double-side polishing, mirror chamfering, and final polishing. Eha can be obtained.
- the double-side polishing step is performed using, for example, an apparatus 70 as shown in FIG.
- Ueno and W are accommodated in a circular hole 78 of a carrier 75, and sandwiched between a pair of upper and lower surface plates 71 and 72 to which polishing cloths 73 and 74 are attached, and polished.
- the upper and lower surface plates 71 and 72 and the carrier 75 are rotated to polish both surfaces of the wafer W simultaneously.
- an oxide film or a nitride film may be formed on the chamfered part or the resist film may adhere, but the chamfered part is roughened. If present, these film components may remain without being removed in the subsequent cleaning process, and may become a source of dust generation. However, if the chamfered portion is mirror-finished, it is easy to remove the resist film and the like attached thereafter.
- polishing cloths 21 and 22 having the inclined polishing surfaces 21a and 22a and the polishing cloth 24 having the vertical surfaces are pressed against the chamfered portion of the rotating wafer W to chamfer. Polishing the chamfered surface on the main surface side of the chamfered part by pressing the reverse cup type polishing cloth 31 against the chamfered part of wafer W as shown in Fig. 10 (A) and (B). Then, there is a method of polishing the end face of the chamfered portion by pressing a polishing cloth 34 perpendicular to the end face (outermost peripheral face).
- the present invention removes scratches and the like on the chamfered portion generated in the double-side polishing step when manufacturing a semiconductor wafer, suppresses the occurrence of overpolishing of the outer peripheral portion of the main surface due to the polishing of the chamfered portion, and the vicinity of the chamfered portion
- an object of the present invention is to provide a method for manufacturing a semiconductor wafer having high flatness and a semiconductor wafer.
- a method for manufacturing a semiconductor wafer comprising at least a double-side polishing step and a chamfered portion polishing step, wherein the first chamfered portion polishing step comprises: At least a chamfered surface on each main surface in the chamfered portion of the wafer is brought into contact with the polishing cloth to polish the chamfered portion, and then double-side polished, and then a second chamfered portion polishing step.
- a semiconductor wafer comprising: polishing a chamfered portion so that at least the end face of the chamfered portion of the wafer is in contact with the polishing cloth, and both main surfaces of the wafer are not in contact with the polishing cloth.
- the semiconductor wafer is preferably a silicon wafer.
- Silicon wafers have the highest demand as a material for semiconductor devices. Particularly in the production of large-diameter silicon wafers having a diameter of 300 mm or more which are mass-produced in recent years, both surfaces are generally polished. It becomes effective.
- first chamfered portion polishing step it is preferable to polish only the chamfered surface on each main surface side of the chamfered portion.
- second chamfered portion polishing step only the end surface of the chamfered portion is preferred. U, prefer to polish.
- the first chamfered portion polishing step only the chamfered surface on each main surface side of the chamfered portion is polished, and in the second chamfered portion polished step, only the end surface of the chamfered portion is polished.
- the chamfered portion can be polished, and overpolishing beyond the boundary between the chamfered portion and the main surface can be prevented more reliably.
- the wafer in the first chamfered portion polishing step, is inclined at an angle within a range of 40 to 50 ° with respect to the polishing surface of the polishing pad.
- the chamfered portion is polished at an angle, and in the second chamfered portion polishing step, the chamfered portion can be polished with the wafer perpendicular to the polishing surface of the polishing pad.
- the chamfered portion is polished easily by bringing the wafer into contact with the polished surface of the polishing cloth at a predetermined angle as described above. It can polish reliably.
- polishing cloths are used as the polishing cloth used in the first chamfered portion polishing step and the polishing cloth used in the second chamfered portion polishing step.
- the chamfered portion is polished in two stages, and different surfaces are polished. Therefore, if a dedicated one is used in each step, a predetermined surface in the chamfered portion can be efficiently polished.
- the present invention provides a semiconductor wafer, characterized in that both sides and chamfered portions are polished and the roll-off amount is 0.5 m or less.
- the chamfered portion polishing is separately performed before and after the double-side polishing.
- overpolishing can be effectively prevented.
- a double-side polished silicon wafer having a diameter of 300 mm or more and a roll-off amount of 0.5 m or less can be provided.
- a predetermined surface of the chamfered portion is polished before and after double-side polishing, so that scratches and the like of the chamfered portion can be reliably removed and the wafer can be removed. It is possible to effectively suppress overpolishing of both main surfaces in the vicinity of the chamfered portion, and to maintain a flat shape made by double-side polishing. Therefore, it is possible to manufacture a semiconductor wafer having an excellent outer peripheral shape that can satisfy not only the currently required 2 mm outer excluded area but also the required lmm outer excluded area in the future.
- FIG. 1 is a flowchart showing an example of a manufacturing process of a semiconductor wafer according to the present invention.
- FIG. 2 is a schematic view showing an example of a chamfering apparatus.
- FIG. 3 is a schematic view showing an example of a cross-sectional shape of a chamfered portion of a wafer.
- FIG. 4 is a schematic sectional view showing an example of a double-side polishing apparatus.
- FIG. 5 is a schematic plan view showing the arrangement of carriers in the double-side polishing apparatus of FIG.
- FIG. 6 is a schematic sectional view showing another example of the double-side polishing apparatus.
- FIG. 7 is a schematic plan view showing the arrangement of carriers in the double-side polishing apparatus of FIG.
- FIG. 8 is a schematic view showing an example of a polishing method for a chamfered portion.
- FIG. 9 is a schematic view showing another example of a polishing method for a chamfered portion.
- FIG. 10 is a schematic view showing another example of a polishing method for a chamfered portion.
- FIG. 11 is a schematic view showing another example of a polishing method for a chamfered portion.
- FIG. 12 is a schematic view showing an example of a polishing method for an end face of a chamfered portion.
- FIG. 13 is a schematic view showing another example of the polishing method for the end face of the chamfered portion.
- FIG. 14 is a graph showing roll-off amounts of examples and comparative examples.
- FIG. 15 is a flowchart showing an example of a conventional silicon wafer manufacturing process.
- FIG. 16 is a diagram showing an overpolished region observed with a microscope.
- FIG. 17 is a schematic diagram showing an example of a cell in site flatness evaluation.
- FIG. 18 is a graph showing the roll-off amount.
- FIG. 19 is an explanatory diagram showing the measurement principle of roll-off.
- the present inventors investigated the outer peripheral shape of the wafer when the chamfered portion was polished after performing double-side polishing of the silicon wafer.
- the conventional site flatness defined by SFQR and SBIR is divided into cells 100 of a predetermined size as shown in Fig. 17.
- the outer peripheral shape in the vicinity of the chamfered portion cannot be accurately grasped. Therefore, recently, an evaluation standard called roll-off has been adopted to evaluate the outer peripheral shape of wafers with high accuracy.
- the roll-off parameter can be evaluated with high accuracy by directly measuring the shape of the outer periphery of the wafer.
- the force that is being standardized by the standards body For example, as shown in FIG. 19, the wafer surface is irradiated with laser light via the prism 90 and reflected light is received by the CCD 91. There is a method to measure by. Then, the surface profile force reference line is calculated, and the roll-off amount can be obtained as a difference from the reference line.
- the inventors measured the roll-off amount after double-side polishing the silicon wafer and further polishing the chamfered portion, and the results shown in FIG. 18 were obtained.
- the width of the chamfered portion C is about 0.3 mm or less. It was found that the roll-off amount in the vicinity of the chamfered portion of the main surface was large.
- the present inventors have conducted intensive research on a method for effectively preventing over-polishing as described above.
- the main surface side in the chamfered portion of the wafer is obtained before the double-side polishing step.
- the end surface of the chamfered portion of the wafer is brought into contact with the polishing cloth, and both main surfaces of the wafer are used as the polishing cloth. It has been found that if the chamfered portion is polished without contact, overpolishing can be prevented, scratches caused by double-sided polishing can be removed while effectively suppressing roll-off badities, and the present invention has been completed. It was.
- FIG. 1 shows an example of steps of a method for manufacturing a semiconductor wafer according to the present invention.
- a silicon single crystal ingot grown by the Chiyoklarsky method (CZ method) or the floating zone melting method (FZ method) is sliced using a wire saw etc. to form a wafer (Fig. 1 (A)).
- the chamfering process is performed by pressing the outer edge of the wafer against the groove 2a of the grindstone la having the same shape as the desired wafer chamfering shape, and the upper surface of the wafer W held by the holding plate 3a.
- the chamfered portion C can be formed by chamfering the corners on the side and the lower surface side and the outermost peripheral portion (end surface) at once.
- the relative position between wafer W and the turret is controlled numerically, and the outermost peripheral portion of the wafer is formed on the bottom surface of groove 2b using a turret lb having an inverted trapezoidal groove 2b. It is also possible to grind the (end face) and chamfer the corner on the upper surface side of the wafer W with the upper taper surface of the groove 2b and the corner on the lower surface side of the wafer W with the lower taper surface of the groove 2b.
- lapping may be performed before chamfering.
- double-sided grinding that simultaneously grinds both sides of a wafer using a pair of grinding wheels, or surface grinding that grinds one side at a time using a turret to a wafer fixed to a holding plate. . Both double-head grinding and surface grinding may be performed.
- Etching is performed by immersing the wafer in an etching solution in order to remove the processing distortion generated on the wafer surface by lapping or the like (FIG. 1 (D)).
- alkali etching using an aqueous solution of sodium hydroxide or potassium hydroxide or acid etching using a mixed solution of hydrofluoric acid and nitric acid can be performed.
- the first chamfering polishing step at least the chamfered surface on each main surface side of the chamfered portion of the wafer is brought into contact with the polishing cloth to polish the chamfered portion (FIG. 1 (E)).
- the chamfered surface on each major surface side in the chamfered portion is, for example, a chamfered portion C having a rectangular cross section as shown in Fig. Corresponds to X2.
- a portion X3 located on the outermost periphery of the wafer and substantially perpendicular to the main surface of the wafer W is referred to as an end face of the chamfered portion in the present invention.
- an outer cylindrical polishing cloth 12 attached to the outer periphery of the rotating drum 11 as shown in FIG. 8A can be used.
- the wafer W is set at a predetermined angle (inclination angle) with respect to the polishing surface 12a of the polishing cloth 12.
- the chamfered portion is polished by inclining and pressing at ⁇ .
- the inclination angle 0 of the wafer W with respect to the polishing surface 12a of the polishing cloth 12 depends on the angle and shape of the chamfered surfaces XI and X2 of the chamfered portion, but if the inclination angle ⁇ is smaller than 40 °, the polishing is performed.
- the cloth 12 is easily contacted with the main surface of the wafer W only at the chamfered portion, and the main surface may be polished.
- the chamfered surfaces XI and X2 will not be sufficiently polished near the main surface, causing partial force in the device process. There is a fear. Therefore, it is usually preferable to polish the chamfered portion by inclining the wafer with respect to the polishing surface 12a of the polishing pad 12 at an angle within the range of 40 to 50 °.
- the polishing cloth passes over the boundary between the chamfered portion and the main surface and the portion of the main surface adjacent to the chamfered portion is polished, the flatness can be restored by the next double-side polishing step.
- the wafer main surface is allowed to be slightly overpolished.
- the polishing cloth (polishing apparatus) is not limited to the outer cylinder type as shown in FIG. 8A, and has polishing surfaces 21a and 22a inclined at a predetermined angle as shown in FIG.
- the upper and lower polishing cloths 21 and 22 may be used to simultaneously polish the chamfered surfaces XI and X2 on both main surfaces in the chamfered portion of the wafer W.
- an inverted cup-type polishing pad 31 as shown in FIG. 10 (A) may be used.
- an inner cylindrical polishing cloth 40 as shown in FIG. 11 may be used.
- a double-side polishing apparatus 70 as shown in FIGS. 4 and 5 can be used.
- the wafer W is accommodated in the holding hole 78 of the carrier 75 and sandwiched between the polishing cloths 73 and 74 attached to the upper and lower surface plates 71 and 72. Then, both surfaces of the wafer W can be simultaneously polished by rotating the carrier 75 by the internal gear 76 and the sun gear 77 while supplying the polishing slurry.
- the surface roughness of wafer W can be improved and the flatness can be improved.
- a double-side polishing apparatus 80 as shown in FIGS. 6 and 7 can be used.
- this apparatus 80 during polishing, all the eccentric arms 82 are rotated synchronously around the rotation shaft 90 via the timing chain 85, so that the carrier 81 held by the carrier holder 88 does not rotate. A circular motion is performed by drawing a small circle in the horizontal plane.
- Such a swing type double-side polishing apparatus 80 can be miniaturized, so that it is relatively narrow and can perform polishing work of a large diameter wafer with a space. Along with the recent large diameter of wafers, such a oscillating double-side polishing apparatus 80 is often used.
- the second chamfered portion polishing step is performed in the present invention (FIG. 1 (G)).
- the chamfered portion is polished such that at least the end surface X3 of the chamfered portion of the wafer is brought into contact with the polishing cloth and both the main surfaces of the wafer are not brought into contact with the polishing cloth.
- the wafer Since the chamfered surfaces XI and X2 on the main surface side in the chamfered portion have already been polished by the first double-side polishing step, the wafer is chamfered with respect to the polishing cloth in the second chamfered portion polishing step. If the end face X3 of the part is brought into contact with the polishing, the chamfered part or the like generated by the contact with the carrier in the double-side polishing process is removed, and the entire chamfered part is polished.
- the second chamfered portion polishing step if polishing is performed in a state where the polishing cloth is in contact with the main surface of wafer W, overpolishing occurs near the boundary with the chamfered portion, and It causes deterioration of the outer shape. Therefore, the chamfered portion is polished so that both main surfaces of wafer W are not in contact with the polishing cloth.
- the chamfered portion is polished with the wafer W perpendicular to the polishing surface 51a of the polishing pad 51 for the end surface.
- both main surfaces of wafer W can be prevented from coming into contact with polishing cloth 51, and end surface X3 of the chamfered portion of wafer W can be reliably in contact with polishing cloth 51 to polish at least end surface X3 of the chamfered portion. it can. Therefore, it is possible to reliably remove the scratches on the end face that occur in the double-side polishing process of the main surface.
- the chamfered portion may be polished using a polishing cloth 61 as shown in FIG. Efficient polishing is achieved by rotating a plurality of polishing cloths 61 arranged around the wafer W synchronously and bringing each polishing cloth 61 into contact with the end face X3 of the chamfered portion of the wafer W. Can do.
- the second chamfered portion polishing step it is preferable to polish only the end surface X3 of the chamfered portion, but the chamfered surfaces XI and X2 of the chamfered portion are also in contact with the polishing cloth due to the sinking of the polishing cloth. It can be touched. Since the chamfered surfaces XI and X2 are polished in the first chamfered portion polishing process, it is not always necessary to polish them here. However, even if the main surface of wafer W does not come into contact with the polishing cloth, overpolishing does not occur. There is no particular problem, and scratches caused by double-side polishing can be more reliably removed.
- the cross-sectional shape of the chamfered portion of the wafer formed by the chamfering process is not limited to the rectangular shape as shown in FIG. 3 (A), and for example, as shown in FIG. 3 (B).
- Most The outer periphery may be a curved surface.
- the chamfered surface on each main surface side in the chamfered portion referred to in the present invention corresponds to the inclined portions X1 and X2 respectively following each main surface, and the outer side of the chamfered portion
- the curved surface portion can be an end surface.
- the boundary between the chamfered surface and the end surface on each main surface side in the chamfered portion is not clear, for example, the cross-sectional shape of the chamfered portion is semicircular or semielliptical.
- an area where the chamfered portion may be damaged by contact with the carrier in the double-side polishing step may be determined as the end surface of the chamfered portion.
- the width of the chamfered portion is usually about 0.3 mm
- the outer 0.1 mm region is the end surface and the inner region is the chamfered surface on the main surface side. Can do.
- the chamfered surface on the main surface side of the chamfered portion that continues from each main surface is polished so that the unpolished portion of the chamfered portion does not remain, and after the double-side polishing, the second chamfered portion is polished.
- polishing cloth used in the second chamfered portion polishing step since the surface to be polished in the chamfered portion is different from the first chamfered portion polishing step, it is preferable to use a dedicated cloth.
- the outer cylindrical polishing cloth 12 as shown in FIGS. 8A and 8B is also used, and the angle of the wafer W with respect to the polishing cloth 12 is adjusted in each step to polish the chamfered portions. It ’s a lot.
- polishing is performed (FIG. 1 (H)).
- one side of the wafer can be adsorbed and held, and only the side on which the device is formed can be polished on one side while supplying the polishing slurry.
- One-side polishing may be performed by attaching wafers to a plate with an adhesive such as wax. If the polishing allowance increases in this final polishing, the flatness of the outer peripheral area of the wafer may be deteriorated. Therefore, the polishing allowance is preferably 2 ⁇ m or less, particularly about 1 ⁇ m.
- the first chamfered part polishing process For silicon wafers with a diameter of 300 mm obtained by sequentially performing the slicing, chamfering, lapping, and etching processes, as the first chamfered part polishing process, chamfering of each major surface side of the wafer chamfered part with respect to the polishing cloth is performed.
- the chamfered portion was polished by bringing the surfaces into contact.
- a chamfered portion of the chamfered portion is polished by using a mirror type chamfering machine manufactured by Speedfam Corporation and tilting the wafer by 45 ° with respect to the polishing surface of the polishing cloth as shown in Fig. 8 (A). Went.
- double-side polishing was performed using a double-side polishing apparatus as shown in FIG.
- a second chamfered portion polishing step was further performed.
- the end surface of the chamfered portion of the wafer is brought into contact with the polishing cloth by bringing the wafer perpendicular to the polishing surface of the polishing cloth as shown in FIG. 8 (B).
- the chamfered portion was polished so that both main surfaces of the wafer were not in contact with the polishing cloth.
- SU BA400 manufactured by Kuchi Dale was used as the polishing pad, and the pH was adjusted to pH 1.0 based on AJ1325 manufactured by Nissan Chemical Co., Ltd. as the polishing agent.
- the chamfered part was polished with a polishing slurry supplied at a flow rate of 2 liters Z and a polishing load of 2. Okgf.
- a single-side polishing apparatus was used to perform final polishing on one side of the wafer.
- the same slurry as that used in the chamfered portion polishing step was supplied so that the polishing allowance was about 1 m.
- Roll-off measurement was performed after double-side polishing, after the second chamfered portion polishing step, and after final polishing.
- a roll-off measuring device manufactured by Kobelco Kaken Co., Ltd., LER-310M
- the measurement conditions were the roll-off amount at a position lmm from the wafer end face, based on the reference outer line calculated by the method of least squares in the area 3mm to 6mm from the wafer end face.
- Wafer roll-off was measured after double-side polishing, after chamfering treatment, and after final polishing.
- the roll-off amount (average value) after double-side polishing was about 0.35 / zm, which was the same as the comparative example. 0.4 ⁇ , and further, it was suppressed by about 0.45 m even after final polishing on one side, and the fact that it maintained a highly accurate shape after double-sided polishing was a major factor.
- the present invention is not limited to the embodiment described above.
- the above-described embodiment is merely an example, and any component that has substantially the same configuration as the technical idea described in the claims of the present invention and has the same operational effects can be used. It is included in the technical scope of the invention.
- the manufacturing process is not limited to that described in the embodiment.
- a cleaning process or a heat treatment process may be covered, or a wafer that has already undergone chamfering is prepared.
- the present invention also includes a case where a mirror surface wafer is manufactured by sequentially performing the first chamfering polishing step, the double-side polishing step, and the second chamfering polishing step according to the present invention.
Abstract
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Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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US11/666,082 US7507146B2 (en) | 2004-10-27 | 2005-10-12 | Method for producing semiconductor wafer and semiconductor wafer |
EP05793132A EP1808887B1 (en) | 2004-10-27 | 2005-10-12 | Production method of semiconductor wafer |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP2004312195A JP4748968B2 (ja) | 2004-10-27 | 2004-10-27 | 半導体ウエーハの製造方法 |
JP2004-312195 | 2004-10-27 |
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WO2006046403A1 true WO2006046403A1 (ja) | 2006-05-04 |
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Country | Link |
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US (1) | US7507146B2 (ja) |
EP (1) | EP1808887B1 (ja) |
JP (1) | JP4748968B2 (ja) |
TW (1) | TWI390616B (ja) |
WO (1) | WO2006046403A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012129416A (ja) * | 2010-12-16 | 2012-07-05 | Shin Etsu Handotai Co Ltd | 半導体ウェーハ及びその製造方法 |
Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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JP6920849B2 (ja) * | 2017-03-27 | 2021-08-18 | 株式会社荏原製作所 | 基板処理方法および装置 |
CN115229602A (zh) * | 2022-09-22 | 2022-10-25 | 苏州恒嘉晶体材料有限公司 | 一种圆片倒角磨削机构及使用方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2002005337A1 (fr) * | 2000-07-10 | 2002-01-17 | Shin-Etsu Handotai Co., Ltd. | Tranche a chanfreinage en miroir, tissu a polir pour chanfreinage en miroir, machine a polir pour chanfreinage en miroir et procede associe |
JP2002299290A (ja) * | 2001-03-30 | 2002-10-11 | Mitsubishi Materials Silicon Corp | 半導体ウェーハの製造方法 |
JP2003340695A (ja) * | 2002-05-30 | 2003-12-02 | Fujikoshi Mach Corp | ウェーハの端面研磨装置 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR0185234B1 (ko) * | 1991-11-28 | 1999-04-15 | 가부시키 가이샤 토쿄 세이미쯔 | 반도체 웨이퍼의 모떼기 방법 |
JPH081493A (ja) * | 1994-06-17 | 1996-01-09 | Shin Etsu Handotai Co Ltd | ウェーハ面取部の鏡面研磨方法および鏡面研磨装置 |
JP2882458B2 (ja) * | 1994-11-28 | 1999-04-12 | 株式会社東京精密 | ウェーハ面取り機 |
JP3828176B2 (ja) * | 1995-02-28 | 2006-10-04 | コマツ電子金属株式会社 | 半導体ウェハの製造方法 |
JP3580600B2 (ja) * | 1995-06-09 | 2004-10-27 | 株式会社ルネサステクノロジ | 半導体装置の製造方法およびそれに使用される半導体ウエハ並びにその製造方法 |
JP3620554B2 (ja) * | 1996-03-25 | 2005-02-16 | 信越半導体株式会社 | 半導体ウェーハ製造方法 |
JPH1190803A (ja) * | 1997-09-11 | 1999-04-06 | Speedfam Co Ltd | ワークエッジの鏡面研磨装置 |
JPH11154655A (ja) * | 1997-11-21 | 1999-06-08 | Komatsu Electron Metals Co Ltd | 半導体ウェハの製造方法 |
JPH11245151A (ja) * | 1998-02-27 | 1999-09-14 | Speedfam Co Ltd | ワークの外周研磨装置 |
JP3334609B2 (ja) * | 1998-05-29 | 2002-10-15 | 信越半導体株式会社 | 薄板縁部の加工方法および加工機 |
JP3328193B2 (ja) * | 1998-07-08 | 2002-09-24 | 信越半導体株式会社 | 半導体ウエーハの製造方法 |
JP3664593B2 (ja) * | 1998-11-06 | 2005-06-29 | 信越半導体株式会社 | 半導体ウエーハおよびその製造方法 |
JP4846915B2 (ja) * | 2000-03-29 | 2011-12-28 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
JPWO2005055302A1 (ja) * | 2003-12-05 | 2007-06-28 | 株式会社Sumco | 片面鏡面ウェーハの製造方法 |
JP2006099936A (ja) * | 2004-08-30 | 2006-04-13 | Hoya Corp | 磁気ディスク用ガラス基板の製造方法、磁気ディスクの製造方法及びガラス基板用の円柱状ガラス母材 |
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2002005337A1 (fr) * | 2000-07-10 | 2002-01-17 | Shin-Etsu Handotai Co., Ltd. | Tranche a chanfreinage en miroir, tissu a polir pour chanfreinage en miroir, machine a polir pour chanfreinage en miroir et procede associe |
JP2002299290A (ja) * | 2001-03-30 | 2002-10-11 | Mitsubishi Materials Silicon Corp | 半導体ウェーハの製造方法 |
JP2003340695A (ja) * | 2002-05-30 | 2003-12-02 | Fujikoshi Mach Corp | ウェーハの端面研磨装置 |
Non-Patent Citations (1)
Title |
---|
See also references of EP1808887A4 * |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012129416A (ja) * | 2010-12-16 | 2012-07-05 | Shin Etsu Handotai Co Ltd | 半導体ウェーハ及びその製造方法 |
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EP1808887A4 (en) | 2009-02-18 |
US20080096474A1 (en) | 2008-04-24 |
US7507146B2 (en) | 2009-03-24 |
JP4748968B2 (ja) | 2011-08-17 |
EP1808887A1 (en) | 2007-07-18 |
JP2006128269A (ja) | 2006-05-18 |
EP1808887B1 (en) | 2011-11-30 |
TWI390616B (zh) | 2013-03-21 |
TW200620447A (en) | 2006-06-16 |
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