Classifications

• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
  • G01R31/302—Contactless testing
  • G01R31/315—Contactless testing by inductive methods
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
  • G01R31/302—Contactless testing
  • G01R31/3025—Wireless interface with the DUT

Definitions

• the present invention relates to an electronic circuit test apparatus suitable for testing an electronic circuit in which communication between substrates such as an IC (Integrated Circuit) bare chip and a PCB (printed circuit board) is performed by inductive coupling.
• substrates such as an IC (Integrated Circuit) bare chip and a PCB (printed circuit board) is performed by inductive coupling.
• the present inventors have implemented a system-in-package in which a plurality of bare chips are encapsulated in one LSI (Large Scale Integration) package by a method in which chips are three-dimensionally mounted and electrically connected by inductive coupling between the chips. Proposed to realize (SiP) (see Patent Document 1).
• LSI Large Scale Integration
• FIG. 3 is a diagram showing the configuration of the electronic circuit of the prior invention.
• This electronic circuit comprises first to third LSI chips 31a to 31c.
• LSI chips are stacked in three layers to form a bus that spans three chips. In other words, one communication channel that can communicate with each other between three parties (three LSI chips) is configured.
• the first to third LSI chips 31a to 31c are stacked vertically, and the chips are fixed to each other with an adhesive.
• first to third transmission coils 33a to 33c used for transmission are formed by wiring, respectively, and first to third reception coils 35a to 35a used for reception are respectively formed.
• 35c is formed by wiring.
• These three pairs of transmitting and receiving coils 33 and 35 are arranged on the first to third LSI chips 31a to 31c so that the centers of the openings coincide with each other. As a result, the three pairs of transmitting and receiving coils 33 and 35 form inductive coupling, and communication is possible.
• the first to third transmission coils 33a to 33c are respectively connected to the first to third transmission circuits 32a to 32c, and the first to third reception coils 35a to 35c are respectively connected to the first to third reception circuits 34a to 34c. 34c is connected.
• the transmission / reception coils 33 and 35 are mounted as three or more turns in a three-dimensional manner within the area allowed for communication using multilayer wiring of process technology.
• the transmission / reception coils 33 and 35 have an optimal shape for communication, and it is necessary to have an optimal number of windings, openings, and line widths. Generally, the transmitter coil 33 is more than the receiver coil 35 / J.
• Patent Document 1 Japanese Patent Application 2004-037242
• test signal is supplied to a chip pad (input pad and Z or test pad) and the chip pad (output pad) is output.
• Z or the test pad) signal (voltage value and Z or current value).
• test pad In addition to the input pad and the output pad, the test pad must be provided as an electronic circuit to be tested. With a multi-function IC or the like, many types of outputs can be output from many types. However, there is a restriction on the design of the electronic circuit because it is necessary to provide a test pad.
• the present invention is particularly suitable for testing an electronic circuit that performs inter-substrate communication by inductive coupling, and can test an electronic circuit without using a test pad. It is an object of the present invention to provide an electronic circuit test apparatus that can be used.
• the electronic circuit test apparatus of the present invention includes a probe having a coil for transmitting and receiving signals.
• the probe is movable in two dimensions, it can be tested with a small number of probes.
• the electronic circuit test apparatus of the present invention includes a probe having a transmission coil for transmitting a signal and a reception coil for receiving the signal.
• the transmission coil and the reception coil are formed by wiring on one substrate, a small electronic circuit can be easily tested.
• the transmitting coil and the corresponding receiving coil are arranged coaxially, so that a test signal is transmitted to a predetermined communication channel and the communication channel force detection signal is received. be able to.
• an electronic circuit can be tested without contact. For this reason, it is not necessary to provide a needle in contact with the pad of the electronic circuit in the electronic circuit testing apparatus, and the life can be extended. In addition, it is not necessary to provide a test node when designing an electronic circuit, and the degree of freedom in circuit design is increased.
• the electrostatic discharge (ESD) protection circuit required for the input / output circuit that is the probe contact part of the electronic circuit is a large transistor used in the circuit. Because of the large capacitance caused by this, it hinders the high-speed input / output circuit, whereas the present invention does not require an ESD protection circuit since it is contactlessly tested.
• I / O operation with the probe can be performed at high speed, and it can be tested on time (slow for testing !, testing at normal operating speed, not operating).
• inductive coupling ie, L coupling
• L coupling itself has the characteristics of a bypass filter, which is advantageous for high-speed operation.
• FIG. 1 is a diagram showing a configuration of an electronic circuit test apparatus according to Embodiment 1 of the present invention and a configuration of an LSI to be tested.
• FIG. 2 is a diagram showing a configuration of an electronic circuit testing apparatus according to Embodiment 2 of the present invention and a configuration of an LSI chip to be tested.
• FIG. 3 is a diagram showing a configuration of an electronic circuit according to the invention of the prior application.
• FIG. 1 is a diagram showing a configuration of an electronic circuit test apparatus according to Embodiment 1 of the present invention and a configuration of an LSI to be tested.
• the electronic circuit test apparatus of the first embodiment tests a completed LSI.
• This electronic circuit test apparatus comprises a tester 11, notches 12 and 13, TxZR ⁇ switch 14, and probe 15.
• the tester 11 creates a test signal, supplies the test signal to the probe 15 via the buffer 12, receives the signal detected by the probe 15 via the buffer 13, and determines the pass / fail of the electronic circuit.
• Buffers 12 and 13 are amplifiers for amplifying signals.
• the TxZ Rx ⁇ switch 14 is a switch for switching the signal flow between transmission and reception.
• connect probe 15 to buffer 12 When transmitting, connect probe 15 to buffer 12, disconnect from buffer 13, and short-circuit the input of notch 13.
• connect probe 15 to buffer 13 When receiving, connect probe 15 to buffer 13, disconnect from notch 12, and open the output of notch 12.
• the probe 15 also has a coil force.
• the magnetic field lines in the vertical direction are radiated, inductively coupled with the coil in the LSI, and the test signal is supplied to the LSI. To detect the signal from the LSI.
• the LSI to be tested has LSI chips 20a and 20b stacked in two layers in this embodiment.
• the LSI chip 20a includes a first transmission coil 21a connected to the first transmission circuit 22a and a first reception coil 23a connected to the first reception circuit 24a.
• the LSI chip 20b includes a second transmission coil 21b connected to the second transmission circuit 22b and a second reception coil 23b connected to the second reception circuit 24b.
• the first and second transmission coils 21a and 21b, and the first and second reception coils 23a and 23b constitute one communication channel.
• the second transmission circuit 22b and the second reception circuit 24b are connected via a pad 25b to a lead 26 that receives the transmission data Txdata and the clock Clk and transmits the reception data Rxdata.
• the 1S LSI chips 20a and 20b (not shown) are provided with electronic circuits for various uses that receive the transmission data Txdata and the clock Clk and transmit the reception data Rxdata. Also, a plurality of such transmission / reception coil sets can be provided to form a plurality of communication channels, and the number of stacked chips can be three or more. If the LSI has multiple communication channels based on inductive coupling, multiple probes 15 may be provided and placed at corresponding positions, or one probe 15 may be moved two-dimensionally on the horizontal plane to move to each position.
• the LSI may be moved.
• the power supply and clock supply to the LSI during testing can also be performed by inductive coupling, but if some direct connections are allowed, the power supply via lead 26 (the lead for the power supply is Show me! / ⁇ , and let's supply the clock, too.
• the probe 15 When actually performing a test, the probe 15 is intervened in a communication channel based on inductive coupling between stacks, a test signal is transmitted from the probe 15, and the probe 15 detects the signal to determine whether the LSI passes or fails. Judge and decide. When a plurality of probes 15 are provided, a signal when one probe 15 sends a test signal may be detected by another probe 15.
• the LSI can be tested with little or no direct contact with the LSI to be tested.
• FIG. 2 is a diagram showing a configuration of an electronic circuit test apparatus according to Embodiment 2 of the present invention and a configuration of an LSI chip to be tested.
• the electronic circuit test apparatus according to the second embodiment tests an LSI chip, and may be one that is still on the wafer and before each LSI chip is cut, or after the cut.
• This electronic circuit test apparatus includes a tester 11, notfers 12, 13, a TxZR switch 14, leads 27, and an LSI chip 20a.
• the electronic circuit test apparatus according to the second embodiment uses the LSI chip 20a in which the first transmitting / receiving coils 21a and 23a are arranged as the probe at a position corresponding to the position of the communication channel of the LSI chip 20b to be tested.
• the configuration of the tester 11, the buffers 12, 13, the Tx / Rx ⁇ switch 14, the transmission / reception coils 21a, 21b, 23a, 23b, and the transmission / reception circuits 22a, 22b, 24a, 24b is the same as that of the first embodiment.
• a lead 27 is connected to the nod 25a to supply a test signal to the LSI chip 20a as a probe and receive a detection signal.
• the power that can be supplied to the LSI chip 20b and the clock by the inductive coupling at the time of the test can be performed by inductive coupling.
• the pad of the figure is ⁇ ⁇ ), and let's supply the clock.
• the LSI chip can be tested with almost no direct contact with the LSI chip to be tested.

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• Engineering & Computer Science (AREA)
• General Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Computer Networks & Wireless Communication (AREA)
• Tests Of Electronic Circuits (AREA)
• Semiconductor Integrated Circuits (AREA)
• Measuring Leads Or Probes (AREA)
• Testing Or Measuring Of Semiconductors Or The Like (AREA)

Priority Applications (1)

Applications Claiming Priority (2)

Publications (1)

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Family Applications (1)

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Cited By (1)

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Citations (5)

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• 2004
  • 2004-09-30 JP JP2004289268A patent/JP5024740B2/ja not_active Expired - Lifetime
• 2005
  • 2005-09-21 KR KR1020077009061A patent/KR101212042B1/ko not_active Expired - Lifetime
  • 2005-09-21 US US11/664,262 patent/US8648614B2/en active Active
  • 2005-09-21 WO PCT/JP2005/017364 patent/WO2006035644A1/ja not_active Ceased
  • 2005-09-28 TW TW094133825A patent/TW200619652A/zh not_active IP Right Cessation

Patent Citations (5)

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