WO2005096364A1 - Dispositif semi-conducteur et procede de fabrication dudit dispositif - Google Patents

Dispositif semi-conducteur et procede de fabrication dudit dispositif Download PDF

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Publication number
WO2005096364A1
WO2005096364A1 PCT/JP2005/006180 JP2005006180W WO2005096364A1 WO 2005096364 A1 WO2005096364 A1 WO 2005096364A1 JP 2005006180 W JP2005006180 W JP 2005006180W WO 2005096364 A1 WO2005096364 A1 WO 2005096364A1
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Prior art keywords
wiring
semiconductor device
metal
circuit
insulating film
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PCT/JP2005/006180
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English (en)
Japanese (ja)
Inventor
Masayoshi Tagami
Yoshihiro Hayashi
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Nec Corporation
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Application filed by Nec Corporation filed Critical Nec Corporation
Priority to JP2006511773A priority Critical patent/JP4946436B2/ja
Publication of WO2005096364A1 publication Critical patent/WO2005096364A1/fr

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    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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Definitions

  • the present invention relates to a semiconductor device, particularly to a semiconductor device having a low dielectric constant film as a wiring interlayer film, and a method of manufacturing the same.
  • the propagation delay in wiring is proportional to the product of the wiring resistance and the capacitance between wirings
  • a material having a low resistivity is used for the wiring material
  • a material having a low dielectric constant is used for the wiring interlayer film. This makes it possible to reduce the propagation delay in the wiring.
  • Cu wiring using Cu or a Cu alloy as a wiring material is generally formed by a damascene (dama scene) method.
  • damascene method after a wiring interlayer film is deposited, a groove is formed from the surface side by a reactive ion etching (RIE) method, and Cu or Cu is filled so as to fill the groove.
  • RIE reactive ion etching
  • the Cu or Cu alloy film other than the Cu or Cu alloy film embedded in the groove is removed by a chemical mechanical polishing (CMP) method or the like, and the film between the wiring layers is removed. And forming a buried Cu wiring!
  • CMP chemical mechanical polishing
  • a method of forming a dummy wiring pattern for CMP in a wiring layer is often used in order to reduce variation in the thickness of the wiring at the time of CMP.
  • FIG. 1 shows an example of a method using a dummy wiring pattern for CMP.
  • the wiring layer (2002) and the insulating layer (2003) are alternately deposited.
  • a metal circuit wiring (2000) is formed in each wiring layer (2002), and a metal via (2004) is formed in the insulating layer (2003).
  • Metal circuit wiring (2000) formed in each wiring layer (2002) is electrically connected to each other via metal via (2004).
  • Each wiring layer (2002) is electrically insulated from the metal circuit wiring (2000).
  • the dielectric constant is reduced and the film strength is also reduced.
  • the wiring interlayer film made of a low dielectric constant film is made of SiO
  • Patent Document 1 discloses an under-pad dummy wiring (10002) under a bonding pad (10001) as shown in FIG. 3 in order to increase the strength under the bonding pad.
  • Non-Patent Document 1 wire bonding is enabled by connecting a dummy pad and a dummy via under a pad in connection with a structure under the pad.
  • Patent Document 1 JP 2001-267323
  • Non-patent Document 1 Y.L.Yang et al., IITC '03 Technical Digest, 2003.6.2, 2.4, P3, Fig. 12, 13
  • the number of wirings and vias that can be arranged under the nod is limited according to the pad area. Therefore, if the strength of the low dielectric constant film, which is the interlayer insulating film, is very low, or if the adhesion between the low dielectric constant film and the films above and below it is very low, dummy wiring under the pad And the number of dummy vias must be huge. In this case, most of the area under the bonding pad is occupied by the dummy wiring and the dummy via. Therefore, it is not a dummy! / ⁇ It is impossible to arrange the wiring and via forming the circuit. No circuit can be formed at the same time. As a result, the chip area increases, and the number of chips that can be collected from one wafer is reduced, resulting in an increase in production cost.
  • the present invention has been made in view of the above-described problems in the conventional example, and has a structure in which the strength of the entire chip is high and the structure is resistant to shocks and stresses during a process and during packaging. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which do not cause problems.
  • An object of the present invention is to further provide a semiconductor device having high structural reliability while reducing production costs, and a method of manufacturing the same.
  • the semiconductor device comprises a semiconductor substrate And at least one interlayer insulating film formed on the semiconductor substrate; and a plurality of wiring layers stacked with the interlayer insulating film interposed therebetween, and a circuit formed on each of the plurality of wiring layers.
  • a semiconductor device in which a wiring, a conductive metal via penetrating through the interlayer insulating film and interconnecting the circuit wirings vertically adjacent to each other, and a powerful multilayer circuit structure are formed; A reinforcing wiring pattern provided on each of the layers, a reinforcing via pattern provided on the inter-layer insulating film and interconnecting the reinforcing wiring patterns adjacent to each other in a vertical direction, and a multilayer support structure capable of providing a force.
  • the multi-layer support structure is characterized in that it is formed in a region of the semiconductor device where the multi-layer circuit structure exists and does not conflict with the multi-layer circuit structure.
  • the CMP flat dummy pattern is formed only on the wiring layer, whereas in the invention according to the first aspect, the regions where the CMP flat dummy wiring patterns overlap each other are connected.
  • a reinforcing via pattern is formed.
  • the structure of the semiconductor device according to the present invention is such that the region where the existing dummy wiring patterns of the upper and lower layers overlap is merely connected by the reinforcing via pattern, so that the arrangement of the wiring in the circuit region is particularly small. It has no effect.
  • the semiconductor device further includes a pad formed on the uppermost layer and electrically transmitting and receiving signals to and from the outside.
  • the multilayer support structure also exists in a region below the pad.
  • the "wiring layer” also serves as an electrically insulating material, and is partially formed with circuit wiring inside! Refers to the layer.
  • a semiconductor device provides a semiconductor substrate, at least one interlayer insulating film formed on the semiconductor substrate, and a plurality of wirings stacked via the interlayer insulating film. And a pad formed on an uppermost layer of the plurality of wiring layers, a circuit wiring formed on each of the plurality of wiring layers, and an upper and lower direction penetrating the interlayer insulating film. And a conductive metal via interconnecting the circuit wiring adjacent to the wiring.
  • a multilayer support structure that also provides a force. At least a part of the multilayer circuit structure is disposed in a region below the pad, and the multilayer support structure is disposed below the pad. , And formed in a region that does not conflict with the multilayer circuit structure.
  • the reinforcing via pattern is formed so as to connect the region under the bonding pad or the region where the reinforcing wiring pattern existing in the wiring layer within a predetermined distance outside the outer edge of the bonding pad overlaps. For this reason, in the region below the bonding pad, it is possible to form a circuit in the region below the bonding pad while increasing the strength against wire bonding. , Process resistance, wire bonding resistance, resin encapsulation resistance, and the like.
  • the semiconductor device preferably further includes a transistor formed on the semiconductor substrate, and the transistor is preferably arranged below the pad.
  • the multilayer support structure is formed not only in a region below the pad but also in a region below a predetermined distance outside the outer periphery of the pad.
  • the predetermined distance is, for example, 10 ⁇ m.
  • a semiconductor device is a semiconductor device, at least one interlayer insulating film formed on the semiconductor substrate, and a plurality of wirings stacked via the interlayer insulating film. And a conductive metal via that penetrates the inter-layer insulating film and interconnects the vertically adjacent circuit wirings, the circuit wiring being formed in each of the plurality of wiring layers.
  • a multilayer support structure comprising a reinforcing via pattern
  • the semiconductor device comprises: a circuit region in which the multilayer circuit structure is formed; and a scribe region in a region around the circuit region, wherein no circuit is formed.
  • the multilayer support structure is formed in the scribing region.
  • a "scribe area" of a semiconductor device is a region outside a circuit region where circuit wiring exists in a semiconductor device, or outside a region below a bonding pad (the periphery of a semiconductor chip). (Near the end). Generally, there are no circuits in the scribe area.
  • the scribe region has a certain width (for example, 100 / zm or more), so that even after the wafer is cut, the scribe region remains near the peripheral edge of the semiconductor chip. It will be.
  • the scribe region of the semiconductor device includes a reinforcing wiring pattern and a reinforcing via pattern connecting the reinforcing wiring patterns existing in the plurality of wiring layers.
  • a multilayer support structure is formed. This enhances the film strength and adhesion of the laminated body composed of the interlayer insulating film and the wiring layer at the peripheral edge of the semiconductor chip, and is caused by the stress at the time of dicing, wire bonding, and sealing of the assembly resin. Peeling of the interlayer insulating film and the wiring layer can be prevented.
  • the multilayer support structure is formed in a region of the circuit region that does not conflict with the multilayer circuit structure.
  • the semiconductor device preferably further includes a pad formed on the uppermost layer and electrically transmitting and receiving signals to and from the outside.
  • the multilayer support structure is also formed in a region below the pad.
  • the multilayer support structure is also formed between the outside of the pad and the scribe area!
  • the length of the reinforcing via pattern in the thickness direction of the semiconductor device is preferably larger than the length of the conductive metal via in the thickness direction of the semiconductor device. Good.
  • the reinforcing via pattern has a slit shape in a cross section of the semiconductor device.
  • the multilayer support structure is formed electrically independent of the circuit wiring and the conductive metal via.
  • the multilayer support structure is formed electrically independent of the circuit wiring, the conductive metal via, and the pad.
  • the multilayer support structure is connected to an element isolation region provided in the semiconductor substrate.
  • the semiconductor device further includes a global wiring in an uppermost layer thereof, and the multilayer support structure formed in the circuit region is connected at one end to the global wiring portion, At the other end, it is preferable that the circuit wiring and the conductive metal via are separated from each other!
  • the multilayer support structure formed in the region below the pad is preferably connected to the pad and another circuit.
  • the reinforcing wiring pattern and the reinforcing via pattern and the circuit wiring and the conductive metal via existing in the same layer are formed of the same material.
  • the ratio of the total area of the conductive metal via and the reinforcing via pattern to the unit area of the interlayer insulating film is 5% or more.
  • a ratio of a total area of the conductive metal via and the reinforcing via pattern to a unit area of the interlayer insulating film is set to 5% or more.
  • the ratio of the total area of the reinforcing via pattern to the unit area of the interlayer insulating film is preferably 5% or more.
  • the reinforcing via pattern connects only areas where the reinforcing wiring patterns overlap each other.
  • the present invention further provides the method for manufacturing a semiconductor device described above, wherein the multilayer support structure is provided.
  • a semiconductor device comprising a step of forming the reinforcing wiring pattern and the reinforcing via pattern to be formed, and the circuit wiring and the conductive metal via existing in the same layer with the same material, respectively. And a method for producing the same.
  • a reinforcing via pattern is formed only in a region where a conventional dummy pattern for CMP (reinforcing wiring pattern) overlaps with each other, productivity is increased without causing an increase in chip area. Can be enhanced. Furthermore, by forming a multilayer support structure, it is possible to suppress the failure of the low dielectric constant interlayer film to be broken or peeled off due to the impact or stress during the manufacturing process and during packaging, and to improve the structural reliability. It is possible to provide a semiconductor device with high reliability.
  • the semiconductor device includes a semiconductor substrate, at least one interlayer insulating film formed on the semiconductor substrate, and a plurality of wiring layers stacked via the interlayer insulating film. And a conductive circuit via formed in each of the plurality of wiring layers and a conductive metal via penetrating through the interlayer insulating film and interconnecting vertically adjacent circuit wirings.
  • a multi-layer support structure wherein the multi-layer support structure is formed in a region that does not conflict with the multi-layer circuit structure in a circuit region of the semiconductor device having the multi-layer circuit structure. In things is there.
  • FIG. 4 is a schematic cross-sectional view showing one embodiment of the semiconductor device according to the first aspect of the present invention.
  • the semiconductor device includes a semiconductor substrate (1001), a transistor (1101) formed on the semiconductor substrate (1001), and a semiconductor substrate (1001) covering the transistor (1101). ), An insulating film (1002) formed thereon, a first wiring layer (1003) formed on the insulating film (1002), and an interlayer insulating film (1006) formed on the first wiring layer (1003). And a second wiring layer (1007) formed on the inter-layer insulating film (1006).
  • the first wiring layer (1003) also becomes a non-conductive material, and the first wiring layer (1003) includes a conductive metal wiring (1004) serving as a circuit wiring and a conductive metal wiring (1004).
  • a metal reinforcing wiring pattern (1005) made of the same conductive material is formed apart from each other.
  • the second wiring layer (1007) also becomes a non-conductive material, and the second wiring layer (1007) includes a conductive metal wiring (1008) serving as a circuit wiring and a conductive metal wiring (1008).
  • the metal reinforcing wiring pattern (1009) made of the same material is formed apart from each other.
  • the interlayer insulating film (1006) sandwiched between the first wiring layer (1003) and the second wiring layer (1007) is provided in the first and second wiring layers (1003, 1007), respectively.
  • a metal reinforcing via pattern (1011) for electrically connecting mutually overlapping areas of the patterns (1005, 1009) is formed.
  • the metal reinforcing via pattern (1011) is made of the same conductive material as the conductive metal via (1010)! RU
  • a multi-layer circuit includes conductive metal wirings (1004, 1008) and conductive metal vias (1010) stacked in the thickness direction of the semiconductor device.
  • a structure is formed.
  • a metal reinforcing wiring pattern (1005, 1009) stacked in the thickness direction of the present semiconductor device, a metal reinforcing via pattern (1011) for interconnecting the metal reinforcing wiring patterns, and a multi-layer supporting structure are formed.
  • the multilayer support structure exists in a gap in a circuit region where the multilayer circuit structure is formed. That is, the multilayer support structure is formed in the region where the multilayer circuit structure does not exist, just like the multilayer circuit structure does not conflict with the inside of the circuit region where the multilayer circuit structure is formed. .
  • the reinforcing wiring patterns (1005, 1009) forming the multilayer support structure and the conductive metal wirings (1004, 1008) existing in the same wiring layer Are formed of the same conductive material
  • the metal reinforcing via pattern (1011) forming the multilayer support structure and the conductive metal via (1010) existing in the same interlayer insulating film are the same conductive material.
  • the reinforcing wiring pattern (1005, 1009) and the conductive metal wiring (1004, 1008) may be made of different materials.
  • the via pattern (1011) and the conductive metal via (1010) may be formed of mutually different conductive materials. However, by forming the same material with the same force, there is an advantage that the number of steps in the manufacturing process can be reduced.
  • the multilayer support structure as described above includes a plurality of wiring layers and interlayer insulating layers stacked on the semiconductor substrate (1001) in the thickness direction of the semiconductor device. It is sufficient that the film is formed over at least two layers of the film.
  • this multilayer support structure includes conductive metal wirings (1004, 1008) and conductive metal vias.
  • the multilayer circuit structure composed of (1010) may also be electrically insulated, or may be electrically connected to the multilayer circuit structure.
  • the multilayer support structure is connected to the multilayer circuit structure only at one end thereof, and is electrically connected at the other end.
  • the multilayer circuit structure is electrically isolated, that is, electrically open.
  • the multi-layer support structure may be such that the force of the second wiring layer (1007), which is the uppermost layer of the present semiconductor device, is also extended to the semiconductor substrate (1001). It may be one that terminates inside the laminated body composed of the interlayer insulating film.
  • FIGS. 5 to 8 are cross-sectional views schematically showing the structure of another embodiment of the semiconductor device according to the first aspect of the present invention.
  • the semiconductor device according to the embodiment shown in FIGS. 5 to 8 is similar to the semiconductor device according to the embodiment shown in FIG. 4, and includes a semiconductor substrate (1001) and a semiconductor substrate (1001).
  • the first wiring layer (1003) also becomes a non-conductive material, and the first wiring layer (1003) includes a conductive metal wiring (1004) serving as a circuit wiring and a conductive metal wiring (1004). From the same conductive material The metal reinforcing wiring pattern (1005) is formed apart from each other.
  • the second wiring layer (1007) also becomes a non-conductive material, and the second wiring layer (1007) includes a conductive metal wiring (1008) serving as a circuit wiring and a conductive metal wiring (1008).
  • the metal reinforcing wiring pattern (1009) made of the same material is formed apart from each other.
  • the interlayer insulating film (1006) sandwiched between the first wiring layer (1003) and the second wiring layer (1007) is provided in the first and second wiring layers (1003, 1007), respectively.
  • a metal reinforcing via pattern (1011) for electrically connecting mutually overlapping areas of the patterns (1005, 1009) is formed.
  • the metal reinforcing via pattern (1011) is made of the same conductive material as the conductive metal via (1010)! RU
  • the third wiring layer (1013) is made of a non-conductive material, and global wiring (power supply wiring, 1015) is formed in the third wiring layer (1013).
  • the global wiring (1015) is a wiring having a wiring length relatively longer than a conductive metal wiring (1004, 1008) which is a local wiring formed below the global wiring (1015). It is.
  • the wiring between adjacent logic circuits is performed by lower-level local wiring (1004, 1008) with a finer wiring pitch, and the wiring between distant logic circuits is reduced.
  • the wiring is performed by the global wiring (1015) in the upper layer.
  • the global wiring (1015) has a larger wiring thickness and a wider wiring width than the local wiring (1004, 1008), and has a wider wiring interval.
  • the semiconductor devices according to the embodiments shown in FIGS. 5 to 8 have the above-described common structure, but have the following differences.
  • the metal reinforcing wiring pattern (1009) of the multilayer support structure includes a metal reinforcing via pattern (1014) provided in the second interlayer insulating film (1012). ), And the multilayer support structure is electrically connected at one end to the global wiring (1015) via the reinforcing via pattern (1014).
  • the multi-layer support structure at the other end, has a metal layer formed in the first wiring layer (1003).
  • a metal reinforcing wiring pattern (1005) is formed. That is, the multi-layer support structure terminates inside a stacked body composed of a plurality of wiring layers and an interlayer insulating film formed on the semiconductor substrate (1001).
  • the multilayer support structure is connected at one end to the global wiring (1015).
  • the multi-layer support structure has a metal reinforcing wiring pattern (1005) formed in the first wiring layer (1003) at the other end. 1002) are connected to the reinforcing via pattern (1017) provided in the semiconductor substrate (1001) through the reinforcing via pattern (1017). It is supported by.
  • the multilayer support structure is a structure that is not connected to the global wiring (1015) and is electrically separated from the global wiring (1015). ing.
  • the multilayer support structure is not connected to the global wiring (1015), and the power of the global wiring (1015) is electrically separated.
  • the multilayer support structure has a metal reinforcing via pattern (1017) provided in the insulating film (1002) at the other end. And is supported by an element isolation region (insulating layer, 1016) of the semiconductor substrate (1001) via a metal reinforcing via pattern (1017).
  • FIG. 9 shows an equivalent circuit when the multilayer support structure is connected at one end to the global wiring (1015) as in the semiconductor device according to the embodiment shown in FIGS. 5 and 6. It is a circuit diagram.
  • the multilayer support structure forms a capacitance between the semiconductor substrate (1001) or the interlayer insulating film
  • the multilayer support structure has a decoupling capacitance with respect to the global wiring (1015) shown as a resistance. Functions as (1112).
  • one end of the multilayer support structure is connected to the global wiring (1015).
  • the uppermost layer of the semiconductor device is reinforced with a multilayer support structure.
  • the multilayer support structure has a decoupling capacitance.
  • the circuit plays the role of a circuit as in (1112), the power supply line can be stabilized.
  • the multilayer support structure When the multilayer support structure is connected to the element isolation region (1016) provided in the semiconductor substrate (1001) as in the semiconductor device according to the embodiment shown in FIGS. Since the supporting structure is supported by the high-strength substrate (1001), the supporting structure has high structural strength, and the strength of the overall structure of the semiconductor device is also increased.
  • the structure of only the circuit region of the semiconductor device has been mainly described.
  • the semiconductor device according to the first embodiment electrically transmits and receives signals to and from the outside.
  • the semiconductor substrate (1001) On the semiconductor substrate (1001).
  • a multilayer support structure can be formed in the circuit region, and in addition, a similar multilayer support structure can be formed in the region below the pad.
  • the length of the metal reinforcing via pattern (1011) forming a part of the multilayer support structure in the thickness direction of the semiconductor device is the same as that of the conductive metal via (1010) in the thickness direction of the semiconductor device. It can be larger than the length. This makes it possible to improve the adhesion to the metal reinforcing wiring patterns (1005, 1009) in the multi-layer support structure and the strength of the interlayer insulating film. It is possible to prevent film peeling and film destruction due to impact and stress applied during packaging.
  • the shape of the metal reinforcing via pattern (1011) in the cross section of the semiconductor device is not particularly limited, and may be various shapes such as a rectangle, a hole, and a slit. It can take the form of For example, by making the shape of the metal reinforcing via pattern (1011) into a slit shape, it is possible to increase the length of the conductive metal via (1010) in the thickness direction of the semiconductor device without increasing the cross-sectional area. Can be.
  • the ratio of the total area of the conductive metal via (1010) and the metal reinforcing via pattern (1011) to the unit area of the interlayer insulating film is not less than power%. More preferably, it is more preferably 10% or more. Form conductive metal vias (1010) and metal reinforcing via patterns (1011) to satisfy these conditions. By doing so, the occurrence of defects during the chemical mechanical polishing (CMP) process can be reduced.
  • CMP chemical mechanical polishing
  • the material of the interlayer insulating films (1006, 1012) is not particularly limited.
  • inorganic materials such as SiN, SiOC, SiC, SiCN, SiO
  • a film called a low dielectric constant film that is, a film having a material strength lower than that of SiO. Examples of combinations are:
  • the local wiring is formed of a low-dielectric-constant film
  • the global wiring is formed of a film of SiO or the like having higher film strength than the low-dielectric-constant film.
  • the low dielectric constant film include various organic polymers, MSQ, HSQ, and carbon-containing silicon oxide film (SiOCH) formed by a CVD method or a coating method.
  • the force that can be achieved is not particularly limited to these.
  • the organic polymer for example, polyimide, polytetrafluoroethylene, polyallyl ether, polybenzoxazole, polyolefin, and polyamide can be used.
  • the organic polymer is not limited thereto.
  • conductive metal wiring (1004, 1008) conductive metal via (1010), metal reinforcing wiring pattern (1005, 1009) and metal reinforcing via pattern (1011)
  • Cu or Cu It is preferable to use an alloy, but it is not limited to these.
  • A is an A1 alloy, and other metals such as W, Ni, Cr, Ti, and Ag or alloys thereof, for example, W—Ti, A1 — Intermetallic compounds such as —W, Al—Ni, and silicide compounds can be used.
  • the semiconductor substrate (1001) for example, a silicon single crystal substrate, various compound semiconductor substrates, or the like can be used.
  • the conductive metal wiring (1004, 1008), the conductive metal via (1010), the metal reinforcing wiring pattern (1005, 1009), and the metal reinforcing via pattern (1011) may include various modes which are not particularly limited.
  • the size, shape, number of wirings, and other factors of the conductive metal wirings (1004, 1008) in each wiring layer can be arbitrary.
  • the method for manufacturing the semiconductor device according to the first embodiment is not particularly limited.
  • Damascene It can be formed using a method.
  • 10 to 19 are cross-sectional views showing respective steps in a damascene method as a method for manufacturing the semiconductor device shown in FIG.
  • FIGS. 10 to 19 an example of a method for manufacturing the semiconductor device shown in FIG. 6 will be described with reference to FIGS.
  • an element isolation region (1016) is formed on the surface of a semiconductor substrate (1001).
  • the transistor (1101) is mounted on the semiconductor substrate (1001).
  • the insulating film (1) is formed on the semiconductor substrate (1001) by, for example, a CVD method or a coating method.
  • a reinforcing via turn (1017) and a conductive metal via (1113) are formed inside the insulating film (1002).
  • the first wiring layer (a)
  • a predetermined portion of the first wiring layer (1003) is etched by a method such as the RIE method to form a wiring groove (1018) in the first wiring layer (1003).
  • the wiring groove (1018) is formed corresponding to the formation position of the conductive metal wiring (1004) and the reinforcing wiring pattern (1005).
  • the metal is removed, for example, so that the wiring groove (1018) is buried.
  • CMP chemical mechanical polishing
  • a first interlayer insulating film (1006) is deposited on the first wiring layer (1003) on which 5) is formed.
  • the first interlayer insulating film (1006) is etched in the same manner as above to form a via hole (1019) in the first interlayer insulating film (1006).
  • a metal is deposited in the via hole (1019), and excess metal is removed by a CMP method to form a conductive metal via (1010) and a reinforcing via pattern (1011). Form.
  • a second wiring layer (1007) is formed on the first interlayer insulating film (1006).
  • a predetermined portion of the second wiring layer (1007) is etched by a method such as the RIE method to form a wiring groove (1020) in the second wiring layer (1007).
  • the wiring groove (1020) is formed corresponding to the formation position of the conductive metal via (1010) and the reinforcing via pattern (1011).
  • a metal is deposited by, for example, a sputtering method so that the wiring groove (1020) is filled. Then, excess metal is removed by a chemical mechanical polishing (CMP) method or the like, and a conductive metal wiring (1008) and a reinforcing wiring pattern (1009) are formed in the second wiring layer (1007).
  • CMP chemical mechanical polishing
  • a second interlayer insulating film (1012) is formed on the second wiring layer (1007).
  • the second interlayer insulating film (1012) is etched in the same manner as described above, and the second interlayer insulating film (1012) is etched.
  • a via hole is formed in (1012).
  • a metal is deposited in the via hole, and a surplus metal is removed by a CMP method to form a reinforcing via pattern (1014) in the second interlayer insulating film (1012).
  • a third wiring layer (1013) is formed on the second interlayer insulating film (1012).
  • a predetermined portion of the third wiring layer (1013) is etched by, eg, RIE to form a wiring groove in the third wiring layer (1013).
  • a metal is deposited in the wiring groove, and a surplus metal is removed by a chemical mechanical polishing (CMP) method to form a global wiring (1015) in the third wiring layer (1013).
  • CMP chemical mechanical polishing
  • the semiconductor device shown in FIG. 6 is formed.
  • a single damascene process in which the conductive metal via (1010) and the conductive metal wiring (1006, 1008) are separately formed is adopted.
  • a dual damascene process can be employed.
  • the dual damascene process for example, after a first interlayer insulating film (1006) and a second wiring layer (1007) are formed, a via hole (1019) and a wiring groove (1020) are formed. A metal film is deposited in (1019) and the wiring groove (1020), and excess metal is removed by a CMP method, so that a conductive metal via (1010) and a conductive metal wiring (1008) are formed at a time. (Conductive metal wiring under pad area)
  • a semiconductor device includes a semiconductor substrate, at least one interlayer insulating film formed on the semiconductor substrate, and a plurality of wiring layers stacked with the interlayer insulating film interposed therebetween.
  • a conductive metal via interconnecting the conductive metal vias a multi-layer circuit structure comprising: a reinforcing wiring pattern provided on each of a plurality of wiring layers; and an inter-layer insulating film; A reinforcing via pattern for interconnecting reinforcing wiring patterns adjacent to each other in the vertical direction, and a multilayer supporting structure that provides a strong force. At least a part of the multilayer circuit structure is arranged in a region below the pad. Below, is a multilayer support structure Are formed in a region that does not conflict with the multilayer circuit structure.
  • FIG. 20 is a schematic cross-sectional view showing one embodiment of a semiconductor device according to the second aspect of the present invention.
  • the semiconductor device includes a semiconductor substrate (1021), a transistor (1101) formed on the semiconductor substrate (1021), and a semiconductor covering the transistor (1101).
  • the first wiring layer (1023) is made of a non-conductive material, and the first wiring layer (1023) includes a conductive metal wiring (1024) serving as a circuit wiring and a conductive metal wiring (1024). ) And a metal reinforcing wiring pattern (1025) made of the same conductive material as that of (1) are formed apart from each other.
  • the second wiring layer (1027) is made of a non-conductive material.
  • the second wiring layer (1027) has a conductive metal wiring (1028) serving as a circuit wiring and a conductive metal wiring (1028).
  • a metal reinforcing wiring pattern (1029) made of the same material as that of (1) are formed apart from each other.
  • the interlayer insulating film (1026) sandwiched between the first wiring layer (1023) and the second wiring layer (1027) is provided in the first and second wiring layers (1023, 1027), respectively.
  • a metal reinforcing via pattern (1031) for electrically connecting mutually overlapping regions to each other.
  • the metal reinforcing via pattern (1031) is made of the same conductive material as the conductive metal via (1030)! RU
  • a multilayer circuit includes conductive metal wirings (1024, 1028) and conductive metal vias (1030) stacked in the thickness direction of the semiconductor device.
  • a structure is formed.
  • a metal reinforcing wiring pattern (1025, 1029) stacked in the thickness direction of the present semiconductor device, a metal reinforcing via pattern (1031) for interconnecting the metal reinforcing wiring patterns (1025, 1029), and a multilayer supporting structure are formed.
  • the multilayer support structure exists in a gap in a circuit region where the multilayer circuit structure is formed. That is, the multilayer support structure is formed in the region where the multilayer circuit structure does not exist, just like the multilayer circuit structure does not conflict with the inside of the circuit region where the multilayer circuit structure is formed. .
  • the multilayer support structure is formed in a region below the metal wire bonding pad (1040), and a part of the multilayer circuit structure is also provided. It is formed in a region below the metal wire bonding pad (1040). Some of the plurality of transistors (1101) are arranged in a region below the metal wire bonding pad (1040).
  • the multilayer support structure includes a region where the metal reinforcing wiring patterns (1025, 1029) of the first and second wiring layers (1023, 1027) overlap with each other and a metal reinforcing via pattern (103). 1), the area occupied by the multilayer support structure can be reduced, and the area under the metal wire bonding pad (1040) can be electrically conductive like the other circuit areas. It is possible to dispose a conductive metal wiring (1024, 1028) and a conductive metal via (1030), or a transistor (1101).
  • the reinforcing wiring patterns (1025, 1029) forming the multilayer support structure and the conductive metal wirings (1024, 1028) existing in the same wiring layer Are formed of the same conductive material
  • the metal reinforcing via pattern (1031) forming the multilayer support structure and the conductive metal via (1030) existing in the same interlayer insulating film are formed of the same conductive material.
  • the reinforcing wiring pattern (1025, 1029) and the conductive metal wiring (1024, 1028) may be formed of mutually different materials.
  • the metal reinforcing via pattern (1031) existing in the same interlayer insulating film may be used.
  • the conductive metal via (1030) may be formed of a conductive material different from the conductive metal via (1030). However, by forming the same material with the same force, there is an advantage that the number of steps in the manufacturing process can be reduced.
  • the multilayer support structure as described above has the following features in the thickness direction of the semiconductor device: It is sufficient that at least two or more of a plurality of wiring layers and interlayer insulating films stacked on the semiconductor substrate (1001) are formed.
  • this multilayered support structure includes conductive metal wiring (1024, 1028) and conductive metal via.
  • the multilayer circuit structure consisting of (1030) or metal wire bonding pads (1040) may also be electrically insulated or electrically connected to the multilayer circuit structure or metal wire bonding pads (1040) It may be something.
  • the multilayer support structure is connected to the multilayer circuit structure only at one end thereof, and is electrically connected to the other end thereof.
  • the multilayer circuit structure is electrically isolated, that is, electrically grounded.
  • the multilayer support structure may extend from the second wiring layer (1027), which is the uppermost layer of the semiconductor device, to the semiconductor substrate (1021), or may be a multilayer circuit structure. It may be terminated at the department.
  • the multilayer support structure can be connected to the element isolation region (1016), similarly to the embodiment shown in FIG. It is possible.
  • FIG. 21 and FIG. 22 are plan views schematically showing an example of an existing area of the multilayer support structure.
  • the multi-layer support structure has a predetermined distance outside the outer periphery of the bonding pad (351, 352) as well as the area below the bonding pad (351, 352). It can also be formed in the area below the range (350).
  • the range (350) of the predetermined distance outside the outer periphery of the bonding pads (351, 352) is not particularly limited. As will be described later, when the multilayer support structure extends to a region outside the outer periphery of the bonding pad, the distance from the outer edge of the bonding pad to the outermost periphery of the multilayer support structure, and the distance between the bonding pad and the bonding wire. Investigation of the relationship with the adhesion strength between them revealed that the multilayer support structure was arranged within a distance range of about 10 m, compared to the case where the multilayer support structure was formed only in the area below the bonding pad. , Good improvement in adhesion strength has been observed. For this reason, by setting the range of the predetermined distance (350) to about 10 m, the adhesion strength between the bonding pad and the bonding wire can be improved.
  • FIG. 21 shows a case where the distance between adjacent bonding pads (351) is 20 ⁇ m, and the number of multilayer circuits within a range (350) of a distance of 10 ⁇ m outside the bonding pads (351) is increased.
  • An example of arranging structures is shown.
  • FIG. 22 shows that, when the distance between adjacent bonding pads (352) is less than 10 m, a multilayer circuit structure within a range (350) up to a distance of 10 ⁇ m outside the bonding pads (352).
  • An example of arranging is shown below.
  • the semiconductor device of the metal reinforcing via pattern (1031) forming a part of the multilayer support structure is provided.
  • the length of the device in the thickness direction can be larger than the length of the conductive metal via (1030) in the thickness direction of the semiconductor device. This makes it possible to improve the adhesion to the metal reinforcing wiring patterns (1025, 1029) in the multilayer support structure and improve the strength of the interlayer insulating film. Peeling and film destruction can be prevented.
  • the shape of the metal reinforcing via pattern (1031) in the cross section of the semiconductor device is not particularly limited, and may be various shapes such as a rectangle, a hole, and a slit. Can be taken. For example, by making the shape of the metal reinforcing via pattern (1031) into a slit shape, it is possible to increase the length of the conductive metal via (1030) in the thickness direction of the semiconductor device without increasing the cross-sectional area. Can be.
  • the ratio of the total area of the conductive metal via (1030) and the metal reinforcing via pattern (1031) to the unit area of the interlayer insulating film is not less than power%. More preferably, it is more preferably 10% or more.
  • the material of the semiconductor substrate is not limited at all, and the same materials as those described in the semiconductor device according to the first embodiment can be used.
  • the conductive metal wiring (1024, 1028), the conductive metal via (1010), the metal reinforcing wiring pattern (1005, 1009), and the metal reinforcing via pattern (1031) may include various modes which are not particularly limited.
  • the size, shape, number of wirings, and other factors in each wiring layer of the conductive metal wirings (1024, 1028) can be arbitrary.
  • the second wiring layer (1027), which is the uppermost layer of the semiconductor device, is provided below the wire bonding pad (1040).
  • the uppermost layer of the semiconductor device, or a plurality of upper layers is formed of the same material as the conductive metal wiring.
  • a large-area wiring layer pad may be formed to support the bonding pad (104).
  • the method for manufacturing the semiconductor device according to the second aspect is not particularly limited, as in the case of the semiconductor device according to the first aspect.
  • it can be formed using a damascene method.
  • a semiconductor device includes a semiconductor substrate, at least one interlayer insulating film formed on the semiconductor substrate, and a plurality of wiring layers stacked with the interlayer insulating film interposed therebetween.
  • a multilayer circuit structure is formed, comprising: a circuit wiring formed in each of a plurality of wiring layers; and a conductive metal via penetrating an interlayer insulating film and interconnecting vertically adjacent circuit wirings.
  • the semiconductor device includes a circuit region in which the multilayer circuit structure is formed, and a scribe region which is a region around the circuit region and in which no circuit is formed. hand
  • the multilayer support structure is formed in the scribe area.
  • FIG. 23 is a schematic cross-sectional view showing one embodiment of a semiconductor device according to the third aspect of the present invention.
  • the semiconductor device includes a semiconductor substrate (1061), a transistor (1101) formed on the semiconductor substrate (1061), and a semiconductor covering the transistor (1101).
  • the first wiring layer (1063) is made of a non-conductive material, and the first wiring layer (1063) has a conductive metal wiring (1091) serving as a circuit wiring in the circuit area (1200). And metal reinforcing wiring patterns (1081, 1086) having the same conductive material strength as the conductive metal wiring (1091) are formed apart from each other.
  • a metal reinforcing wiring pattern (1071) having the same conductive material strength as the conductive metal wiring (1091) is formed in the scribe region (1300).
  • the second wiring layer (1065) is made of a non-conductive material, and the second wiring layer (1065) has a conductive metal wiring (1093) serving as a circuit wiring in the circuit area (1200). And metal reinforcing wiring patterns (1083, 1088) having the same material strength as the conductive metal wiring (1093) are formed apart from each other.
  • a metal reinforcing wiring pattern (1073) having the same conductive material strength as that of the conductive metal wiring (1093) is formed in the scribe region (1300).
  • the third wiring layer (1067) is made of a non-conductive material, and the third wiring layer (1067) has a conductive metal wiring (1095) serving as a circuit wiring in the circuit area (1200). And a metal reinforcing wiring pattern (1085) having the same material strength as the conductive metal wiring (1095) are formed apart from each other.
  • a metal reinforcing wiring pattern (1075) having the same conductive material strength as the conductive metal wiring (1095) is formed in the scribe region (1300).
  • a part of the conductive metal wiring (1095) formed in the uppermost third wiring layer (1067) has a large area, and the large area wiring Form a layer pad (1095B)! / The wire bonding pad (1040) is formed above the large area wiring layer pad (1095B).
  • the first interlayer insulating film (1064) sandwiched between the first wiring layer (1063) and the second wiring layer (1065) has first and second layers in the circuit region (1200). Conductors for electrically connecting the conductive metal wires (1091, 1093) provided in the two wiring layers (1063, 1065), respectively. A metal that electrically connects an electrically conductive metal via (1092) and a region where the metal reinforcing wiring patterns (1081, 1083) provided in the first and second wiring layers (1063, 1065) respectively overlap each other. A reinforcing via pattern (1082, 1087) is formed. The metal reinforcing via patterns (1082, 1087) are formed of the same conductive material as the conductive metal via (1092).
  • the metal reinforcing wiring patterns (1010) provided in the first and second wiring layers (1063, 1065) in the scribe region (1300), respectively.
  • the second interlayer insulating film (1066) sandwiched between the second wiring layer (1065) and the third wiring layer (1067) has the second and third wiring layers in the circuit region (1200).
  • a conductive metal via (1094) for electrically connecting the conductive metal wirings (1093, 1095) provided in the wiring layers (1065, 1067) to each other; and second and third wiring layers (1065, 1065). 1067) are provided with metal reinforcing via patterns (1084, 1089) for electrically connecting mutually overlapping regions provided with metal reinforcing wiring patterns (1083, 1085).
  • the metal reinforcing via patterns (1084, 1089) are formed of the same conductive material as the conductive metal via (1094).
  • the metal reinforcing wiring patterns (10 73) provided in the second and third wiring layers (1065, 1067) in the scribe region (1300), respectively. , 1075) are formed with a metal reinforcing via pattern (1074) for electrically connecting mutually overlapping regions to each other.
  • the conductive metal stacked in the thickness direction of the semiconductor device below the wire bonding pad (1040) in the circuit region (1200) Wirings (1091, 1093, 1095), conductive metal vias (1092, 1094), and a multi-layer circuit structure are formed.
  • the force also forms a multilayer support structure.
  • Multi-layer support The structure exists in a gap in a circuit region where the multilayer circuit structure is formed. That is, the multilayer support structure is formed in a region where the multilayer circuit structure does not exist so as not to conflict with the multilayer circuit structure inside the circuit region (1200) where the multilayer circuit structure is formed.
  • the metal reinforcing wiring patterns (1071, 1073, 1075) stacked in the thickness direction of the semiconductor device and the metal reinforcing via patterns (107, 1073, 1075) interconnecting the metal reinforcing wiring patterns (1071, 1073, 1075) are also provided.
  • 1072, 1074) also form a multilayer support structure.
  • a metal reinforced via pattern (1089) is provided on the interlayer insulating film (1066) and supports the metal reinforced wiring pattern (1088) on the large area wiring layer pad (1095B) on the top, and a multi-layered support structure is provided. ing.
  • FIG. 24 is a plan view schematically showing a positional relationship between the circuit region (1200) and the scribe region (1300) in the semiconductor device according to the embodiment shown in FIG. 23, and FIG. 25 is an enlarged plan view of a region B shown in FIG.
  • the scribe region (1300) in the semiconductor device is defined by the conductive metal wiring (1091, 1093, 1095) and the conductive metal via (1092, 1094). It is located outside the circuit area (1200) (including the area below the wire bonding nod (1040)) where the multilayer circuit structure to be formed exists, and the outer peripheral edge of the circuit area (1200) and the peripheral edge of the semiconductor chip. Refers to the area between E and Generally, there are no circuits in the scribe area (1300).
  • the portion indicated by the symbol X existing in one corner of the semiconductor chip represents a "cross-shaped mark".
  • the cross mark X has a cross shape literally on the wafer before chip cutting, and is used for alignment when dicing the wafer. This is the mark used.
  • Each semiconductor chip (semiconductor device) after dicing has an almost L-shaped shape as shown in FIG. , And remain at the four corners of the semiconductor chip.
  • the first to third scribe regions (1300) outside the circuit region (1200) are located.
  • a multi-layered support structure composed of metal reinforcing via patterns (1072, 1074) for electrically connecting the metal reinforcing wiring patterns (1071, 1073, 1075) to each other is formed.
  • the reinforcing wiring patterns (1071, 1073, 1075) forming the multilayer support structure and the conductive metal wirings (1091, 1093, 1095) are formed of the same conductive material, and furthermore, the metal reinforcing via patterns (1072, 1074) forming the multilayer support structure and the conductive metal vias (1092) existing in the same interlayer insulating film are formed. , 1094) is not necessarily limited to the force formed of the same conductive material.
  • the reinforcing wiring pattern (1071, 1073, 1075) and the conductive metal wiring (1091, 1093, 1095) may be formed of mutually different materials.
  • metal reinforcing via patterns existing in the same interlayer insulating film The (1072, 1074) and the conductive metal vias (1092, 1094) may be formed of mutually different conductive materials. However, there is an advantage in that the number of steps in the manufacturing process can be reduced by forming the same material while using force.
  • the position of the multilayer support structure in the scribe region (1300) is not particularly limited, and is arranged at an arbitrary position in the scribe region (1300). Possible Force It is desirable to dispose the multilayer support structure at each corner of the semiconductor chip, that is, in the region below the cross mark X as shown in FIG.
  • FIG. 27 is a schematic cross-sectional view showing another embodiment of the semiconductor device according to the third aspect of the present invention.
  • FIG. 28 shows a circuit region and a scribe region in the semiconductor device shown in FIG. 29 is a plan view schematically showing the positional relationship of FIG. 29, and
  • FIG. 29 is an enlarged plan view of a region E shown in FIG.
  • the semiconductor device according to the embodiment shown in FIG. 27 differs from the semiconductor devices according to the embodiment shown in FIGS. 23, 24 and 25 from the position where the wire bonding pad (1040) is formed. The difference is also that a shield (1100) is formed between a circuit region on the outer peripheral side of the chip, that is, the outside of the wire bonding pad (1040) and the scribe region (1300).
  • the shield (1100) has a laminated body strength in which a metal reinforcing wiring pattern and a metal reinforcing via pattern are stacked.
  • the shield (1100) is arranged continuously over the entire periphery along the outer peripheral edge of the semiconductor chip. Therefore, it is possible to effectively prevent moisture from entering the circuit region (1200) from outside the semiconductor device. Further, since the shield (1100) is also a multilayer support structure including a metal reinforcing wiring pattern and a metal reinforcing via pattern, it also exerts an effect of increasing the strength and adhesion at the outer peripheral edge of the semiconductor chip.
  • the multilayer support structure may be formed at least in the scribe region (1300) as long as the condition is satisfied.
  • the following embodiment can be adopted.
  • a multilayer support structure is formed in a region below the scribe region (1300) and the wire bonding pad (1040), and a multilayer support structure is not formed in the circuit region (1200).
  • a multi-layer support structure is formed in the scribe area (1300) and the circuit area (1200), and the multi-layer support structure is not formed in a region below the wire bonding pad (1040).
  • the multilayer support structure has a structure in the thickness direction of the semiconductor device. It is sufficient that at least two or more of a plurality of wiring layers and interlayer insulating films stacked on the semiconductor substrate (1061) are formed.
  • the multilayer support structure is electrically insulated from the multilayer circuit structure or the wire bonding pad (1040) that also has the force of the conductive metal wiring (1091, 1093, 1095) and the conductive metal via (1092, 1094). It may be one that is electrically connected to a multilayer circuit structure or a wire bonding pad (1040).
  • the multilayer support structure is connected to the multilayer circuit structure only at one end thereof, and is electrically connected at the other end.
  • the multilayer circuit structure is electrically isolated, that is, electrically grounded.
  • the scribe region (1300) when the element isolation region (1016) is provided in the semiconductor substrate (1061), similarly to the semiconductor device according to the first embodiment of the present invention, the multi-layer support is provided.
  • the structure can be connected to the element isolation region (1016).
  • the multilayer support structure may be configured such that the force of the third wiring layer (1067), which is the uppermost layer of the present semiconductor device, is also extended to the semiconductor substrate (1061), or a plurality of wiring layers and It may be one that terminates inside the laminated body composed of the interlayer insulating film.
  • the metal reinforcing via pattern (1082, 1084) forming a part of the multilayer support structure in the thickness direction of the semiconductor device.
  • the length can be larger than the length of the conductive metal via (1092, 1094) in the thickness direction of the semiconductor device. This makes it possible to improve the adhesion to the metal-reinforced wiring patterns (1081, 1083, 1085) and the strength of the interlayer insulating film in the multi-layered support structure. It is possible to prevent film peeling and film destruction due to the above.
  • the metal reinforcement in the cross section of the semiconductor device (the surface orthogonal to the paper surface in FIGS. 23 and 27)
  • the shape of the via pattern (1082, 1084) is not particularly limited, and may take various forms such as a rectangle, a hole, and a slit.
  • the shape of the metal reinforcing via pattern (1082, 1084) into a slit shape, it is possible to increase the length of the conductive metal via (1092, 1094) in the thickness direction of the semiconductor device without increasing the cross-sectional area. It can be.
  • the ratio of the total area of the metal reinforcing via patterns (1072, 1074) to the unit area of the interlayer insulating film in the scribe region (1300) is 5% or more. More preferably, it is more preferably 10% or more.
  • the semiconductor device also includes an interlayer insulating film material, a conductive metal wiring (circuit wiring), a conductive metal via, a reinforcing wiring pattern, a conductive material forming a reinforcing via, and
  • the material of the semiconductor substrate is not limited at all, and the same materials as those described in the semiconductor device according to the first embodiment can be used.
  • the method for manufacturing a semiconductor device according to the third embodiment is not particularly limited, as in the case of the semiconductor device according to the first embodiment.
  • it can be formed using a damascene method.
  • FIG. 30 is a sectional view of one embodiment of the semiconductor device according to the first aspect of the present invention described above.
  • the semiconductor device according to this example includes a semiconductor substrate (111) and an insulating film (112) formed on the semiconductor substrate (111).
  • the semiconductor substrate (111) is a single crystal silicon substrate.
  • the insulating film (112) is made of borophosphosilicate 'glass (BPSG: borophosphosilic). ate glass), phosphosilicate glass (PSG: phosphosilicate glass), silicon oxide silicon (SiO 2), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxyfluoride (SiOF),
  • SiC silicon carbide
  • SiCN silicon carbonitride
  • a first wiring layer (113) is formed on the insulating film (112).
  • the first wiring layer (113) is made of an organic polymer of a low dielectric constant material, MSQ
  • HSQ a carbon-containing silicon oxide film.
  • a stacked film strength with SiN, SiOC, SiC, SiCN, SiO, etc. forming an etching stopper and a node mask can also be formed.
  • the first wiring layer (113) includes a metal circuit wiring (or a conductive metal wiring) (115) for electrically connecting a circuit and a metal reinforcing wiring pattern having no electrical connection to the circuit. (116) are formed.
  • a first interlayer insulating film (117) is formed on the first wiring layer (113).
  • a conductive metal via (118) for electrically connecting the upper and lower metal circuit wirings (115, 121) to each other, and an upper and lower metal reinforcing wiring pattern are provided.
  • a metal reinforcing via pattern (119) to be connected is formed.
  • the first interlayer insulating film (117) is made of an organic polymer of low dielectric constant material, MSQ, HSQ, or a silicon-containing film containing carbon. It can also be composed of a laminated film of SiCN, SiO, etc.
  • a second wiring layer (120) is formed on the first interlayer insulating film (117).
  • a metal circuit wiring (121) and a metal reinforcing wiring pattern (122) are formed.
  • the second wiring layer (120) is made of an organic polymer of a low dielectric constant material, MSQ, HSQ, or a silicon-oxide film containing carbon. Etching stopper and SiN, SiOC forming a node mask. , SiC, SiCN, SiO, etc. can also be configured.
  • a multilayer circuit structure is formed by alternately stacking the wiring layers and the interlayer insulating films.
  • the metal reinforcing via pattern (119) forms a multilayer support structure by connecting the metal reinforcing wiring patterns (116, 122) of the first and second wiring layers (113, 120) to each other.
  • FIG. 31 is a plan view of the semiconductor device according to the present embodiment.
  • the metal reinforcing via patterns (119 ) are arranged so as to connect only the region (123) where the metal reinforcing wiring patterns (116, 122) overlap. For this reason, it is possible to introduce a metal reinforcing via pattern (119) that does not change the size and shape of the CMP dummy pattern, which is also conventionally formed, that is, does not increase the chip area.
  • FIG. 32 shows the area occupancy of the metal-reinforced via pattern (the ratio of the area of the metal-reinforced via pattern to the unit area of the semiconductor device) when the low-dielectric-constant film is used as the interlayer insulating film, and the CMP occupancy. It is a graph which shows the relationship with the rate of film peeling.
  • the force conductive metal via (118) and the conductive metal via (115, 121) formed separately using a single damascene process are used. It is also possible to use a dual damascene process for simultaneously forming 118) and the conductive metal wiring (121).
  • FIG. 33 is a cross-sectional view of one embodiment of the semiconductor device according to the second aspect of the present invention described above.
  • the semiconductor device includes a semiconductor substrate (211) and a semiconductor substrate (211).
  • the semiconductor substrate (211) is a single crystal silicon substrate.
  • the insulating film (212) is made of borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), phosphosilicate glass (PSG), silicon oxide (SiO 2), silicon nitride (SiN), Silicon oxynitride (SiON), silicon oxyfluoride (SiOF),
  • BPSG borophosphosilicate glass
  • PSG phosphosilicate glass
  • PSG silicon oxide
  • SiN silicon nitride
  • SiON Silicon oxynitride
  • SiOF silicon oxyfluoride
  • SiC silicon carbide
  • SiCN silicon carbonitride
  • the first wiring layer (213) is formed on the insulating film (212).
  • the first wiring layer (213) is made of an organic polymer of low dielectric constant material, MSQ, HSQ, or a silicon-containing silicon oxide film. Etching stopper and SiN, SiOC forming a node mask are used. , SiC, SiCN, SiO, etc. can also be configured.
  • the first wiring layer (213) includes a metal circuit wiring (or a conductive metal wiring) (215) for electrically connecting a circuit and a metal dummy wiring ( 216) is formed.
  • a first interlayer insulating film (217) is formed on the first wiring layer (213.
  • a conductive metal via (224) for electrically connecting the upper and lower metal circuit wirings (215, 219) to each other, and an upper and lower metal reinforcing wiring pattern are provided.
  • a metal reinforcing via pattern (225) to be connected is formed.
  • the first interlayer insulating film (217) is an organic polymer of a low dielectric constant material
  • It can be composed of a laminated film of SiC, SiCN, SiO or the like forming a force etching stopper and a node mask which is MSQ, HSQ or carbon-containing silicon oxide film.
  • a second wiring layer (218) is formed on the first interlayer insulating film (217).
  • a metal circuit wiring (219) and a metal reinforcing wiring pattern (220) are formed.
  • the second wiring layer (218) is made of an organic polymer of low dielectric constant material, MSQ, HSQ, or a silicon-containing silicon oxide film. , SiC, SiCN, SiO, etc. can also be configured.
  • the multilayer circuit structure is formed by alternately laminating the wiring layers and the interlayer insulating films. Is formed.
  • a metal bonding pad (221) for transmitting and receiving electric signals to and from the outside of the chip is formed.
  • the metal bonding pad (221) is electrically connected to the metal circuit wiring (219) formed on the uppermost second wiring layer (218).
  • the transistor (2211) and the metal circuit wiring (215) have the metal bonding pad (221) in the same manner as the non-metal region (circuit region).
  • the metal reinforcing via patterns (216, 220) connecting the regions where the upper and lower metal reinforcing wiring patterns (216, 220) overlap each other are connected. 225) exists.
  • FIG. 34 is a plan view of the semiconductor device according to the example shown in FIG.
  • FIG. 35 shows the area ratio of the metal reinforcing via pattern in the region below the metal bonding pad when the low dielectric constant film is used as the interlayer insulating film in the semiconductor device according to the example shown in FIG. 7 is a graph showing a relationship between a via occupation ratio (%)) and a film peeling ratio during wire bonding (bonding defect ratio (%)).
  • a transistor (2211) forming a circuit area below the metal bonding pad (221), and a multilayer circuit including metal circuit wirings (215, 219) and conductive metal vias (224)
  • the region below the metal bonding pad (221) includes one of the transistor (2211) and one of the metal circuit wiring and the conductive metal via forming the multilayer circuit structure. Only one is arranged.
  • neither the transistor (2211) nor the multilayer circuit structure is disposed in the region below the metal bonding pad (221), and the region below the metal bonding pad (221) is provided with a metal reinforcing wiring pattern ( 216, 220) and a metal reinforcing via pattern (225) alone may be arranged.
  • FIG. 36 is a cross-sectional view of a high-spec LSI to which the above embodiment is applied.
  • the global wiring layer (231) includes a via interlayer insulating film (230), which is an insulating film having a higher dielectric constant and film strength than the low dielectric constant material constituting the multilayer local wiring layer (228), and a via interlayer insulating film.
  • the wiring layer (229) formed of an insulating film having a higher dielectric constant and a higher film strength than the low dielectric constant material forming the multilayer local wiring layer (228) is formed above the film (230).
  • a metal bonding pad (232) for transmitting and receiving an electric signal to / from the outside of the chip is arranged above the local wiring (236) and the global wiring (237).
  • the wiring layer (229) and the via interlayer insulating film (230) are each made of SiO 2.
  • the metal bond in the local wiring layer (228) made of a low dielectric constant interlayer insulating film is formed.
  • a metal reinforcing via pattern (233) for connecting the metal reinforcing wiring patterns (238) of the upper and lower layers to each other is formed only in a region below the bonding pad (232).
  • the global wiring layer (231) has high film strength and adhesion of the wiring layer (229) and the via interlayer insulating film (230) against the shock at the time of bonding. Alternatively, it is possible to withstand stress.
  • the presence of the metal reinforcing via pattern (233) in the local wiring layer (228) makes it possible to increase the strength and adhesion of the interlayer insulating film, resulting in the impact and stress during bonding. It is possible to prevent film peeling and film destruction.
  • a single damascene process in which a conductive metal via and a conductive metal wiring are formed separately is used. It is also possible to use a dual damascene process formed at the same time.
  • FIG. 37 is a cross-sectional view of a first modification of the embodiment shown in FIG.
  • an insulating film (212) and a first wiring layer are formed on a semiconductor substrate (211) on which a transistor (2211) is formed. (213), a first interlayer insulating film (217), a second wiring layer (218), a second interlayer insulating film (240), and a third wiring layer (241) are stacked in this order.
  • a metal bonding pad (221) is arranged on the third wiring layer (241.
  • a large-area wiring layer pad (242) is formed immediately below the metal bonding pad (221). (242) has a structure for supporting the metal bonding pad (221) stacked thereon.
  • the large-area wiring layer pad (242) is formed of the same material as the metal circuit wiring (243) provided in the circuit region of the third wiring layer (241).
  • the area below the large-area wiring layer pad (242) does not include the metal bonding pad (221) (the circuit).
  • the metal bonding pad (221) the circuit.
  • FIG. 38 is a sectional view of a second modification of the embodiment shown in FIG.
  • the uppermost third wiring layer (241) in the semiconductor device shown in FIG. 37 has a single-layer structure, whereas the uppermost third wiring layer (245) 37) is different from the semiconductor device shown in FIG.
  • a laminate (245) in which a plurality of wiring layers are stacked is formed as a third wiring layer on the second interlayer insulating film (240).
  • a large area wiring layer pad (246) is formed on the laminate (245) immediately below the metal bonding pad (221).
  • This large-area wiring layer pad (246) is also composed of a laminate of a plurality of layers, and has a structure in which the large-area wiring layer pad (246) supports the metal bonding pad (221) mounted thereon! /
  • the large-area wiring layer pad (246) is formed of the same material as the metal circuit wiring (247) provided in the circuit region of the multilayer body (245).
  • the area below the large-area wiring layer pad (246) does not include the metal bonding pad (221) (the circuit).
  • the area below the large-area wiring layer pad (246) does not include the metal bonding pad (221) (the circuit).
  • a metal bonding pad (221) is supported by a large-strength large-area wiring layer pad (246).
  • the second interlayer insulating film (240) located under the area wiring layer pad (246) is the same as the via interlayer insulating film (230) in the green wiring layer (231) shown in FIG. It is not necessary to form a metal reinforcing via pattern in the second interlayer insulating film (240) because it can have high strength and high adhesion.
  • the third wiring layer (245) having the large-area wiring layer pad (246) has high film strength and high adhesion to the impact during bonding.
  • the layer below the third wiring layer (245) has a multilayer support structure, so that the strength and adhesion of the interlayer insulating film can be increased. It is possible to prevent film peeling and film destruction due to shock and stress during bonding.
  • FIGS. 39 and 40 are plan views showing examples of the shape of the large-area wiring layer pads (242, 246) in the semiconductor device shown in FIGS. 37 and 38.
  • the large-area wiring layer pads (242, 246) can be formed in a rectangular shape entirely made of metal R, as shown in FIG. 39, for example.
  • the outer shape may be a rectangular shape made of metal R, and a rectangular island I made of an insulating film may be formed therein.
  • the number of islands I can be one or more (four in the example shown in FIG. 40).
  • the arrangement of the islands I is optional.
  • the large-area wiring layer pads (242, 246) are more likely to be displaced than the semiconductor device having the global wiring layer (231) shown in FIG. 36 or the semiconductor device having no global wiring layer 231). It is also applicable.
  • FIG. 41 is a cross-sectional view of another example of the semiconductor device according to the second embodiment of the present invention.
  • the semiconductor device according to the present embodiment will be described with reference to FIG.
  • the semiconductor device according to the present example includes a semiconductor substrate (311) and an insulating film (312) formed on the semiconductor substrate (311).
  • the semiconductor substrate (311) is a single crystal silicon substrate.
  • the insulating film (312) is made of borophosphosilicate 'glass (8-30: 1) 01: 0 1105 110511 ate glass), phosphosilicate glass (PSG: phosphosilicate glass), silicon oxide silicon (SiO 2), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxyfluoride (SiOF),
  • SiC silicon carbide
  • SiCN silicon carbonitride
  • the first wiring layer (313) is formed on the insulating film (312).
  • the first wiring layer (313) is made of an organic polymer of a low dielectric constant material, MSQ
  • HSQ a carbon-containing silicon oxide film.
  • a stacked film strength with SiN, SiOC, SiC, SiCN, SiO, etc. forming an etching stopper and a node mask can also be formed.
  • the first wiring layer (313) includes a metal circuit wiring (or a conductive metal wiring) (315) for electrically connecting the circuit and a metal reinforcing wiring pattern having no electrical connection to the circuit. (316) is formed.
  • a first interlayer insulating film (317) is formed on the first wiring layer (313.
  • a conductive metal via (324) for electrically connecting the upper and lower metal circuit wirings (319, 315) to each other, and an upper and lower metal reinforcing wiring pattern are provided.
  • a metal reinforcing via pattern (325) to be connected is formed.
  • the first interlayer insulating film (317) is made of an organic polymer of low dielectric constant material, MSQ, HSQ or a silicon-containing film containing carbon. It can also be composed of a laminated film of SiCN, SiO, etc.
  • a second wiring layer (318) is formed on the first interlayer insulating film (317).
  • a metal circuit wiring (319) and a metal reinforcing wiring pattern (320) are formed.
  • the second wiring layer (318) is made of an organic polymer of low dielectric constant material, MSQ, HSQ, or a silicon-containing film containing carbon. Etching stopper and SiN, SiOC forming a node mask. , SiC, SiCN, SiO, etc. can also be configured. As described above, a multilayer circuit structure is formed by alternately stacking the wiring layers and the interlayer insulating films.
  • the metal reinforcing via pattern (325) forms a multilayer support structure by connecting the metal reinforcing wiring patterns (316, 320) of the first and second wiring layers (313, 318) to each other.
  • a metal bonding pad (321) for transmitting and receiving electric signals to and from the outside of the chip is formed.
  • the metal bonding pad (321) is electrically connected to the metal circuit wiring (319) formed on the uppermost second wiring layer (318).
  • the impact or stress at the time of wire bonding may also diffuse to a region outside the metal bonding pad (321), which can be seen only below the metal bonding pad (321). For this reason, in the present embodiment, as shown in FIG. 41, which is formed only in the region below the metal bonding pad (321), the upper and lower portions existing within a predetermined distance (3251) from the outer edge of the metal bonding pad (321) are formed.
  • a metal reinforcing via pattern (325) for connecting a region where the metal reinforcing wiring patterns (316, 320) adjacent to each other overlap each other is formed.
  • the fixed distance (3251) from the outer edge of the metal bonding pad (321) changes according to the strength and adhesion of the low dielectric constant material. It may be necessary to form a metal reinforced via pattern (325) over the entire chip.
  • the metal reinforcing via pattern (325) is located not only immediately below the metal bonding pad (321) but also within a predetermined distance (3251) from the outer edge of the metal bonding pad (321).
  • the metal bonding pad (321) and its surroundings This makes it possible to increase the strength and adhesion of the interlayer insulating film, and to prevent film peeling and film destruction due to impact and stress during wire bonding.
  • FIG. 42 shows a region where the multilayer support structure exists when the interlayer support film is formed of a low dielectric constant film and the downward force of the metal bonding pad (321) is also spread outward.
  • 7 is a graph showing the relationship between the distance from the outer edge of the metal bonding pad (321) and the adhesion strength of the bonding portion measured by the ball shear method.
  • the outer peripheral force of the metal bonding pad (321) is also within a range of about 10 m by providing the multilayer support structure, so that only the area below the metal bonding pad (321) is provided. It is possible to significantly increase the strength for wire bonding as compared to the case where a multilayer support structure is present.
  • FIG. 43 is a plan view of the semiconductor device shown in FIG.
  • the space between the lower metal reinforcing wiring patterns existing under the metal bonding pad (321) and within a certain distance (3251) from the outer edge of the metal bonding pad (321) is reduced. Even when there is a metal reinforcing via pattern (325) for connection, the metal reinforcing via pattern (325) exists only in the region (326) where the metal reinforcing wiring patterns vertically adjacent to each other overlap with each other. It is possible to increase the strength against wire bonding without causing an electrical effect on circuit wiring or conductive metal vias or an increase in chip area.
  • a transistor (3211) forming a circuit area below the metal bonding pad (321), a multilayer circuit including metal circuit wirings (315, 319) and conductive metal vias (324)
  • the region below the metal bonding pad (321) includes one of the transistor (3211) and one of the metal circuit wiring and the conductive metal via forming the multilayer circuit structure. Only one is arranged.
  • neither the transistor (3211) nor the multilayer circuit structure is arranged in the region below the metal bonding pad (321), and the region below the metal bonding pad (321) is provided with a metal reinforcing wiring pattern ( 316, 320) and a metal reinforcing via pattern (325) alone may be arranged.
  • FIG. 44 is a cross-sectional view of a high-spec LSI to which the above embodiment is applied.
  • a multilayer local wiring layer (328) made of a low dielectric constant material and a global wiring layer (331) above the multilayer local wiring layer (328). And are formed.
  • the global wiring layer (331) includes a via interlayer insulating film (330), which is an insulating film having higher dielectric constant and film strength than the low dielectric constant material constituting the multilayer local wiring layer (328), and a via interlayer insulating film.
  • the wiring layer (329) formed of an insulating film having a higher dielectric constant and a higher film strength than the low dielectric constant material forming the multilayer local wiring layer (328) is formed above the film (330).
  • a metal bonding pad (332) for transmitting and receiving electric signals to and from the outside of the chip is arranged above the multi-layer wiring that acts as the local wiring (336) and the global wiring (337).
  • the wiring layer (329) and the via interlayer insulating film (330) are each made of SiO 2.
  • a metal reinforcing via pattern (333) for connecting the metal reinforcing wiring patterns (338) of the upper and lower layers to each other is formed in the region (1).
  • the global wiring layer (331) has high film strength and adhesion of the wiring layer (329) and the via interlayer insulating film (330) against the shock at the time of bonding. Alternatively, it is possible to withstand stress.
  • the presence of the metal reinforcing via pattern (333) in the local wiring layer (328) makes it possible to increase the strength and adhesion of the interlayer insulating film, resulting in the impact and stress during bonding. It is possible to prevent film peeling and film destruction.
  • FIG. 45 is a cross-sectional view of another example of the semiconductor device according to the first embodiment of the present invention.
  • the semiconductor device according to the present embodiment will be described with reference to FIG.
  • the semiconductor device according to the present example includes a semiconductor substrate (411) and an insulating film (412) formed on the semiconductor substrate (411).
  • the semiconductor substrate (411) is a single crystal silicon substrate.
  • the insulating film (412) is made of borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), phosphosilicate glass (PSG), silicon nitride (SiO 2), silicon nitride (SiN ), Silicon oxynitride (SiON), silicon oxyfluoride (SiOF),
  • BPSG borophosphosilicate glass
  • PSG phosphosilicate glass
  • PSG phosphosilicate glass
  • SiO 2 silicon nitride
  • SiN silicon nitride
  • SiON Silicon oxynitride
  • SiOF silicon oxyfluoride
  • SiC silicon carbide
  • SiCN silicon carbonitride
  • a first wiring layer (413) is formed on the insulating film (412).
  • the first wiring layer (413) is made of an organic polymer of a low dielectric constant material, MSQ
  • HSQ a carbon-containing silicon oxide film.
  • a stacked film strength with SiN, SiOC, SiC, SiCN, SiO, etc. forming an etching stopper and a node mask can also be formed.
  • the first wiring layer (413) includes a metal circuit wiring (or a conductive metal wiring) (415) for electrically connecting the circuit and a metal reinforcing wiring pattern having no electrical connection to the circuit. (416) are formed.
  • a first interlayer insulating film (417) is formed on the first wiring layer (413.
  • the length of the metal reinforcing via pattern (419) in the thickness direction of the present semiconductor device is set to be longer than the length of the conductive metal via (418) formed in the same layer in the same direction. .
  • the first interlayer insulating film (417) is a low dielectric constant material organic polymer, MSQ, HSQ or a carbon-containing silicon oxide film. It can also be composed of a laminated film of SiCN, SiO, etc.
  • a second wiring layer (420) is formed on the first interlayer insulating film (417).
  • the second wiring layer (420) a metal circuit wiring (421) and a metal reinforcing wiring pattern (422) are formed.
  • the second wiring layer (420) is formed of an organic polymer of a low dielectric constant material, MSQ, HSQ or a carbon-containing silicon oxide film. An etching stopper and a node mask are used. The laminated film strength with SiN, SiOC, SiC, SiCN, SiO, or the like can be configured.
  • a multilayer circuit structure is formed by alternately stacking the wiring layers and the interlayer insulating films.
  • the metal reinforcing via pattern (419) forms a multi-layer support structure by connecting the metal reinforcing wiring patterns (416, 422) of the first and second wiring layers (413, 420) to each other.
  • FIG. 46 is a plan view of the semiconductor device according to the example shown in FIG.
  • the metal reinforcing via patterns (419 ) are arranged so as to connect only the region (423) where the metal reinforcing wiring pattern (or dummy wiring) (416, 422) overlaps. For this reason, it is possible to introduce a metal reinforcing via pattern (or dummy via) (419) that does not change the dimensions and shape of the dummy pattern for CMP in which the conventional force is also formed, that is, does not increase the chip area. .
  • FIG. 47, FIG. 48 and FIG. 49 are plan views showing examples of the shape of the metal reinforcing via pattern (419) in the semiconductor device shown in FIG.
  • the length of the metal reinforcing via pattern (419) in the thickness direction of the semiconductor device is the length of the conductive metal via (418) formed in the same layer in the thickness direction of the semiconductor device. It is set larger than.
  • the metal reinforcing via pattern (419) is, for example, as shown in FIG.
  • It can be formed as a cylindrical via (424) having a larger diameter than (418). In this case, one or more cylindrical vias (424) can be formed.
  • the metal reinforcing via pattern (419) can be formed as a slit-shaped via or a via (425) having a rectangular cross section. In this case, one or more rectangular vias (425) can be formed.
  • the metal reinforcing via patterns (419) are such that the metal reinforcing wiring patterns (416, 422) in the first and second wiring layers (413, 420) overlap each other. It is also possible to form a via (426) that is formed entirely in the region.
  • the etching speed at the time of via etching in the metal reinforcing via pattern (419) can be reduced. Since the etching rate of the via (418) is higher than that of the via (418), as shown in FIG. In this case, the conductive metal via (418) eats more than the amount of food.
  • the conductive metal via (418) and the metal reinforcement via pattern (419) have the same dimensions.
  • CMP chemical mechanical polishing
  • a conductive metal via (418) using a single damascene process of separately forming a conductive metal via (418) and a conductive metal wiring (421) is used.
  • the conductive metal wiring (421) can be formed at the same time.
  • FIG. 50 is a cross-sectional view of another example of the semiconductor device according to the second embodiment of the present invention.
  • the semiconductor device according to the present embodiment will be described with reference to FIG.
  • the semiconductor device includes a semiconductor substrate (511), a transistor (5221) formed on the semiconductor substrate (511), and a transistor (5221).
  • the semiconductor substrate (511) is a single crystal silicon substrate.
  • the insulating film (512) is made of borophosphosilicate 'glass (8-30: 1) 01: 0 1105 110511ate glass), phosphosilicate' glass (PSG: phosphosilicate glass), silicon oxide silicon (SiO 2), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxyfluoride (SiOF),
  • Insulating materials such as silicon carbide (SiC) and silicon carbonitride (SiCN), or a combination thereof It is composed of
  • the first wiring layer (513) is formed on the insulating film (512).
  • the first wiring layer (513) is made of an organic polymer of low dielectric constant material, MSQ, HSQ, or a silicon-containing silicon oxide film. Etching stopper and SiN, SiOC forming a node mask are used. , SiC, SiCN, SiO and the like can also be formed.
  • the first wiring layer (513) includes a metal circuit wiring (or a conductive metal wiring) (515) for electrically connecting the circuit and a metal reinforcing wiring pattern having no electrical connection to the circuit. (516) are formed.
  • a first interlayer insulating film (517) is formed on the first wiring layer (513).
  • conductive metal vias (524) for electrically connecting the upper and lower metal circuit wirings (515, 519) to each other, and upper and lower metal reinforcing wiring patterns (515) are provided.
  • the first interlayer insulating film (517) is made of an organic polymer of a low dielectric constant material, MSQ, HSQ, or a silicon-containing silicon oxide film. It can also be composed of a laminated film of SiCN, SiO, etc.
  • a second wiring layer (518) is formed on the first interlayer insulating film (517).
  • a metal circuit wiring (519) and a metal reinforcing wiring pattern (520) are formed.
  • the second wiring layer (518) is made of an organic polymer of a low dielectric constant material, MSQ, HSQ or a silicon-containing silicon oxide film. , SiC, SiCN, SiO and the like can also be formed.
  • a multilayer circuit structure is formed by alternately stacking the wiring layers and the interlayer insulating films.
  • a metal bonding pad (521) for transmitting and receiving electric signals to and from the outside of the chip is formed on the multilayer circuit structure.
  • the metal bonding pad (521) is electrically connected to the metal circuit wiring (519) formed on the uppermost second wiring layer (518).
  • the length of the metal reinforcing via pattern (525) in the thickness direction of the semiconductor device is set to be longer than the length of the conductive metal via (524) formed in the same layer in the same direction. .
  • FIG. 51 is a plan view of the semiconductor device according to the example shown in FIG.
  • the metal reinforcing via pattern (525) is connected to the metal bonding pad (521).
  • the metal reinforcing wiring patterns (516, 520) existing under () are formed so as to connect the mutually overlapping regions. For this reason, it is possible to increase the strength against wire bonding without causing an electrical influence on wirings and vias forming a circuit and an increase in chip area.
  • FIGS. 52, 53 and 54 are plan views showing examples of the shape of the metal reinforcing via pattern (525) in the semiconductor device shown in FIG.
  • the length of the metal reinforcing via pattern (525) in the thickness direction of the semiconductor device is equal to the length of the conductive metal via (524) formed in the same layer in the thickness direction of the semiconductor device. It is set larger than.
  • the metal reinforcing via pattern (525) is, for example, as shown in FIG.
  • the diameter is larger than (524) and can be formed as a cylindrical via (528A). in this case
  • One or more cylindrical vias (528A) can be formed.
  • the metal reinforcing via pattern (525) can be formed as a slit-shaped via or a via (528B) having a rectangular cross section.
  • 8B can form one or a plurality.
  • the metal reinforcing via pattern (525) is formed in an area where the metal reinforcing wiring patterns (516, 520) in the first and second wiring layers (513, 518) overlap each other. It is also possible to form as a via (528C) formed in all.
  • the dimensions are larger than the conductive metal vias (524)! / ),
  • the etching speed at the time of via etching in the metal reinforcing via pattern (525) becomes faster than the etching speed of the conductive metal via (524), and as shown in FIG.
  • the amount of penetration of the metal reinforcing via pattern (525) with respect to the wiring pattern (516) becomes larger than the amount of penetration of the conductive metal via (524) with respect to the metal circuit wiring (515).
  • the conductive metal via (524) and the metal reinforcement via pattern (525) have the same dimensions. It is possible to further improve the adhesion with the metal strength wiring pattern (516) of the lower layer and the strength of the interlayer insulating film (517) as compared with the case, and this is caused by the impact stress applied during wire bonding. It is possible to prevent film peeling and film destruction.
  • a transistor (5211) forming a circuit area below the metal bonding pad (521), a multilayer circuit including metal circuit wirings (515, 519) and conductive metal vias (524)
  • the region below the metal bonding pad (521) includes one of the transistor (5211) and one of the metal circuit wiring and the conductive metal via forming the multilayer circuit structure. Only one is arranged.
  • neither the transistor (5211) nor the multilayer circuit structure is disposed in the region below the metal bonding pad (521), and the region below the metal bonding pad (521) is provided with a metal reinforcing wiring pattern ( 516, 520) and a metal supporting via pattern (525) alone.
  • FIG. 55 is a cross-sectional view of a high-spec LSI to which the above embodiment is applied.
  • the global wiring layer (531) includes a via interlayer insulating film (530), which is an insulating film having a higher dielectric constant and film strength than the low dielectric constant material constituting the multilayer local wiring layer (528), and a via interlayer insulating film.
  • the wiring layer (529) formed of an insulating film having a higher dielectric constant and a higher film strength than the low dielectric constant material forming the multilayer local wiring layer (528) is formed above the film (530).
  • a metal bonding pad (532) for transmitting and receiving electric signals to and from the outside of the chip is arranged.
  • the wiring layer (529) and the via interlayer insulating film (530) are each made of SiO
  • the metal wiring via pattern does not exist in the global wiring layer (531), and only in the region below the metal bonding pad (532), the local wiring layer (528) made of a low dielectric constant interlayer film is formed.
  • a metal reinforcing via pattern (533) for connecting the metal reinforcing wiring patterns adjacent to each other in the vertical direction is formed.
  • the length of the metal reinforcing via pattern (533) in the thickness direction of the present semiconductor device is set to be longer than the length of the conductive metal via (524) in the same layer in the thickness direction of the present semiconductor device. I have.
  • the global wiring layer (531) has high film strength and adhesion of the wiring layer (529) and the via interlayer insulating film (530) due to the bonding shock. Alternatively, it is possible to withstand stress.
  • the presence of the metal reinforcing via pattern (533) in the local wiring layer (528) makes it possible to increase the strength and adhesion of the interlayer insulating film, resulting in impact and stress during bonding. It is possible to prevent film peeling and film destruction.
  • FIG. 56 is a sectional view of another example of the semiconductor device according to the second embodiment of the present invention.
  • the semiconductor device according to the present embodiment will be described with reference to FIG.
  • the semiconductor device includes a semiconductor substrate (611) and a semiconductor
  • the semiconductor device includes a transistor (6221) formed on a substrate (611) and an insulating film (612) formed on a semiconductor substrate (611) so as to cover the transistor (6221).
  • the semiconductor substrate (611) is a single crystal silicon substrate.
  • the insulating film (612) is made of borophosphosilicate 'glass (8-30: 1) 01: 0 1105 110511ate glass), phosphosilicate glass (PSG: phosphosilicate glass), silicon oxide silicon (SiO 2), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxyfluoride (SiOF),
  • SiC silicon carbide
  • SiCN silicon carbonitride
  • a first wiring layer (613) is formed on the insulating film (612).
  • the first wiring layer (613) is made of an organic polymer of a low dielectric constant material, MSQ
  • HSQ a carbon-containing silicon oxide film.
  • a stacked film strength with SiN, SiOC, SiC, SiCN, SiO, etc. forming an etching stopper and a node mask can also be formed.
  • the first wiring layer (613) includes a metal circuit wiring (or a conductive metal wiring) (615) for electrically connecting a circuit and a metal reinforcing wiring pattern having no electrical connection to the circuit. (616) is formed.
  • a first interlayer insulating film (617) is formed on the first wiring layer (613.
  • conductive metal vias (624) for electrically connecting the upper and lower metal circuit wirings (615, 619) to each other, and upper and lower metal reinforcing wiring patterns ( 616, 620) are formed.
  • the first interlayer insulating film (617) is made of an organic polymer of a low dielectric constant material, MSQ, HSQ or SiC forming a force etching stopper and a node mask, which is a carbon-containing silicon oxide film. It can also be composed of a laminated film of SiCN, SiO, etc.
  • a second wiring layer (618) is formed on the first interlayer insulating film (617).
  • a metal circuit wiring (619) and a metal reinforcing wiring pattern (620) are formed.
  • the second wiring layer (618) is made of an organic polymer of low dielectric constant material, MSQ, HSQ, or a silicon-containing silicon-containing film. Etching stopper and SiN, SiOC forming a node mask. , SiC, SiCN, SiO, etc. can also be configured. [0358] As described above, a multilayer circuit structure is formed by alternately laminating the wiring layers and the interlayer insulating films.
  • a metal bonding pad (621) for transmitting and receiving an electric signal to and from the outside of the chip is formed.
  • the metal bonding pad (621) is electrically connected to the metal circuit wiring (619) formed on the uppermost second wiring layer (618).
  • the impact or stress at the time of wire bonding may also diffuse to a region outside the metal bonding pad (621), which can be seen only below the metal bonding pad (621). For this reason, in the present embodiment, as shown in FIG. 57, which is formed only in the region below the metal bonding pad (621), the upper and lower portions existing within a certain distance (6231) from the outer edge of the metal bonding pad (621) are formed. A metal reinforcing via pattern (625) connecting regions where the metal reinforcing wiring patterns (616, 620) adjacent to each other overlap each other is formed.
  • the length of the metal reinforcing via pattern (625) in the thickness direction of the present semiconductor device is set to be larger than the length of the conductive metal via (624) of the same layer in the thickness direction of the present semiconductor device. I have.
  • the fixed distance (6231) from the outer edge of the metal bonding pad (621) changes according to the strength and adhesion of the low dielectric constant material. It may be necessary to form a metal reinforced via pattern (625) over the entire chip.
  • a multilayer support structure in a semiconductor device using a low dielectric constant film as an interlayer insulating film, a multilayer support structure must exist within a range of about 10 ⁇ m from the outer edge of the metal bonding pad. Thus, it was shown that the strength for wire bonding can be considerably increased as compared with the case where the multilayer support structure exists only in the region below the metal bonding pad.
  • FIG. 57 is a plan view of the semiconductor device shown in FIG.
  • the lower metal reinforcing wiring pattern located below the metal bonding pad (621) and within a certain distance (6231) from the outer edge of the metal bonding pad (621). Even if there is a metal reinforcing via pattern (625) that connects between the metal reinforcing wires (616, 620), the metal only in the area (626) where the vertically adjacent metal reinforcing wiring patterns (616, 620) overlap each other. The presence of the reinforcing via pattern (625) makes it possible to increase the strength against wire bonding without causing an electrical influence on the wiring forming the circuit or the conductive metal via or an increase in the chip area.
  • FIG. 58, FIG. 59 and FIG. 60 are plan views showing examples of the shape of the metal reinforcing via pattern (625) in the semiconductor device shown in FIG.
  • the length of the metal reinforcing via pattern (625) in the thickness direction of the semiconductor device is equal to the length of the conductive metal via (624) formed in the same layer in the thickness direction of the semiconductor device. It is set larger than.
  • the metal reinforcing via pattern (625) is, for example, as shown in FIG.
  • the metal reinforcing via pattern (625) can be formed as a slit-shaped via or a via (629) having a rectangular cross section. In this case, one or more rectangular vias (629) can be formed.
  • the metal reinforcing via pattern (625) is formed in an area where the metal reinforcing wiring patterns (616, 620) in the first and second wiring layers (613, 618) overlap each other. All of them can be formed as a via (630).
  • the etching speed at the time of via etching in the metal reinforcing via pattern (625) becomes conductive. Since the etching speed of the metal via (624) is faster than that of the metal circuit wiring (615) as shown in FIG. ) Of the conductive metal via (624) with respect to).
  • the conductive metal via (624) and the metal reinforcement via pattern (625) have the same dimensions. Furthermore, the adhesion to the lower metal strength wiring pattern (616) and the interlayer insulation film (61 It is possible to improve the strength of 7), and it is possible to prevent film peeling and film destruction due to impact and stress during wire bonding.
  • the metal reinforcing via pattern (625) is formed within a certain distance (6231) from the outer edge of the metal bonding pad (621), and By making the length of the metal reinforcing via pattern (625) longer than the length of the conductive metal via (624), the adhesion to the underlying metal reinforcing wiring pattern (616) and the strength of the interlayer insulating film (617) are increased. This makes it possible to prevent film peeling and film destruction caused by impact and stress during wire bonding.
  • a transistor (6221) forming a circuit area below the metal bonding pad (621) and a multilayer circuit including metal circuit wirings (615, 619) and conductive metal vias (624)
  • the region below the metal bonding pad (621) includes one of the transistor (6221) and one of the metal circuit wiring and the conductive metal via constituting the multilayer circuit structure. Only one is arranged.
  • neither the transistor (6221) nor the multilayer circuit structure is arranged in the area below the metal bonding pad (621), and the area below the metal bonding pad (621) is provided with a metal reinforcing wiring pattern ( 616, 620) and the metal reinforcing via pattern (625), and only a multi-layered support structure that is powerful.
  • FIG. 61 is a cross-sectional view of a high-spec LSI to which the above embodiment is applied.
  • the global wiring layer (634) includes a via interlayer insulating film (633), which is an insulating film having a higher dielectric constant and film strength than the low dielectric constant material forming the multilayer local wiring layer (631), and a via interlayer insulating film.
  • the wiring layer (632) formed of an insulating film having a higher dielectric constant and a higher film strength than the low dielectric constant material forming the multilayer local wiring layer (631) is formed above the film (633).
  • a metal bonding pad (635) for transmitting and receiving an electric signal to and from the outside of the chip is arranged above the multi-layer wiring which serves as the local wiring (638) and the global wiring (639).
  • the wiring layer (632) and the via interlayer insulating film (633) are each made of SiO 2.
  • metal reinforcing via pattern in the global wiring layer (634), and a certain distance (6331) from the area below the metal bonding pad (635) and the outer edge of the metal bonding pad (635).
  • Metal reinforcing via patterns (636) connecting between vertically adjacent metal reinforcing wiring patterns in the local wiring layer (631) made of a low dielectric constant interlayer film are formed in the region in parentheses. .
  • the length of the metal reinforcing via pattern (636) in the thickness direction of the present semiconductor device is set to be longer than the length of the conductive metal via (637) in the same layer in the thickness direction of the present semiconductor device. I have.
  • the global wiring layer (634) has a high film strength and adhesion of the wiring layer (632) and the via interlayer insulating film (633) against the shock at the time of bonding. Alternatively, it is possible to withstand stress.
  • the presence of the metal reinforcing via pattern (636) in the local wiring layer (631) makes it possible to increase the strength and adhesion of the interlayer insulating film, resulting in the impact and stress during bonding. It is possible to prevent film peeling and film destruction.
  • the semiconductor device according to this example was formed in the same manner as the semiconductor device according to Example 1.
  • an insulating film (112) formed on a semiconductor substrate (111) is formed, and further, an insulating film (112) is formed.
  • a first wiring layer (113) is formed on (112).
  • the first wiring layer (113) includes a metal circuit wiring (or conductive metal wiring) (115) for electrically connecting the circuit and a metal reinforcing wiring pattern having no electrical connection to the circuit. (116 ) Is formed.
  • a first interlayer insulating film (117) is formed on the first wiring layer (113).
  • a conductive metal via (118) for electrically connecting the upper and lower metal circuit wirings (115, 121) to each other, and an upper and lower metal reinforcing wiring pattern are provided.
  • a metal reinforcing via pattern (119) to be connected is formed.
  • a second wiring layer (120) is formed on the first interlayer insulating film (117).
  • a metal circuit wiring (121) and a metal reinforcing wiring pattern (122) are formed in the second wiring layer (120).
  • a multilayer circuit structure is formed by alternately stacking the wiring layers and the interlayer insulating films.
  • the metal reinforced via pattern (119) forms a multilayer support structure by connecting the metal reinforced wiring patterns (116, 122) of the first and second wiring layers (113, 120) to each other.
  • the ratio of the total area of the vias per unit area of the semiconductor device that is, the area of the conductive metal via (118) and the metal reinforcement
  • the ratio of the sum of the area of the via pattern (119) and the unit area of the semiconductor device was varied.
  • FIG. 62 shows vias per unit area of a semiconductor device using a low dielectric constant film as an interlayer insulating film.
  • the optical defect monitor monitors the ratio of the total area of the (conductive metal via and metal reinforcing via pattern) and the number of defects that occur due to peeling of the interlayer insulating film when Cu-CMP is performed under a load of 2 psi. It is a graph which shows the relationship with the number measured with the apparatus.
  • the semiconductor device according to this example was formed in the same manner as the semiconductor device according to Example 2. As in the case of the semiconductor device shown in FIG. 33, in forming the semiconductor device according to this example, first, an insulating film (212) is formed on a semiconductor substrate (211) on which a transistor (2211) is formed. Then, a first wiring layer (213) was formed on the insulating film (212).
  • the first wiring layer (213) includes a metal circuit wiring (or a conductive metal wiring) (215) for electrically connecting a circuit and a metal dummy wiring (215) having no electrical connection to the circuit. 216) is formed.
  • a first interlayer insulating film (217) is formed on the first wiring layer (213).
  • conductive metal vias (224) for electrically connecting the upper and lower metal circuit wirings (223, 219) to each other, and upper and lower metal reinforcing wiring patterns are provided.
  • a metal reinforcing via pattern (225) to be connected is formed.
  • a second wiring layer (218) is formed on the first interlayer insulating film (217).
  • a metal circuit wiring (219) and a metal reinforcing wiring pattern (220) are formed.
  • a multilayer circuit structure is formed by alternately stacking the wiring layers and the interlayer insulating films.
  • a metal bonding pad (221) for transmitting and receiving electric signals to and from the outside of the chip is formed.
  • the metal bonding pad (221) is electrically connected to the metal circuit wiring (219) formed on the uppermost second wiring layer (218).
  • the metal reinforcing via patterns (216, 220) connecting the areas where the upper and lower metal reinforcing wiring patterns (216, 220) overlap each other are formed only in the area below the metal bonding pad (221). 225) exists.
  • FIG. 63 shows the ratio of the total area of vias (conductive metal vias and metal reinforcing via patterns) to the unit area of the region below the metal bonding pad of a semiconductor device using a low dielectric constant film as an interlayer insulating film.
  • 4 is a graph showing the relationship between the adhesion hardness between a metal bonding pad and a bonding wire measured by a ball shear method.
  • FIGS. 64 and 65 are cross-sectional views of another example of the semiconductor device according to the third embodiment of the present invention.
  • the semiconductor device according to the present example includes a semiconductor substrate (711), a transistor (7221) formed on the semiconductor substrate (711), and a transistor (7221). And an insulating film (712) formed on the semiconductor substrate (711).
  • the semiconductor substrate (711) in this embodiment also has a single crystal silicon substrate strength.
  • the insulating film (712) is made of borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), phosphosilicate glass (PSG), silicon dioxide (SiO 2), silicon nitride (SiN ), Silicon oxynitride (SiON), silicon oxyfluoride (SiOF),
  • SiC silicon carbide
  • SiCN silicon carbonitride
  • the first wiring layer (713) is formed on the insulating film (712).
  • the first wiring layer (713) is made of an organic polymer of low dielectric constant material, MSQ
  • HSQ a carbon-containing silicon oxide film.
  • a stacked film strength with SiN, SiOC, SiC, SiCN, SiO, etc. forming an etching stopper and a node mask can also be formed.
  • a metal circuit wiring (715) for electrically connecting circuits, and a circuit Has no electrical connection a metal reinforced wiring pattern (716) is formed!
  • a first interlayer insulating film (717) is formed on the first wiring layer (713.
  • the first interlayer insulating film (717) is electrically connected to conductive metal wirings (715, 719) provided in the first and second wiring layers (713, 718), respectively. And a metal reinforcing via pattern (726) interconnecting the metal reinforcing wiring patterns (716, 720) provided in the first and second wiring layers (713, 718), respectively. Are formed.
  • the first interlayer insulating film (717) is an organic polymer of a low dielectric constant material, MSQ, HSQ or a silicon-containing film containing carbon. It can also be composed of a laminated film of SiCN, SiO, etc.
  • a second wiring layer (718) is formed on the first interlayer insulating film (717.
  • a metal circuit wiring (719) and a metal reinforcing wiring pattern (720) are formed.
  • the second wiring layer (718) is made of an organic polymer of low dielectric constant material, MSQ, HSQ or a silicon-containing film containing carbon.
  • the etching stopper and the SiN, SiOC forming the node mask are used. , SiC, SiCN, SiO and the like can also be formed.
  • a second interlayer insulating film (721) is formed on the second wiring layer (718).
  • the second interlayer insulating film (721) has the same material strength as the first interlayer insulating film (717).
  • a third wiring layer (722) is formed on the second interlayer insulating film (721).
  • the third wiring layer (722) is formed of the same material as the second wiring layer (718).
  • a multilayer circuit structure is formed by alternately stacking the wiring layers and the interlayer insulating films.
  • a metal bonding pad (723) for transmitting and receiving an electric signal to and from the outside of the chip is formed.
  • the metal bonding pad (723) is electrically connected to the metal circuit wiring (724) formed on the uppermost third wiring layer (722).
  • the transistor (7221) and the metal circuit wiring (7 15, 719), metal conductive metal vias (725) are present.
  • the metal circuits stacked in the thickness direction of the semiconductor device below the metal bonding pad (723) in the circuit region (1200) Wirings (724, 719, 715), conductive metal vias (727, 725), and a multilayer circuit structure are formed by force.
  • the force also forms a multilayer support structure.
  • the multilayer support structure is present in a gap in a circuit area where the multilayer circuit structure is formed. That is, the multilayer support structure is formed in a region where the multilayer circuit structure does not exist so as not to conflict with the multilayer circuit structure inside the circuit region (1200) where the multilayer circuit structure is formed.
  • the semiconductor device is stacked in the thickness direction.
  • Metal supporting wiring patterns (729, 720, 716) and metal reinforcing via patterns (728, 726) interconnecting them form a multilayer support structure.
  • the multilayer support structure including the metal reinforcing wiring patterns (716, 720, 729) and the metal reinforcing via patterns (726, 728) formed in the scribe area (1300) is shown in Figs. As shown in FIG. 28 and FIG. 28, the scribe area (1300) is uniformly distributed over the entire area, and is also formed in the four corners of the semiconductor chip, that is, in the area below the cross mark X. .
  • the planar arrangement of the multilayer support structure is not limited to the above example.
  • the multilayer support structure may be formed only in the region below the cross mark X or excluding the corners of the semiconductor chip. It can also be formed only in the region along the peripheral edge.
  • the semiconductor device according to the embodiment shown in FIG. 65 is different from the semiconductor device according to the embodiment shown in FIG. 64 in that the outer peripheral edge of the chip is located at a position closer to the position where the metal bonding pad (723) is formed.
  • the difference lies in that a shield (730) is formed between the circuit region on the side, that is, the outside of the metal bonding pad (723) and the scribe region (1300).
  • the shield (730) also has a laminated body strength in which the metal reinforcing wiring pattern and the metal reinforcing via pattern are stacked. That is, the shield (730) has the same structure as the multilayer support structure.
  • the shield (730) is arranged continuously over the entire periphery along the outer peripheral edge of the semiconductor chip. Therefore, it is possible to effectively prevent moisture from entering the circuit region (1200) from outside the semiconductor device.
  • the shield (730) is also a multi-layered support structure that also acts as a metal reinforcing wiring pattern and a metal reinforcing via pattern, a layer is formed between the outside of the metal bonding pad (723) and the scribe area (1300). It also exerts the effect of increasing the adhesion between the layers constituting the body.
  • both the circuit region (1200) (including the region below the metal bonding pad (723)) and the scribe region Similarly to (1300), a multi-layer support structure composed of metal reinforcing wiring patterns (716, 720, 729) and metal reinforcing via patterns (726, 728) is formed.
  • the strength and adhesion of the LSI can be increased, so that it can be used during a chemical mechanical polishing (CMP) process or chip packaging.
  • CMP chemical mechanical polishing
  • Film peeling and film destruction can be prevented by the applied impact and stress.
  • a multilayer support structure is formed in the circuit region (12000) (including the region below the metal bonding pad (723)). It is not necessary!
  • the transistor (7221) and one of the metal circuit wiring and the conductive metal via forming the multilayer circuit structure are arranged. Is also good.
  • neither the transistor (7221) nor the multilayer circuit structure is arranged in the region below the metal bonding pad (723), and the region below the metal bonding pad (723) is formed in the metal reinforcing wiring pattern. Only a multi-layer support structure consisting of (716, 720, 729) and metal reinforcing via patterns (726, 728) may be arranged.
  • a single damascene process for separately forming a conductive metal via and a conductive metal wiring is used. It is also possible to use a dual damascene process for simultaneously forming conductive metal vias and conductive metal wiring.
  • FIG. 1 is a cross-sectional view of a conventional semiconductor device.
  • FIG. 2 is a diagram showing pad peeling during bonding in a conventional semiconductor device.
  • FIG. 3 is a cross-sectional view showing one example of a conventional bonding pad structure.
  • FIG. 4 is a schematic sectional view showing one embodiment of the semiconductor device according to the first aspect of the present invention.
  • FIG. 5 is a schematic sectional view showing another embodiment of the semiconductor device according to the first aspect of the present invention.
  • FIG. 6 is a schematic sectional view showing another embodiment of the semiconductor device according to the first aspect of the present invention.
  • FIG. 7 is a schematic sectional view showing another embodiment of the semiconductor device according to the first aspect of the present invention.
  • FIG. 8 is a schematic sectional view showing another embodiment of the semiconductor device according to the first aspect of the present invention.
  • FIG. 9 is a circuit diagram showing an equivalent circuit of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 10 is a cross-sectional view showing one manufacturing step in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 11 is a cross-sectional view showing one manufacturing step in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 12 is a cross-sectional view showing one manufacturing step in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 13 is a cross-sectional view showing one manufacturing step in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 14 is a cross-sectional view showing one manufacturing step in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 15 is a cross-sectional view showing one manufacturing step in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 16 is a cross-sectional view showing one manufacturing step in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 17 is a cross-sectional view showing one manufacturing step in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 18 is a cross-sectional view showing one manufacturing step in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 19 is a cross-sectional view showing one manufacturing step in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 20 is a schematic cross-sectional view showing one embodiment of a semiconductor device according to a second aspect of the present invention.
  • FIG. 21 is a plan view schematically showing an example of a region where a multilayer support structure exists in a semiconductor device according to a second embodiment of the present invention.
  • FIG. 22 is a plan view schematically showing an example of a region where a multilayer support structure exists in a semiconductor device according to a second embodiment of the present invention.
  • FIG. 23 is a schematic sectional view showing one embodiment of a semiconductor device according to a third aspect of the present invention.
  • FIG. 24 is a plan view schematically showing a positional relationship between a circuit region and a scribe region in a semiconductor device according to a third embodiment of the present invention.
  • 25 is an enlarged plan view of a region B shown in FIG. 24.
  • FIG. 26 is a plan view showing the shape of a cross mark provided at a corner of a semiconductor chip.
  • FIG. 27 is a schematic sectional view showing another embodiment of the semiconductor device according to the third aspect of the present invention.
  • FIG. 28 is a plan view schematically showing a positional relationship between a circuit region and a scribe region in the semiconductor device shown in FIG. 27.
  • FIG. 29 is an enlarged plan view of a region E shown in FIG. 28.
  • FIG. 30 is a cross-sectional view of one example of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 31 is a plan view of the semiconductor device according to the embodiment shown in FIG. 30.
  • the area occupation ratio of the metal reinforcing via pattern (the ratio of the area of the metal reinforcing via pattern to the unit area of the semiconductor device)
  • 6 is a graph showing a relationship with a rate of film peeling during CMP.
  • FIG. 33 is a sectional view of an example of a semiconductor device according to a second embodiment of the present invention.
  • FIG. 34 is a plan view of the semiconductor device according to the embodiment shown in FIG. 33.
  • FIG. 36 is a cross-sectional view of a high-spec LSI to which an example of the semiconductor device according to the second embodiment of the present invention is applied.
  • FIG. 37 is a sectional view of a first modification of the embodiment shown in FIG. 36.
  • FIG. 38 is a sectional view of a second modification of the embodiment shown in FIG. 36.
  • FIG. 39 is a plan view showing an example of the shape of a large-area wiring layer pad in the semiconductor device shown in FIGS. 37 and 38.
  • FIG. 40 is a plan view showing an example of the shape of a large-area wiring layer pad in the semiconductor device shown in FIGS. 37 and 38.
  • FIG. 41 is a cross-sectional view of another example of the semiconductor device according to the second embodiment of the present invention.
  • ⁇ 42] A graph showing the relationship between the distance from the outer edge of the metal bonding pad in the region where the multilayer support structure exists and the adhesion strength of the bonding portion measured by the ball shear method.
  • FIG. 43 is a plan view of the semiconductor device shown in FIG. 41.
  • FIG. 44 is a sectional view of a noise-spec LSI to which the embodiment shown in FIG. 41 is applied.
  • FIG. 45 is a cross-sectional view of another example of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 46 is a plan view of the semiconductor device according to the embodiment shown in FIG. 45.
  • FIG. 47 is a plan view showing an example of the shape of a metal reinforcing via pattern in the semiconductor device shown in FIG. 45.
  • FIG. 48 is a plan view showing an example of the shape of a metal reinforcing via pattern in the semiconductor device shown in FIG. 45.
  • FIG. 45 is a plan view showing an example of the shape of a metal reinforcing via pattern in the semiconductor device shown in FIG. 45.
  • FIG. 50 is a cross-sectional view of another example of the semiconductor device according to the second embodiment of the present invention.
  • FIG. 51 is a plan view of the semiconductor device according to the embodiment shown in FIG. 50.
  • FIG. 52 is a plan view showing an example of the shape of the metal reinforcing via pattern in the semiconductor device shown in FIG. 50.
  • FIG. 53 is a plan view showing an example of the shape of a metal reinforcing via pattern in the semiconductor device shown in FIG. 50.
  • FIG. 54 is a plan view showing an example of the shape of a metal reinforcing via pattern in the semiconductor device shown in FIG. 50.
  • FIG. 55 is a cross-sectional view of a Nos. Ispec LSI to which the embodiment shown in FIG. 50 is applied.
  • FIG. 56 is a cross-sectional view of another example of the semiconductor device according to the second embodiment of the present invention.
  • FIG. 57 is a plan view of the semiconductor device shown in FIG. 56.
  • FIG. 58 is a plan view showing an example of the shape of a metal reinforcing via pattern in the semiconductor device shown in FIG. 56.
  • FIG. 59 is a plan view showing an example of the shape of the metal reinforcing via pattern in the semiconductor device shown in FIG. 56.
  • [60] shows an example of the shape of a metal reinforcing via pattern in the semiconductor device shown in FIG. FIG.
  • FIG. 61 is a cross-sectional view of a noise-spec LSI to which the embodiment shown in FIG. 56 is applied.
  • Cu-CMP is performed with the ratio of the total area of vias (conductive metal vias and metal reinforcing via patterns) to the unit area of a semiconductor device using a low dielectric constant film as an interlayer insulating film, and a load of 2 psi.
  • 4 is a graph showing a relationship between the number of defects generated due to peeling of an interlayer insulating film and the number measured by an optical defect monitoring device when the optical insulating film is removed.
  • the ratio of the total area of the vias (conductive metal vias and metal reinforcing via patterns) to the unit area of the area under the metal bonding pad of the semiconductor device using the low dielectric constant film as the interlayer insulating film, and the ball share 6 is a graph showing the relationship between the adhesion hardness between a metal bonding pad and a bonding wire measured by a method.
  • FIG. 64 is a cross-sectional view of another example of the semiconductor device according to the third embodiment of the present invention.
  • FIG. 65 is a cross-sectional view of another example of the semiconductor device according to the third embodiment of the present invention.
  • Second wiring layer 720 Metal reinforced wiring pattern

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Dans un dispositif semi-conducteur utilisant un fil isolant intercouche de faible constante diélectrique de faible résistance et adhérence de film, on supprime la séparation du film et la cassure du film pendant le traitement ou l’emballage en accroissant la résistance structurelle sans affecter la zone des puces ou la configuration des circuits. Conventionnellement, des motifs de câblage de renfort (motifs factices de câblage) ont été formés dans les couches de câblage. Dans la présente invention, de nombreux motifs traversants de renfort qui ne sont pas connectés électriquement aux circuits, sont constitués dans une région du film isolant intercouche dans laquelle les motifs de câblage de renfort formés dans les couches de câblage se chevauchent des deux côtés, connectant ainsi les motifs de câblage de renfort les uns aux autres.
PCT/JP2005/006180 2004-03-31 2005-03-30 Dispositif semi-conducteur et procede de fabrication dudit dispositif WO2005096364A1 (fr)

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Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007180363A (ja) * 2005-12-28 2007-07-12 Matsushita Electric Ind Co Ltd 半導体集積回路装置
JP2008124271A (ja) * 2006-11-13 2008-05-29 Rohm Co Ltd 半導体装置
JP2010016268A (ja) * 2008-07-07 2010-01-21 Nec Electronics Corp 半導体装置の製造方法および半導体装置
JP2010153677A (ja) * 2008-12-26 2010-07-08 Consortium For Advanced Semiconductor Materials & Related Technologies 半導体装置、及び半導体装置の製造方法
CN101937893A (zh) * 2009-05-29 2011-01-05 瑞萨电子株式会社 半导体器件
JP2012134543A (ja) * 2012-03-08 2012-07-12 Fujitsu Ltd 半導体装置
WO2012160736A1 (fr) * 2011-05-20 2012-11-29 パナソニック株式会社 Dispositif à semi-conducteurs
JP2013175798A (ja) * 2013-06-14 2013-09-05 Renesas Electronics Corp 半導体装置
US8912657B2 (en) 2006-11-08 2014-12-16 Rohm Co., Ltd. Semiconductor device
WO2020000435A1 (fr) * 2018-06-29 2020-01-02 华为技术有限公司 Circuit intégré et sa structure d'interconnexion
KR102095208B1 (ko) * 2018-11-21 2020-03-31 (주)샘씨엔에스 반도체 소자 테스트를 위한 다층 세라믹 기판 및 그 제조 방법
US11282744B2 (en) * 2019-09-30 2022-03-22 Systems On Silicon Manufacturing Co. Pte. Ltd. Enhanced intermetal dielectric adhesion

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10335333A (ja) * 1997-03-31 1998-12-18 Hitachi Ltd 半導体集積回路装置およびその製造方法ならびに設計方法
JP2001196372A (ja) * 2000-01-13 2001-07-19 Mitsubishi Electric Corp 半導体装置
JP2001267323A (ja) * 2000-03-21 2001-09-28 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP2002270776A (ja) * 2001-03-13 2002-09-20 Sanyo Electric Co Ltd 半導体装置の配線構造
JP2003318179A (ja) * 2002-04-26 2003-11-07 Mitsubishi Electric Corp 半導体装置及びその製造方法
JP2004071927A (ja) * 2002-08-08 2004-03-04 Renesas Technology Corp 半導体装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6232662B1 (en) * 1998-07-14 2001-05-15 Texas Instruments Incorporated System and method for bonding over active integrated circuits
US6037668A (en) * 1998-11-13 2000-03-14 Motorola, Inc. Integrated circuit having a support structure
JP4192348B2 (ja) * 1999-08-09 2008-12-10 株式会社デンソー 半導体装置
US6495917B1 (en) * 2000-03-17 2002-12-17 International Business Machines Corporation Method and structure of column interconnect
JP4250006B2 (ja) * 2002-06-06 2009-04-08 富士通マイクロエレクトロニクス株式会社 半導体装置及びその製造方法
JP4005873B2 (ja) * 2002-08-15 2007-11-14 株式会社東芝 半導体装置
JP2004153015A (ja) * 2002-10-30 2004-05-27 Fujitsu Ltd 半導体装置及びその製造方法
JP3811473B2 (ja) * 2003-02-25 2006-08-23 富士通株式会社 半導体装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10335333A (ja) * 1997-03-31 1998-12-18 Hitachi Ltd 半導体集積回路装置およびその製造方法ならびに設計方法
JP2001196372A (ja) * 2000-01-13 2001-07-19 Mitsubishi Electric Corp 半導体装置
JP2001267323A (ja) * 2000-03-21 2001-09-28 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP2002270776A (ja) * 2001-03-13 2002-09-20 Sanyo Electric Co Ltd 半導体装置の配線構造
JP2003318179A (ja) * 2002-04-26 2003-11-07 Mitsubishi Electric Corp 半導体装置及びその製造方法
JP2004071927A (ja) * 2002-08-08 2004-03-04 Renesas Technology Corp 半導体装置

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4675231B2 (ja) * 2005-12-28 2011-04-20 パナソニック株式会社 半導体集積回路装置
JP2007180363A (ja) * 2005-12-28 2007-07-12 Matsushita Electric Ind Co Ltd 半導体集積回路装置
US9786601B2 (en) 2006-11-08 2017-10-10 Rohm Co., Ltd. Semiconductor device having wires
US8912657B2 (en) 2006-11-08 2014-12-16 Rohm Co., Ltd. Semiconductor device
US9337090B2 (en) 2006-11-08 2016-05-10 Rohm Co., Ltd. Semiconductor device
US9184132B2 (en) 2006-11-08 2015-11-10 Rohm Co., Ltd. Semiconductor device
JP2008124271A (ja) * 2006-11-13 2008-05-29 Rohm Co Ltd 半導体装置
JP2010016268A (ja) * 2008-07-07 2010-01-21 Nec Electronics Corp 半導体装置の製造方法および半導体装置
JP2010153677A (ja) * 2008-12-26 2010-07-08 Consortium For Advanced Semiconductor Materials & Related Technologies 半導体装置、及び半導体装置の製造方法
US8310056B2 (en) 2009-05-29 2012-11-13 Renesas Electronics Corporation Semiconductor device
CN101937893B (zh) * 2009-05-29 2012-10-03 瑞萨电子株式会社 半导体器件
CN101937893A (zh) * 2009-05-29 2011-01-05 瑞萨电子株式会社 半导体器件
WO2012160736A1 (fr) * 2011-05-20 2012-11-29 パナソニック株式会社 Dispositif à semi-conducteurs
US9305863B2 (en) 2011-05-20 2016-04-05 Panasonic Corporation Semiconductor device
JP2012134543A (ja) * 2012-03-08 2012-07-12 Fujitsu Ltd 半導体装置
JP2013175798A (ja) * 2013-06-14 2013-09-05 Renesas Electronics Corp 半導体装置
WO2020000435A1 (fr) * 2018-06-29 2020-01-02 华为技术有限公司 Circuit intégré et sa structure d'interconnexion
CN112400220A (zh) * 2018-06-29 2021-02-23 华为技术有限公司 集成电路及其互连结构
CN112400220B (zh) * 2018-06-29 2022-04-22 华为技术有限公司 集成电路及其互连结构
KR102095208B1 (ko) * 2018-11-21 2020-03-31 (주)샘씨엔에스 반도체 소자 테스트를 위한 다층 세라믹 기판 및 그 제조 방법
US11282744B2 (en) * 2019-09-30 2022-03-22 Systems On Silicon Manufacturing Co. Pte. Ltd. Enhanced intermetal dielectric adhesion

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