CN101937893A - 半导体器件 - Google Patents
半导体器件 Download PDFInfo
- Publication number
- CN101937893A CN101937893A CN2010101949557A CN201010194955A CN101937893A CN 101937893 A CN101937893 A CN 101937893A CN 2010101949557 A CN2010101949557 A CN 2010101949557A CN 201010194955 A CN201010194955 A CN 201010194955A CN 101937893 A CN101937893 A CN 101937893A
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- interconnect structure
- multilayer interconnect
- hole
- pad
- insulation interbed
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Abstract
本发明涉及一种半导体器件。在半导体器件中,下部多层互连结构、中间通孔级绝缘间层、以及上部多层互连结构被按照此顺序堆叠在平面图中与焊盘重叠的区域中;上部多层互连结构的上部互连和通孔被形成为连接至焊盘布置区域中的焊盘;中间通孔级绝缘间层不具有形成在其中的连接上部多层互连结构中的通孔或者互连与下部多层互连结构中的通孔或者互连的导电材料层;并且由被包含在下部多层互连结构中的通孔级绝缘间层中的通孔占据的面积的比率小于由被包含在上部多层互连结构中的通孔级绝缘间层中的通孔占据的面积的比率。
Description
本申请基于日本专利申请No.2009-131030,其内容在此通过引用并入。
技术领域
本发明涉及一种半导体器件,并且更加具体地涉及具有在基板的上方提供的诸如焊盘的衬垫的半导体器件。
背景技术
近年来,通常具有2.7或者更小的介电常数(k值)的低介电常数绝缘膜(低k膜)已经被日益更多地用于多层互连结构中的绝缘间层。然而,低k膜的机械强度通常较差。因此存在下述问题,在引线键合、探针探测等等的工艺中焊盘被施加有负荷时绝缘间层可能破裂或分离,并且因此成品的产量趋于降低。
国际专利公开No.WO2005/096364公布一种半导体器件,该半导体器件使用具有差的强度和粘性的低介电常数绝缘间层,其被构造为大量的没有被电气地连接至电路的加强通孔图案形成在上和下互连层中形成的加强互连图案相互重叠的区域中,以相互连接加强互连图案。根据此描述,由于增加的结构强度,在制造工艺或者封装中的膜的破裂或者分离可以是可抑制的。
日本特开专利公开No.2004-235416公布了一种半导体器件,该半导体器件具有焊盘,该焊盘形成在半导体基板上;上部铜互连层,该上部铜互连层形成在焊盘下方,并且具有比其中形成电路互连的层更大的面积的比率;以及下部铜互连层,该下部铜互连层电气地分离上部铜互连层,并且比上部铜互连层更加接近于半导体基板地形成。
发明内容
根据日本特开专利申请No.2004-235416的描述,通过在焊盘的下方提供具有大的铜的面积比率的上部铜互连层,可以在探测或引线键合的工艺中缓和可能被施加给诸如低k膜的绝缘膜的负荷,并且因此在抵抗焊盘上的冲击方面改进层结构。然而,随着近来在新一代的LSI中的焊盘间节距的减小,焊接线的直径也减小。因此,存在焊接工艺中每单位面积的负荷增加的趋势。因此,特别在低k膜的增加的组成比率下,仅通过被提供在焊盘的下方的具有大的铜的面积的比率的上部铜互连层,时常不能将施加给焊盘的冲击吸收到令人满意的程度。在这样的情况下,预计在下层中可能发生绝缘间层的分离从而使层结构变形,并且因此增加焊盘的分离的发生几率。
根据本发明,提供了一种半导体器件,其包括:
基板;
多层互连结构,该多层互连结构形成在基板的上方,并且至少在层的一部分中包含由低k膜组成的绝缘间层;以及
焊盘,该焊盘形成在基板上方的多层互连结构上方,
该多层互连结构进一步包括:
下部多层互连结构,该下部多层互连结构具有在其中堆叠的包含形成于在平面图中与焊盘重叠的区域中的互连的互连级绝缘间层,和包含形成于在平面图中与焊盘重叠的区域中的通孔的通孔级绝缘间层;
上部多层互连结构,该上部多层互连结构形成在下部多层互连结构的上方并具有在其中堆叠的包含形成于在平面图中与焊盘重叠的区域中的互连的互连级绝缘间层;和包含形成于在平面图与焊盘重叠的区域中的通孔的通孔级绝缘间层;以及
中间绝缘膜,该中间绝缘膜形成在下部多层互连结构和上部多层互连结构之间,
在平面图中与焊盘重叠的区域中,上部多层互连结构中的通孔和互连形成为与焊盘电气地连接。
在平面图中与焊盘相重叠的区域中,中间绝缘膜不具有在其中形成的导电材料层,该导电材料层连接上部多层互连结构中的通孔或者互连和下部多层互连结构中的通孔或者互连,并且
在平面图中与焊盘重叠的区域中,由被包含在下部多层互连结构中的通孔级绝缘间层中的通孔占据的面积的比率小于由被包含在上部多层互连结构中的通孔级绝缘间层中的通孔占据的面积的比率。
注意,而且上面描述的组件的所有的任意组合,并且在方法、器件等等当中进行的本发明中的表述的任何交换都可以作为本发明的实施例。
附图说明
结合附图,根据某些优选实施例的以下描述,本发明的以上和其它方面、优点和特征将更加明显,其中:
图1是示出本发明的一个实施例的半导体器件的示例性构造的截面图;
图2是示出本发明的一个实施例中的半导体器件的示例性构造的平面图;
图3A和图3B是图1中所示的半导体器件的横剖图;
图4是示出将焊接线焊接到半导体器件的焊盘的过程的截面图;
图5A和图5B是示出本发明的第一实施例中的半导体器件的效果的截面图;
图6是示出本发明的一个实施例中的半导体器件的效果的图;
图7A和图7B是示出本发明的实施例中的半导体器件的其它示例性构造的截面图;以及
图8至图10是示出本发明的实施例中的半导体器件的其它示例性构造的截面图。
具体实施方式
根据我们的深入调查本发明人发现,通过将半导体器件构造为可以随着负荷朝着更深侧传播,通过绝缘间层逐渐地吸收在引线键合或者探针探测的工艺中施加给焊盘的负荷,从而可以成功地避免通常由于绝缘间层的分离导致的层结构的变形,并且从而可以减少焊盘的分离的发生几率。为了实现该构造,本发明采用中间绝缘膜以分离多层互连结构的下部分和上部分,同时将由通孔占据的面积的不同比率设置给单独的部分。
国际专利申请No.WO2005/096364描述被提供有增强通孔图案的构造,但是与本发明的构造不同,没有考虑进入上和下部分的多层互连结构的分离,同时将由通孔占据的面积的不同比率设置给单独的部分。虽然日本特开专利申请公开No.2004-235416描述了由互连占据的面积的比率,但也没有考虑通孔。因此,考虑到防止通常由于绝缘间层的分离导致的层结构变形并且考虑到将焊盘的分离的发生抑制到低水平还存在问题。
根据本发明的构造,被连接至焊盘的互连和通孔被提供在平面图中与焊盘重叠的区域中的上部多层互连结构中。由于此构造,即使在探针探测或者引线键合的工艺中被施加有负荷,可以改进上部多层互连结构的强度,并且从而可以防止绝缘间层破裂。此外,不具有在其中形成的导电材料的中间绝缘膜,被提供在上部多层互连结构的下面。因此,通过中间绝缘膜可以缓和被施加给焊盘的任何冲击,并且因此在一定程度上可以改进对冲击的抵抗。另外,由于在被形成在中间绝缘膜的下面的下部多层互连结构中由通孔占据的面积的比率设置为小的值,随着负荷朝着更深(更下)侧传播可以通过下部多层互连结构逐渐地吸收并且缓和不能通过上部多层互连结构和中间绝缘膜吸收的冲击。因此,绝缘间层和焊盘的分离的发生可以被抑制到低水平,并且因此可以改进最终产品的产量。
根据本发明,在其中形成有焊盘的半导体器件中,即使焊盘被施加有负荷,绝缘间层和焊盘的分离的发生可以被抑制到低水平,并且从而可以改进最终产品的产量。
现在在此将参考示例性实施例来描述本发明。本领域的技术人员将会理解能够使用本发明的教导完成许多可替选的实施例并且本发明不限于为解释性目的而示出的实施例。
参考附图将会解释本发明的实施例。注意,附图中所有类似的组件被给予类似的附图标记或者符号,其解释将没有必要进行重复。
图1是示出本实施例的半导体器件的示例性构造的截面图,并且图2是本实施例的半导体器件的示例性构造的平面图。
半导体器件100包括基板1;多层互连结构,该多层互连结构被形成在基板的上方;以及焊盘72(衬垫),该焊盘72被形成在多层互连结构的上方。由于在平面图中与焊盘72重叠的下方的区域(在下文中,被称为“焊盘布置区域94”)中,本实施例中的半导体器件100在结构上具有特性特征,从而在此附图仅示出其中形成有焊盘72的区域。
在基板1的上方,形成通常其中掩埋有晶体管等等的绝缘间层2。多层互连结构形成在绝缘间层2的上方。通过使用诸如氧化硅膜的具有相对大的机械强度的材料可以构造这里的绝缘间层2。尽管在这里没有示出,但是绝缘间层2具有多个其中形成的接触,通过该接触基板1中的扩散层与上层中的互连相接触。
在本实施例中,形成在基板1上的绝缘间层2的上方的多层互连结构包含形成在其下部分中并且更加接近基板1的下部多层互连结构90,和形成其上部分中、在下部多层互连结构90上方并且更加接近焊盘72的上部多层互连结构92。在下部多层互连结构90和上部多层互连结构92之间,提供中间通孔级绝缘间层48(中间绝缘膜)。
通过诸如硅基板的半导体基板可以构造基板1。尽管在附图中没有示出,基板1被提供有诸如晶体管、电阻器以及电容器的半导体基板,以及包含用于连接这些半导体元件的电路互连的内部电路。通过形成在多层互连结构中的任何层中的互连、形成在基板1中的扩散层、以及通常由杂质扩散多晶硅组成的导电层可以构造电路互连。在本实施例中,内部电路可以被提供在焊盘布置区域94外部的区域中,或者内部电路的一部分可以被布置在焊盘布置区域94中以给出焊盘下电路(CUP)结构。在焊盘下电路(CUP)结构中,内部电路可以被提供在焊盘布置区域94中的下部多层互连结构90中。
通过按照此顺序堆叠的蚀刻停止膜13、下部互连级绝缘间层14、阻挡绝缘膜17、下部通孔级绝缘间层18、下部互连级绝缘间层24、阻挡绝缘膜27、下部通孔级绝缘间层28、下部互连级绝缘间层34、阻挡绝缘膜37、下部通孔级绝缘间层38、下部互连级绝缘间层44、以及阻挡绝缘膜47来构造下部多层互连结构90。
下部互连级绝缘间层14、下部互连绝缘间层24、下部互连级绝缘间层34、以及下部互连级绝缘间层44具有分别形成在其中的下部互连15、下部互连25、下部互连35、以及下部互连45。可以通过主要由铜组成的金属膜、以及分别被形成为与金属膜的侧表面和下表面接触的阻挡金属膜26、阻挡金属膜36、阻挡金属膜46来构造下部互连15、下部互连25、下部互连35、以及下部互连45中的每一个。可以通过通常含有诸如Ta或者Ru的难熔金属的材料来构造阻挡金属膜16、阻挡金属膜26、阻挡金属膜36、以及阻挡金属膜46。在一个示例性情况下,这些阻挡金属膜可以由含有堆叠的膜的Ta组成。
下部通孔级绝缘间层18、下部通孔级绝缘间层28、以及下部通孔级绝缘间层38具有分别形成在其中的下部通孔19、下部通孔29、以及下部通孔39。类似于互连,也可以通过主要由铜组成的金属膜以及分别形成为与金属膜的下表面和侧表面接触的阻挡金属膜26、阻挡金属膜36、以及阻挡金属膜46来构造下部通孔19、下部通孔29、以及下部通孔39中的每一个。而且可以类似于诸如阻挡金属膜16的上述阻挡金属膜来构造这些阻挡金属膜。注意,在这里示出为构造双镶嵌结构同时分别与下部互连25、下部互连35、以及下部互连45集成在一起的下部通孔19、下部通孔29、以及下部通孔39可以替代地构造单镶嵌结构。
通过按照此顺序堆叠的上部互连级绝缘间层54、阻挡绝缘膜57、上部通孔级绝缘间层58、以及上部互连级绝缘间层64来构造上部多层互连结构92。
上部互连级绝缘间层54和上部互连级绝缘间层64具有分别形成在其中的上部互连55和上部互连65。类似于下部多层互连结构90中的互连,也通过主要由铜组成的金属膜,和分别形成为与金属膜的下表面和侧表面接触的阻挡金属膜56和阻挡金属膜66来构造上部互连55和上部互连65中的每一个。上部通孔级绝缘间层58具有形成在其中的上部通孔59。也可以通过主要由铜组成的金属膜,和形成为与金属膜的下表面和侧表面接触的阻挡金属膜66来构造上部通孔59中的每一个。而且可以类似于阻挡金属膜16来构造阻挡金属膜。注意,在这里示出为构造双镶嵌结构同时与上部互连65集成在一起的上部通孔59可以替代地构造单镶嵌结构。通过上部通孔59连接上部互连55和上部互连65。
例如,被包括在下部多层互连结构90和上部多层互连结构92中的与单独的互连和单独的通孔接触的阻挡金属膜的厚度可以被调整为大约3nm到20nm。例如在32nm结中,各个互连可以总计金属膜和阻挡金属膜的厚度从而给出大约80nm到120nm的总厚度。
通过由多孔硅、多孔SiOC、多孔SiOCH、无孔SiOC或者SiOCH、HSQ(含氢倍半硅氧烷)、梯形氧化物(Lox)、以及无定形碳示例的通常采用的低k膜材料来构造下部互连级绝缘间层14、下部互连级绝缘间层24、下部互连级绝缘间层34、以及下部互连级绝缘间层44。这些绝缘间层的厚度通常可以被调整为大约50nm到120nm。
而且可以使用类似于在下部多层互连结构90中的下部互连级绝缘间层中使用的材料来构造上部互连级绝缘间层54和上部互连级绝缘间层64。上部互连级绝缘间层54的厚度通常可以被调整为大约50nm到120nm。上部互连级绝缘间层64的厚度通常可以被调整为大约800nm。
通过由诸如多孔硅、多孔SiOC、多孔SiOCH、无孔SiOC或者SiOCH、HSQ(含氢倍半硅氧烷)、梯形氧化物(Lox)、以及无定形碳的低k膜材料示例的通常采用的绝缘膜材料;和诸如SiO2的绝缘膜材料来构造下部通孔级绝缘间层18、下部通孔级绝缘间层28、下部通孔级绝缘间层38、中间通孔级绝缘间层以及上部通孔级绝缘间层58。这些绝缘间层的厚度通常可以被调整为大约30nm到150nm。
通常可以通过SiCN和SiC来构造阻挡绝缘膜17、阻挡绝缘膜27、阻挡绝缘膜37、阻挡绝缘膜47、阻挡绝缘膜57、以及阻挡绝缘膜67。这些绝缘膜的厚度通常可以调整为大约10nm到50nm。
可以使用类似于在下部多层互连结构90中的下部通孔级绝缘间层中使用的材料来构造中间通孔级绝缘间层48。中间通孔级绝缘间层48的厚度通常可以被调整为大约30nm到180nm。
在上部多层互连结构92中的上部互连级绝缘间层64的上方,提供的按照此顺序堆叠的阻挡绝缘膜67、通孔级绝缘间层68、保护绝缘膜73、以及聚酰亚胺膜74。通过保护绝缘膜73和聚酰亚胺膜74来构造钝化膜。例如,可以通过SiCN膜构造保护绝缘膜73。
注意,为了便于解释,使得在图2中实际上形成在焊盘互连75上方的聚酰亚胺膜74为透明的。图2示出焊盘互连75的焊盘内边缘75a和焊盘外边缘75b、和聚酰亚胺膜74的内边缘74a、以及焊盘通孔69的外边缘69b。焊盘互连75和焊盘72的焊盘通孔69的外周部分覆盖有聚酰亚胺膜74,从而焊盘通孔69仅暴露在由聚酰亚胺膜74的内边缘74a指定的区域中。焊盘互连75的焊盘外边缘75b和焊盘内边缘75a覆盖有聚酰亚胺膜74。如图2中所示,本实施例中的焊盘布置区域94可以是由焊盘72的焊盘外边缘75b包围的区域。
通过焊盘通孔69和焊盘互连75来构造焊盘72。通常通过主要由铝组成的金属材料来构造焊盘通孔69和焊盘互连75。其扁平部分中的焊盘通孔69的厚度通常可以被调整为大约0.8μm至2μm。焊盘72被形成为在被布置在被形成在其下方的阻挡金属膜70和上部互连65之间的同时与上部互连65相接触。可以通过包含诸如Ta的难熔金属的材料来构造阻挡金属膜70。例如,可以通过使用包含TiN的材料来构造阻挡金属膜70。在其扁平部分中的阻挡金属膜70的厚度通常可以被调整为大约50nm至300nm。
在本实施例中,被包含在上部多层互连结构92中的上部互连65和上部互连55在平面图中几乎占据与焊盘72相同的区域。上部互连65和上部互连55可以被形成为分别以一体的方式分布在焊盘布置区域94的整个区域的上方。在本实施例中,上部互连65和上部互连55可以被构造为具有大于具有形成在其中的内部电路的层的面积的比率。在本实施例中,由被包含在上部多层互连结构92中的上部互连级绝缘间层中的互连占据的面积的比率可以被调整为70%或者更大。因此可以改进冲击抵抗。由被包括在上部多层互连结构92中的互连级绝缘间层中的互连占据的面积的比率可以被调整为95%或者更小。因此可以避免在用于形成互连的化学机械抛光(CMP)的工艺中可能出现的碟形。这里的面积的比率(也被称为“数据比率”)可以被定义为通过将在平面图中位于焊盘布置区域94中的互连的总面积除以焊盘布置区域94的面积(由附图中的焊盘外边缘75b包围的区域)获得的值。
通过上部通孔59,上部互连65和上部互连55可以被包含在焊盘布置区域94中。换言之,本实施例中的上部多层互连结构92可以理解为具有形成在其中的被电气地连接至焊盘布置区域94中的焊盘72的互连和通孔的层。在这里焊盘72可以被构造为通过上部互连65、上部通孔59、以及上部互连55被连接至半导体器件100的内部电路(未示出)。
另一方面,在本实施例中的焊盘布置区域94中,不存在连接下部多层互连结构90的顶层中的下部互连45和上部多层互连结构92的底层中的上部互连55的诸如通孔的导电材料。在本实施例中,在下部多层互连结构90和上部多层互连结构92之间提供中间通孔级绝缘间层48。在中间通孔级绝缘间层48中,在焊盘布置区域94中,不存在连接下部多层互连结构90的顶层中的下部互连45和上部多层互连结构92的底层中的上部互连55的导电材料。换言之,本实施例中的下部多层互连结构90可以理解为具有形成在其中的没有被连接至焊盘布置区域94中的焊盘72的通孔和互连的层。然而,下部多层互连结构90可以被构造为被包含在其中的互连和通孔通过形成在焊盘布置区域94的外部的通孔被电气地连接至焊盘72。
尽管没有具体地限制,由被包含在下部多层互连结构90中的下部互连级绝缘间层中的互连占据的面积的比率通常可以被调整为15%或者较大。因此可以提高冲击抵抗。由被包括在下部多层互连结构90中的下部互连级绝缘间层中的互连占据的面积的比率可以被调整为95%或者较小。因此可以避免在用于形成互连的化学机械抛光(CMP)的工艺中可能出现的碟形。
在如此构造的半导体器件中100中,在焊盘布置区域94中,由被包含在下部多层互连结构90中的通孔级绝缘间层中的下部通孔占据的面积比率可以被设置为小于被包含在上部多层互连结构92中的上部通孔级绝缘间层58中的上部通孔59占据的面积的比率。这里的面积的比率(而且被称为“数据比率”)可以被定义为将平面图中位于焊盘布置区域94中的通孔的基于掩模的总面积除以焊盘布置区域94的面积(由附图中的焊盘外边缘75b包围的区域)获得的值。
图3A是示出被包含在上部多层互连结构92中的上部通孔级绝缘间层58和形成在其中的上部通孔59的示例性构造的横剖图。图3A对应于沿着图1的线A-A’截取的截面图。图3B是示出被包含在下部多层互连结构90中的下部通孔级绝缘间层38和形成在其中的下部通孔39的示例性构造的横剖图。图3B对应于沿着图1的线B-B’截取的截面图。为了简单理解单层中由通孔占据的面积的比率,示意性地示出这些附图中的通孔。
如图3A中所示,二十五个上部通孔59被布置在上部通孔级绝缘间层58中以形成5×5矩阵。另一方面,如图3B中所示,四个下部通孔39被布置在下部通孔级绝缘间层38中以形成2×2矩阵。尽管没有示出,但是在下部通孔级绝缘间层28中并且在下部通孔级绝缘间层18中,单层中由通孔占据的面积的比率可以被设置为小于上部通孔级绝缘间层58的面积的比率,类似于下部通孔级绝缘间层38。
图3A和图3B示出上部通孔59和下部通孔39具有相同的开口尺寸的示例性情况。对于所有的通孔具有相同的开口尺寸的情况,下部通孔级绝缘间层18、下部通孔级绝缘间层28、以及下部通孔级绝缘间层38中的每一个可以具有比上部通孔级绝缘间层58具有的数目小的通孔。
通过此构造,可以吸收在探测和引线键合的工艺中被施加给焊盘72的任何冲击,并且因此可以将绝缘间层的分离的发生抑制到低水平。在下面将会解释可能的机制。
图4是示出将焊接线78焊接到半导体器件100的焊盘72的过程的剖视图。在到焊盘72的引线键合的工艺中,形成在焊接线78的末端处的球77接触焊盘72,并且被焊接到焊盘72,同时在预定的条件下被施加有负荷和超声波。在此工艺中,焊盘72被施加有负荷,并且结果产生冲击。
图5A是示意性地示出在焊盘72处产生的冲击传播到本实施例的半导体器件100的多层互连结构的模式的剖视图。
在本实施例中,几乎占据与焊盘72相同的区域的上部互连65形成在焊盘72的下方,如上所述。在上部互连65的下方,形成几乎占据与焊盘72相同的区域的上部互连55。在上部互连65和上部互连55之间,提供具有大的面积比率的上部通孔59。结果,上部互连55、上部通孔59以及上部互连65被构造为好像它们给出单个的厚的焊盘。此部分被示出为图5A中的上部多层互连结构92。与通常由氧化膜组成的绝缘间层相比较,由于由诸如铜的金属的膜组成的通孔和互连在弹性上较大,这表示对外部施加的力的排斥性质,从而通过在焊盘72的下方提供这样构造的互连和通孔可以在强度上和在对在引线键合的工艺中可能施加的冲击的抵抗方面改进上部多层互连结构。因此,在半导体器件100的上部分中,可以防止绝缘间层引起破裂。
在上部多层互连结构92的下方,提供不具有形成在其中的导电材料层的中间通孔级绝缘间层48。因此,通过中间通孔级绝缘间层48可以缓和可能被施加给焊盘72的任何冲击,并且因此在一定程度上可以改进对于冲击的抵抗。
然而,上部多层互连结构92和中间通孔级绝缘间层48没有完全吸收的引起施加给焊盘72的冲击的一部分的负荷可能时常通过中间通孔级绝缘间层48施加给下部多层互连结构90。结果,下部多层互连结构90可以偶然地引起膜的分离,和层结构的变形。
考虑防止膜的这种分离,重要的是,均匀地分布从上部分传播的负荷。通过减少由诸如本实施例的半导体器件100中的下部多层互连结构90的单独的通孔级绝缘间层中的通孔占据的面积的比率,可以以有效的方式表达在引线键合和探测的工艺中向下分布负荷的操作。通过减少单独的通孔级绝缘间层中由通孔占据的面积的比率,随着它朝着更深侧传播可以逐渐地缓和从上部分施加的负荷,并且从而可以吸收冲击。这样可以防止膜的分离。
另一方面,对于由下部多层互连结构90中的单独的通孔级绝缘间层中的通孔占据的面积的比率大的情况,可以仅在小缓和程度的情况下直接地允许被施加给下部多层互连结构90的负荷朝着更深侧传播。图5B示出具有大的由下部多层互连结构90的通孔级绝缘间层中的通孔占据的面积比率的构造。在此种构造中,可以直接地允许被施加给下部多层互连结构90的负荷朝着更深侧传播,并且然后集中在底层中的下部互连15和下部通孔19层之间(由附图中的虚线包围的部分)。作为形成在基板1的上方的第一互连层的形成在基板1和下部互连15之间的绝缘间层2通常由除了低k膜之外的诸如二氧化硅膜的相对硬的绝缘膜组成。而且基板1具有大的硬度。为此,在下部多层互连结构90的下方不存在缓和层,从而不能分布负荷。如果仅没有如上所述地成功地分布负荷,那么在负荷集中的位置处可能出现膜的分离,并且层结构可以变形。结果,焊盘72可以更容易由于在传输期间对包装材料的滚压或碰撞、在探测和线焊接工艺中在绝缘间层中产生的破裂、或者在组装为成品的工艺中可能施加的冲击而引起分离等等。
从另一方面,每个下部通孔级绝缘间层包含两种类型的组成,即通常由具有大的杨氏模量的铜组成的通孔,和具有小的杨氏模量的绝缘间层。在探测和引线键合的工艺中向下施加的负荷下,在同一层中存在杨氏模量一很大地不同的两种组成可以导致各处不同变形模式。例如,由多孔SiOC组成的通孔级绝缘间层将会具有大约4Gpa的杨氏模量。另一方面,铜具有大约110Gpa的杨氏模量。因此,在下部通孔级绝缘间层中可能出现不同的变形模式。在杨氏模量很大地不同的两种材料的存在下,通过极度地增加材料中的任意一个的组成比率,系统的整个杨氏模量可以更能假定为均匀的,并且因此在负荷下系统可以不易变形。
在本实施例中,由被包含在下部多层互连结构90中的下部通孔级层问绝缘膜18、下部通孔级绝缘间层28、以及下部通孔级绝缘间层38中的每一个中的通孔占据的面积的比率可以被调整为小于4%。通过调整,在每层中可以增加绝缘膜的组成比率,整层的整体弹性可以近似为均匀的值,并且因此在负荷下层可以不易变形。结果,可以以更加有效的方式避免在探测和线焊接工艺中的绝缘间层的破裂,以及绝缘膜或者焊盘72的分离。
图6是示出在图1中所示的构造中的焊盘布置区域94中由包含在下部多层互连结构90中的下部互连级绝缘间层中的通孔占据的面积的比率与线剪切测试中的缺陷率之间的关系的图。
在测试中,多孔SiOC被用于单独的通孔级绝缘间层,并且多孔硅被用于单独的互连级绝缘间层。由被包含在上部多层互连结构92中的上部通孔级绝缘间层58中的上部通孔占据的面积的比率被设置为20%。由被包含在下部多层互连结构90中的下部互连级绝缘间层中的每一个中的互连占据的面积的比率分别被设置为25%,并且由被包含在上部多层互连结构92中的上部互连级绝缘间层中的每一个占据的面积的比率分别被设置为88.9%。
这样构造的半导体器件100进行球剪切测试,其中探针被勾在焊接线78上并且在横向方向中进行拉动。在12g的焊接中的最佳负荷下,对于由通孔占据的面积的比率为3.2%,发现球剪切测试中的缺陷率几乎为零。另一方面,对于由通孔占据的面积的比率为4.5%,发现球剪切测试中的缺陷率约为2%,并且对于面积比率为7.3%,缺陷率增加达到约8%。另外,在不是最佳负荷的10g的负荷下,对于由通孔占据的面积的比率为3.2%,球剪切测试中的缺陷率被减少成低至对于由通孔占据的面积的比率为7.3%时获得的值的约80%。
在本实施例中,由被包括在上部多层互连结构92中的上部通孔绝缘间层58中的通孔占据的面积的比率可以被调整为4%或者更大,并且更加优选为7%或者更大。通过将由通孔占据的面积的比率调整为7%或者更大,上部多层互连结构92可以保持在足够的强度级别上。
如上所述,根据本实施例的半导体器件100的构造,被连接至焊盘72的通孔和互连被提供在上部多层互连结构92中的焊盘布置区域中。由于由被包含在上部多层互连结构92中的层的通孔占据的面积的比率被设置为高级别,可以改进上部多层互连结构92的强度,并且因此即使在探测和引线键合的工艺中可能施加的负荷下可以防止绝缘间层破裂。
另外,不具有形成在其中的导电材料层的中间通孔级绝缘间层48被提供在上部多层互连结构92的下方。因此,通过中间通孔级绝缘间层48可以缓和可能施加给焊盘72的冲击,并且因此在一定程度上可以提高对冲击的抵抗。因此可以防止焊盘布置区域94中的单层变形,并且因此可以防止焊盘72分离。
由于在中间通孔级绝缘间层48的下方形成的下部多层互连结构90中由通孔占据的面积的比率被设置为低级别,从而随着它朝着更深侧传播可以通过绝缘间层逐渐地吸收被施加给焊盘72、但是没有被上部多层互连结构92和中间通孔级绝缘间层48充分地吸收的冲击。因此,绝缘间层和焊盘的分离的发生可以被抑制到低水平,并且因此可以提高最终产品的产量。
当在装运之前通过探针探测检查产品时,用于探测的探针接触焊盘72。根据本发明的产品充分地防止可能施加的冲击,从而可以防止焊盘72下方的绝缘间层破裂。
由于由被包含在下部多层互连结构90中的下部通孔级绝缘间层中的通孔占据的面积的比率小,因此对于内部电路的一部分被形成焊盘布置区域94中以给出焊盘下电路(CUP)结构的情况也可以获得上述效果,而没有反面影响内部电路的互连的布局。
接下来,将会解释本实施例的半导体器件100的修改示例。
图7A和图7B是示出图5A中所示的半导体器件100的修改示例的示意图。虽然在图5A中示出的示例是被包括在下部多层互连结构90中的单独的下部通孔级绝缘间层具有相同的由通孔占据的面积的比率,但是它们可以替代地具有不同的面积的比率。
在图7A和图7B中示出的示例中,在所有下部通孔级绝缘间层中最下面的下部通孔级绝缘间层18(具有形成在其中的通孔19的绝缘间层)中,由包含在下部多层互连结构90中的单独的下部通孔级绝缘间层的通孔占据的面积的比率最大。如参考图5B已经解释的,由于在下部多层互连结构90的下方不存在缓和层,从而在下部多层互连结构90的下方不能缓和负荷。如果下部互连15向下下沉,那么层结构不会被压缩,并且因此可能变形。因此下部通孔级绝缘间层18可以被构造为具有由通孔占据的大的面积比率,从而保持足够的强度级别。即使通过此构造,由下部通孔级绝缘间层18中的通孔占据的面积的比率还被保持小于与上述相类似的下部多层互连结构90的上部通孔级绝缘间层中的面积的比率,从而下部多层互连结构90可以保持吸收冲击的效应。
在图7A中所示的构造中,在较高级别的高度的层中由通孔占据的面积的比率被设置为较小。图8是示出与此种构造相对应的半导体器件100的示例性构造的图。借助于此构造,从上部分可以逐渐地向下缓和施加给上部多层互连结构92的负荷。
在图7B中所示的构造中,在结构的中间的下部通孔级绝缘间层28(具有形成在其中的通孔29的绝缘间层)中使由通孔占据的面积的比率最小。图9是示出与此种构造相对应的半导体器件100的示例性构造的图。借助于此构造,可以通过结构的中间的层(下部通孔级绝缘间层28)缓和施加给下部多层互连结构90的负荷和从下部互连15反作用的力。
图10是示出其中通过倒装芯片焊接本实施例的半导体器件100通过凸块79连接至互连基板80的构造的截面图。
这里的半导体器件100具有焊盘82替代图1中所示的焊盘72。类似于焊盘72,通过焊盘通孔69和焊盘互连75来构造焊盘82。通过诸如主要由铝或者铜组成的金属材料的通常被用于芯片倒装焊接的焊盘材料可以构造焊盘通孔69和焊盘互连75。通过诸如金、金/镍合金、焊料等等的通常被用于倒装芯片焊接的凸块材料来构造凸块79。构造的其它方面可以与图1中所示的半导体器件100的相同。
而且在此构造中,当将凸块79放置在其中的同时焊接半导体器件100的焊盘82和互连基板80时焊盘82会被施加有冲击。由于本实施例的半导体器件100被构造为如上所述地缓和冲击,从而可以将绝缘间层和凸块的分离的发生抑制到低级别,并且因此可以提高最终产品的产量。
参考附图,在上面已经描述本发明的实施例,仅用于解释目的,同时允许采用除了在上面描述的那些之外的任何其它构造。
例如,虽然本实施例示例上部多层互连结构92包含两层互连,并且下部多层互连结构90包含四层互连,包括焊盘72的焊盘互连的总共七层互连的情况,但是可以适当地修改单个结构中的互连的层的数目。
尽管在上述实施例中没有示出,但是在具有形成在其中的互连或者通孔的绝缘层的上方常常提供用于在化学机械抛光的工艺中保护目的的覆盖绝缘膜。被包含在下部多层互连结构90中的绝缘间层的一部分可以是除了低k膜的膜,并且被用于上部多层互连结构92的绝缘间层的一部分可以是低k膜,其中可以适当地组合两种情况。
例如,还可以允许的是,将被包含在下部多层互连结构90中的下部通孔级绝缘间层中的下部通孔的节距设置为比包含在上部多层互连结构92中的上部通孔级绝缘间层中的上部通孔的节距宽。
显然的是,本发明不限于上述实施例,而是可以在不脱离本发明的范围和精神的情况下进行修改和变化。
Claims (8)
1.一种半导体器件,包括:
基板;
多层互连结构,所述多层互连结构形成在所述基板的上方,并且至少在一部分层中包含由低k膜组成的绝缘间层;以及
焊盘,所述焊盘形成在所述基板的上方的所述多层互连结构的上方,
所述多层互连结构进一步包括:
下部多层互连结构,所述下部多层互连结构具有堆叠在其中的包含形成于在平面图中与所述焊盘重叠的区域中的互连的互连级绝缘间层,和包含形成于在平面图中与所述焊盘重叠的区域中的通孔的通孔级绝缘间层;
上部多层互连结构,所述上部多层互连结构具有堆叠在其中的包含形成于在平面图中与所述焊盘重叠的区域中的互连的互连级绝缘间层,和包含形成于在平面图中与所述焊盘重叠的区域中的通孔的通孔级绝缘间层,并且所述上部多层互连结构形成在所述下部多层互连结构的上方;以及
中间绝缘膜,所述中间绝缘膜形成在所述下部多层互连结构和所述上部多层互连结构之间,
其中在平面图中与所述焊盘重叠的区域中,所述上部多层互连结构中的所述通孔和所述互连形成为与所述焊盘电气地连接,
其中在平面图中与所述焊盘重叠的所述区域中,所述中间绝缘膜不具有形成在其中的下述导电材料层,所述导电材料层连接所述上部多层互连结构中的所述通孔或者所述互连与所述下部多层互连结构中的所述通孔或者所述互连,并且
其中在平面图中与所述焊盘重叠的所述区域中,由被包含在所述下部多层互连结构中的所述通孔级绝缘间层中的所述通孔占据的面积的比率小于由被包含在所述上部多层互连结构中的所述通孔级绝缘间层中的所述通孔占据的面积的比率。
2.根据权利要求1所述的半导体器件,
其中所述下部多层互连结构包括由所述低k膜组成的所述通孔级绝缘间层中的至少一个。
3.根据权利要求1所述的半导体器件,
其中所述低k膜是多孔膜。
4.根据权利要求2所述的半导体器件,
其中所述低k膜是多孔膜。
5.根据权利要求1所述的半导体器件,
其中,在平面图中与所述焊盘重叠的所述区域中,由被包含在所述下部多层互连结构中的所述通孔级绝缘间层中的所述通孔占据的面积的比率小于4%。
6.根据权利要求1所述的半导体器件,
其中,在平面图中与所述焊盘重叠的所述区域中,由被包含在所述上部多层互连结构中的所述通孔级绝缘间层中的所述通孔占据的面积的比率是7%或者更大。
7.根据权利要求1所述的半导体器件,
其中,在平面图中与所述焊盘重叠的所述区域中,由被包含在所述上部多层互连结构中的所述互连级绝缘间层中的所述互连占据的面积的比率是70%或者更大。
8.根据权利要求1所述的半导体器件,
其中,所述下部多层互连结构包含多个所述通孔级绝缘间层,并且
在平面图中与所述焊盘重叠的所述区域中,由被包含在所述下部多层互连结构中的所述多个通孔级绝缘间层当中最接近所述基板的通孔级绝缘间层中的所述通孔占据的面积的比率大于由其它通孔级绝缘间层中的所述通孔占据的面积的比率。
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