CN112349658A - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN112349658A
CN112349658A CN202010315686.9A CN202010315686A CN112349658A CN 112349658 A CN112349658 A CN 112349658A CN 202010315686 A CN202010315686 A CN 202010315686A CN 112349658 A CN112349658 A CN 112349658A
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CN
China
Prior art keywords
insulating layer
pad
protective insulating
disposed
semiconductor device
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Pending
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CN202010315686.9A
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English (en)
Inventor
崔慜贞
申树浩
李瑌真
韩正勋
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN112349658A publication Critical patent/CN112349658A/zh
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Abstract

公开了一种半导体器件。所述半导体器件包括：层间绝缘层，设置在基底上；多个中部互连件，设置在层间绝缘层中；垫，设置在层间绝缘层上；上部互连件，设置在层间绝缘层上；保护绝缘层，覆盖垫的边缘、上部互连件以及垫与上部互连件之间的水平的间隙，保护绝缘层在垫上具有开口；以及凸块，设置在垫上，凸块在保护绝缘层上延伸并且从自顶向下的视图来看与上部互连件叠置。所述多个中部互连件中的在竖直方向上最靠近垫的中部互连件之中的至少一个中部互连件具有第一竖直厚度，垫具有为第一竖直厚度的两倍至100倍的第二竖直厚度，垫与上部互连件之间的所述间隙的长度为1μm或更大，并且保护绝缘层的上表面是平坦的。

Description

半导体器件
本专利申请要求于2019年8月9日在韩国知识产权局(KIPO)提交的第10-2019-0097284号韩国专利申请的优先权和权益，该韩国专利申请的公开内容通过引用全部包含于此。
技术领域
与示例实施例一致的器件和方法涉及具有厚金属层和凸块的半导体器件和形成该半导体器件的方法。
背景技术
正在对采用形成在电极垫(“pad”，也称为焊盘)上的凸块的半导体器件进行研究。凸块的形状可以由与电极垫和凸块相邻的保护绝缘层的构造来确定。凸块的台阶导致诸如接触电阻增加和接合缺陷的问题。
发明内容
发明构思的示例实施例意图提供具有改善的电流驱动性、高信号传输速率和高物理/化学可靠性的半导体器件及其形成方法。
根据一些实施例，半导体器件包括：层间绝缘层，设置在基底上；多个中部互连件，设置在层间绝缘层中；垫，设置在层间绝缘层上；上部互连件，设置在层间绝缘层上；保护绝缘层，覆盖垫的边缘、上部互连件以及垫与上部互连件之间的水平的间隙，保护绝缘层在垫上具有开口；以及凸块，设置在垫上，凸块在保护绝缘层上延伸并且从自顶向下的视图来看与上部互连件叠置。所述多个中部互连件中的在竖直方向上最靠近垫的中部互连件之中的至少一个中部互连件具有第一竖直厚度，垫具有为第一竖直厚度的两倍至100倍的第二竖直厚度，垫与上部互连件之间的所述间隙的长度为1μm或更大，并且保护绝缘层的上表面是平坦的。
根据一些实施例，半导体器件包括：层间绝缘层，设置在基底上；多个有源/无源元件，设置在基底上；多个中部互连件，设置在层间绝缘层中；垫，设置在层间绝缘层上；上部互连件，设置在层间绝缘层上；保护绝缘层，覆盖垫的边缘、上部互连件以及垫与上部互连件之间的间隙，保护绝缘层在垫上具有开口；凸块，设置在垫上，凸块在保护绝缘层上延伸并且与上部互连件在竖直方向上叠置；以及贯穿电极，穿过基底并且连接到所述多个中部互连件或垫。所述多个中部互连件中的在竖直方向上最靠近垫的中部互连件之中的一个中部互连件电连接到垫并且具有第一竖直厚度，垫具有为第一竖直厚度的两倍至100倍的第二竖直厚度，垫与上部互连件之间的所述间隙为1μm或更大，并且保护绝缘层的上表面是平坦的。
根据一些实施例，半导体器件包括：层间绝缘层，设置在基底上；多个中部互连件，设置在层间绝缘层中；垫，设置在层间绝缘层上；上部互连件，设置在层间绝缘层上；保护绝缘层，覆盖垫的边缘、上部互连件以及垫与上部互连件之间的间隙，保护绝缘层在垫上具有开口；以及凸块，设置在垫上，凸块在保护绝缘层上延伸并且与上部互连件在竖直方向上叠置。所述多个中部互连件中的在竖直方向上最靠近垫的中部互连件之中的一个中部互连件具有第一竖直厚度，垫具有为第一竖直厚度的两倍至100倍的第二竖直厚度，并且垫与上部互连件之间的所述间隙的水平长度大于或等于第二竖直厚度，并且保护绝缘层的上表面是平坦的。
附图说明
图1至图3是各自示出根据发明构思的实施例的半导体器件的部分的剖视图。
图4是示出图1至图3的部分的放大图。
图5至图8是各自示出根据发明构思的实施例的半导体器件的部分的剖视图。
图9是示出根据发明构思的实施例的半导体器件的剖视图。
图10是图9的部分的放大图。
图11是图9的一些组件的放大图。
图12至图22是用于描述根据发明构思的实施例的形成半导体器件的方法的剖视图。
具体实施方式
图1至图3是各自示出根据发明构思的实施例的半导体器件的部分的剖视图。图4是示出图1至图3的部分的放大图。根据发明构思的实施例的半导体器件可以包括厚顶部金属(TTM)。如在这里所描述的半导体器件可以包括包含针对外部器件的连接端子的半导体芯片或裸片，半导体器件可以包括半导体封装件，其中，所述半导体封装件包括设置在封装件基底上的一个或更多个半导体芯片并且包括针对外部器件的连接端子，或者半导体器件可以包括封装件上封装件器件。
参照图1，根据发明构思的实施例的半导体器件可以包括基底21、多个层间绝缘层31、32、33、34和35、多个中部互连件41和42、多个接触插塞52、垫61、多个上部互连件62、多个保护绝缘层71和72、开口73W以及第一凸块89。多个层间绝缘层31、32、33、34和35可以包括第一层间绝缘层31、第二层间绝缘层32、第三层间绝缘层33、第四层间绝缘层34和第五层间绝缘层35。多个层间绝缘层31、32、33、34和35中的两个或更多个相邻的层可以一起被描述为层间绝缘层。多个中部互连件41和42可以包括多个第一中部互连件41和多个第二中部互连件42。多个保护绝缘层71和72可以一起被描述为保护绝缘层，并且可以包括第一保护绝缘层71和第二保护绝缘层72。第一凸块89可以包括柱结构85和焊料87。柱结构85可以具有大致平坦的顶表面和底表面以及基本垂直的侧表面。焊料87可以具有大致平坦的底表面，但是具有圆形的且弯曲的顶表面和侧表面。柱结构85可以包括阻挡层81、种子层82和柱83。柱结构85可以包括第一部分85A和第二部分85B。
将理解的是，尽管在这里可以使用术语第一、第二、第三等来描述各种元件、组件、区域、层和/或部分，但是这些元件、组件、区域、层和/或部分不应受这些术语限制。例如作为命名惯例，除非上下文另有指示，否则这些术语仅用于将一个元件、组件、区域、层或部分与另一元件、组件、区域、层或部分区分开。因此，在不脱离本发明的教导的情况下，下面在说明书的一个部分中讨论的第一元件、第一组件、第一区域、第一层或第一部分可以在说明书的另一部分中或权利要求中被命名为第二元件、第二组件、第二区域、第二层或第二部分。另外，在某些情况下，即使在说明书中没有使用“第一”、“第二”等来描述术语，在权利要求中仍然可以将其称为“第一”或“第二”，以将彼此不同的要求保护的元件区分。
此外，在这里所描述的器件的各种垫可以为连接到器件的内部布线的导电端子，并且可以在器件的内部布线和/或内部电路与外部源之间传输信号和/或电源电压。例如，半导体芯片的芯片垫可以电连接到半导体芯片的集成电路和半导体芯片连接到的器件，并且可以在半导体芯片的集成电路与半导体芯片连接到的器件之间传输电源电压和/或信号。各种垫可以设置在器件的外表面上或附近，并且通常可以具有平坦的表面区域(通常大于它们所连接到的内部布线的对应表面区域)，以促进连接到诸如凸块或焊球的其他端子和/或外部布线。
第一层间绝缘层31至第五层间绝缘层35可以顺序地堆叠在基底21上。多个中部互连件41和42中的每个可以设置在基底21上的第一层间绝缘层31至第五层间绝缘层35中。与多个第一中部互连件41相比，多个第二中部互连件42可以设置为距基底21的上表面相对较远。例如，多个第一中部互连件41可以设置在第一层间绝缘层31中。多个第二中部互连件42可以设置在第二层间绝缘层32中。多个第二中部互连件42可以呈现第一厚度d1。
多个接触插塞52可以延伸到多个层间绝缘层31、32、33、34和35中。在实施例中，多个接触插塞52中的每个可以穿过第五层间绝缘层35、第四层间绝缘层34和第三层间绝缘层33，并且可以接触多个第二中部互连件42中的对应的一个。将理解的是，当元件被称为“连接”或“结合”到另一元件或者“在”另一元件“上”时，该元件可以直接连接或直接结合到所述另一元件或者在所述另一元件上，或者可以存在中间元件。相反，当元件被称为“直接连接”或“直接结合”到另一元件，或者“接触”另一元件或“与”另一元件“接触”时，不存在中间元件。用于描述元件之间的关系的其它词语应该以类似的方式解释(例如，“在……之间”与“直接在……之间”，“相邻”与“直接相邻”等)。除非上下文另有指示，否则如在这里所使用的术语“接触”是指直接连接(即，触摸)。
垫61和多个上部互连件62可以相对于基底21的顶表面设置在比多个中部互连件41和42的水平高的水平(例如，较高的竖直水平)处。在实施例中，垫61和多个上部互连件62可以直接设置在第五层间绝缘层35上。垫61和多个上部互连件62可以物理连接且电连接到多个接触插塞52。例如，多个上部互连件62中的每个和垫61可以接触多个接触插塞52中的至少对应的一个接触插塞52的上表面。
多个中部互连件41和42可以设置在垫61与基底21之间。垫61和多个上部互连件62可以经由多个接触插塞52物理连接且电连接到多个第二中部互连件42。多个第二中部互连件42可以在竖直方向上比多个第一中部互连件41靠近垫61，并且可以是中部互连件41和42之中的在竖直方向上最靠近垫61(例如，在竖直方向上最邻近垫61)的中部互连件。在实施例中，多个第二中部互连件42中的所选择的一个可以在多个中部互连件41和42之中最靠近垫61。此外，多个第二中部互连件42中的所选择的一个可以例如通过接触插塞52电连接到垫61。多个中部互连件41和42中的每个可以具有大于其竖直高度的横向宽度。多个接触插塞52中的每个可以具有大于其横向宽度的竖直高度。
垫61可以呈现第二厚度d2。多个上部互连件62中的每个可以呈现第三厚度d3。在实施例中，垫61和多个上部互连件62可以包括同时形成的相同材料。第三厚度d3可以基本等于第二厚度d2。垫61和多个上部互连件62可以设置在基本相同的竖直水平处。垫61的下表面和多个上部互连件62的下表面可以基本共面。垫61的上表面和多个上部互连件62的上表面可以基本共面。
当涉及方位、布局、位置、形状、尺寸、组成、量或其它量度时，如在这里所使用的诸如“相同(同一)”、“相等”、“平坦”或“共面”的术语不一定表示完全相同的方位、布局、位置、形状、尺寸、组成、量或其它量度，而是意图包含几乎相同的方位、布局、位置、形状、尺寸、组成、量或在例如由于制造工艺而可能发生的可接受的变化范围内的其它量度。除非上下文或其它陈述另外指出，否则在这里可以使用术语“基本”来强调该含义。例如，被描述为“基本相同”、“基本相等”或“基本平坦”的项可以是完全相同、相等或平坦，或者可以在例如由于制造工艺而可能发生的可接受的变化范围内相同、相等或平坦。
第二厚度d2可以大于第一厚度d1。第二厚度d2可以是第一厚度d1的至少两倍。在实施例中，第二厚度d2可以是第一厚度d1的两倍至100倍，并且在一些实施例中，第二厚度d2可以是第一厚度d1的三倍至十倍。第二厚度d2可以为1μm或更大。在实施例中，第二厚度d2可以在1μm至5μm的范围内。在一些实施例中，第一厚度d1可以在0.01μm至0.5μm的范围内。例如，在一个实施例中，第二厚度d2可以为约2.5μm。互连电阻可以由于垫61的厚度和多个上部互连件62的厚度(即，第二厚度d2和第三厚度d3)而减小。垫61和多个上部互连件62的构造可以具有增加电流驱动性的效果。
多个上部互连件62中的每个可以设置为与垫61相邻。多个上部互连件62中的每个可以与垫61间隔开。多个上部互连件62与垫61之间的每个间隙G1可以为1μm或更大。多个上部互连件62与垫61之间的间隙G1中的每个可以在1μm至10μm的范围内。在实施例中，间隙G1中的每个可以在2.5μm至7.2μm的范围内。多个上部互连件62与垫61之间的间隙G1中的每个可以大于或等于第二厚度d2。由于多个上部互连件62与垫61之间的间隙G1，可以使诸如电阻-电容(RC)延迟的信号延迟最小化。垫61和多个上部互连件62的构造可以具有提高操作速度的效果。尽管在图1中未示出，但是在示出类似于图1或其它附图的特征的示例实施例中，从自顶向下的视图来看，垫61具有基本圆形的形状或者可以具有正方形、矩形或线性形状(例如，细长矩形形状)，并且上部互连件62具有线性形状(例如，细长矩形形状)。
多个保护绝缘层71和72可以覆盖垫61的边缘(例如，垫61的一个侧面或多个侧面以及相邻的上表面)、多个上部互连件62以及垫61与多个上部互连件62之间的间隙G1。开口73W可以设置在垫61上，并且穿过多个保护绝缘层71和72。例如，开口73W可以穿过整个第二保护绝缘层72和第一保护绝缘层71的部分。多个保护绝缘层71和72的上表面可以是基本平坦的。
第一保护绝缘层71可以覆盖垫61的边缘、多个上部互连件62以及垫61与多个上部互连件62之间的间隙G1。第一保护绝缘层71的上表面可以是基本平坦的。第二保护绝缘层72可以设置在第一保护绝缘层71上。第二保护绝缘层72可以包括与第一保护绝缘层71的材料不同的材料，或者由与第一保护绝缘层71的材料不同的材料形成。第二保护绝缘层72的上表面可以是基本平坦的。
在示例性实施例中，第一保护绝缘层71和第二保护绝缘层72中的每个可以包括单层或多层结构。第一保护绝缘层71和第二保护绝缘层72中的每个可以包括诸如高密度等离子体(HDP)氧化物的第一氧化物层、使用原硅酸四乙酯(TEOS)或氟化原硅酸四乙酯(FTEOS)的第二氧化物层或者第一氧化物层和第二氧化物层的组合。
第一凸块89可以设置在垫61上并在多个保护绝缘层71和72上延伸，并且与多个上部互连件62叠置。第一凸块89可以延伸到多个保护绝缘层71和72中，并且可以通过开口73W(例如，通过穿过开口73W接触垫61)连接到垫61。以这种方式，第一凸块89的底表面的第一部分可以通过开口73W接触垫61的顶表面，并且第一凸块89的底表面的第二部分可以接触保护绝缘层(例如，层71和72)中的最上层的顶表面。柱结构85可以设置在垫61上并在多个保护绝缘层71和72上延伸，并且与多个上部互连件62叠置。柱结构85可以延伸到多个保护绝缘层71和72中，并且通过开口73W连接到垫61。焊料87可以设置在柱结构85上。
柱结构85的第一部分85A可以布置在开口73W上。柱结构85的第二部分85B可以在多个保护绝缘层71和72上延伸。第二部分85B可以与垫61的边缘、多个上部互连件62以及垫61与多个上部互连件62之间的间隙G1叠置。例如，在一个实施例中，柱结构85和焊料87从自顶向下的视图来看是基本圆形的，并且第一部分85A被第二部分85B，第一部分85A和第二部分85B中的每个是基本圆形的。
第二部分85B的下表面可以接触第二保护绝缘层72的顶部。第二部分85B的下表面可以形成为基本平坦的。第一部分85A可以延伸到多个保护绝缘层71和72中，并且可以通过开口73W连接到垫61。第一部分85A的下表面可以与垫61接触。第一部分85A的上表面可以比第二部分85B的上表面靠近基底21。第二部分85B的上表面可以形成为基本平坦的。由于第一保护绝缘层71、第二保护绝缘层72和柱结构85的平坦构造，所以可以确保第一凸块89的物理和化学可靠性。
参照图2，根据发明构思的实施例的半导体器件可以包括基底21、多个层间绝缘层31、32、33、34和35、多个中部互连件41和42、多个接触插塞52、垫61、上部互连件62、多个保护绝缘层71和72、开口73W以及第一凸块89。上部互连件62可以设置在垫61的一侧上。垫61和上部互连件62可以设置在基本相同的水平处。第一保护绝缘层71和第二保护绝缘层72中的每个的上表面可以是基本平坦的。
参照图3，根据发明构思的实施例的半导体器件可以包括基底21、多个层间绝缘层31、32、33、34和35、多个中部互连件41和42、多个接触插塞52、垫61、多个保护绝缘层71和72、开口73W以及第一凸块89。该示例不包括上部互连件62。第一保护绝缘层71和第二保护绝缘层72中的每个的上表面可以是基本平坦的。
参照图4，多个上部互连件62中的每个和垫61可以包括下阻挡层65、导电层66和上阻挡层67。导电层66可以置于下阻挡层65与上阻挡层67之间。在实施例中，下阻挡层65可以包括钛(Ti)层。导电层66可以包括铝(Al)层或铜(Cu)层。上阻挡层67可以包括钛/氮化钛(Ti/TiN)层(例如，上阻挡层67可以包括多于一个的层，诸如覆盖有氮化钛层的钛层)。
图5至图8是示出根据发明构思的实施例的半导体器件的部分的剖视图。
参照图5，根据发明构思的实施例的半导体器件可以包括基底21、多个层间绝缘层31、32、33、34和35、多个中部互连件41和42、多个接触插塞52、垫61、多个上部互连件62、多个保护绝缘层76和77、开口73W以及第一凸块89。多个保护绝缘层76和77可以包括第一保护绝缘层76和第二保护绝缘层77。
在实施例中，第一保护绝缘层76可以包括氮化硅，第二保护绝缘层77可以包括氧化硅。第一保护绝缘层76可以共形地覆盖第五层间绝缘层35、垫61和多个上部互连件62的表面。第二保护绝缘层77可以覆盖第一保护绝缘层76。开口73W可以穿过第二保护绝缘层77和第一保护绝缘层76。第二保护绝缘层77的上表面可以包括多个凹入部分，多个凹入部分各自设置在垫61与多个上部互连件62中的一个之间。柱结构85的下表面可以包括多个凸起部分，多个凸起部分从自顶向下的视图来看设置在垫61与多个上部互连件62之间并且对应于第二保护绝缘层77的多个凹入部分。柱结构85的上表面可以包括多个凹入部分，多个凹入部分从自顶向下的视图来看设置在垫61与多个上部互连件62之间，并且多个凹入部分对应于柱结构85的多个凸起部分和第二保护绝缘层77的多个凹入部分并且与柱结构85的多个凸起部分和第二保护绝缘层77的多个凹入部分在竖直方向上叠置。
参照图6，根据发明构思的实施例的半导体器件可以包括基底21、多个层间绝缘层31、32、33、34和35、多个中部互连件41和42、多个接触插塞52、垫61、多个上部互连件62、多个保护绝缘层71、72和74、开口73W以及第一凸块89。多个保护绝缘层71、72和74可以包括第一保护绝缘层71、第二保护绝缘层72和第三保护绝缘层74。第三保护绝缘层74可以设置在第一保护绝缘层71与第二保护绝缘层72之间。第三保护绝缘层74可以包括与第二保护绝缘层72的材料不同的材料或者由与第二保护绝缘层72的材料不同的材料形成。第三保护绝缘层74可以在稍后的工艺中由第一保护绝缘层71形成。第三保护绝缘层74的底表面可以在第三保护绝缘层74与第一保护绝缘层71之间的界面处接触第一保护绝缘层71的顶表面。
第一保护绝缘层71、垫61和多个上部互连件62的上表面可以基本共面。第一保护绝缘层71可以填充垫61与多个上部互连件62之间的间隙G1。第三保护绝缘层74可以覆盖垫61的边缘、多个上部互连件62以及垫61与多个上部互连件62之间的间隙G1。第一保护绝缘层71、第二保护绝缘层72和第三保护绝缘层74中的每个的上表面可以是基本平坦的。开口73W可以穿过第二保护绝缘层72和第三保护绝缘层74。开口73W的宽度可以在竖直方向上基本相同。也就是说，从剖视图来看，开口73W可以是矩形的。
参照图7，根据发明构思的实施例的半导体器件可以包括基底21、多个层间绝缘层31、32、33、34和35、多个中部互连件41和42、多个接触插塞52、垫61、多个上部互连件62、多个保护绝缘层71、72和74、开口73W以及第一凸块89。开口73W从剖视图来看可以呈现梯形形状，并且具有比其上部宽度小的下部宽度。开口73W的侧壁可以倾斜，使得开口73W的宽度在远离基底21的顶表面的方向上增加。
参照图8，根据发明构思的实施例的半导体器件可以包括基底21、多个层间绝缘层31、32、33、34和35、多个中部互连件41和42、多个接触插塞52、垫61、多个上部互连件62、多个保护绝缘层71、72和78、开口73W以及第一凸块89。多个保护绝缘层71、72和78可以包括第一保护绝缘层71、第二保护绝缘层72和第三保护绝缘层78。
第三保护绝缘层78可以设置在第二保护绝缘层72上。在实施例中，第三保护绝缘层78可以包括光敏聚酰亚胺(PSPI)。开口73W可以穿过第三保护绝缘层78、第二保护绝缘层72和第一保护绝缘层71。从剖视图来看，开口73W可以是部分矩形的且可以是部分梯形的。第一凸块89可以延伸到多个保护绝缘层71、72和78中，并且通过开口73W连接到垫61。
图9是示出根据发明构思的实施例的半导体器件的剖视图。图10是图9的部分90的放大图。图11是图9的一些组件的放大图。根据发明构思的某些实施例的半导体器件可以包括多芯片封装件。在实施例中，半导体器件可以包括高带宽存储器(HBM)。在实施例中，半导体器件可以包括动态随机存取存储器(DRAM)。
参照图9，半导体器件可以包括印刷电路板(PCB)PC、中介体IP、多个半导体芯片CP、LD和MD1至MD4、多个凸块89、489、589和689以及密封剂99。多个半导体芯片CP、LD和MD1至MD4可以包括微处理器CP、控制芯片LD(例如，控制器)和多个存储器芯片MD1至MD4。多个存储器芯片MD1至MD4可以包括第一存储器芯片MD1、第二存储器芯片MD2、第三存储器芯片MD3和第四存储器芯片MD4。多个存储器芯片MD1至MD4中的至少一些可以包括多个贯穿电极93。多个凸块89、489、589和689可以包括多个第一凸块89、多个第二凸块489、多个第三凸块589和多个第四凸块689。
PCB PC可以包括刚性PCB、柔性PCB或刚性-柔性PCB。PCB PC可以包括多层电路基底。PCB PC可以对应于封装件基底或主板。多个第四凸块689可以设置在PCB PC的下表面上。中介体IP可以设置在PCB PC上。多个第三凸块589可以设置在PCB PC与中介体IP之间。在PCB PC对应于主板的情况下，中介体IP可以对应于封装件基底。
多个半导体芯片CP、LD和MD1至MD4可以设置在中介体IP上。中介体IP可以包括诸如硅中介体的半导体基底。在实施例中，微处理器CP和控制芯片LD设置在中介体IP上。多个第二凸块489可以设置在微处理器CP与中介体IP之间以及控制芯片LD与中介体IP之间。微处理器CP可以包括诸如图形处理单元(GPU)或应用处理器(AP)的各种类型的处理器。控制芯片LD可以包括诸如存储器控制器的各种元件。控制芯片LD可以经由中介体IP和多个第二凸块489连接到微处理器CP。
多个存储器芯片MD1至MD4可以顺序地堆叠在控制芯片LD上。多个存储器芯片MD1至MD4中的每个可以包括与参照图1至图8描述的组件类似的多个组件。例如，多个存储器芯片MD1至MD4中的每个可以包括多个第一凸块89。在实施例中，多个第一凸块89可以设置在多个存储器芯片MD1至MD4之间以及第一存储器芯片MD1与控制芯片LD之间。多个存储器芯片MD1至MD4可以经由多个第一凸块89和多个贯穿电极93连接到控制芯片LD。
密封剂99可以设置在控制芯片LD上，以覆盖多个存储器芯片MD1至MD4。密封剂99可以包括环氧模塑化合物(EMC)、底部填料或其组合。
在示例性实施例中，控制芯片LD可以包括主芯片。多个存储器芯片MD1至MD4中的每个可以表示从芯片。在示例性实施例中，第一存储器芯片MD1可以表示主芯片。第二存储器芯片MD2、第三存储器芯片MD3和第四存储器芯片MD4中的每个可以表示从芯片。
参照图9和图10，第三存储器芯片MD3可以包括贯穿电极93、突出电极95、基底绝缘层97、基底21、多个层间绝缘层31、32、33、34和35、多个中部互连件41和42、多个接触插塞52、垫61、多个上部互连件62、多个保护绝缘层71和72以及第一凸块89。基底绝缘层97可以覆盖基底21的一个表面。基底21可以设置在基底绝缘层97与第一层间绝缘层31之间。突出电极95可以设置在基底绝缘层97上。贯穿电极93可以穿过基底21，并且可以连接到多个第一中部互连件41中的对应的一个和突出电极95。在实施例中，贯穿电极93可以穿过基底21，并且可以连接到多个第二中部互连件42中的对应的一个或垫61。
第二存储器芯片MD2可以包括与第三存储器芯片MD3的构造类似的构造。第三存储器芯片MD3的焊料87可以附着到第二存储器芯片MD2的突出电极95。第四存储器芯片MD4的焊料87可以附着到第三存储器芯片MD3的突出电极95。
参照图9至图11，多个半导体芯片CP、LD和MD1至MD4中的每个可以包括多个有源/无源元件。在实施例中，多个有源/无源元件可以包括设置在基底21上的多个单元晶体管149和多个单元电容器159。
例如，多个存储器芯片MD1至MD4中的每个可以包括基底21、器件隔离层123、第六层间绝缘层131、第七层间绝缘层132、多个单元晶体管149、位线BL、多个掩埋接触插塞BC和多个单元电容器159。多个单元晶体管149中的每个可以包括栅电极141、栅极介电层143和多个源区/漏区145。多个单元电容器159中的每个可以包括第一电极151、电容器介电层153和第二电极155。
多个单元晶体管149和多个单元电容器159可以构成多个存储器单元MC。多个单元晶体管149中的每个可以对应于凹进的沟道晶体管。在实施例中，多个单元晶体管149中的每个可以包括鳍式场效应晶体管(finFET)、多桥沟道(MBC)晶体管、纳米线晶体管、竖直晶体管、凹进的沟道晶体管、三维(3D)晶体管、平面晶体管或其组合。第一电极151可以被称为下电极、存储电极或存储节点。第二电极155可以被称为上电极、板电极或板节点。多个单元电容器159中的每个可以包括各种类型的三维(3D)电容器。
第六层间绝缘层131可以设置在与图1的第一层间绝缘层31的水平类似的水平处。第七层间绝缘层132可以设置在与图1的第二层间绝缘层32或第三层间绝缘层33的水平类似的水平处。多个单元晶体管149和多个单元电容器159可以电连接到与其对应的图1的多个中部互连件41和42、垫61和多个上部互连件62中的至少一个。
图12至图19是用于描述根据发明构思的实施例的形成半导体器件的方法的剖视图。
参照图12，在基底21上形成多个层间绝缘层31、32、33、34和35、多个中部互连件41和42、多个接触插塞52、垫61以及多个上部互连件62。多个层间绝缘层31、32、33、34和35可以包括第一层间绝缘层31、第二层间绝缘层32、第三层间绝缘层33、第四层间绝缘层34和第五层间绝缘层35。多个中部互连件41和42可以包括多个第一中部互连件41和多个第二中部互连件42。
基底21可以包括诸如硅晶片或绝缘体上硅(SOI)晶片的半导体基底。可以在基底21上堆叠多个层间绝缘层31、32、33、34和35。多个层间绝缘层31、32、33、34和35可以包括氧化硅、氮化硅、氮氧化硅、低k电介质、高k电介质或它们的组合。第四层间绝缘层34可以对应于蚀刻停止层。第四层间绝缘层34可以包括与第五层间绝缘层35的材料不同的材料，或者由与第五层间绝缘层35的材料不同的材料形成。例如，第一层间绝缘层31、第二层间绝缘层32、第三层间绝缘层33和第五层间绝缘层35可以包括氧化硅，并且第四层间绝缘层34可以包括氮化硅。
多个中部互连件41和42和多个接触插塞52中的每个可以包括诸如金属、金属氮化物、金属硅化物、金属氧化物、多晶硅、导电碳或其组合的导电材料，或者由诸如金属、金属氮化物、金属硅化物、金属氧化物、多晶硅、导电碳或其组合的导电材料形成。每个单独的中部互连件41或42可以具有由连续的单片材料形成的一体结构。在实施例中，可以在第一层间绝缘层31中形成多个第一中部互连件41。可以在第二层间绝缘层32中形成多个第二中部互连件42。多个第二中部互连件42中的每个可以呈现第一厚度d1。
多个接触插塞52可以延伸到多个层间绝缘层31、32、33、34和35中的一个或更多个中。在实施例中，多个接触插塞52中的每个穿过第五层间绝缘层35、第四层间绝缘层34和第三层间绝缘层33，并且接触多个第二中部互连件42中的对应的一个。多个中部互连件41和42和多个接触插塞52的形成可以包括多个薄膜形成工艺和图案化工艺。
可以在第五层间绝缘层35上形成垫61和多个上部互连件62。垫61和多个上部互连件62的形成可以包括薄膜形成工艺和图案化工艺。多个上部互连件62中的每个和垫61可以包括诸如金属、金属氮化物、金属硅化物、金属氧化物、多晶硅、导电碳或其组合的导电材料，或者由诸如金属、金属氮化物、金属硅化物、金属氧化物、多晶硅、导电碳或其组合的导电材料形成。多个上部互连件62中的每个和垫61可以包括单层或多层结构。多个上部互连件62中的每个和垫61可以各自具有由连续的单片材料形成的一体结构。在实施例中，多个上部互连件62中的每个和垫61可以包括铝(Al)、铜(Cu)、镍(Ni)、钴(Co)、银(Ag)、铂(Pt)、钌(Ru)、钨(W)、氮化钨(WN)、钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)或其组合，或者由铝(Al)、铜(Cu)、镍(Ni)、钴(Co)、银(Ag)、铂(Pt)、钌(Ru)、钨(W)、氮化钨(WN)、钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)或其组合形成。
可以在垫61与基底21之间形成多个中部互连件41和42。多个上部互连件62中的每个和垫61可以至少接触多个接触插塞52中的对应的一个。在实施例中，多个中部互连件41和42之中，多个第二中部互连件42中的所选择的一个从自顶向下的视图来看最靠近垫61的中心。
垫61可以呈现第二厚度d2。多个上部互连件62中的每个可以呈现第三厚度d3。在实施例中，垫61和多个上部互连件62可以包括同时形成的相同材料，并且由同时形成的相同材料形成。第三厚度d3可以基本等于第二厚度d2。垫61和多个上部互连件62可以形成在基本相同的竖直水平处。第二厚度d2可以大于第一厚度d1。第二厚度d2可以是第一厚度d1的两倍至100倍。第二厚度d2可以为1μm或更大。在实施例中，第二厚度d2可以在1μm至5μm的范围内。例如，第二厚度d2可以为约2.5μm。
可以将多个上部互连件62中的每个形成为与垫61相邻(例如，在水平方向上与垫61相邻)。多个上部互连件62与垫61之间的每个间隙G1可以为1μm或更大。多个上部互连件62与垫61之间的间隙G1中的每个可以在1μm至10μm的范围内。在实施例中，间隙G1中的每个可以在2.5μm至7.2μm的范围内。多个上部互连件62与垫61之间的间隙G1中的每个可以大于或等于第二厚度d2。
参照图13，在第五层间绝缘层35上形成第一保护绝缘层71。第一保护绝缘层71可以覆盖垫61、多个上部互连件62以及垫61与多个上部互连件62之间的间隙G1。第一保护绝缘层71可以包括氧化硅、氮化硅、氮氧化硅、低k电介质或其组合，或者由氧化硅、氮化硅、氮氧化硅、低k电介质或其组合形成。在实施例中，第一保护绝缘层71可以包括使用原硅酸四乙酯(TEOS)形成的氧化硅层。第一保护绝缘层71的上表面可以形成在比垫61和多个上部互连件62的最上端(例如，顶表面)的水平高的水平处。
参照图14，可以使用平坦化工艺将第一保护绝缘层71的上表面形成为基本平坦的。平坦化工艺可以包括化学机械抛光(CMP)工艺、回蚀工艺或其组合。在实施例中，第一保护绝缘层71覆盖垫61、多个上部互连件62以及垫61与多个上部互连件62之间的间隙G1。
参照图15，在第一保护绝缘层71上形成第二保护绝缘层72。第二保护绝缘层72可以包括与第一保护绝缘层71的材料不同的材料。在实施例中，第二保护绝缘层72包括氮化硅。第二保护绝缘层72可以以恒定的厚度覆盖第一保护绝缘层71的上表面。第二保护绝缘层72的上表面可以形成为基本平坦的。
参照图16，可以使用图案化工艺将开口73W形成为穿过第二保护绝缘层72和第一保护绝缘层71并且暴露垫61的上表面。在实施例中，可以将开口73W布置在垫61的中心内。垫61的边缘可以保持被第一保护绝缘层71和第二保护绝缘层72覆盖。开口73W可以呈现各种剖面形状，诸如矩形形状或具有比其上水平宽度小的下水平宽度的梯形形状。在以下描述中，可以假定开口73W的下水平宽度和上水平宽度基本相同。从自顶向下的视图来看，开口73W可以具有例如圆形形状、正方形或矩形形状或者线性形状。
参照图17，在第二保护绝缘层72上顺序地形成阻挡层81和种子层82。阻挡层81可以包括钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)或其组合，或者由钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)或其组合形成。种子层82可以包括铜(Cu)或者由铜(Cu)形成。阻挡层81可以延伸到开口73W中。阻挡层81接触垫61的上表面。种子层82共形地覆盖阻挡层81的上表面。
参照图18，在种子层82上形成掩模图案80。在种子层82上形成柱83。柱83可以包括镍(Ni)、铜(Cu)、铝(Al)、银(Ag)、铂(Pt)、钌(Ru)、锡(Sn)、金(Au)、钨(W)、氮化钨(WN)、钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)或其组合，或者由镍(Ni)、铜(Cu)、铝(Al)、银(Ag)、铂(Pt)、钌(Ru)、锡(Sn)、金(Au)、钨(W)、氮化钨(WN)、钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)或其组合形成。例如，柱83可以包括镍层。可以使用电镀工艺形成柱83。可以通过掩模图案80限定柱83。
阻挡层81、种子层82和柱83可以构成柱结构85。柱结构85可以包括第一部分85A和第二部分85B。可以在开口73W上布置第一部分85A。第二部分85B可以在第二保护绝缘层72上延伸。第二部分85B可以与垫61的边缘、多个上部互连件62以及垫61与多个上部互连件62之间的间隙G1叠置。
第一部分85A的上表面可以比第二部分85B的上表面靠近基底21。第二部分85B的下表面可以形成为基本平坦的。第二部分85B的上表面可以形成为基本平坦的。
参照图19，在柱结构85上形成焊料87。焊料87可以包括Sn、Ag、Cu、Ni、Au或其组合，或者由Sn、Ag、Cu、Ni、Au或其组合形成。例如，焊料87可以是Sn-Ag-Cu层。可以在柱结构85与焊料87之间进一步形成界面金属层，但是为了简洁将省略其描述。
再次参照图1和图19，可以去除掩模图案80以暴露柱83和焊料87的侧表面。可以部分地去除种子层82和阻挡层81以部分地暴露第二保护绝缘层72的上表面。种子层82和阻挡层81可以限定在垫61与柱83之间、在垫61的边缘上在第二保护绝缘层72与柱83之间、在垫61与多个上部互连件62之间的间隙G1上在第二保护绝缘层72与柱83之间以及在多个上部互连件62上在第二保护绝缘层72与柱83之间。
可以使用诸如回流工艺的退火工艺使焊料87倒圆。在实施例中，焊料87的横向宽度可以大于柱83的横向宽度。焊料87的上表面可以具有弯曲的半球形状。
图20至图22是用于描述根据发明构思的实施例的形成半导体器件的方法的剖视图。
参照图20，可以使用平坦化工艺将第一保护绝缘层71的上表面形成为基本平坦的。第一保护绝缘层71、垫61和多个上部互连件62的上表面可以基本共面并且被暴露。第一保护绝缘层71可以填充垫61与多个上部互连件62之间的间隙G1。
参照图21，在第一保护绝缘层71、垫61和多个上部互连件62上形成第三保护绝缘层74。可以在第三保护绝缘层74上形成第二保护绝缘层72。第三保护绝缘层74可以包括与第二保护绝缘层72的材料不同的材料。例如，第一保护绝缘层71和第三保护绝缘层74中的每个可以包括使用原硅酸四乙酯(TEOS)形成的氧化硅层。第二保护绝缘层72可以包括氮化硅层。第一保护绝缘层71、第三保护绝缘层74和第二保护绝缘层72的上表面中的每个可以形成为基本平坦的。
参照图22，可以使用图案化工艺将开口73W形成为穿过第二保护绝缘层72和第三保护绝缘层74并且使垫61的上表面暴露。
根据发明构思的示例实施例，可以提供具有为中部互连件的厚度的至少两倍的厚度的垫和上部互连件。保护绝缘层可以覆盖垫的边缘、上部互连件以及垫与上部互连件之间的间隙，并且在垫上具有开口。凸块可以设置在垫上。凸块可以在保护绝缘层上延伸并且与上部互连件叠置。垫与上部互连件之间的间隙可以为1μm或更大。保护绝缘层的上表面可以是基本平坦的。能够实现具有优异的电流驱动性、高信号传输速率和高物理/化学可靠性的半导体器件。
尽管已经参照附图描述了发明构思的实施例，但是本领域技术人员应该理解的是，在不脱离发明构思的范围并且不改变其必要特征的情况下，可以进行各种修改。因此，上述实施例应该仅在描述性的意义上考虑，而不是出于限制的目的。

Claims (23)

1.一种半导体器件，所述半导体器件包括：
层间绝缘层，设置在基底上；
多个中部互连件，设置在层间绝缘层中；
垫，设置在层间绝缘层上；
上部互连件，设置在层间绝缘层上；
保护绝缘层，覆盖垫的边缘、上部互连件以及垫与上部互连件之间的间隙，保护绝缘层在垫上具有开口；以及
凸块，设置在垫上，凸块在保护绝缘层上延伸并且从自顶向下的视图来看与上部互连件叠置，
其中，所述多个中部互连件中的在竖直方向上最靠近垫的中部互连件之中的至少一个中部互连件具有第一竖直厚度，
垫具有为第一竖直厚度的两倍至100倍的第二竖直厚度，
垫与上部互连件之间的所述间隙的长度为1μm或更大，并且
保护绝缘层的上表面是平坦的。
2.根据权利要求1所述的半导体器件，其中，第二竖直厚度具有在1μm和5μm之间的范围内的值。
3.根据权利要求1所述的半导体器件，其中，垫与上部互连件之间的所述间隙具有大于或等于第二竖直厚度的长度。
4.根据权利要求1所述的半导体器件，其中，垫与上部互连件之间的所述间隙具有在2.5μm和10μm之间的范围内的长度。
5.根据权利要求1所述的半导体器件，其中，上部互连件与垫具有相同的竖直厚度。
6.根据权利要求1所述的半导体器件，其中，保护绝缘层包括：
第一保护绝缘层；以及
第二保护绝缘层，设置在第一保护绝缘层上并且包括与第一保护绝缘层的材料不同的材料，使得第一保护绝缘层位于基底与第二保护绝缘层之间，
其中，第一保护绝缘层的上表面是平坦的。
7.根据权利要求6所述的半导体器件，其中，第一保护绝缘层覆盖垫的所述边缘、上部互连件以及垫与上部互连件之间的所述间隙。
8.根据权利要求6所述的半导体器件，其中，第一保护绝缘层包括氧化硅，并且
第二保护绝缘层包括氮化硅。
9.根据权利要求6所述的半导体器件，所述半导体器件还包括第三保护绝缘层，所述第三保护绝缘层设置在第一保护绝缘层与第二保护绝缘层之间并且包括与第二保护绝缘层的材料不同的材料，
其中，第一保护绝缘层、垫和上部互连件的上表面共面。
10.根据权利要求9所述的半导体器件，其中，第三保护绝缘层覆盖垫的所述边缘、上部互连件以及垫与上部互连件之间的所述间隙。
11.根据权利要求1所述的半导体器件，其中，凸块包括：
柱结构，设置在垫上，柱结构在保护绝缘层上延伸并且与上部互连件在竖直方向上叠置；以及
焊料，设置在柱结构上，
其中，柱结构包括：第一部分，布置在所述开口上并延伸到所述开口中；以及第二部分，在保护绝缘层上延伸并且与上部互连件在竖直方向上叠置，
其中，第二部分的下表面是平坦的。
12.根据权利要求11所述的半导体器件，其中，第一部分的上表面比第二部分的上表面靠近基底的上表面。
13.根据权利要求11所述的半导体器件，其中，第二部分的上表面是平坦的。
14.根据权利要求11所述的半导体器件，其中，柱结构包括镍、铜、钛、氮化钛、钽、氮化钽或其组合。
15.根据权利要求1所述的半导体器件，所述半导体器件还包括在竖直方向上设置在垫与所述多个中部互连件之间的接触插塞。
16.根据权利要求15所述的半导体器件，其中，所述多个中部互连件中的每个具有大于其竖直高度的横向宽度，并且
接触插塞具有大于其横向宽度的竖直高度。
17.一种半导体器件，所述半导体器件包括：
层间绝缘层，设置在基底上；
多个有源/无源元件，设置在基底上；
多个中部互连件，设置在层间绝缘层中；
垫，设置在层间绝缘层上；
上部互连件，设置在层间绝缘层上；
保护绝缘层，覆盖所述垫的边缘、所述上部互连件以及所述垫与所述上部互连件之间的间隙，所述保护绝缘层在所述垫上具有开口；
凸块，设置在所述垫上，所述凸块在所述保护绝缘层上延伸并且与所述上部互连件在竖直方向上叠置；以及
贯穿电极，穿过基底并且连接到所述多个中部互连件或所述垫，
其中，所述多个中部互连件中的在竖直方向上最靠近所述垫的中部互连件之中的一个中部互连件电连接到所述垫并且具有第一竖直厚度，
所述垫具有为第一竖直厚度的两倍至100倍的第二竖直厚度，
所述垫与所述上部互连件之间的所述间隙的长度为1μm或更大，并且
所述保护绝缘层的上表面是平坦的。
18.根据权利要求17所述的半导体器件，所述半导体器件包括：多个半导体芯片，顺序地堆叠在印刷电路板上，
其中，所述多个半导体芯片中的至少一个包括：
设置在基底上的所述层间绝缘层；
设置在基底上的所述多个有源/无源元件；
设置在层间绝缘层中的所述多个中部互连件；
设置在层间绝缘层上的所述垫；
设置在层间绝缘层上的所述上部互连件；
覆盖所述垫的所述边缘、所述上部互连件以及所述垫与所述上部互连件之间的所述间隙的所述保护绝缘层；
设置在所述垫上的所述凸块，所述凸块在所述保护绝缘层上延伸并且与所述上部互连件在竖直方向上叠置；以及
穿过基底并且连接到所述多个中部互连件或所述垫的所述贯穿电极。
19.根据权利要求18所述的半导体器件，其中，所述多个半导体芯片包括顺序地堆叠的多个存储器芯片。
20.根据权利要求19所述的半导体器件，其中，所述多个有源/无源元件包括：
单元晶体管；以及
单元电容器，连接到单元晶体管。
21.一种半导体器件，所述半导体器件包括：
层间绝缘层，设置在基底上；
多个中部互连件，设置在层间绝缘层中；
垫，设置在层间绝缘层上；
上部互连件，设置在层间绝缘层上；
保护绝缘层，覆盖垫的边缘、上部互连件以及垫与上部互连件之间的间隙，保护绝缘层在垫上具有开口；以及
凸块，设置在垫上，凸块在保护绝缘层上延伸并且与上部互连件在竖直方向上叠置，
其中，所述多个中部互连件中的在竖直方向上最靠近垫的中部互连件之中的一个中部互连件具有第一竖直厚度，
垫具有为第一竖直厚度的两倍至100倍的第二竖直厚度，
垫与上部互连件之间的所述间隙的水平长度大于或等于第二竖直厚度，并且
保护绝缘层的上表面是平坦的。
22.根据权利要求21所述的半导体器件，其中，第二竖直厚度具有在1μm和5μm之间的范围内的值。
23.根据权利要求21所述的半导体器件，其中，垫与上部互连件之间的所述间隙具有在1μm和10μm之间的范围内的长度。
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