WO2005096364A1 - Semiconductor device and method for manufacturing same - Google Patents

Semiconductor device and method for manufacturing same Download PDF

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Publication number
WO2005096364A1
WO2005096364A1 PCT/JP2005/006180 JP2005006180W WO2005096364A1 WO 2005096364 A1 WO2005096364 A1 WO 2005096364A1 JP 2005006180 W JP2005006180 W JP 2005006180W WO 2005096364 A1 WO2005096364 A1 WO 2005096364A1
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WIPO (PCT)
Prior art keywords
wiring
semiconductor device
metal
circuit
insulating film
Prior art date
Application number
PCT/JP2005/006180
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French (fr)
Japanese (ja)
Inventor
Masayoshi Tagami
Yoshihiro Hayashi
Original Assignee
Nec Corporation
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Filing date
Publication date
Application filed by Nec Corporation filed Critical Nec Corporation
Priority to JP2006511773A priority Critical patent/JP4946436B2/en
Publication of WO2005096364A1 publication Critical patent/WO2005096364A1/en

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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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Definitions

  • the present invention relates to a semiconductor device, particularly to a semiconductor device having a low dielectric constant film as a wiring interlayer film, and a method of manufacturing the same.
  • the propagation delay in wiring is proportional to the product of the wiring resistance and the capacitance between wirings
  • a material having a low resistivity is used for the wiring material
  • a material having a low dielectric constant is used for the wiring interlayer film. This makes it possible to reduce the propagation delay in the wiring.
  • Cu wiring using Cu or a Cu alloy as a wiring material is generally formed by a damascene (dama scene) method.
  • damascene method after a wiring interlayer film is deposited, a groove is formed from the surface side by a reactive ion etching (RIE) method, and Cu or Cu is filled so as to fill the groove.
  • RIE reactive ion etching
  • the Cu or Cu alloy film other than the Cu or Cu alloy film embedded in the groove is removed by a chemical mechanical polishing (CMP) method or the like, and the film between the wiring layers is removed. And forming a buried Cu wiring!
  • CMP chemical mechanical polishing
  • a method of forming a dummy wiring pattern for CMP in a wiring layer is often used in order to reduce variation in the thickness of the wiring at the time of CMP.
  • FIG. 1 shows an example of a method using a dummy wiring pattern for CMP.
  • the wiring layer (2002) and the insulating layer (2003) are alternately deposited.
  • a metal circuit wiring (2000) is formed in each wiring layer (2002), and a metal via (2004) is formed in the insulating layer (2003).
  • Metal circuit wiring (2000) formed in each wiring layer (2002) is electrically connected to each other via metal via (2004).
  • Each wiring layer (2002) is electrically insulated from the metal circuit wiring (2000).
  • the dielectric constant is reduced and the film strength is also reduced.
  • the wiring interlayer film made of a low dielectric constant film is made of SiO
  • Patent Document 1 discloses an under-pad dummy wiring (10002) under a bonding pad (10001) as shown in FIG. 3 in order to increase the strength under the bonding pad.
  • Non-Patent Document 1 wire bonding is enabled by connecting a dummy pad and a dummy via under a pad in connection with a structure under the pad.
  • Patent Document 1 JP 2001-267323
  • Non-patent Document 1 Y.L.Yang et al., IITC '03 Technical Digest, 2003.6.2, 2.4, P3, Fig. 12, 13
  • the number of wirings and vias that can be arranged under the nod is limited according to the pad area. Therefore, if the strength of the low dielectric constant film, which is the interlayer insulating film, is very low, or if the adhesion between the low dielectric constant film and the films above and below it is very low, dummy wiring under the pad And the number of dummy vias must be huge. In this case, most of the area under the bonding pad is occupied by the dummy wiring and the dummy via. Therefore, it is not a dummy! / ⁇ It is impossible to arrange the wiring and via forming the circuit. No circuit can be formed at the same time. As a result, the chip area increases, and the number of chips that can be collected from one wafer is reduced, resulting in an increase in production cost.
  • the present invention has been made in view of the above-described problems in the conventional example, and has a structure in which the strength of the entire chip is high and the structure is resistant to shocks and stresses during a process and during packaging. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which do not cause problems.
  • An object of the present invention is to further provide a semiconductor device having high structural reliability while reducing production costs, and a method of manufacturing the same.
  • the semiconductor device comprises a semiconductor substrate And at least one interlayer insulating film formed on the semiconductor substrate; and a plurality of wiring layers stacked with the interlayer insulating film interposed therebetween, and a circuit formed on each of the plurality of wiring layers.
  • a semiconductor device in which a wiring, a conductive metal via penetrating through the interlayer insulating film and interconnecting the circuit wirings vertically adjacent to each other, and a powerful multilayer circuit structure are formed; A reinforcing wiring pattern provided on each of the layers, a reinforcing via pattern provided on the inter-layer insulating film and interconnecting the reinforcing wiring patterns adjacent to each other in a vertical direction, and a multilayer support structure capable of providing a force.
  • the multi-layer support structure is characterized in that it is formed in a region of the semiconductor device where the multi-layer circuit structure exists and does not conflict with the multi-layer circuit structure.
  • the CMP flat dummy pattern is formed only on the wiring layer, whereas in the invention according to the first aspect, the regions where the CMP flat dummy wiring patterns overlap each other are connected.
  • a reinforcing via pattern is formed.
  • the structure of the semiconductor device according to the present invention is such that the region where the existing dummy wiring patterns of the upper and lower layers overlap is merely connected by the reinforcing via pattern, so that the arrangement of the wiring in the circuit region is particularly small. It has no effect.
  • the semiconductor device further includes a pad formed on the uppermost layer and electrically transmitting and receiving signals to and from the outside.
  • the multilayer support structure also exists in a region below the pad.
  • the "wiring layer” also serves as an electrically insulating material, and is partially formed with circuit wiring inside! Refers to the layer.
  • a semiconductor device provides a semiconductor substrate, at least one interlayer insulating film formed on the semiconductor substrate, and a plurality of wirings stacked via the interlayer insulating film. And a pad formed on an uppermost layer of the plurality of wiring layers, a circuit wiring formed on each of the plurality of wiring layers, and an upper and lower direction penetrating the interlayer insulating film. And a conductive metal via interconnecting the circuit wiring adjacent to the wiring.
  • a multilayer support structure that also provides a force. At least a part of the multilayer circuit structure is disposed in a region below the pad, and the multilayer support structure is disposed below the pad. , And formed in a region that does not conflict with the multilayer circuit structure.
  • the reinforcing via pattern is formed so as to connect the region under the bonding pad or the region where the reinforcing wiring pattern existing in the wiring layer within a predetermined distance outside the outer edge of the bonding pad overlaps. For this reason, in the region below the bonding pad, it is possible to form a circuit in the region below the bonding pad while increasing the strength against wire bonding. , Process resistance, wire bonding resistance, resin encapsulation resistance, and the like.
  • the semiconductor device preferably further includes a transistor formed on the semiconductor substrate, and the transistor is preferably arranged below the pad.
  • the multilayer support structure is formed not only in a region below the pad but also in a region below a predetermined distance outside the outer periphery of the pad.
  • the predetermined distance is, for example, 10 ⁇ m.
  • a semiconductor device is a semiconductor device, at least one interlayer insulating film formed on the semiconductor substrate, and a plurality of wirings stacked via the interlayer insulating film. And a conductive metal via that penetrates the inter-layer insulating film and interconnects the vertically adjacent circuit wirings, the circuit wiring being formed in each of the plurality of wiring layers.
  • a multilayer support structure comprising a reinforcing via pattern
  • the semiconductor device comprises: a circuit region in which the multilayer circuit structure is formed; and a scribe region in a region around the circuit region, wherein no circuit is formed.
  • the multilayer support structure is formed in the scribing region.
  • a "scribe area" of a semiconductor device is a region outside a circuit region where circuit wiring exists in a semiconductor device, or outside a region below a bonding pad (the periphery of a semiconductor chip). (Near the end). Generally, there are no circuits in the scribe area.
  • the scribe region has a certain width (for example, 100 / zm or more), so that even after the wafer is cut, the scribe region remains near the peripheral edge of the semiconductor chip. It will be.
  • the scribe region of the semiconductor device includes a reinforcing wiring pattern and a reinforcing via pattern connecting the reinforcing wiring patterns existing in the plurality of wiring layers.
  • a multilayer support structure is formed. This enhances the film strength and adhesion of the laminated body composed of the interlayer insulating film and the wiring layer at the peripheral edge of the semiconductor chip, and is caused by the stress at the time of dicing, wire bonding, and sealing of the assembly resin. Peeling of the interlayer insulating film and the wiring layer can be prevented.
  • the multilayer support structure is formed in a region of the circuit region that does not conflict with the multilayer circuit structure.
  • the semiconductor device preferably further includes a pad formed on the uppermost layer and electrically transmitting and receiving signals to and from the outside.
  • the multilayer support structure is also formed in a region below the pad.
  • the multilayer support structure is also formed between the outside of the pad and the scribe area!
  • the length of the reinforcing via pattern in the thickness direction of the semiconductor device is preferably larger than the length of the conductive metal via in the thickness direction of the semiconductor device. Good.
  • the reinforcing via pattern has a slit shape in a cross section of the semiconductor device.
  • the multilayer support structure is formed electrically independent of the circuit wiring and the conductive metal via.
  • the multilayer support structure is formed electrically independent of the circuit wiring, the conductive metal via, and the pad.
  • the multilayer support structure is connected to an element isolation region provided in the semiconductor substrate.
  • the semiconductor device further includes a global wiring in an uppermost layer thereof, and the multilayer support structure formed in the circuit region is connected at one end to the global wiring portion, At the other end, it is preferable that the circuit wiring and the conductive metal via are separated from each other!
  • the multilayer support structure formed in the region below the pad is preferably connected to the pad and another circuit.
  • the reinforcing wiring pattern and the reinforcing via pattern and the circuit wiring and the conductive metal via existing in the same layer are formed of the same material.
  • the ratio of the total area of the conductive metal via and the reinforcing via pattern to the unit area of the interlayer insulating film is 5% or more.
  • a ratio of a total area of the conductive metal via and the reinforcing via pattern to a unit area of the interlayer insulating film is set to 5% or more.
  • the ratio of the total area of the reinforcing via pattern to the unit area of the interlayer insulating film is preferably 5% or more.
  • the reinforcing via pattern connects only areas where the reinforcing wiring patterns overlap each other.
  • the present invention further provides the method for manufacturing a semiconductor device described above, wherein the multilayer support structure is provided.
  • a semiconductor device comprising a step of forming the reinforcing wiring pattern and the reinforcing via pattern to be formed, and the circuit wiring and the conductive metal via existing in the same layer with the same material, respectively. And a method for producing the same.
  • a reinforcing via pattern is formed only in a region where a conventional dummy pattern for CMP (reinforcing wiring pattern) overlaps with each other, productivity is increased without causing an increase in chip area. Can be enhanced. Furthermore, by forming a multilayer support structure, it is possible to suppress the failure of the low dielectric constant interlayer film to be broken or peeled off due to the impact or stress during the manufacturing process and during packaging, and to improve the structural reliability. It is possible to provide a semiconductor device with high reliability.
  • the semiconductor device includes a semiconductor substrate, at least one interlayer insulating film formed on the semiconductor substrate, and a plurality of wiring layers stacked via the interlayer insulating film. And a conductive circuit via formed in each of the plurality of wiring layers and a conductive metal via penetrating through the interlayer insulating film and interconnecting vertically adjacent circuit wirings.
  • a multi-layer support structure wherein the multi-layer support structure is formed in a region that does not conflict with the multi-layer circuit structure in a circuit region of the semiconductor device having the multi-layer circuit structure. In things is there.
  • FIG. 4 is a schematic cross-sectional view showing one embodiment of the semiconductor device according to the first aspect of the present invention.
  • the semiconductor device includes a semiconductor substrate (1001), a transistor (1101) formed on the semiconductor substrate (1001), and a semiconductor substrate (1001) covering the transistor (1101). ), An insulating film (1002) formed thereon, a first wiring layer (1003) formed on the insulating film (1002), and an interlayer insulating film (1006) formed on the first wiring layer (1003). And a second wiring layer (1007) formed on the inter-layer insulating film (1006).
  • the first wiring layer (1003) also becomes a non-conductive material, and the first wiring layer (1003) includes a conductive metal wiring (1004) serving as a circuit wiring and a conductive metal wiring (1004).
  • a metal reinforcing wiring pattern (1005) made of the same conductive material is formed apart from each other.
  • the second wiring layer (1007) also becomes a non-conductive material, and the second wiring layer (1007) includes a conductive metal wiring (1008) serving as a circuit wiring and a conductive metal wiring (1008).
  • the metal reinforcing wiring pattern (1009) made of the same material is formed apart from each other.
  • the interlayer insulating film (1006) sandwiched between the first wiring layer (1003) and the second wiring layer (1007) is provided in the first and second wiring layers (1003, 1007), respectively.
  • a metal reinforcing via pattern (1011) for electrically connecting mutually overlapping areas of the patterns (1005, 1009) is formed.
  • the metal reinforcing via pattern (1011) is made of the same conductive material as the conductive metal via (1010)! RU
  • a multi-layer circuit includes conductive metal wirings (1004, 1008) and conductive metal vias (1010) stacked in the thickness direction of the semiconductor device.
  • a structure is formed.
  • a metal reinforcing wiring pattern (1005, 1009) stacked in the thickness direction of the present semiconductor device, a metal reinforcing via pattern (1011) for interconnecting the metal reinforcing wiring patterns, and a multi-layer supporting structure are formed.
  • the multilayer support structure exists in a gap in a circuit region where the multilayer circuit structure is formed. That is, the multilayer support structure is formed in the region where the multilayer circuit structure does not exist, just like the multilayer circuit structure does not conflict with the inside of the circuit region where the multilayer circuit structure is formed. .
  • the reinforcing wiring patterns (1005, 1009) forming the multilayer support structure and the conductive metal wirings (1004, 1008) existing in the same wiring layer Are formed of the same conductive material
  • the metal reinforcing via pattern (1011) forming the multilayer support structure and the conductive metal via (1010) existing in the same interlayer insulating film are the same conductive material.
  • the reinforcing wiring pattern (1005, 1009) and the conductive metal wiring (1004, 1008) may be made of different materials.
  • the via pattern (1011) and the conductive metal via (1010) may be formed of mutually different conductive materials. However, by forming the same material with the same force, there is an advantage that the number of steps in the manufacturing process can be reduced.
  • the multilayer support structure as described above includes a plurality of wiring layers and interlayer insulating layers stacked on the semiconductor substrate (1001) in the thickness direction of the semiconductor device. It is sufficient that the film is formed over at least two layers of the film.
  • this multilayer support structure includes conductive metal wirings (1004, 1008) and conductive metal vias.
  • the multilayer circuit structure composed of (1010) may also be electrically insulated, or may be electrically connected to the multilayer circuit structure.
  • the multilayer support structure is connected to the multilayer circuit structure only at one end thereof, and is electrically connected at the other end.
  • the multilayer circuit structure is electrically isolated, that is, electrically open.
  • the multi-layer support structure may be such that the force of the second wiring layer (1007), which is the uppermost layer of the present semiconductor device, is also extended to the semiconductor substrate (1001). It may be one that terminates inside the laminated body composed of the interlayer insulating film.
  • FIGS. 5 to 8 are cross-sectional views schematically showing the structure of another embodiment of the semiconductor device according to the first aspect of the present invention.
  • the semiconductor device according to the embodiment shown in FIGS. 5 to 8 is similar to the semiconductor device according to the embodiment shown in FIG. 4, and includes a semiconductor substrate (1001) and a semiconductor substrate (1001).
  • the first wiring layer (1003) also becomes a non-conductive material, and the first wiring layer (1003) includes a conductive metal wiring (1004) serving as a circuit wiring and a conductive metal wiring (1004). From the same conductive material The metal reinforcing wiring pattern (1005) is formed apart from each other.
  • the second wiring layer (1007) also becomes a non-conductive material, and the second wiring layer (1007) includes a conductive metal wiring (1008) serving as a circuit wiring and a conductive metal wiring (1008).
  • the metal reinforcing wiring pattern (1009) made of the same material is formed apart from each other.
  • the interlayer insulating film (1006) sandwiched between the first wiring layer (1003) and the second wiring layer (1007) is provided in the first and second wiring layers (1003, 1007), respectively.
  • a metal reinforcing via pattern (1011) for electrically connecting mutually overlapping areas of the patterns (1005, 1009) is formed.
  • the metal reinforcing via pattern (1011) is made of the same conductive material as the conductive metal via (1010)! RU
  • the third wiring layer (1013) is made of a non-conductive material, and global wiring (power supply wiring, 1015) is formed in the third wiring layer (1013).
  • the global wiring (1015) is a wiring having a wiring length relatively longer than a conductive metal wiring (1004, 1008) which is a local wiring formed below the global wiring (1015). It is.
  • the wiring between adjacent logic circuits is performed by lower-level local wiring (1004, 1008) with a finer wiring pitch, and the wiring between distant logic circuits is reduced.
  • the wiring is performed by the global wiring (1015) in the upper layer.
  • the global wiring (1015) has a larger wiring thickness and a wider wiring width than the local wiring (1004, 1008), and has a wider wiring interval.
  • the semiconductor devices according to the embodiments shown in FIGS. 5 to 8 have the above-described common structure, but have the following differences.
  • the metal reinforcing wiring pattern (1009) of the multilayer support structure includes a metal reinforcing via pattern (1014) provided in the second interlayer insulating film (1012). ), And the multilayer support structure is electrically connected at one end to the global wiring (1015) via the reinforcing via pattern (1014).
  • the multi-layer support structure at the other end, has a metal layer formed in the first wiring layer (1003).
  • a metal reinforcing wiring pattern (1005) is formed. That is, the multi-layer support structure terminates inside a stacked body composed of a plurality of wiring layers and an interlayer insulating film formed on the semiconductor substrate (1001).
  • the multilayer support structure is connected at one end to the global wiring (1015).
  • the multi-layer support structure has a metal reinforcing wiring pattern (1005) formed in the first wiring layer (1003) at the other end. 1002) are connected to the reinforcing via pattern (1017) provided in the semiconductor substrate (1001) through the reinforcing via pattern (1017). It is supported by.
  • the multilayer support structure is a structure that is not connected to the global wiring (1015) and is electrically separated from the global wiring (1015). ing.
  • the multilayer support structure is not connected to the global wiring (1015), and the power of the global wiring (1015) is electrically separated.
  • the multilayer support structure has a metal reinforcing via pattern (1017) provided in the insulating film (1002) at the other end. And is supported by an element isolation region (insulating layer, 1016) of the semiconductor substrate (1001) via a metal reinforcing via pattern (1017).
  • FIG. 9 shows an equivalent circuit when the multilayer support structure is connected at one end to the global wiring (1015) as in the semiconductor device according to the embodiment shown in FIGS. 5 and 6. It is a circuit diagram.
  • the multilayer support structure forms a capacitance between the semiconductor substrate (1001) or the interlayer insulating film
  • the multilayer support structure has a decoupling capacitance with respect to the global wiring (1015) shown as a resistance. Functions as (1112).
  • one end of the multilayer support structure is connected to the global wiring (1015).
  • the uppermost layer of the semiconductor device is reinforced with a multilayer support structure.
  • the multilayer support structure has a decoupling capacitance.
  • the circuit plays the role of a circuit as in (1112), the power supply line can be stabilized.
  • the multilayer support structure When the multilayer support structure is connected to the element isolation region (1016) provided in the semiconductor substrate (1001) as in the semiconductor device according to the embodiment shown in FIGS. Since the supporting structure is supported by the high-strength substrate (1001), the supporting structure has high structural strength, and the strength of the overall structure of the semiconductor device is also increased.
  • the structure of only the circuit region of the semiconductor device has been mainly described.
  • the semiconductor device according to the first embodiment electrically transmits and receives signals to and from the outside.
  • the semiconductor substrate (1001) On the semiconductor substrate (1001).
  • a multilayer support structure can be formed in the circuit region, and in addition, a similar multilayer support structure can be formed in the region below the pad.
  • the length of the metal reinforcing via pattern (1011) forming a part of the multilayer support structure in the thickness direction of the semiconductor device is the same as that of the conductive metal via (1010) in the thickness direction of the semiconductor device. It can be larger than the length. This makes it possible to improve the adhesion to the metal reinforcing wiring patterns (1005, 1009) in the multi-layer support structure and the strength of the interlayer insulating film. It is possible to prevent film peeling and film destruction due to impact and stress applied during packaging.
  • the shape of the metal reinforcing via pattern (1011) in the cross section of the semiconductor device is not particularly limited, and may be various shapes such as a rectangle, a hole, and a slit. It can take the form of For example, by making the shape of the metal reinforcing via pattern (1011) into a slit shape, it is possible to increase the length of the conductive metal via (1010) in the thickness direction of the semiconductor device without increasing the cross-sectional area. Can be.
  • the ratio of the total area of the conductive metal via (1010) and the metal reinforcing via pattern (1011) to the unit area of the interlayer insulating film is not less than power%. More preferably, it is more preferably 10% or more. Form conductive metal vias (1010) and metal reinforcing via patterns (1011) to satisfy these conditions. By doing so, the occurrence of defects during the chemical mechanical polishing (CMP) process can be reduced.
  • CMP chemical mechanical polishing
  • the material of the interlayer insulating films (1006, 1012) is not particularly limited.
  • inorganic materials such as SiN, SiOC, SiC, SiCN, SiO
  • a film called a low dielectric constant film that is, a film having a material strength lower than that of SiO. Examples of combinations are:
  • the local wiring is formed of a low-dielectric-constant film
  • the global wiring is formed of a film of SiO or the like having higher film strength than the low-dielectric-constant film.
  • the low dielectric constant film include various organic polymers, MSQ, HSQ, and carbon-containing silicon oxide film (SiOCH) formed by a CVD method or a coating method.
  • the force that can be achieved is not particularly limited to these.
  • the organic polymer for example, polyimide, polytetrafluoroethylene, polyallyl ether, polybenzoxazole, polyolefin, and polyamide can be used.
  • the organic polymer is not limited thereto.
  • conductive metal wiring (1004, 1008) conductive metal via (1010), metal reinforcing wiring pattern (1005, 1009) and metal reinforcing via pattern (1011)
  • Cu or Cu It is preferable to use an alloy, but it is not limited to these.
  • A is an A1 alloy, and other metals such as W, Ni, Cr, Ti, and Ag or alloys thereof, for example, W—Ti, A1 — Intermetallic compounds such as —W, Al—Ni, and silicide compounds can be used.
  • the semiconductor substrate (1001) for example, a silicon single crystal substrate, various compound semiconductor substrates, or the like can be used.
  • the conductive metal wiring (1004, 1008), the conductive metal via (1010), the metal reinforcing wiring pattern (1005, 1009), and the metal reinforcing via pattern (1011) may include various modes which are not particularly limited.
  • the size, shape, number of wirings, and other factors of the conductive metal wirings (1004, 1008) in each wiring layer can be arbitrary.
  • the method for manufacturing the semiconductor device according to the first embodiment is not particularly limited.
  • Damascene It can be formed using a method.
  • 10 to 19 are cross-sectional views showing respective steps in a damascene method as a method for manufacturing the semiconductor device shown in FIG.
  • FIGS. 10 to 19 an example of a method for manufacturing the semiconductor device shown in FIG. 6 will be described with reference to FIGS.
  • an element isolation region (1016) is formed on the surface of a semiconductor substrate (1001).
  • the transistor (1101) is mounted on the semiconductor substrate (1001).
  • the insulating film (1) is formed on the semiconductor substrate (1001) by, for example, a CVD method or a coating method.
  • a reinforcing via turn (1017) and a conductive metal via (1113) are formed inside the insulating film (1002).
  • the first wiring layer (a)
  • a predetermined portion of the first wiring layer (1003) is etched by a method such as the RIE method to form a wiring groove (1018) in the first wiring layer (1003).
  • the wiring groove (1018) is formed corresponding to the formation position of the conductive metal wiring (1004) and the reinforcing wiring pattern (1005).
  • the metal is removed, for example, so that the wiring groove (1018) is buried.
  • CMP chemical mechanical polishing
  • a first interlayer insulating film (1006) is deposited on the first wiring layer (1003) on which 5) is formed.
  • the first interlayer insulating film (1006) is etched in the same manner as above to form a via hole (1019) in the first interlayer insulating film (1006).
  • a metal is deposited in the via hole (1019), and excess metal is removed by a CMP method to form a conductive metal via (1010) and a reinforcing via pattern (1011). Form.
  • a second wiring layer (1007) is formed on the first interlayer insulating film (1006).
  • a predetermined portion of the second wiring layer (1007) is etched by a method such as the RIE method to form a wiring groove (1020) in the second wiring layer (1007).
  • the wiring groove (1020) is formed corresponding to the formation position of the conductive metal via (1010) and the reinforcing via pattern (1011).
  • a metal is deposited by, for example, a sputtering method so that the wiring groove (1020) is filled. Then, excess metal is removed by a chemical mechanical polishing (CMP) method or the like, and a conductive metal wiring (1008) and a reinforcing wiring pattern (1009) are formed in the second wiring layer (1007).
  • CMP chemical mechanical polishing
  • a second interlayer insulating film (1012) is formed on the second wiring layer (1007).
  • the second interlayer insulating film (1012) is etched in the same manner as described above, and the second interlayer insulating film (1012) is etched.
  • a via hole is formed in (1012).
  • a metal is deposited in the via hole, and a surplus metal is removed by a CMP method to form a reinforcing via pattern (1014) in the second interlayer insulating film (1012).
  • a third wiring layer (1013) is formed on the second interlayer insulating film (1012).
  • a predetermined portion of the third wiring layer (1013) is etched by, eg, RIE to form a wiring groove in the third wiring layer (1013).
  • a metal is deposited in the wiring groove, and a surplus metal is removed by a chemical mechanical polishing (CMP) method to form a global wiring (1015) in the third wiring layer (1013).
  • CMP chemical mechanical polishing
  • the semiconductor device shown in FIG. 6 is formed.
  • a single damascene process in which the conductive metal via (1010) and the conductive metal wiring (1006, 1008) are separately formed is adopted.
  • a dual damascene process can be employed.
  • the dual damascene process for example, after a first interlayer insulating film (1006) and a second wiring layer (1007) are formed, a via hole (1019) and a wiring groove (1020) are formed. A metal film is deposited in (1019) and the wiring groove (1020), and excess metal is removed by a CMP method, so that a conductive metal via (1010) and a conductive metal wiring (1008) are formed at a time. (Conductive metal wiring under pad area)
  • a semiconductor device includes a semiconductor substrate, at least one interlayer insulating film formed on the semiconductor substrate, and a plurality of wiring layers stacked with the interlayer insulating film interposed therebetween.
  • a conductive metal via interconnecting the conductive metal vias a multi-layer circuit structure comprising: a reinforcing wiring pattern provided on each of a plurality of wiring layers; and an inter-layer insulating film; A reinforcing via pattern for interconnecting reinforcing wiring patterns adjacent to each other in the vertical direction, and a multilayer supporting structure that provides a strong force. At least a part of the multilayer circuit structure is arranged in a region below the pad. Below, is a multilayer support structure Are formed in a region that does not conflict with the multilayer circuit structure.
  • FIG. 20 is a schematic cross-sectional view showing one embodiment of a semiconductor device according to the second aspect of the present invention.
  • the semiconductor device includes a semiconductor substrate (1021), a transistor (1101) formed on the semiconductor substrate (1021), and a semiconductor covering the transistor (1101).
  • the first wiring layer (1023) is made of a non-conductive material, and the first wiring layer (1023) includes a conductive metal wiring (1024) serving as a circuit wiring and a conductive metal wiring (1024). ) And a metal reinforcing wiring pattern (1025) made of the same conductive material as that of (1) are formed apart from each other.
  • the second wiring layer (1027) is made of a non-conductive material.
  • the second wiring layer (1027) has a conductive metal wiring (1028) serving as a circuit wiring and a conductive metal wiring (1028).
  • a metal reinforcing wiring pattern (1029) made of the same material as that of (1) are formed apart from each other.
  • the interlayer insulating film (1026) sandwiched between the first wiring layer (1023) and the second wiring layer (1027) is provided in the first and second wiring layers (1023, 1027), respectively.
  • a metal reinforcing via pattern (1031) for electrically connecting mutually overlapping regions to each other.
  • the metal reinforcing via pattern (1031) is made of the same conductive material as the conductive metal via (1030)! RU
  • a multilayer circuit includes conductive metal wirings (1024, 1028) and conductive metal vias (1030) stacked in the thickness direction of the semiconductor device.
  • a structure is formed.
  • a metal reinforcing wiring pattern (1025, 1029) stacked in the thickness direction of the present semiconductor device, a metal reinforcing via pattern (1031) for interconnecting the metal reinforcing wiring patterns (1025, 1029), and a multilayer supporting structure are formed.
  • the multilayer support structure exists in a gap in a circuit region where the multilayer circuit structure is formed. That is, the multilayer support structure is formed in the region where the multilayer circuit structure does not exist, just like the multilayer circuit structure does not conflict with the inside of the circuit region where the multilayer circuit structure is formed. .
  • the multilayer support structure is formed in a region below the metal wire bonding pad (1040), and a part of the multilayer circuit structure is also provided. It is formed in a region below the metal wire bonding pad (1040). Some of the plurality of transistors (1101) are arranged in a region below the metal wire bonding pad (1040).
  • the multilayer support structure includes a region where the metal reinforcing wiring patterns (1025, 1029) of the first and second wiring layers (1023, 1027) overlap with each other and a metal reinforcing via pattern (103). 1), the area occupied by the multilayer support structure can be reduced, and the area under the metal wire bonding pad (1040) can be electrically conductive like the other circuit areas. It is possible to dispose a conductive metal wiring (1024, 1028) and a conductive metal via (1030), or a transistor (1101).
  • the reinforcing wiring patterns (1025, 1029) forming the multilayer support structure and the conductive metal wirings (1024, 1028) existing in the same wiring layer Are formed of the same conductive material
  • the metal reinforcing via pattern (1031) forming the multilayer support structure and the conductive metal via (1030) existing in the same interlayer insulating film are formed of the same conductive material.
  • the reinforcing wiring pattern (1025, 1029) and the conductive metal wiring (1024, 1028) may be formed of mutually different materials.
  • the metal reinforcing via pattern (1031) existing in the same interlayer insulating film may be used.
  • the conductive metal via (1030) may be formed of a conductive material different from the conductive metal via (1030). However, by forming the same material with the same force, there is an advantage that the number of steps in the manufacturing process can be reduced.
  • the multilayer support structure as described above has the following features in the thickness direction of the semiconductor device: It is sufficient that at least two or more of a plurality of wiring layers and interlayer insulating films stacked on the semiconductor substrate (1001) are formed.
  • this multilayered support structure includes conductive metal wiring (1024, 1028) and conductive metal via.
  • the multilayer circuit structure consisting of (1030) or metal wire bonding pads (1040) may also be electrically insulated or electrically connected to the multilayer circuit structure or metal wire bonding pads (1040) It may be something.
  • the multilayer support structure is connected to the multilayer circuit structure only at one end thereof, and is electrically connected to the other end thereof.
  • the multilayer circuit structure is electrically isolated, that is, electrically grounded.
  • the multilayer support structure may extend from the second wiring layer (1027), which is the uppermost layer of the semiconductor device, to the semiconductor substrate (1021), or may be a multilayer circuit structure. It may be terminated at the department.
  • the multilayer support structure can be connected to the element isolation region (1016), similarly to the embodiment shown in FIG. It is possible.
  • FIG. 21 and FIG. 22 are plan views schematically showing an example of an existing area of the multilayer support structure.
  • the multi-layer support structure has a predetermined distance outside the outer periphery of the bonding pad (351, 352) as well as the area below the bonding pad (351, 352). It can also be formed in the area below the range (350).
  • the range (350) of the predetermined distance outside the outer periphery of the bonding pads (351, 352) is not particularly limited. As will be described later, when the multilayer support structure extends to a region outside the outer periphery of the bonding pad, the distance from the outer edge of the bonding pad to the outermost periphery of the multilayer support structure, and the distance between the bonding pad and the bonding wire. Investigation of the relationship with the adhesion strength between them revealed that the multilayer support structure was arranged within a distance range of about 10 m, compared to the case where the multilayer support structure was formed only in the area below the bonding pad. , Good improvement in adhesion strength has been observed. For this reason, by setting the range of the predetermined distance (350) to about 10 m, the adhesion strength between the bonding pad and the bonding wire can be improved.
  • FIG. 21 shows a case where the distance between adjacent bonding pads (351) is 20 ⁇ m, and the number of multilayer circuits within a range (350) of a distance of 10 ⁇ m outside the bonding pads (351) is increased.
  • An example of arranging structures is shown.
  • FIG. 22 shows that, when the distance between adjacent bonding pads (352) is less than 10 m, a multilayer circuit structure within a range (350) up to a distance of 10 ⁇ m outside the bonding pads (352).
  • An example of arranging is shown below.
  • the semiconductor device of the metal reinforcing via pattern (1031) forming a part of the multilayer support structure is provided.
  • the length of the device in the thickness direction can be larger than the length of the conductive metal via (1030) in the thickness direction of the semiconductor device. This makes it possible to improve the adhesion to the metal reinforcing wiring patterns (1025, 1029) in the multilayer support structure and improve the strength of the interlayer insulating film. Peeling and film destruction can be prevented.
  • the shape of the metal reinforcing via pattern (1031) in the cross section of the semiconductor device is not particularly limited, and may be various shapes such as a rectangle, a hole, and a slit. Can be taken. For example, by making the shape of the metal reinforcing via pattern (1031) into a slit shape, it is possible to increase the length of the conductive metal via (1030) in the thickness direction of the semiconductor device without increasing the cross-sectional area. Can be.
  • the ratio of the total area of the conductive metal via (1030) and the metal reinforcing via pattern (1031) to the unit area of the interlayer insulating film is not less than power%. More preferably, it is more preferably 10% or more.
  • the material of the semiconductor substrate is not limited at all, and the same materials as those described in the semiconductor device according to the first embodiment can be used.
  • the conductive metal wiring (1024, 1028), the conductive metal via (1010), the metal reinforcing wiring pattern (1005, 1009), and the metal reinforcing via pattern (1031) may include various modes which are not particularly limited.
  • the size, shape, number of wirings, and other factors in each wiring layer of the conductive metal wirings (1024, 1028) can be arbitrary.
  • the second wiring layer (1027), which is the uppermost layer of the semiconductor device, is provided below the wire bonding pad (1040).
  • the uppermost layer of the semiconductor device, or a plurality of upper layers is formed of the same material as the conductive metal wiring.
  • a large-area wiring layer pad may be formed to support the bonding pad (104).
  • the method for manufacturing the semiconductor device according to the second aspect is not particularly limited, as in the case of the semiconductor device according to the first aspect.
  • it can be formed using a damascene method.
  • a semiconductor device includes a semiconductor substrate, at least one interlayer insulating film formed on the semiconductor substrate, and a plurality of wiring layers stacked with the interlayer insulating film interposed therebetween.
  • a multilayer circuit structure is formed, comprising: a circuit wiring formed in each of a plurality of wiring layers; and a conductive metal via penetrating an interlayer insulating film and interconnecting vertically adjacent circuit wirings.
  • the semiconductor device includes a circuit region in which the multilayer circuit structure is formed, and a scribe region which is a region around the circuit region and in which no circuit is formed. hand
  • the multilayer support structure is formed in the scribe area.
  • FIG. 23 is a schematic cross-sectional view showing one embodiment of a semiconductor device according to the third aspect of the present invention.
  • the semiconductor device includes a semiconductor substrate (1061), a transistor (1101) formed on the semiconductor substrate (1061), and a semiconductor covering the transistor (1101).
  • the first wiring layer (1063) is made of a non-conductive material, and the first wiring layer (1063) has a conductive metal wiring (1091) serving as a circuit wiring in the circuit area (1200). And metal reinforcing wiring patterns (1081, 1086) having the same conductive material strength as the conductive metal wiring (1091) are formed apart from each other.
  • a metal reinforcing wiring pattern (1071) having the same conductive material strength as the conductive metal wiring (1091) is formed in the scribe region (1300).
  • the second wiring layer (1065) is made of a non-conductive material, and the second wiring layer (1065) has a conductive metal wiring (1093) serving as a circuit wiring in the circuit area (1200). And metal reinforcing wiring patterns (1083, 1088) having the same material strength as the conductive metal wiring (1093) are formed apart from each other.
  • a metal reinforcing wiring pattern (1073) having the same conductive material strength as that of the conductive metal wiring (1093) is formed in the scribe region (1300).
  • the third wiring layer (1067) is made of a non-conductive material, and the third wiring layer (1067) has a conductive metal wiring (1095) serving as a circuit wiring in the circuit area (1200). And a metal reinforcing wiring pattern (1085) having the same material strength as the conductive metal wiring (1095) are formed apart from each other.
  • a metal reinforcing wiring pattern (1075) having the same conductive material strength as the conductive metal wiring (1095) is formed in the scribe region (1300).
  • a part of the conductive metal wiring (1095) formed in the uppermost third wiring layer (1067) has a large area, and the large area wiring Form a layer pad (1095B)! / The wire bonding pad (1040) is formed above the large area wiring layer pad (1095B).
  • the first interlayer insulating film (1064) sandwiched between the first wiring layer (1063) and the second wiring layer (1065) has first and second layers in the circuit region (1200). Conductors for electrically connecting the conductive metal wires (1091, 1093) provided in the two wiring layers (1063, 1065), respectively. A metal that electrically connects an electrically conductive metal via (1092) and a region where the metal reinforcing wiring patterns (1081, 1083) provided in the first and second wiring layers (1063, 1065) respectively overlap each other. A reinforcing via pattern (1082, 1087) is formed. The metal reinforcing via patterns (1082, 1087) are formed of the same conductive material as the conductive metal via (1092).
  • the metal reinforcing wiring patterns (1010) provided in the first and second wiring layers (1063, 1065) in the scribe region (1300), respectively.
  • the second interlayer insulating film (1066) sandwiched between the second wiring layer (1065) and the third wiring layer (1067) has the second and third wiring layers in the circuit region (1200).
  • a conductive metal via (1094) for electrically connecting the conductive metal wirings (1093, 1095) provided in the wiring layers (1065, 1067) to each other; and second and third wiring layers (1065, 1065). 1067) are provided with metal reinforcing via patterns (1084, 1089) for electrically connecting mutually overlapping regions provided with metal reinforcing wiring patterns (1083, 1085).
  • the metal reinforcing via patterns (1084, 1089) are formed of the same conductive material as the conductive metal via (1094).
  • the metal reinforcing wiring patterns (10 73) provided in the second and third wiring layers (1065, 1067) in the scribe region (1300), respectively. , 1075) are formed with a metal reinforcing via pattern (1074) for electrically connecting mutually overlapping regions to each other.
  • the conductive metal stacked in the thickness direction of the semiconductor device below the wire bonding pad (1040) in the circuit region (1200) Wirings (1091, 1093, 1095), conductive metal vias (1092, 1094), and a multi-layer circuit structure are formed.
  • the force also forms a multilayer support structure.
  • Multi-layer support The structure exists in a gap in a circuit region where the multilayer circuit structure is formed. That is, the multilayer support structure is formed in a region where the multilayer circuit structure does not exist so as not to conflict with the multilayer circuit structure inside the circuit region (1200) where the multilayer circuit structure is formed.
  • the metal reinforcing wiring patterns (1071, 1073, 1075) stacked in the thickness direction of the semiconductor device and the metal reinforcing via patterns (107, 1073, 1075) interconnecting the metal reinforcing wiring patterns (1071, 1073, 1075) are also provided.
  • 1072, 1074) also form a multilayer support structure.
  • a metal reinforced via pattern (1089) is provided on the interlayer insulating film (1066) and supports the metal reinforced wiring pattern (1088) on the large area wiring layer pad (1095B) on the top, and a multi-layered support structure is provided. ing.
  • FIG. 24 is a plan view schematically showing a positional relationship between the circuit region (1200) and the scribe region (1300) in the semiconductor device according to the embodiment shown in FIG. 23, and FIG. 25 is an enlarged plan view of a region B shown in FIG.
  • the scribe region (1300) in the semiconductor device is defined by the conductive metal wiring (1091, 1093, 1095) and the conductive metal via (1092, 1094). It is located outside the circuit area (1200) (including the area below the wire bonding nod (1040)) where the multilayer circuit structure to be formed exists, and the outer peripheral edge of the circuit area (1200) and the peripheral edge of the semiconductor chip. Refers to the area between E and Generally, there are no circuits in the scribe area (1300).
  • the portion indicated by the symbol X existing in one corner of the semiconductor chip represents a "cross-shaped mark".
  • the cross mark X has a cross shape literally on the wafer before chip cutting, and is used for alignment when dicing the wafer. This is the mark used.
  • Each semiconductor chip (semiconductor device) after dicing has an almost L-shaped shape as shown in FIG. , And remain at the four corners of the semiconductor chip.
  • the first to third scribe regions (1300) outside the circuit region (1200) are located.
  • a multi-layered support structure composed of metal reinforcing via patterns (1072, 1074) for electrically connecting the metal reinforcing wiring patterns (1071, 1073, 1075) to each other is formed.
  • the reinforcing wiring patterns (1071, 1073, 1075) forming the multilayer support structure and the conductive metal wirings (1091, 1093, 1095) are formed of the same conductive material, and furthermore, the metal reinforcing via patterns (1072, 1074) forming the multilayer support structure and the conductive metal vias (1092) existing in the same interlayer insulating film are formed. , 1094) is not necessarily limited to the force formed of the same conductive material.
  • the reinforcing wiring pattern (1071, 1073, 1075) and the conductive metal wiring (1091, 1093, 1095) may be formed of mutually different materials.
  • metal reinforcing via patterns existing in the same interlayer insulating film The (1072, 1074) and the conductive metal vias (1092, 1094) may be formed of mutually different conductive materials. However, there is an advantage in that the number of steps in the manufacturing process can be reduced by forming the same material while using force.
  • the position of the multilayer support structure in the scribe region (1300) is not particularly limited, and is arranged at an arbitrary position in the scribe region (1300). Possible Force It is desirable to dispose the multilayer support structure at each corner of the semiconductor chip, that is, in the region below the cross mark X as shown in FIG.
  • FIG. 27 is a schematic cross-sectional view showing another embodiment of the semiconductor device according to the third aspect of the present invention.
  • FIG. 28 shows a circuit region and a scribe region in the semiconductor device shown in FIG. 29 is a plan view schematically showing the positional relationship of FIG. 29, and
  • FIG. 29 is an enlarged plan view of a region E shown in FIG.
  • the semiconductor device according to the embodiment shown in FIG. 27 differs from the semiconductor devices according to the embodiment shown in FIGS. 23, 24 and 25 from the position where the wire bonding pad (1040) is formed. The difference is also that a shield (1100) is formed between a circuit region on the outer peripheral side of the chip, that is, the outside of the wire bonding pad (1040) and the scribe region (1300).
  • the shield (1100) has a laminated body strength in which a metal reinforcing wiring pattern and a metal reinforcing via pattern are stacked.
  • the shield (1100) is arranged continuously over the entire periphery along the outer peripheral edge of the semiconductor chip. Therefore, it is possible to effectively prevent moisture from entering the circuit region (1200) from outside the semiconductor device. Further, since the shield (1100) is also a multilayer support structure including a metal reinforcing wiring pattern and a metal reinforcing via pattern, it also exerts an effect of increasing the strength and adhesion at the outer peripheral edge of the semiconductor chip.
  • the multilayer support structure may be formed at least in the scribe region (1300) as long as the condition is satisfied.
  • the following embodiment can be adopted.
  • a multilayer support structure is formed in a region below the scribe region (1300) and the wire bonding pad (1040), and a multilayer support structure is not formed in the circuit region (1200).
  • a multi-layer support structure is formed in the scribe area (1300) and the circuit area (1200), and the multi-layer support structure is not formed in a region below the wire bonding pad (1040).
  • the multilayer support structure has a structure in the thickness direction of the semiconductor device. It is sufficient that at least two or more of a plurality of wiring layers and interlayer insulating films stacked on the semiconductor substrate (1061) are formed.
  • the multilayer support structure is electrically insulated from the multilayer circuit structure or the wire bonding pad (1040) that also has the force of the conductive metal wiring (1091, 1093, 1095) and the conductive metal via (1092, 1094). It may be one that is electrically connected to a multilayer circuit structure or a wire bonding pad (1040).
  • the multilayer support structure is connected to the multilayer circuit structure only at one end thereof, and is electrically connected at the other end.
  • the multilayer circuit structure is electrically isolated, that is, electrically grounded.
  • the scribe region (1300) when the element isolation region (1016) is provided in the semiconductor substrate (1061), similarly to the semiconductor device according to the first embodiment of the present invention, the multi-layer support is provided.
  • the structure can be connected to the element isolation region (1016).
  • the multilayer support structure may be configured such that the force of the third wiring layer (1067), which is the uppermost layer of the present semiconductor device, is also extended to the semiconductor substrate (1061), or a plurality of wiring layers and It may be one that terminates inside the laminated body composed of the interlayer insulating film.
  • the metal reinforcing via pattern (1082, 1084) forming a part of the multilayer support structure in the thickness direction of the semiconductor device.
  • the length can be larger than the length of the conductive metal via (1092, 1094) in the thickness direction of the semiconductor device. This makes it possible to improve the adhesion to the metal-reinforced wiring patterns (1081, 1083, 1085) and the strength of the interlayer insulating film in the multi-layered support structure. It is possible to prevent film peeling and film destruction due to the above.
  • the metal reinforcement in the cross section of the semiconductor device (the surface orthogonal to the paper surface in FIGS. 23 and 27)
  • the shape of the via pattern (1082, 1084) is not particularly limited, and may take various forms such as a rectangle, a hole, and a slit.
  • the shape of the metal reinforcing via pattern (1082, 1084) into a slit shape, it is possible to increase the length of the conductive metal via (1092, 1094) in the thickness direction of the semiconductor device without increasing the cross-sectional area. It can be.
  • the ratio of the total area of the metal reinforcing via patterns (1072, 1074) to the unit area of the interlayer insulating film in the scribe region (1300) is 5% or more. More preferably, it is more preferably 10% or more.
  • the semiconductor device also includes an interlayer insulating film material, a conductive metal wiring (circuit wiring), a conductive metal via, a reinforcing wiring pattern, a conductive material forming a reinforcing via, and
  • the material of the semiconductor substrate is not limited at all, and the same materials as those described in the semiconductor device according to the first embodiment can be used.
  • the method for manufacturing a semiconductor device according to the third embodiment is not particularly limited, as in the case of the semiconductor device according to the first embodiment.
  • it can be formed using a damascene method.
  • FIG. 30 is a sectional view of one embodiment of the semiconductor device according to the first aspect of the present invention described above.
  • the semiconductor device according to this example includes a semiconductor substrate (111) and an insulating film (112) formed on the semiconductor substrate (111).
  • the semiconductor substrate (111) is a single crystal silicon substrate.
  • the insulating film (112) is made of borophosphosilicate 'glass (BPSG: borophosphosilic). ate glass), phosphosilicate glass (PSG: phosphosilicate glass), silicon oxide silicon (SiO 2), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxyfluoride (SiOF),
  • SiC silicon carbide
  • SiCN silicon carbonitride
  • a first wiring layer (113) is formed on the insulating film (112).
  • the first wiring layer (113) is made of an organic polymer of a low dielectric constant material, MSQ
  • HSQ a carbon-containing silicon oxide film.
  • a stacked film strength with SiN, SiOC, SiC, SiCN, SiO, etc. forming an etching stopper and a node mask can also be formed.
  • the first wiring layer (113) includes a metal circuit wiring (or a conductive metal wiring) (115) for electrically connecting a circuit and a metal reinforcing wiring pattern having no electrical connection to the circuit. (116) are formed.
  • a first interlayer insulating film (117) is formed on the first wiring layer (113).
  • a conductive metal via (118) for electrically connecting the upper and lower metal circuit wirings (115, 121) to each other, and an upper and lower metal reinforcing wiring pattern are provided.
  • a metal reinforcing via pattern (119) to be connected is formed.
  • the first interlayer insulating film (117) is made of an organic polymer of low dielectric constant material, MSQ, HSQ, or a silicon-containing film containing carbon. It can also be composed of a laminated film of SiCN, SiO, etc.
  • a second wiring layer (120) is formed on the first interlayer insulating film (117).
  • a metal circuit wiring (121) and a metal reinforcing wiring pattern (122) are formed.
  • the second wiring layer (120) is made of an organic polymer of a low dielectric constant material, MSQ, HSQ, or a silicon-oxide film containing carbon. Etching stopper and SiN, SiOC forming a node mask. , SiC, SiCN, SiO, etc. can also be configured.
  • a multilayer circuit structure is formed by alternately stacking the wiring layers and the interlayer insulating films.
  • the metal reinforcing via pattern (119) forms a multilayer support structure by connecting the metal reinforcing wiring patterns (116, 122) of the first and second wiring layers (113, 120) to each other.
  • FIG. 31 is a plan view of the semiconductor device according to the present embodiment.
  • the metal reinforcing via patterns (119 ) are arranged so as to connect only the region (123) where the metal reinforcing wiring patterns (116, 122) overlap. For this reason, it is possible to introduce a metal reinforcing via pattern (119) that does not change the size and shape of the CMP dummy pattern, which is also conventionally formed, that is, does not increase the chip area.
  • FIG. 32 shows the area occupancy of the metal-reinforced via pattern (the ratio of the area of the metal-reinforced via pattern to the unit area of the semiconductor device) when the low-dielectric-constant film is used as the interlayer insulating film, and the CMP occupancy. It is a graph which shows the relationship with the rate of film peeling.
  • the force conductive metal via (118) and the conductive metal via (115, 121) formed separately using a single damascene process are used. It is also possible to use a dual damascene process for simultaneously forming 118) and the conductive metal wiring (121).
  • FIG. 33 is a cross-sectional view of one embodiment of the semiconductor device according to the second aspect of the present invention described above.
  • the semiconductor device includes a semiconductor substrate (211) and a semiconductor substrate (211).
  • the semiconductor substrate (211) is a single crystal silicon substrate.
  • the insulating film (212) is made of borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), phosphosilicate glass (PSG), silicon oxide (SiO 2), silicon nitride (SiN), Silicon oxynitride (SiON), silicon oxyfluoride (SiOF),
  • BPSG borophosphosilicate glass
  • PSG phosphosilicate glass
  • PSG silicon oxide
  • SiN silicon nitride
  • SiON Silicon oxynitride
  • SiOF silicon oxyfluoride
  • SiC silicon carbide
  • SiCN silicon carbonitride
  • the first wiring layer (213) is formed on the insulating film (212).
  • the first wiring layer (213) is made of an organic polymer of low dielectric constant material, MSQ, HSQ, or a silicon-containing silicon oxide film. Etching stopper and SiN, SiOC forming a node mask are used. , SiC, SiCN, SiO, etc. can also be configured.
  • the first wiring layer (213) includes a metal circuit wiring (or a conductive metal wiring) (215) for electrically connecting a circuit and a metal dummy wiring ( 216) is formed.
  • a first interlayer insulating film (217) is formed on the first wiring layer (213.
  • a conductive metal via (224) for electrically connecting the upper and lower metal circuit wirings (215, 219) to each other, and an upper and lower metal reinforcing wiring pattern are provided.
  • a metal reinforcing via pattern (225) to be connected is formed.
  • the first interlayer insulating film (217) is an organic polymer of a low dielectric constant material
  • It can be composed of a laminated film of SiC, SiCN, SiO or the like forming a force etching stopper and a node mask which is MSQ, HSQ or carbon-containing silicon oxide film.
  • a second wiring layer (218) is formed on the first interlayer insulating film (217).
  • a metal circuit wiring (219) and a metal reinforcing wiring pattern (220) are formed.
  • the second wiring layer (218) is made of an organic polymer of low dielectric constant material, MSQ, HSQ, or a silicon-containing silicon oxide film. , SiC, SiCN, SiO, etc. can also be configured.
  • the multilayer circuit structure is formed by alternately laminating the wiring layers and the interlayer insulating films. Is formed.
  • a metal bonding pad (221) for transmitting and receiving electric signals to and from the outside of the chip is formed.
  • the metal bonding pad (221) is electrically connected to the metal circuit wiring (219) formed on the uppermost second wiring layer (218).
  • the transistor (2211) and the metal circuit wiring (215) have the metal bonding pad (221) in the same manner as the non-metal region (circuit region).
  • the metal reinforcing via patterns (216, 220) connecting the regions where the upper and lower metal reinforcing wiring patterns (216, 220) overlap each other are connected. 225) exists.
  • FIG. 34 is a plan view of the semiconductor device according to the example shown in FIG.
  • FIG. 35 shows the area ratio of the metal reinforcing via pattern in the region below the metal bonding pad when the low dielectric constant film is used as the interlayer insulating film in the semiconductor device according to the example shown in FIG. 7 is a graph showing a relationship between a via occupation ratio (%)) and a film peeling ratio during wire bonding (bonding defect ratio (%)).
  • a transistor (2211) forming a circuit area below the metal bonding pad (221), and a multilayer circuit including metal circuit wirings (215, 219) and conductive metal vias (224)
  • the region below the metal bonding pad (221) includes one of the transistor (2211) and one of the metal circuit wiring and the conductive metal via forming the multilayer circuit structure. Only one is arranged.
  • neither the transistor (2211) nor the multilayer circuit structure is disposed in the region below the metal bonding pad (221), and the region below the metal bonding pad (221) is provided with a metal reinforcing wiring pattern ( 216, 220) and a metal reinforcing via pattern (225) alone may be arranged.
  • FIG. 36 is a cross-sectional view of a high-spec LSI to which the above embodiment is applied.
  • the global wiring layer (231) includes a via interlayer insulating film (230), which is an insulating film having a higher dielectric constant and film strength than the low dielectric constant material constituting the multilayer local wiring layer (228), and a via interlayer insulating film.
  • the wiring layer (229) formed of an insulating film having a higher dielectric constant and a higher film strength than the low dielectric constant material forming the multilayer local wiring layer (228) is formed above the film (230).
  • a metal bonding pad (232) for transmitting and receiving an electric signal to / from the outside of the chip is arranged above the local wiring (236) and the global wiring (237).
  • the wiring layer (229) and the via interlayer insulating film (230) are each made of SiO 2.
  • the metal bond in the local wiring layer (228) made of a low dielectric constant interlayer insulating film is formed.
  • a metal reinforcing via pattern (233) for connecting the metal reinforcing wiring patterns (238) of the upper and lower layers to each other is formed only in a region below the bonding pad (232).
  • the global wiring layer (231) has high film strength and adhesion of the wiring layer (229) and the via interlayer insulating film (230) against the shock at the time of bonding. Alternatively, it is possible to withstand stress.
  • the presence of the metal reinforcing via pattern (233) in the local wiring layer (228) makes it possible to increase the strength and adhesion of the interlayer insulating film, resulting in the impact and stress during bonding. It is possible to prevent film peeling and film destruction.
  • a single damascene process in which a conductive metal via and a conductive metal wiring are formed separately is used. It is also possible to use a dual damascene process formed at the same time.
  • FIG. 37 is a cross-sectional view of a first modification of the embodiment shown in FIG.
  • an insulating film (212) and a first wiring layer are formed on a semiconductor substrate (211) on which a transistor (2211) is formed. (213), a first interlayer insulating film (217), a second wiring layer (218), a second interlayer insulating film (240), and a third wiring layer (241) are stacked in this order.
  • a metal bonding pad (221) is arranged on the third wiring layer (241.
  • a large-area wiring layer pad (242) is formed immediately below the metal bonding pad (221). (242) has a structure for supporting the metal bonding pad (221) stacked thereon.
  • the large-area wiring layer pad (242) is formed of the same material as the metal circuit wiring (243) provided in the circuit region of the third wiring layer (241).
  • the area below the large-area wiring layer pad (242) does not include the metal bonding pad (221) (the circuit).
  • the metal bonding pad (221) the circuit.
  • FIG. 38 is a sectional view of a second modification of the embodiment shown in FIG.
  • the uppermost third wiring layer (241) in the semiconductor device shown in FIG. 37 has a single-layer structure, whereas the uppermost third wiring layer (245) 37) is different from the semiconductor device shown in FIG.
  • a laminate (245) in which a plurality of wiring layers are stacked is formed as a third wiring layer on the second interlayer insulating film (240).
  • a large area wiring layer pad (246) is formed on the laminate (245) immediately below the metal bonding pad (221).
  • This large-area wiring layer pad (246) is also composed of a laminate of a plurality of layers, and has a structure in which the large-area wiring layer pad (246) supports the metal bonding pad (221) mounted thereon! /
  • the large-area wiring layer pad (246) is formed of the same material as the metal circuit wiring (247) provided in the circuit region of the multilayer body (245).
  • the area below the large-area wiring layer pad (246) does not include the metal bonding pad (221) (the circuit).
  • the area below the large-area wiring layer pad (246) does not include the metal bonding pad (221) (the circuit).
  • a metal bonding pad (221) is supported by a large-strength large-area wiring layer pad (246).
  • the second interlayer insulating film (240) located under the area wiring layer pad (246) is the same as the via interlayer insulating film (230) in the green wiring layer (231) shown in FIG. It is not necessary to form a metal reinforcing via pattern in the second interlayer insulating film (240) because it can have high strength and high adhesion.
  • the third wiring layer (245) having the large-area wiring layer pad (246) has high film strength and high adhesion to the impact during bonding.
  • the layer below the third wiring layer (245) has a multilayer support structure, so that the strength and adhesion of the interlayer insulating film can be increased. It is possible to prevent film peeling and film destruction due to shock and stress during bonding.
  • FIGS. 39 and 40 are plan views showing examples of the shape of the large-area wiring layer pads (242, 246) in the semiconductor device shown in FIGS. 37 and 38.
  • the large-area wiring layer pads (242, 246) can be formed in a rectangular shape entirely made of metal R, as shown in FIG. 39, for example.
  • the outer shape may be a rectangular shape made of metal R, and a rectangular island I made of an insulating film may be formed therein.
  • the number of islands I can be one or more (four in the example shown in FIG. 40).
  • the arrangement of the islands I is optional.
  • the large-area wiring layer pads (242, 246) are more likely to be displaced than the semiconductor device having the global wiring layer (231) shown in FIG. 36 or the semiconductor device having no global wiring layer 231). It is also applicable.
  • FIG. 41 is a cross-sectional view of another example of the semiconductor device according to the second embodiment of the present invention.
  • the semiconductor device according to the present embodiment will be described with reference to FIG.
  • the semiconductor device according to the present example includes a semiconductor substrate (311) and an insulating film (312) formed on the semiconductor substrate (311).
  • the semiconductor substrate (311) is a single crystal silicon substrate.
  • the insulating film (312) is made of borophosphosilicate 'glass (8-30: 1) 01: 0 1105 110511 ate glass), phosphosilicate glass (PSG: phosphosilicate glass), silicon oxide silicon (SiO 2), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxyfluoride (SiOF),
  • SiC silicon carbide
  • SiCN silicon carbonitride
  • the first wiring layer (313) is formed on the insulating film (312).
  • the first wiring layer (313) is made of an organic polymer of a low dielectric constant material, MSQ
  • HSQ a carbon-containing silicon oxide film.
  • a stacked film strength with SiN, SiOC, SiC, SiCN, SiO, etc. forming an etching stopper and a node mask can also be formed.
  • the first wiring layer (313) includes a metal circuit wiring (or a conductive metal wiring) (315) for electrically connecting the circuit and a metal reinforcing wiring pattern having no electrical connection to the circuit. (316) is formed.
  • a first interlayer insulating film (317) is formed on the first wiring layer (313.
  • a conductive metal via (324) for electrically connecting the upper and lower metal circuit wirings (319, 315) to each other, and an upper and lower metal reinforcing wiring pattern are provided.
  • a metal reinforcing via pattern (325) to be connected is formed.
  • the first interlayer insulating film (317) is made of an organic polymer of low dielectric constant material, MSQ, HSQ or a silicon-containing film containing carbon. It can also be composed of a laminated film of SiCN, SiO, etc.
  • a second wiring layer (318) is formed on the first interlayer insulating film (317).
  • a metal circuit wiring (319) and a metal reinforcing wiring pattern (320) are formed.
  • the second wiring layer (318) is made of an organic polymer of low dielectric constant material, MSQ, HSQ, or a silicon-containing film containing carbon. Etching stopper and SiN, SiOC forming a node mask. , SiC, SiCN, SiO, etc. can also be configured. As described above, a multilayer circuit structure is formed by alternately stacking the wiring layers and the interlayer insulating films.
  • the metal reinforcing via pattern (325) forms a multilayer support structure by connecting the metal reinforcing wiring patterns (316, 320) of the first and second wiring layers (313, 318) to each other.
  • a metal bonding pad (321) for transmitting and receiving electric signals to and from the outside of the chip is formed.
  • the metal bonding pad (321) is electrically connected to the metal circuit wiring (319) formed on the uppermost second wiring layer (318).
  • the impact or stress at the time of wire bonding may also diffuse to a region outside the metal bonding pad (321), which can be seen only below the metal bonding pad (321). For this reason, in the present embodiment, as shown in FIG. 41, which is formed only in the region below the metal bonding pad (321), the upper and lower portions existing within a predetermined distance (3251) from the outer edge of the metal bonding pad (321) are formed.
  • a metal reinforcing via pattern (325) for connecting a region where the metal reinforcing wiring patterns (316, 320) adjacent to each other overlap each other is formed.
  • the fixed distance (3251) from the outer edge of the metal bonding pad (321) changes according to the strength and adhesion of the low dielectric constant material. It may be necessary to form a metal reinforced via pattern (325) over the entire chip.
  • the metal reinforcing via pattern (325) is located not only immediately below the metal bonding pad (321) but also within a predetermined distance (3251) from the outer edge of the metal bonding pad (321).
  • the metal bonding pad (321) and its surroundings This makes it possible to increase the strength and adhesion of the interlayer insulating film, and to prevent film peeling and film destruction due to impact and stress during wire bonding.
  • FIG. 42 shows a region where the multilayer support structure exists when the interlayer support film is formed of a low dielectric constant film and the downward force of the metal bonding pad (321) is also spread outward.
  • 7 is a graph showing the relationship between the distance from the outer edge of the metal bonding pad (321) and the adhesion strength of the bonding portion measured by the ball shear method.
  • the outer peripheral force of the metal bonding pad (321) is also within a range of about 10 m by providing the multilayer support structure, so that only the area below the metal bonding pad (321) is provided. It is possible to significantly increase the strength for wire bonding as compared to the case where a multilayer support structure is present.
  • FIG. 43 is a plan view of the semiconductor device shown in FIG.
  • the space between the lower metal reinforcing wiring patterns existing under the metal bonding pad (321) and within a certain distance (3251) from the outer edge of the metal bonding pad (321) is reduced. Even when there is a metal reinforcing via pattern (325) for connection, the metal reinforcing via pattern (325) exists only in the region (326) where the metal reinforcing wiring patterns vertically adjacent to each other overlap with each other. It is possible to increase the strength against wire bonding without causing an electrical effect on circuit wiring or conductive metal vias or an increase in chip area.
  • a transistor (3211) forming a circuit area below the metal bonding pad (321), a multilayer circuit including metal circuit wirings (315, 319) and conductive metal vias (324)
  • the region below the metal bonding pad (321) includes one of the transistor (3211) and one of the metal circuit wiring and the conductive metal via forming the multilayer circuit structure. Only one is arranged.
  • neither the transistor (3211) nor the multilayer circuit structure is arranged in the region below the metal bonding pad (321), and the region below the metal bonding pad (321) is provided with a metal reinforcing wiring pattern ( 316, 320) and a metal reinforcing via pattern (325) alone may be arranged.
  • FIG. 44 is a cross-sectional view of a high-spec LSI to which the above embodiment is applied.
  • a multilayer local wiring layer (328) made of a low dielectric constant material and a global wiring layer (331) above the multilayer local wiring layer (328). And are formed.
  • the global wiring layer (331) includes a via interlayer insulating film (330), which is an insulating film having higher dielectric constant and film strength than the low dielectric constant material constituting the multilayer local wiring layer (328), and a via interlayer insulating film.
  • the wiring layer (329) formed of an insulating film having a higher dielectric constant and a higher film strength than the low dielectric constant material forming the multilayer local wiring layer (328) is formed above the film (330).
  • a metal bonding pad (332) for transmitting and receiving electric signals to and from the outside of the chip is arranged above the multi-layer wiring that acts as the local wiring (336) and the global wiring (337).
  • the wiring layer (329) and the via interlayer insulating film (330) are each made of SiO 2.
  • a metal reinforcing via pattern (333) for connecting the metal reinforcing wiring patterns (338) of the upper and lower layers to each other is formed in the region (1).
  • the global wiring layer (331) has high film strength and adhesion of the wiring layer (329) and the via interlayer insulating film (330) against the shock at the time of bonding. Alternatively, it is possible to withstand stress.
  • the presence of the metal reinforcing via pattern (333) in the local wiring layer (328) makes it possible to increase the strength and adhesion of the interlayer insulating film, resulting in the impact and stress during bonding. It is possible to prevent film peeling and film destruction.
  • FIG. 45 is a cross-sectional view of another example of the semiconductor device according to the first embodiment of the present invention.
  • the semiconductor device according to the present embodiment will be described with reference to FIG.
  • the semiconductor device according to the present example includes a semiconductor substrate (411) and an insulating film (412) formed on the semiconductor substrate (411).
  • the semiconductor substrate (411) is a single crystal silicon substrate.
  • the insulating film (412) is made of borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), phosphosilicate glass (PSG), silicon nitride (SiO 2), silicon nitride (SiN ), Silicon oxynitride (SiON), silicon oxyfluoride (SiOF),
  • BPSG borophosphosilicate glass
  • PSG phosphosilicate glass
  • PSG phosphosilicate glass
  • SiO 2 silicon nitride
  • SiN silicon nitride
  • SiON Silicon oxynitride
  • SiOF silicon oxyfluoride
  • SiC silicon carbide
  • SiCN silicon carbonitride
  • a first wiring layer (413) is formed on the insulating film (412).
  • the first wiring layer (413) is made of an organic polymer of a low dielectric constant material, MSQ
  • HSQ a carbon-containing silicon oxide film.
  • a stacked film strength with SiN, SiOC, SiC, SiCN, SiO, etc. forming an etching stopper and a node mask can also be formed.
  • the first wiring layer (413) includes a metal circuit wiring (or a conductive metal wiring) (415) for electrically connecting the circuit and a metal reinforcing wiring pattern having no electrical connection to the circuit. (416) are formed.
  • a first interlayer insulating film (417) is formed on the first wiring layer (413.
  • the length of the metal reinforcing via pattern (419) in the thickness direction of the present semiconductor device is set to be longer than the length of the conductive metal via (418) formed in the same layer in the same direction. .
  • the first interlayer insulating film (417) is a low dielectric constant material organic polymer, MSQ, HSQ or a carbon-containing silicon oxide film. It can also be composed of a laminated film of SiCN, SiO, etc.
  • a second wiring layer (420) is formed on the first interlayer insulating film (417).
  • the second wiring layer (420) a metal circuit wiring (421) and a metal reinforcing wiring pattern (422) are formed.
  • the second wiring layer (420) is formed of an organic polymer of a low dielectric constant material, MSQ, HSQ or a carbon-containing silicon oxide film. An etching stopper and a node mask are used. The laminated film strength with SiN, SiOC, SiC, SiCN, SiO, or the like can be configured.
  • a multilayer circuit structure is formed by alternately stacking the wiring layers and the interlayer insulating films.
  • the metal reinforcing via pattern (419) forms a multi-layer support structure by connecting the metal reinforcing wiring patterns (416, 422) of the first and second wiring layers (413, 420) to each other.
  • FIG. 46 is a plan view of the semiconductor device according to the example shown in FIG.
  • the metal reinforcing via patterns (419 ) are arranged so as to connect only the region (423) where the metal reinforcing wiring pattern (or dummy wiring) (416, 422) overlaps. For this reason, it is possible to introduce a metal reinforcing via pattern (or dummy via) (419) that does not change the dimensions and shape of the dummy pattern for CMP in which the conventional force is also formed, that is, does not increase the chip area. .
  • FIG. 47, FIG. 48 and FIG. 49 are plan views showing examples of the shape of the metal reinforcing via pattern (419) in the semiconductor device shown in FIG.
  • the length of the metal reinforcing via pattern (419) in the thickness direction of the semiconductor device is the length of the conductive metal via (418) formed in the same layer in the thickness direction of the semiconductor device. It is set larger than.
  • the metal reinforcing via pattern (419) is, for example, as shown in FIG.
  • It can be formed as a cylindrical via (424) having a larger diameter than (418). In this case, one or more cylindrical vias (424) can be formed.
  • the metal reinforcing via pattern (419) can be formed as a slit-shaped via or a via (425) having a rectangular cross section. In this case, one or more rectangular vias (425) can be formed.
  • the metal reinforcing via patterns (419) are such that the metal reinforcing wiring patterns (416, 422) in the first and second wiring layers (413, 420) overlap each other. It is also possible to form a via (426) that is formed entirely in the region.
  • the etching speed at the time of via etching in the metal reinforcing via pattern (419) can be reduced. Since the etching rate of the via (418) is higher than that of the via (418), as shown in FIG. In this case, the conductive metal via (418) eats more than the amount of food.
  • the conductive metal via (418) and the metal reinforcement via pattern (419) have the same dimensions.
  • CMP chemical mechanical polishing
  • a conductive metal via (418) using a single damascene process of separately forming a conductive metal via (418) and a conductive metal wiring (421) is used.
  • the conductive metal wiring (421) can be formed at the same time.
  • FIG. 50 is a cross-sectional view of another example of the semiconductor device according to the second embodiment of the present invention.
  • the semiconductor device according to the present embodiment will be described with reference to FIG.
  • the semiconductor device includes a semiconductor substrate (511), a transistor (5221) formed on the semiconductor substrate (511), and a transistor (5221).
  • the semiconductor substrate (511) is a single crystal silicon substrate.
  • the insulating film (512) is made of borophosphosilicate 'glass (8-30: 1) 01: 0 1105 110511ate glass), phosphosilicate' glass (PSG: phosphosilicate glass), silicon oxide silicon (SiO 2), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxyfluoride (SiOF),
  • Insulating materials such as silicon carbide (SiC) and silicon carbonitride (SiCN), or a combination thereof It is composed of
  • the first wiring layer (513) is formed on the insulating film (512).
  • the first wiring layer (513) is made of an organic polymer of low dielectric constant material, MSQ, HSQ, or a silicon-containing silicon oxide film. Etching stopper and SiN, SiOC forming a node mask are used. , SiC, SiCN, SiO and the like can also be formed.
  • the first wiring layer (513) includes a metal circuit wiring (or a conductive metal wiring) (515) for electrically connecting the circuit and a metal reinforcing wiring pattern having no electrical connection to the circuit. (516) are formed.
  • a first interlayer insulating film (517) is formed on the first wiring layer (513).
  • conductive metal vias (524) for electrically connecting the upper and lower metal circuit wirings (515, 519) to each other, and upper and lower metal reinforcing wiring patterns (515) are provided.
  • the first interlayer insulating film (517) is made of an organic polymer of a low dielectric constant material, MSQ, HSQ, or a silicon-containing silicon oxide film. It can also be composed of a laminated film of SiCN, SiO, etc.
  • a second wiring layer (518) is formed on the first interlayer insulating film (517).
  • a metal circuit wiring (519) and a metal reinforcing wiring pattern (520) are formed.
  • the second wiring layer (518) is made of an organic polymer of a low dielectric constant material, MSQ, HSQ or a silicon-containing silicon oxide film. , SiC, SiCN, SiO and the like can also be formed.
  • a multilayer circuit structure is formed by alternately stacking the wiring layers and the interlayer insulating films.
  • a metal bonding pad (521) for transmitting and receiving electric signals to and from the outside of the chip is formed on the multilayer circuit structure.
  • the metal bonding pad (521) is electrically connected to the metal circuit wiring (519) formed on the uppermost second wiring layer (518).
  • the length of the metal reinforcing via pattern (525) in the thickness direction of the semiconductor device is set to be longer than the length of the conductive metal via (524) formed in the same layer in the same direction. .
  • FIG. 51 is a plan view of the semiconductor device according to the example shown in FIG.
  • the metal reinforcing via pattern (525) is connected to the metal bonding pad (521).
  • the metal reinforcing wiring patterns (516, 520) existing under () are formed so as to connect the mutually overlapping regions. For this reason, it is possible to increase the strength against wire bonding without causing an electrical influence on wirings and vias forming a circuit and an increase in chip area.
  • FIGS. 52, 53 and 54 are plan views showing examples of the shape of the metal reinforcing via pattern (525) in the semiconductor device shown in FIG.
  • the length of the metal reinforcing via pattern (525) in the thickness direction of the semiconductor device is equal to the length of the conductive metal via (524) formed in the same layer in the thickness direction of the semiconductor device. It is set larger than.
  • the metal reinforcing via pattern (525) is, for example, as shown in FIG.
  • the diameter is larger than (524) and can be formed as a cylindrical via (528A). in this case
  • One or more cylindrical vias (528A) can be formed.
  • the metal reinforcing via pattern (525) can be formed as a slit-shaped via or a via (528B) having a rectangular cross section.
  • 8B can form one or a plurality.
  • the metal reinforcing via pattern (525) is formed in an area where the metal reinforcing wiring patterns (516, 520) in the first and second wiring layers (513, 518) overlap each other. It is also possible to form as a via (528C) formed in all.
  • the dimensions are larger than the conductive metal vias (524)! / ),
  • the etching speed at the time of via etching in the metal reinforcing via pattern (525) becomes faster than the etching speed of the conductive metal via (524), and as shown in FIG.
  • the amount of penetration of the metal reinforcing via pattern (525) with respect to the wiring pattern (516) becomes larger than the amount of penetration of the conductive metal via (524) with respect to the metal circuit wiring (515).
  • the conductive metal via (524) and the metal reinforcement via pattern (525) have the same dimensions. It is possible to further improve the adhesion with the metal strength wiring pattern (516) of the lower layer and the strength of the interlayer insulating film (517) as compared with the case, and this is caused by the impact stress applied during wire bonding. It is possible to prevent film peeling and film destruction.
  • a transistor (5211) forming a circuit area below the metal bonding pad (521), a multilayer circuit including metal circuit wirings (515, 519) and conductive metal vias (524)
  • the region below the metal bonding pad (521) includes one of the transistor (5211) and one of the metal circuit wiring and the conductive metal via forming the multilayer circuit structure. Only one is arranged.
  • neither the transistor (5211) nor the multilayer circuit structure is disposed in the region below the metal bonding pad (521), and the region below the metal bonding pad (521) is provided with a metal reinforcing wiring pattern ( 516, 520) and a metal supporting via pattern (525) alone.
  • FIG. 55 is a cross-sectional view of a high-spec LSI to which the above embodiment is applied.
  • the global wiring layer (531) includes a via interlayer insulating film (530), which is an insulating film having a higher dielectric constant and film strength than the low dielectric constant material constituting the multilayer local wiring layer (528), and a via interlayer insulating film.
  • the wiring layer (529) formed of an insulating film having a higher dielectric constant and a higher film strength than the low dielectric constant material forming the multilayer local wiring layer (528) is formed above the film (530).
  • a metal bonding pad (532) for transmitting and receiving electric signals to and from the outside of the chip is arranged.
  • the wiring layer (529) and the via interlayer insulating film (530) are each made of SiO
  • the metal wiring via pattern does not exist in the global wiring layer (531), and only in the region below the metal bonding pad (532), the local wiring layer (528) made of a low dielectric constant interlayer film is formed.
  • a metal reinforcing via pattern (533) for connecting the metal reinforcing wiring patterns adjacent to each other in the vertical direction is formed.
  • the length of the metal reinforcing via pattern (533) in the thickness direction of the present semiconductor device is set to be longer than the length of the conductive metal via (524) in the same layer in the thickness direction of the present semiconductor device. I have.
  • the global wiring layer (531) has high film strength and adhesion of the wiring layer (529) and the via interlayer insulating film (530) due to the bonding shock. Alternatively, it is possible to withstand stress.
  • the presence of the metal reinforcing via pattern (533) in the local wiring layer (528) makes it possible to increase the strength and adhesion of the interlayer insulating film, resulting in impact and stress during bonding. It is possible to prevent film peeling and film destruction.
  • FIG. 56 is a sectional view of another example of the semiconductor device according to the second embodiment of the present invention.
  • the semiconductor device according to the present embodiment will be described with reference to FIG.
  • the semiconductor device includes a semiconductor substrate (611) and a semiconductor
  • the semiconductor device includes a transistor (6221) formed on a substrate (611) and an insulating film (612) formed on a semiconductor substrate (611) so as to cover the transistor (6221).
  • the semiconductor substrate (611) is a single crystal silicon substrate.
  • the insulating film (612) is made of borophosphosilicate 'glass (8-30: 1) 01: 0 1105 110511ate glass), phosphosilicate glass (PSG: phosphosilicate glass), silicon oxide silicon (SiO 2), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxyfluoride (SiOF),
  • SiC silicon carbide
  • SiCN silicon carbonitride
  • a first wiring layer (613) is formed on the insulating film (612).
  • the first wiring layer (613) is made of an organic polymer of a low dielectric constant material, MSQ
  • HSQ a carbon-containing silicon oxide film.
  • a stacked film strength with SiN, SiOC, SiC, SiCN, SiO, etc. forming an etching stopper and a node mask can also be formed.
  • the first wiring layer (613) includes a metal circuit wiring (or a conductive metal wiring) (615) for electrically connecting a circuit and a metal reinforcing wiring pattern having no electrical connection to the circuit. (616) is formed.
  • a first interlayer insulating film (617) is formed on the first wiring layer (613.
  • conductive metal vias (624) for electrically connecting the upper and lower metal circuit wirings (615, 619) to each other, and upper and lower metal reinforcing wiring patterns ( 616, 620) are formed.
  • the first interlayer insulating film (617) is made of an organic polymer of a low dielectric constant material, MSQ, HSQ or SiC forming a force etching stopper and a node mask, which is a carbon-containing silicon oxide film. It can also be composed of a laminated film of SiCN, SiO, etc.
  • a second wiring layer (618) is formed on the first interlayer insulating film (617).
  • a metal circuit wiring (619) and a metal reinforcing wiring pattern (620) are formed.
  • the second wiring layer (618) is made of an organic polymer of low dielectric constant material, MSQ, HSQ, or a silicon-containing silicon-containing film. Etching stopper and SiN, SiOC forming a node mask. , SiC, SiCN, SiO, etc. can also be configured. [0358] As described above, a multilayer circuit structure is formed by alternately laminating the wiring layers and the interlayer insulating films.
  • a metal bonding pad (621) for transmitting and receiving an electric signal to and from the outside of the chip is formed.
  • the metal bonding pad (621) is electrically connected to the metal circuit wiring (619) formed on the uppermost second wiring layer (618).
  • the impact or stress at the time of wire bonding may also diffuse to a region outside the metal bonding pad (621), which can be seen only below the metal bonding pad (621). For this reason, in the present embodiment, as shown in FIG. 57, which is formed only in the region below the metal bonding pad (621), the upper and lower portions existing within a certain distance (6231) from the outer edge of the metal bonding pad (621) are formed. A metal reinforcing via pattern (625) connecting regions where the metal reinforcing wiring patterns (616, 620) adjacent to each other overlap each other is formed.
  • the length of the metal reinforcing via pattern (625) in the thickness direction of the present semiconductor device is set to be larger than the length of the conductive metal via (624) of the same layer in the thickness direction of the present semiconductor device. I have.
  • the fixed distance (6231) from the outer edge of the metal bonding pad (621) changes according to the strength and adhesion of the low dielectric constant material. It may be necessary to form a metal reinforced via pattern (625) over the entire chip.
  • a multilayer support structure in a semiconductor device using a low dielectric constant film as an interlayer insulating film, a multilayer support structure must exist within a range of about 10 ⁇ m from the outer edge of the metal bonding pad. Thus, it was shown that the strength for wire bonding can be considerably increased as compared with the case where the multilayer support structure exists only in the region below the metal bonding pad.
  • FIG. 57 is a plan view of the semiconductor device shown in FIG.
  • the lower metal reinforcing wiring pattern located below the metal bonding pad (621) and within a certain distance (6231) from the outer edge of the metal bonding pad (621). Even if there is a metal reinforcing via pattern (625) that connects between the metal reinforcing wires (616, 620), the metal only in the area (626) where the vertically adjacent metal reinforcing wiring patterns (616, 620) overlap each other. The presence of the reinforcing via pattern (625) makes it possible to increase the strength against wire bonding without causing an electrical influence on the wiring forming the circuit or the conductive metal via or an increase in the chip area.
  • FIG. 58, FIG. 59 and FIG. 60 are plan views showing examples of the shape of the metal reinforcing via pattern (625) in the semiconductor device shown in FIG.
  • the length of the metal reinforcing via pattern (625) in the thickness direction of the semiconductor device is equal to the length of the conductive metal via (624) formed in the same layer in the thickness direction of the semiconductor device. It is set larger than.
  • the metal reinforcing via pattern (625) is, for example, as shown in FIG.
  • the metal reinforcing via pattern (625) can be formed as a slit-shaped via or a via (629) having a rectangular cross section. In this case, one or more rectangular vias (629) can be formed.
  • the metal reinforcing via pattern (625) is formed in an area where the metal reinforcing wiring patterns (616, 620) in the first and second wiring layers (613, 618) overlap each other. All of them can be formed as a via (630).
  • the etching speed at the time of via etching in the metal reinforcing via pattern (625) becomes conductive. Since the etching speed of the metal via (624) is faster than that of the metal circuit wiring (615) as shown in FIG. ) Of the conductive metal via (624) with respect to).
  • the conductive metal via (624) and the metal reinforcement via pattern (625) have the same dimensions. Furthermore, the adhesion to the lower metal strength wiring pattern (616) and the interlayer insulation film (61 It is possible to improve the strength of 7), and it is possible to prevent film peeling and film destruction due to impact and stress during wire bonding.
  • the metal reinforcing via pattern (625) is formed within a certain distance (6231) from the outer edge of the metal bonding pad (621), and By making the length of the metal reinforcing via pattern (625) longer than the length of the conductive metal via (624), the adhesion to the underlying metal reinforcing wiring pattern (616) and the strength of the interlayer insulating film (617) are increased. This makes it possible to prevent film peeling and film destruction caused by impact and stress during wire bonding.
  • a transistor (6221) forming a circuit area below the metal bonding pad (621) and a multilayer circuit including metal circuit wirings (615, 619) and conductive metal vias (624)
  • the region below the metal bonding pad (621) includes one of the transistor (6221) and one of the metal circuit wiring and the conductive metal via constituting the multilayer circuit structure. Only one is arranged.
  • neither the transistor (6221) nor the multilayer circuit structure is arranged in the area below the metal bonding pad (621), and the area below the metal bonding pad (621) is provided with a metal reinforcing wiring pattern ( 616, 620) and the metal reinforcing via pattern (625), and only a multi-layered support structure that is powerful.
  • FIG. 61 is a cross-sectional view of a high-spec LSI to which the above embodiment is applied.
  • the global wiring layer (634) includes a via interlayer insulating film (633), which is an insulating film having a higher dielectric constant and film strength than the low dielectric constant material forming the multilayer local wiring layer (631), and a via interlayer insulating film.
  • the wiring layer (632) formed of an insulating film having a higher dielectric constant and a higher film strength than the low dielectric constant material forming the multilayer local wiring layer (631) is formed above the film (633).
  • a metal bonding pad (635) for transmitting and receiving an electric signal to and from the outside of the chip is arranged above the multi-layer wiring which serves as the local wiring (638) and the global wiring (639).
  • the wiring layer (632) and the via interlayer insulating film (633) are each made of SiO 2.
  • metal reinforcing via pattern in the global wiring layer (634), and a certain distance (6331) from the area below the metal bonding pad (635) and the outer edge of the metal bonding pad (635).
  • Metal reinforcing via patterns (636) connecting between vertically adjacent metal reinforcing wiring patterns in the local wiring layer (631) made of a low dielectric constant interlayer film are formed in the region in parentheses. .
  • the length of the metal reinforcing via pattern (636) in the thickness direction of the present semiconductor device is set to be longer than the length of the conductive metal via (637) in the same layer in the thickness direction of the present semiconductor device. I have.
  • the global wiring layer (634) has a high film strength and adhesion of the wiring layer (632) and the via interlayer insulating film (633) against the shock at the time of bonding. Alternatively, it is possible to withstand stress.
  • the presence of the metal reinforcing via pattern (636) in the local wiring layer (631) makes it possible to increase the strength and adhesion of the interlayer insulating film, resulting in the impact and stress during bonding. It is possible to prevent film peeling and film destruction.
  • the semiconductor device according to this example was formed in the same manner as the semiconductor device according to Example 1.
  • an insulating film (112) formed on a semiconductor substrate (111) is formed, and further, an insulating film (112) is formed.
  • a first wiring layer (113) is formed on (112).
  • the first wiring layer (113) includes a metal circuit wiring (or conductive metal wiring) (115) for electrically connecting the circuit and a metal reinforcing wiring pattern having no electrical connection to the circuit. (116 ) Is formed.
  • a first interlayer insulating film (117) is formed on the first wiring layer (113).
  • a conductive metal via (118) for electrically connecting the upper and lower metal circuit wirings (115, 121) to each other, and an upper and lower metal reinforcing wiring pattern are provided.
  • a metal reinforcing via pattern (119) to be connected is formed.
  • a second wiring layer (120) is formed on the first interlayer insulating film (117).
  • a metal circuit wiring (121) and a metal reinforcing wiring pattern (122) are formed in the second wiring layer (120).
  • a multilayer circuit structure is formed by alternately stacking the wiring layers and the interlayer insulating films.
  • the metal reinforced via pattern (119) forms a multilayer support structure by connecting the metal reinforced wiring patterns (116, 122) of the first and second wiring layers (113, 120) to each other.
  • the ratio of the total area of the vias per unit area of the semiconductor device that is, the area of the conductive metal via (118) and the metal reinforcement
  • the ratio of the sum of the area of the via pattern (119) and the unit area of the semiconductor device was varied.
  • FIG. 62 shows vias per unit area of a semiconductor device using a low dielectric constant film as an interlayer insulating film.
  • the optical defect monitor monitors the ratio of the total area of the (conductive metal via and metal reinforcing via pattern) and the number of defects that occur due to peeling of the interlayer insulating film when Cu-CMP is performed under a load of 2 psi. It is a graph which shows the relationship with the number measured with the apparatus.
  • the semiconductor device according to this example was formed in the same manner as the semiconductor device according to Example 2. As in the case of the semiconductor device shown in FIG. 33, in forming the semiconductor device according to this example, first, an insulating film (212) is formed on a semiconductor substrate (211) on which a transistor (2211) is formed. Then, a first wiring layer (213) was formed on the insulating film (212).
  • the first wiring layer (213) includes a metal circuit wiring (or a conductive metal wiring) (215) for electrically connecting a circuit and a metal dummy wiring (215) having no electrical connection to the circuit. 216) is formed.
  • a first interlayer insulating film (217) is formed on the first wiring layer (213).
  • conductive metal vias (224) for electrically connecting the upper and lower metal circuit wirings (223, 219) to each other, and upper and lower metal reinforcing wiring patterns are provided.
  • a metal reinforcing via pattern (225) to be connected is formed.
  • a second wiring layer (218) is formed on the first interlayer insulating film (217).
  • a metal circuit wiring (219) and a metal reinforcing wiring pattern (220) are formed.
  • a multilayer circuit structure is formed by alternately stacking the wiring layers and the interlayer insulating films.
  • a metal bonding pad (221) for transmitting and receiving electric signals to and from the outside of the chip is formed.
  • the metal bonding pad (221) is electrically connected to the metal circuit wiring (219) formed on the uppermost second wiring layer (218).
  • the metal reinforcing via patterns (216, 220) connecting the areas where the upper and lower metal reinforcing wiring patterns (216, 220) overlap each other are formed only in the area below the metal bonding pad (221). 225) exists.
  • FIG. 63 shows the ratio of the total area of vias (conductive metal vias and metal reinforcing via patterns) to the unit area of the region below the metal bonding pad of a semiconductor device using a low dielectric constant film as an interlayer insulating film.
  • 4 is a graph showing the relationship between the adhesion hardness between a metal bonding pad and a bonding wire measured by a ball shear method.
  • FIGS. 64 and 65 are cross-sectional views of another example of the semiconductor device according to the third embodiment of the present invention.
  • the semiconductor device according to the present example includes a semiconductor substrate (711), a transistor (7221) formed on the semiconductor substrate (711), and a transistor (7221). And an insulating film (712) formed on the semiconductor substrate (711).
  • the semiconductor substrate (711) in this embodiment also has a single crystal silicon substrate strength.
  • the insulating film (712) is made of borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), phosphosilicate glass (PSG), silicon dioxide (SiO 2), silicon nitride (SiN ), Silicon oxynitride (SiON), silicon oxyfluoride (SiOF),
  • SiC silicon carbide
  • SiCN silicon carbonitride
  • the first wiring layer (713) is formed on the insulating film (712).
  • the first wiring layer (713) is made of an organic polymer of low dielectric constant material, MSQ
  • HSQ a carbon-containing silicon oxide film.
  • a stacked film strength with SiN, SiOC, SiC, SiCN, SiO, etc. forming an etching stopper and a node mask can also be formed.
  • a metal circuit wiring (715) for electrically connecting circuits, and a circuit Has no electrical connection a metal reinforced wiring pattern (716) is formed!
  • a first interlayer insulating film (717) is formed on the first wiring layer (713.
  • the first interlayer insulating film (717) is electrically connected to conductive metal wirings (715, 719) provided in the first and second wiring layers (713, 718), respectively. And a metal reinforcing via pattern (726) interconnecting the metal reinforcing wiring patterns (716, 720) provided in the first and second wiring layers (713, 718), respectively. Are formed.
  • the first interlayer insulating film (717) is an organic polymer of a low dielectric constant material, MSQ, HSQ or a silicon-containing film containing carbon. It can also be composed of a laminated film of SiCN, SiO, etc.
  • a second wiring layer (718) is formed on the first interlayer insulating film (717.
  • a metal circuit wiring (719) and a metal reinforcing wiring pattern (720) are formed.
  • the second wiring layer (718) is made of an organic polymer of low dielectric constant material, MSQ, HSQ or a silicon-containing film containing carbon.
  • the etching stopper and the SiN, SiOC forming the node mask are used. , SiC, SiCN, SiO and the like can also be formed.
  • a second interlayer insulating film (721) is formed on the second wiring layer (718).
  • the second interlayer insulating film (721) has the same material strength as the first interlayer insulating film (717).
  • a third wiring layer (722) is formed on the second interlayer insulating film (721).
  • the third wiring layer (722) is formed of the same material as the second wiring layer (718).
  • a multilayer circuit structure is formed by alternately stacking the wiring layers and the interlayer insulating films.
  • a metal bonding pad (723) for transmitting and receiving an electric signal to and from the outside of the chip is formed.
  • the metal bonding pad (723) is electrically connected to the metal circuit wiring (724) formed on the uppermost third wiring layer (722).
  • the transistor (7221) and the metal circuit wiring (7 15, 719), metal conductive metal vias (725) are present.
  • the metal circuits stacked in the thickness direction of the semiconductor device below the metal bonding pad (723) in the circuit region (1200) Wirings (724, 719, 715), conductive metal vias (727, 725), and a multilayer circuit structure are formed by force.
  • the force also forms a multilayer support structure.
  • the multilayer support structure is present in a gap in a circuit area where the multilayer circuit structure is formed. That is, the multilayer support structure is formed in a region where the multilayer circuit structure does not exist so as not to conflict with the multilayer circuit structure inside the circuit region (1200) where the multilayer circuit structure is formed.
  • the semiconductor device is stacked in the thickness direction.
  • Metal supporting wiring patterns (729, 720, 716) and metal reinforcing via patterns (728, 726) interconnecting them form a multilayer support structure.
  • the multilayer support structure including the metal reinforcing wiring patterns (716, 720, 729) and the metal reinforcing via patterns (726, 728) formed in the scribe area (1300) is shown in Figs. As shown in FIG. 28 and FIG. 28, the scribe area (1300) is uniformly distributed over the entire area, and is also formed in the four corners of the semiconductor chip, that is, in the area below the cross mark X. .
  • the planar arrangement of the multilayer support structure is not limited to the above example.
  • the multilayer support structure may be formed only in the region below the cross mark X or excluding the corners of the semiconductor chip. It can also be formed only in the region along the peripheral edge.
  • the semiconductor device according to the embodiment shown in FIG. 65 is different from the semiconductor device according to the embodiment shown in FIG. 64 in that the outer peripheral edge of the chip is located at a position closer to the position where the metal bonding pad (723) is formed.
  • the difference lies in that a shield (730) is formed between the circuit region on the side, that is, the outside of the metal bonding pad (723) and the scribe region (1300).
  • the shield (730) also has a laminated body strength in which the metal reinforcing wiring pattern and the metal reinforcing via pattern are stacked. That is, the shield (730) has the same structure as the multilayer support structure.
  • the shield (730) is arranged continuously over the entire periphery along the outer peripheral edge of the semiconductor chip. Therefore, it is possible to effectively prevent moisture from entering the circuit region (1200) from outside the semiconductor device.
  • the shield (730) is also a multi-layered support structure that also acts as a metal reinforcing wiring pattern and a metal reinforcing via pattern, a layer is formed between the outside of the metal bonding pad (723) and the scribe area (1300). It also exerts the effect of increasing the adhesion between the layers constituting the body.
  • both the circuit region (1200) (including the region below the metal bonding pad (723)) and the scribe region Similarly to (1300), a multi-layer support structure composed of metal reinforcing wiring patterns (716, 720, 729) and metal reinforcing via patterns (726, 728) is formed.
  • the strength and adhesion of the LSI can be increased, so that it can be used during a chemical mechanical polishing (CMP) process or chip packaging.
  • CMP chemical mechanical polishing
  • Film peeling and film destruction can be prevented by the applied impact and stress.
  • a multilayer support structure is formed in the circuit region (12000) (including the region below the metal bonding pad (723)). It is not necessary!
  • the transistor (7221) and one of the metal circuit wiring and the conductive metal via forming the multilayer circuit structure are arranged. Is also good.
  • neither the transistor (7221) nor the multilayer circuit structure is arranged in the region below the metal bonding pad (723), and the region below the metal bonding pad (723) is formed in the metal reinforcing wiring pattern. Only a multi-layer support structure consisting of (716, 720, 729) and metal reinforcing via patterns (726, 728) may be arranged.
  • a single damascene process for separately forming a conductive metal via and a conductive metal wiring is used. It is also possible to use a dual damascene process for simultaneously forming conductive metal vias and conductive metal wiring.
  • FIG. 1 is a cross-sectional view of a conventional semiconductor device.
  • FIG. 2 is a diagram showing pad peeling during bonding in a conventional semiconductor device.
  • FIG. 3 is a cross-sectional view showing one example of a conventional bonding pad structure.
  • FIG. 4 is a schematic sectional view showing one embodiment of the semiconductor device according to the first aspect of the present invention.
  • FIG. 5 is a schematic sectional view showing another embodiment of the semiconductor device according to the first aspect of the present invention.
  • FIG. 6 is a schematic sectional view showing another embodiment of the semiconductor device according to the first aspect of the present invention.
  • FIG. 7 is a schematic sectional view showing another embodiment of the semiconductor device according to the first aspect of the present invention.
  • FIG. 8 is a schematic sectional view showing another embodiment of the semiconductor device according to the first aspect of the present invention.
  • FIG. 9 is a circuit diagram showing an equivalent circuit of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 10 is a cross-sectional view showing one manufacturing step in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 11 is a cross-sectional view showing one manufacturing step in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 12 is a cross-sectional view showing one manufacturing step in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 13 is a cross-sectional view showing one manufacturing step in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 14 is a cross-sectional view showing one manufacturing step in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 15 is a cross-sectional view showing one manufacturing step in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 16 is a cross-sectional view showing one manufacturing step in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 17 is a cross-sectional view showing one manufacturing step in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 18 is a cross-sectional view showing one manufacturing step in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 19 is a cross-sectional view showing one manufacturing step in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 20 is a schematic cross-sectional view showing one embodiment of a semiconductor device according to a second aspect of the present invention.
  • FIG. 21 is a plan view schematically showing an example of a region where a multilayer support structure exists in a semiconductor device according to a second embodiment of the present invention.
  • FIG. 22 is a plan view schematically showing an example of a region where a multilayer support structure exists in a semiconductor device according to a second embodiment of the present invention.
  • FIG. 23 is a schematic sectional view showing one embodiment of a semiconductor device according to a third aspect of the present invention.
  • FIG. 24 is a plan view schematically showing a positional relationship between a circuit region and a scribe region in a semiconductor device according to a third embodiment of the present invention.
  • 25 is an enlarged plan view of a region B shown in FIG. 24.
  • FIG. 26 is a plan view showing the shape of a cross mark provided at a corner of a semiconductor chip.
  • FIG. 27 is a schematic sectional view showing another embodiment of the semiconductor device according to the third aspect of the present invention.
  • FIG. 28 is a plan view schematically showing a positional relationship between a circuit region and a scribe region in the semiconductor device shown in FIG. 27.
  • FIG. 29 is an enlarged plan view of a region E shown in FIG. 28.
  • FIG. 30 is a cross-sectional view of one example of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 31 is a plan view of the semiconductor device according to the embodiment shown in FIG. 30.
  • the area occupation ratio of the metal reinforcing via pattern (the ratio of the area of the metal reinforcing via pattern to the unit area of the semiconductor device)
  • 6 is a graph showing a relationship with a rate of film peeling during CMP.
  • FIG. 33 is a sectional view of an example of a semiconductor device according to a second embodiment of the present invention.
  • FIG. 34 is a plan view of the semiconductor device according to the embodiment shown in FIG. 33.
  • FIG. 36 is a cross-sectional view of a high-spec LSI to which an example of the semiconductor device according to the second embodiment of the present invention is applied.
  • FIG. 37 is a sectional view of a first modification of the embodiment shown in FIG. 36.
  • FIG. 38 is a sectional view of a second modification of the embodiment shown in FIG. 36.
  • FIG. 39 is a plan view showing an example of the shape of a large-area wiring layer pad in the semiconductor device shown in FIGS. 37 and 38.
  • FIG. 40 is a plan view showing an example of the shape of a large-area wiring layer pad in the semiconductor device shown in FIGS. 37 and 38.
  • FIG. 41 is a cross-sectional view of another example of the semiconductor device according to the second embodiment of the present invention.
  • ⁇ 42] A graph showing the relationship between the distance from the outer edge of the metal bonding pad in the region where the multilayer support structure exists and the adhesion strength of the bonding portion measured by the ball shear method.
  • FIG. 43 is a plan view of the semiconductor device shown in FIG. 41.
  • FIG. 44 is a sectional view of a noise-spec LSI to which the embodiment shown in FIG. 41 is applied.
  • FIG. 45 is a cross-sectional view of another example of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 46 is a plan view of the semiconductor device according to the embodiment shown in FIG. 45.
  • FIG. 47 is a plan view showing an example of the shape of a metal reinforcing via pattern in the semiconductor device shown in FIG. 45.
  • FIG. 48 is a plan view showing an example of the shape of a metal reinforcing via pattern in the semiconductor device shown in FIG. 45.
  • FIG. 45 is a plan view showing an example of the shape of a metal reinforcing via pattern in the semiconductor device shown in FIG. 45.
  • FIG. 50 is a cross-sectional view of another example of the semiconductor device according to the second embodiment of the present invention.
  • FIG. 51 is a plan view of the semiconductor device according to the embodiment shown in FIG. 50.
  • FIG. 52 is a plan view showing an example of the shape of the metal reinforcing via pattern in the semiconductor device shown in FIG. 50.
  • FIG. 53 is a plan view showing an example of the shape of a metal reinforcing via pattern in the semiconductor device shown in FIG. 50.
  • FIG. 54 is a plan view showing an example of the shape of a metal reinforcing via pattern in the semiconductor device shown in FIG. 50.
  • FIG. 55 is a cross-sectional view of a Nos. Ispec LSI to which the embodiment shown in FIG. 50 is applied.
  • FIG. 56 is a cross-sectional view of another example of the semiconductor device according to the second embodiment of the present invention.
  • FIG. 57 is a plan view of the semiconductor device shown in FIG. 56.
  • FIG. 58 is a plan view showing an example of the shape of a metal reinforcing via pattern in the semiconductor device shown in FIG. 56.
  • FIG. 59 is a plan view showing an example of the shape of the metal reinforcing via pattern in the semiconductor device shown in FIG. 56.
  • [60] shows an example of the shape of a metal reinforcing via pattern in the semiconductor device shown in FIG. FIG.
  • FIG. 61 is a cross-sectional view of a noise-spec LSI to which the embodiment shown in FIG. 56 is applied.
  • Cu-CMP is performed with the ratio of the total area of vias (conductive metal vias and metal reinforcing via patterns) to the unit area of a semiconductor device using a low dielectric constant film as an interlayer insulating film, and a load of 2 psi.
  • 4 is a graph showing a relationship between the number of defects generated due to peeling of an interlayer insulating film and the number measured by an optical defect monitoring device when the optical insulating film is removed.
  • the ratio of the total area of the vias (conductive metal vias and metal reinforcing via patterns) to the unit area of the area under the metal bonding pad of the semiconductor device using the low dielectric constant film as the interlayer insulating film, and the ball share 6 is a graph showing the relationship between the adhesion hardness between a metal bonding pad and a bonding wire measured by a method.
  • FIG. 64 is a cross-sectional view of another example of the semiconductor device according to the third embodiment of the present invention.
  • FIG. 65 is a cross-sectional view of another example of the semiconductor device according to the third embodiment of the present invention.
  • Second wiring layer 720 Metal reinforced wiring pattern

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Abstract

In a semiconductor device using a low dielectric constant interlayer insulating film having low film strength and adhesion, film separation and film breakage during processing or packaging are suppressed by enhancing structural strength without affecting the chip area or arrangement of circuits. Conventionally, reinforcing wiring patterns (wiring dummy patterns) have been formed only in wiring layers. In the present invention, many reinforcing via patterns which are not electrically connected with the circuits are formed in a region of the interlayer insulating film where the reinforcing wiring patterns formed in the wiring layers on both sides overlap, thereby connecting the reinforcing wiring patterns with each other.

Description

半導体装置及びその製造方法  Semiconductor device and manufacturing method thereof
技術分野  Technical field
[0001] 本発明は、半導体装置、特に、低誘電率膜を配線層間膜として有する半導体装置 及びその製造方法に関する。  The present invention relates to a semiconductor device, particularly to a semiconductor device having a low dielectric constant film as a wiring interlayer film, and a method of manufacturing the same.
背景技術  Background art
[0002] 近年、ロジック LSIの高速ィ匕が求められている。半導体装置の動作速度を決定する 要因はトランジスタにおけるスイッチング遅延と配線における伝搬遅延とに大きく分け られる。ロジック LSIはメモリに比べて配線面積が全体に占める割合が大きいため、口 ジック LSIを高速ィ匕するためには、配線における伝搬遅延を低減する必要がある。  In recent years, there has been a demand for high-speed logic LSIs. Factors that determine the operation speed of a semiconductor device can be broadly divided into switching delay in a transistor and propagation delay in a wiring. Since a logic LSI has a larger wiring area than a memory in a whole area, it is necessary to reduce a propagation delay in a wiring in order to perform a high speed operation of a logic LSI.
[0003] 配線における伝搬遅延は配線抵抗と配線層間容量との積に比例するので、配線材 料に抵抗率の低 ヽ材料を、配線層間膜材料に比誘電率の低 、材料を用いること〖こ より、配線における伝搬遅延を低減することが可能である。  [0003] Since the propagation delay in wiring is proportional to the product of the wiring resistance and the capacitance between wirings, a material having a low resistivity is used for the wiring material, and a material having a low dielectric constant is used for the wiring interlayer film. This makes it possible to reduce the propagation delay in the wiring.
[0004] そこで、次世代配線材料として、従来のアルミニウム (A1)あるいは A1合金よりも比抵 抗の小さ 、銅 (Cu)ある 、は Cu合金が検討されて 、る。  [0004] Therefore, as a next-generation wiring material, copper (Cu) or copper alloy having a lower specific resistance than conventional aluminum (A1) or A1 alloy has been studied.
[0005] Cuあるいは Cu合金を配線材料に用いた Cu配線は、一般的には、ダマシン (dama scene)法により、形成される。一般的に、ダマシン法は、配線層間膜を堆積後に、そ の表面側から反応性イオンエッチング (Reactive Ion Etching :RIE)法などにより 溝を形成する過程と、その溝を埋め込むように Cuあるいは Cu合金膜を堆積する過 程と、溝に埋め込まれた Cuあるいは Cu合金膜以外の Cuあるいは Cu合金膜をィ匕学 機械研磨（Chemical Mechanical Polishing : CMP)法等により除去し、配線層 間膜に埋め込まれた Cu配線を形成する過程と、を備えて!/ヽる。  [0005] Cu wiring using Cu or a Cu alloy as a wiring material is generally formed by a damascene (dama scene) method. Generally, in the damascene method, after a wiring interlayer film is deposited, a groove is formed from the surface side by a reactive ion etching (RIE) method, and Cu or Cu is filled so as to fill the groove. During the process of depositing the alloy film, the Cu or Cu alloy film other than the Cu or Cu alloy film embedded in the groove is removed by a chemical mechanical polishing (CMP) method or the like, and the film between the wiring layers is removed. And forming a buried Cu wiring!
[0006] ダマシン法を用いて Cu配線を形成する場合、 CMP時の配線の厚さのバラツキを 低減するために、配線層に CMP用ダミー配線パターンを形成する方法が用いられる ことが多い。  When a Cu wiring is formed by using the damascene method, a method of forming a dummy wiring pattern for CMP in a wiring layer is often used in order to reduce variation in the thickness of the wiring at the time of CMP.
[0007] 図 1は、 CMP用ダミー配線パターンを用いる方法の一例を示す。  FIG. 1 shows an example of a method using a dummy wiring pattern for CMP.
[0008] 図 1に示す電気的な回路は、配線層 (2002)と絶縁層 (2003)とが交互に堆積して 形成されており、各配線層 (2002)には金属回路配線（2000)が形成され、絶縁層 ( 2003)には金属ビア（2004)が形成されている。各配線層 (2002)に形成されている 金属回路配線（2000)は金属ビア（2004)を介して電気的に相互に接続されている [0008] In the electrical circuit shown in Fig. 1, the wiring layer (2002) and the insulating layer (2003) are alternately deposited. A metal circuit wiring (2000) is formed in each wiring layer (2002), and a metal via (2004) is formed in the insulating layer (2003). Metal circuit wiring (2000) formed in each wiring layer (2002) is electrically connected to each other via metal via (2004).
[0009] また、各配線層 (2002)には、金属回路配線（2000)とは電気的に絶縁されている[0009] Each wiring layer (2002) is electrically insulated from the metal circuit wiring (2000).
CMP用ダミー配線パターン（2001)が形成されて!、る。 A dummy wiring pattern for CMP (2001) is formed!
[0010] また、配線層間膜の材料としては、従来の SiOよりも比誘電率が低い、有機物のみ [0010] In addition, as a material of the wiring interlayer film, only an organic substance having a lower relative dielectric constant than conventional SiO is used.
2  2
カゝら構成される材料や、従来の SiO膜に有機基を含有させた材料が検討されている  Materials composed of glass and materials containing organic groups in conventional SiO films are being studied.
2  2
[0011] しカゝしながら、これらの一般に低誘電率膜と呼ばれる材料カゝら配線層間膜を形成す ると、誘電率の低減と同時に、膜の強度も低下することが確認されている。さらに、低 誘電率膜からなる配線層間膜は、 SiO [0011] However, it has been confirmed that, when forming a wiring interlayer film using a material generally called a low dielectric constant film, the dielectric constant is reduced and the film strength is also reduced. . Furthermore, the wiring interlayer film made of a low dielectric constant film is made of SiO
2膜と比べて、他の膜との密着性が低いため、 配線層間膜に用いて多層配線を形成した場合、図 2の写真に示すように、ワイヤボン デイング時にボンディングパッド部の膜剥がれが発生するという問題があった。  Due to the lower adhesion to other films than the two films, when multilayer wiring is used as a wiring interlayer film, film peeling of the bonding pad occurs during wire bonding as shown in the photo in Figure 2. There was a problem of doing.
[0012] これらの課題を解決するために、特許文献 1は、ボンディングパッド下の強度を高め るため、図 3に示すように、ボンディングパッド（10001)下に存在するパッド下ダミー 配線（10002)及びパッド下ダミービア（10003)により、ボンディングパッド（10001) を直接的に支持する構造を提案して!/ヽる。 [0012] In order to solve these problems, Patent Document 1 discloses an under-pad dummy wiring (10002) under a bonding pad (10001) as shown in FIG. 3 in order to increase the strength under the bonding pad. We propose a structure to directly support the bonding pad (10001) with the dummy via (10003) under the pad and! / ヽ.
[0013] また、非特許文献 1にお 、ても、パッド下の構造にぉ ヽて、ダミーパッドとパッド下ダ ミービアとを接続させることにより、ワイヤボンディングを可能としている。 [0013] Also, in Non-Patent Document 1, wire bonding is enabled by connecting a dummy pad and a dummy via under a pad in connection with a structure under the pad.
特許文献 1：特開 2001— 267323  Patent Document 1: JP 2001-267323
非特許文献 1 :Y. L. Yang et al.、 IITC '03 Technical Digest, 2003 . 6. 2、 2. 4、 P3、 Fig. 12, 13  Non-patent Document 1: Y.L.Yang et al., IITC '03 Technical Digest, 2003.6.2, 2.4, P3, Fig. 12, 13
発明の開示  Disclosure of the invention
発明が解決しょうとする課題  Problems to be solved by the invention
[0014] 従来例のように、ノッド下ダミーパッドまたはパッド下ダミー配線とパッド下ダミービ ァとが接続された構造を形成した場合、以下のような多数の問題が考えられる。 [0014] When a structure in which a dummy pad under a nod or a dummy wiring under a pad and a dummy via under a pad are formed as in a conventional example, a number of problems as described below are conceivable.
[0015] まず、 LSIの強度を向上させるために、パッド下にのみダミー配線とダミービアとを 形成しても、必要な LSIの強度を得られな 、ことがある。 [0015] First, in order to improve the strength of the LSI, dummy wirings and dummy vias are formed only under the pads. Even if formed, the required LSI strength may not be obtained.
[0016] すなわち、ノッド下にのみダミー配線及びダミービアを形成した場合、プロセス中の Cu— CMP等の際に、パッド下以外の領域に存在する強度の低い低誘電率膜や低 誘電率膜界面において、膜剥がれが発生する可能性がある。たとえ、プロセス中に 膜剥がれが発生しなカゝつた場合においても、組立実装時の榭脂封入時における応 力により、密着性の低い部分や強度の低い低誘電率膜内において、膜剥がれが発 生する可能性がある。 [0016] That is, when the dummy wiring and the dummy via are formed only under the nod, during the Cu-CMP or the like during the process, the low-dielectric-constant film or the low-dielectric-constant film interface existing in the region other than under the pad is low. In this case, film peeling may occur. Even if film peeling does not occur during the process, film peeling may occur in parts with low adhesion or in low-dielectric-constant films with low strength due to stress during resin encapsulation during assembly and mounting. May occur.
[0017] 次に、 CMP等のプロセス時にパッド下以外の領域で膜剥がれが発生しな力つた場 合、または、榭脂封入時の樹脂の応力によってもパッド下以外の領域で膜剥がれが 発生しな力つた場合であっても、パッドの強度と生産性の効率の関係として、問題が 発生する可能性がある。  [0017] Next, when a force such that film peeling does not occur in a region other than under the pad during a process such as CMP, or film peeling occurs in a region other than under the pad due to the stress of the resin at the time of resin sealing. Even with low effort, problems can arise as a relationship between pad strength and productivity efficiency.
[0018] それは、パッド下にダミー配線及びダミービアを形成する場合、ノッド下に配置する ことが可能な配線及びビアの個数はパッド面積に応じて制限される。そのため、層間 絶縁膜である低誘電率膜の強度が非常に低 ヽ場合や、低誘電率膜とその上下の膜 との間の密着性が非常に低い場合には、パッド下に入れるダミー配線及びダミービア は膨大な数にならざるを得ない。この場合、ボンディングパッド下の領域のほとんどが ダミー配線及びダミービアに占有されてしまうため、ダミーではな!/ヽ回路を形成する 配線及びビアを配置することが不可能となり、結果的に、パッド下には回路を形成す ることができなくなる。そのため、チップ面積が増大して、一枚あたりのウエノ、から採取 できるチップの数が減少するため、生産コストの増大を招く。  [0018] When forming a dummy wiring and a dummy via under a pad, the number of wirings and vias that can be arranged under the nod is limited according to the pad area. Therefore, if the strength of the low dielectric constant film, which is the interlayer insulating film, is very low, or if the adhesion between the low dielectric constant film and the films above and below it is very low, dummy wiring under the pad And the number of dummy vias must be huge. In this case, most of the area under the bonding pad is occupied by the dummy wiring and the dummy via. Therefore, it is not a dummy! / ヽ It is impossible to arrange the wiring and via forming the circuit. No circuit can be formed at the same time. As a result, the chip area increases, and the number of chips that can be collected from one wafer is reduced, resulting in an increase in production cost.
[0019] 本発明は、上記のような従来例における問題点に鑑みてなされたものであり、チッ プ全体としての強度が高ぐプロセス中及びパッケージング時の衝撃や応力に対して 構造的破壊を生じることがな ヽ半導体装置及びその製造方法を提供することを目的 とする。  The present invention has been made in view of the above-described problems in the conventional example, and has a structure in which the strength of the entire chip is high and the structure is resistant to shocks and stresses during a process and during packaging. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which do not cause problems.
[0020] 本発明は、さら〖こ、生産コストを低減させるとともに、高い構造信頼性を有する半導 体装置及びその製造方法を提供することを目的とする。  An object of the present invention is to further provide a semiconductor device having high structural reliability while reducing production costs, and a method of manufacturing the same.
課題を解決するための手段  Means for solving the problem
[0021] この目的を達成するため、本発明の第一の態様に係る半導体装置は、半導体基板 と、前記半導体基板上に形成された少なくとも一つの層間絶縁膜と、前記層間絶縁 膜を介して積層された複数の配線層と、を備え、前記複数の配線層の各々に形成さ れた回路配線と、前記層間絶縁膜を貫通し、上下方向に隣接する前記回路配線を 相互に接続する導電性金属ビアと、力 なる多層回路構造が形成されている半導体 装置であって、前記複数の配線層の各々に設けられた補強配線パターンと、前記層 間絶縁膜に設けられ、上下方向に隣接する前記補強配線パターンを相互に接続す る補強ビアパターンと、力もなる多層支持構造を備え、前記多層支持構造は、前記 多層回路構造が存在する前記半導体装置の回路領域において、前記多層回路構 造と抵触しな 、領域に形成されて 、ることを特徴とする。 [0021] To achieve this object, the semiconductor device according to the first aspect of the present invention comprises a semiconductor substrate And at least one interlayer insulating film formed on the semiconductor substrate; and a plurality of wiring layers stacked with the interlayer insulating film interposed therebetween, and a circuit formed on each of the plurality of wiring layers. A semiconductor device in which a wiring, a conductive metal via penetrating through the interlayer insulating film and interconnecting the circuit wirings vertically adjacent to each other, and a powerful multilayer circuit structure are formed; A reinforcing wiring pattern provided on each of the layers, a reinforcing via pattern provided on the inter-layer insulating film and interconnecting the reinforcing wiring patterns adjacent to each other in a vertical direction, and a multilayer support structure capable of providing a force. The multi-layer support structure is characterized in that it is formed in a region of the semiconductor device where the multi-layer circuit structure exists and does not conflict with the multi-layer circuit structure.
[0022] 従来、 CMP平坦用ダミーパターンは配線層のみに形成されていたのに対して、第 1の態様に係る発明においては、 CMP平坦用ダミー配線パターンが相互に重なり合 う領域を接続するように補強ビアパターンが形成される。このように、回路領域におい ても、ビア層 (層間絶縁膜)に補強ビアパターンが存在するため、半導体装置全体の 強度を向上させることが可能となる。また、本発明に係る半導体装置の構造は、従来 より存在した上下層のダミー配線パターンが重なり合う領域を補強ビアパターンで接 続するだけのものであるため、回路領域における配線の配置に対して特段影響を与 えるものではない。  Conventionally, the CMP flat dummy pattern is formed only on the wiring layer, whereas in the invention according to the first aspect, the regions where the CMP flat dummy wiring patterns overlap each other are connected. Thus, a reinforcing via pattern is formed. As described above, even in the circuit region, since the reinforcing via pattern exists in the via layer (interlayer insulating film), the strength of the entire semiconductor device can be improved. In addition, the structure of the semiconductor device according to the present invention is such that the region where the existing dummy wiring patterns of the upper and lower layers overlap is merely connected by the reinforcing via pattern, so that the arrangement of the wiring in the circuit region is particularly small. It has no effect.
[0023] 第一の態様に係る半導体装置は、最上層上に形成され、外部と電気的に信号の送 受信を行なうパッドをさらに有するものであることが好ましい。  It is preferable that the semiconductor device according to the first aspect further includes a pad formed on the uppermost layer and electrically transmitting and receiving signals to and from the outside.
[0024] また、前記多層支持構造は前記パッドの下方の領域にも存在していることが好まし い。 [0024] Further, it is preferable that the multilayer support structure also exists in a region below the pad.
[0025] なお、本明細書において、「配線層」とは、電気的絶縁性材料力もなり、内部に部分 的に回路配線が形成されて！ヽる層を指す。  [0025] In the present specification, the "wiring layer" also serves as an electrically insulating material, and is partially formed with circuit wiring inside! Refers to the layer.
[0026] 本発明の第二の態様に係る半導体装置は、半導体基板と、前記半導体基板上に 形成された少なくとも一つの層間絶縁膜と、前記層間絶縁膜を介して積層された複 数の配線層と、前記複数の配線層のうちの最上層上に形成されたパッドと、を備え、 前記複数の配線層の各々に形成された回路配線と、前記層間絶縁膜を貫通し、上 下方向に隣接する前記回路配線を相互に接続する導電性金属ビアと、からなる多層 回路構造が形成されている半導体装置であって、前記複数の配線層の各々に設け られた補強配線パターンと、前記層間絶縁膜に設けられ、上下方向に隣接する前記 補強配線パターンを相互に接続する補強ビアパターンと、力もなる多層支持構造を 備え、前記パッドの下方の領域には、前記多層回路構造の少なくとも一部が配置さ れており、前記パッドの下方には、前記多層支持構造が、前記多層回路構造と抵触 しな 、領域に形成されて 、ることを特徴とする。 [0026] A semiconductor device according to a second aspect of the present invention provides a semiconductor substrate, at least one interlayer insulating film formed on the semiconductor substrate, and a plurality of wirings stacked via the interlayer insulating film. And a pad formed on an uppermost layer of the plurality of wiring layers, a circuit wiring formed on each of the plurality of wiring layers, and an upper and lower direction penetrating the interlayer insulating film. And a conductive metal via interconnecting the circuit wiring adjacent to the wiring. A semiconductor device in which a circuit structure is formed, wherein a reinforcing wiring pattern provided on each of the plurality of wiring layers and the reinforcing wiring pattern provided on the interlayer insulating film and vertically adjacent to each other are connected to each other. And a multilayer support structure that also provides a force. At least a part of the multilayer circuit structure is disposed in a region below the pad, and the multilayer support structure is disposed below the pad. , And formed in a region that does not conflict with the multilayer circuit structure.
[0027] 第 2の態様に係る発明においては、ボンディングパッドの下方の領域にも、他の回 路領域と同じ形態で回路配線、導電性金属ビア、補強配線パターンを存在させた場 合に、ボンディングパッドの下方の領域、あるいは、ボンディングパッドの外縁から外 側の所定距離の範囲内の配線層に存在する補強配線パターンが重なり合う領域を 接続するように、補強ビアパターンが形成される。このため、ボンディングパッドの下 方の領域においては、ワイヤボンディングに対する強度を高めながら、かつ、ボンデ イングパッドの下方の領域に回路を形成することが可能であるため、生産コストを向上 させながら、同時に、プロセス耐性、ワイヤボンディング耐性、榭脂封入耐性等を向 上させることができる。  [0027] In the invention according to the second aspect, when circuit wiring, conductive metal vias, and reinforcing wiring patterns are also provided in a region below the bonding pad in the same form as the other circuit regions, The reinforcing via pattern is formed so as to connect the region under the bonding pad or the region where the reinforcing wiring pattern existing in the wiring layer within a predetermined distance outside the outer edge of the bonding pad overlaps. For this reason, in the region below the bonding pad, it is possible to form a circuit in the region below the bonding pad while increasing the strength against wire bonding. , Process resistance, wire bonding resistance, resin encapsulation resistance, and the like.
[0028] 第二の態様に係る半導体装置は、前記半導体基板上に形成されたトランジスタをさ らに備えており、前記トランジスタは、前記パッドの下方に配置されていることが好まし い。  [0028] The semiconductor device according to the second aspect preferably further includes a transistor formed on the semiconductor substrate, and the transistor is preferably arranged below the pad.
[0029] 前記多層支持構造は、前記パッドの下方の領域のみならず、前記パッドの外周より も外側の所定距離の範囲の下方の領域にも形成されていることが好ましい。  [0029] It is preferable that the multilayer support structure is formed not only in a region below the pad but also in a region below a predetermined distance outside the outer periphery of the pad.
[0030] 所定距離とは、例えば、 10 μ mである。 [0030] The predetermined distance is, for example, 10 µm.
[0031] 本発明の第三の態様に係る半導体装置は、半導体基板と、前記半導体基板上に 形成された少なくとも一つの層間絶縁膜と、前記層間絶縁膜を介して積層された複 数の配線層と、を備え、前記複数の配線層の各々に形成された回路配線と、前記層 間絶縁膜を貫通し、上下方向に隣接する前記回路配線を相互に接続する導電性金 属ビアと、力 なる多層回路構造が形成されている半導体装置であって、前記半導 体装置は、前記複数の配線層の各々に設けられた補強配線パターンと、前記層間 絶縁膜に設けられ、上下方向に隣接する前記補強配線パターンを相互に接続する 補強ビアパターンと、からなる多層支持構造を備え、前記半導体装置は、前記多層 回路構造が形成されている回路領域と、前記回路領域の周囲の領域であって、回路 が形成されていないスクライブ領域と、を有しており、前記多層支持構造は前記スクラ イブ領域に形成されて 、ることを特徴とする。 [0031] A semiconductor device according to a third aspect of the present invention is a semiconductor device, at least one interlayer insulating film formed on the semiconductor substrate, and a plurality of wirings stacked via the interlayer insulating film. And a conductive metal via that penetrates the inter-layer insulating film and interconnects the vertically adjacent circuit wirings, the circuit wiring being formed in each of the plurality of wiring layers. A semiconductor device in which a powerful multilayer circuit structure is formed, wherein the semiconductor device is provided on a reinforcing wiring pattern provided on each of the plurality of wiring layers and on the interlayer insulating film, and is provided in a vertical direction. Connecting adjacent reinforcing wiring patterns to each other A multilayer support structure comprising a reinforcing via pattern, wherein the semiconductor device comprises: a circuit region in which the multilayer circuit structure is formed; and a scribe region in a region around the circuit region, wherein no circuit is formed. And the multilayer support structure is formed in the scribing region.
[0032] 本明細書において、半導体装置の「スクライブ領域」とは、半導体装置において回 路配線が存在する回路領域よりも外側の領域、または、ボンディングパッドの下方の 領域よりも外側 (半導体チップ周縁端部近傍)の領域を指す。一般に、スクライブ領域 には回路は存在しない。  [0032] In this specification, a "scribe area" of a semiconductor device is a region outside a circuit region where circuit wiring exists in a semiconductor device, or outside a region below a bonding pad (the periphery of a semiconductor chip). (Near the end). Generally, there are no circuits in the scribe area.
[0033] 例えば、ウェハをダイシングにより切断して、複数の半導体チップ（半導体装置）と する際に、切断する部位がこの「スクライブ領域」に相当する。ウェハ上においては、 スクライブ領域の幅はある程度大きく取られているため（例えば、 100 /z m以上）、ゥ ハの切断後においても、このスクライブ領域は、半導体チップの周縁端部の近傍に 残存することとなる。  For example, when a wafer is cut by dicing to form a plurality of semiconductor chips (semiconductor devices), a portion to be cut corresponds to the “scribe area”. On the wafer, the scribe region has a certain width (for example, 100 / zm or more), so that even after the wafer is cut, the scribe region remains near the peripheral edge of the semiconductor chip. It will be.
[0034] 第 3の態様に係る発明にお 、ては、半導体装置のスクライブ領域に、補強配線バタ ーンと、複数の配線層に存在する補強配線パターン間を接続する補強ビアパターン とからなる多層支持構造が形成される。これにより、半導体チップの周縁端部におけ る層間絶縁膜及び配線層カゝらなる積層体の膜強度や密着性を高め、ダイシング時、 ワイヤボンディング時、組立榭脂封入時の応力に起因する層間絶縁膜及び配線層 の剥がれを防止することができる。  [0034] In the invention according to the third aspect, the scribe region of the semiconductor device includes a reinforcing wiring pattern and a reinforcing via pattern connecting the reinforcing wiring patterns existing in the plurality of wiring layers. A multilayer support structure is formed. This enhances the film strength and adhesion of the laminated body composed of the interlayer insulating film and the wiring layer at the peripheral edge of the semiconductor chip, and is caused by the stress at the time of dicing, wire bonding, and sealing of the assembly resin. Peeling of the interlayer insulating film and the wiring layer can be prevented.
[0035] 前記多層支持構造は、前記回路領域において、前記多層回路構造と抵触しない 領域に形成される。  [0035] The multilayer support structure is formed in a region of the circuit region that does not conflict with the multilayer circuit structure.
[0036] 第 3の態様に係る半導体装置は、最上層上に形成され、外部と電気的に信号の送 受信を行なうパッドをさらに有するものであることが好ましい。  [0036] The semiconductor device according to the third aspect preferably further includes a pad formed on the uppermost layer and electrically transmitting and receiving signals to and from the outside.
[0037] 前記パッドの下方の領域にも前記多層支持構造が形成されて!ヽることが好ま ヽ。 [0037] Preferably, the multilayer support structure is also formed in a region below the pad.
[0038] 前記パッドの外側と前記スクライブ領域との間にも前記多層支持構造が形成されて 、ることが好まし!/、。 [0038] Preferably, the multilayer support structure is also formed between the outside of the pad and the scribe area!
[0039] 前記補強ビアパターンの前記半導体装置の厚さ方向における長さは前記導電性 金属ビアの前記半導体装置の厚さ方向における長さよりも大きいものであることが好 ましい。 The length of the reinforcing via pattern in the thickness direction of the semiconductor device is preferably larger than the length of the conductive metal via in the thickness direction of the semiconductor device. Good.
[0040] 前記補強ビアパターンの前記半導体装置の横断面における形状力スリット状である ことが好ましい。  It is preferable that the reinforcing via pattern has a slit shape in a cross section of the semiconductor device.
[0041] 前記多層支持構造は前記回路配線及び前記導電性金属ビアから電気的に独立し て形成されて 、るものであることが好まし 、。  [0041] Preferably, the multilayer support structure is formed electrically independent of the circuit wiring and the conductive metal via.
[0042] 前記多層支持構造は、前記回路配線、前記導電性金属ビア及び前記パッドから電 気的に独立して形成されて!、るものであることが好ま 、。 [0042] It is preferable that the multilayer support structure is formed electrically independent of the circuit wiring, the conductive metal via, and the pad.
[0043] 前記多層支持構造は前記半導体基板中に設けられた素子分離領域に接続されて[0043] The multilayer support structure is connected to an element isolation region provided in the semiconductor substrate.
V、るものであることが好まし!/、。 V, that's what it is! / ,.
[0044] 前記半導体装置は、その最上層において、グローバル配線をさらに備えており、前 記回路領域に形成された前記多層支持構造は、その一端部において、前記グロ一 バル配線部に接続され、他端部においては、前記回路配線及び前記導電性金属ビ ァとは隔離されて 、ることが好まし!/、。  [0044] The semiconductor device further includes a global wiring in an uppermost layer thereof, and the multilayer support structure formed in the circuit region is connected at one end to the global wiring portion, At the other end, it is preferable that the circuit wiring and the conductive metal via are separated from each other!
[0045] 前記パッドの下方の領域に形成された多層支持構造は、前記パッド及び他の回路 と接続されて 、るものであることが好まし 、。 [0045] The multilayer support structure formed in the region below the pad is preferably connected to the pad and another circuit.
[0046] 前記補強配線パターン及び前記補強ビアパターンと、それらと同一層に存在する 前記回路配線及び前記導電性金属ビアとはそれぞれ同一の材料で形成されている ものであることが好ましい。 [0046] It is preferable that the reinforcing wiring pattern and the reinforcing via pattern and the circuit wiring and the conductive metal via existing in the same layer are formed of the same material.
[0047] 前記層間絶縁膜の単位面積当たりに占める、前記導電性金属ビアと前記補強ビア パターンとの総面積の割合が 5%以上とされて 、るものであることが好ま U、。 [0047] It is preferable that the ratio of the total area of the conductive metal via and the reinforcing via pattern to the unit area of the interlayer insulating film is 5% or more.
[0048] 前記パッドの下方の領域において、前記層間絶縁膜の単位面積当たりに占める、 前記導電性金属ビアと前記補強ビアパターンとの総面積の割合が 5%以上とされてIn a region below the pad, a ratio of a total area of the conductive metal via and the reinforcing via pattern to a unit area of the interlayer insulating film is set to 5% or more.
V、るものであることが好まし!/、。 V, that's what it is! / ,.
[0049] 前記スクライブ領域において、前記層間絶縁膜の単位面積当たりに占める前記補 強ビアパターンの総面積の割合が 5%以上とされて 、るものであることが好まし 、。  [0049] In the scribe region, the ratio of the total area of the reinforcing via pattern to the unit area of the interlayer insulating film is preferably 5% or more.
[0050] 前記補強ビアパターンは前記補強配線パターンが相互に重なり合う領域のみを接 続するものであることが好まし 、。  [0050] It is preferable that the reinforcing via pattern connects only areas where the reinforcing wiring patterns overlap each other.
[0051] 本発明は、さらに、上記の半導体装置の製造方法であって、前記多層支持構造を 形成する前記補強配線パターンと前記補強ビアパターンと、それらと同一層に存在 する前記回路配線及び前記導電性金属ビアとをそれぞれ同一の材料で形成する過 程を備える、ことを特徴とする半導体装置の製造方法を提供する。 [0051] The present invention further provides the method for manufacturing a semiconductor device described above, wherein the multilayer support structure is provided. A semiconductor device comprising a step of forming the reinforcing wiring pattern and the reinforcing via pattern to be formed, and the circuit wiring and the conductive metal via existing in the same layer with the same material, respectively. And a method for producing the same.
発明の効果  The invention's effect
[0052] 本発明によれば、従来の CMP用ダミーパターン (補強配線パターン）が相互に重 なり合う領域にのみ補強ビアパターンを形成するため、チップ面積の増大を引き起こ さずに生産性を高めることができる。さらに、多層支持構造を形成することにより、製 造工程中及びパッケージング時の衝撃や応力に起因して、低誘電率層間膜が破壊 したり、剥がれたりする不良を抑制して、構造信頼性の高い半導体装置を提供するこ とがでさる。  According to the present invention, since a reinforcing via pattern is formed only in a region where a conventional dummy pattern for CMP (reinforcing wiring pattern) overlaps with each other, productivity is increased without causing an increase in chip area. Can be enhanced. Furthermore, by forming a multilayer support structure, it is possible to suppress the failure of the low dielectric constant interlayer film to be broken or peeled off due to the impact or stress during the manufacturing process and during packaging, and to improve the structural reliability. It is possible to provide a semiconductor device with high reliability.
発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION
[0053] 以下、本発明を具体的な実施形態に基づき詳細に説明する。 Hereinafter, the present invention will be described in detail based on specific embodiments.
[0054] まず、本発明の第 1の態様に係る半導体装置は、半導体基板と、半導体基板上に 形成された少なくとも一つの層間絶縁膜と、層間絶縁膜を介して積層された複数の 配線層と、を備え、複数の配線層の各々に形成された回路配線と、層間絶縁膜を貫 通し、上下方向に隣接する回路配線を相互に接続する導電性金属ビアと、からなる 多層回路構造が形成されている半導体装置であって、複数の配線層の各々に設け られた補強配線パターンと、層間絶縁膜に設けられ、上下方向に隣接する前記補強 配線パターンを相互に接続する補強ビアパターンと、カゝらなる多層支持構造を備え、 多層支持構造は、多層回路構造が存在する前記半導体装置の回路領域において、 多層回路構造と抵触しな ヽ領域に形成されて ヽることを特徴とするものである。 First, the semiconductor device according to the first embodiment of the present invention includes a semiconductor substrate, at least one interlayer insulating film formed on the semiconductor substrate, and a plurality of wiring layers stacked via the interlayer insulating film. And a conductive circuit via formed in each of the plurality of wiring layers and a conductive metal via penetrating through the interlayer insulating film and interconnecting vertically adjacent circuit wirings. A reinforcing wiring pattern provided on each of a plurality of wiring layers, and a reinforcing via pattern provided on an interlayer insulating film and interconnecting the reinforcing wiring patterns adjacent to each other in a vertical direction. A multi-layer support structure, wherein the multi-layer support structure is formed in a region that does not conflict with the multi-layer circuit structure in a circuit region of the semiconductor device having the multi-layer circuit structure. In things is there.
[0055] 図 4は、本発明の第 1の態様に係る半導体装置の一実施形態を示す模式的断面 図である。 FIG. 4 is a schematic cross-sectional view showing one embodiment of the semiconductor device according to the first aspect of the present invention.
[0056] 図 4に示す本実施形態に係る半導体装置は、半導体基板（1001)と、半導体基板 ( 1001)上に形成されたトランジスタ（1101)と、トランジスタ（1101)を覆って半導体 基板（1001)上に形成された絶縁膜（1002)と、絶縁膜（1002)上に形成された第 一配線層（1003)と、第一配線層（1003)上に形成された層間絶縁膜（1006)と、層 間絶縁膜 (1006)上に形成された第二配線層（1007)と、を備えている。 [0057] 第一配線層 (1003)は非導電性材料力もなり、第一配線層 (1003)には、回路配 線となる導電性金属配線（1004)と、導電性金属配線（1004)と同じ導電性物質から なる金属補強配線パターン（1005)とが相互に離間して形成されている。 The semiconductor device according to the present embodiment shown in FIG. 4 includes a semiconductor substrate (1001), a transistor (1101) formed on the semiconductor substrate (1001), and a semiconductor substrate (1001) covering the transistor (1101). ), An insulating film (1002) formed thereon, a first wiring layer (1003) formed on the insulating film (1002), and an interlayer insulating film (1006) formed on the first wiring layer (1003). And a second wiring layer (1007) formed on the inter-layer insulating film (1006). The first wiring layer (1003) also becomes a non-conductive material, and the first wiring layer (1003) includes a conductive metal wiring (1004) serving as a circuit wiring and a conductive metal wiring (1004). A metal reinforcing wiring pattern (1005) made of the same conductive material is formed apart from each other.
[0058] 第二配線層 (1007)は非導電性材料力もなり、第二配線層 (1007)には、回路配 線となる導電性金属配線（1008)と、導電性金属配線（1008)と同じ物質からなる金 属補強配線パターン（1009)とが相互に離間して形成されて!ヽる。  [0058] The second wiring layer (1007) also becomes a non-conductive material, and the second wiring layer (1007) includes a conductive metal wiring (1008) serving as a circuit wiring and a conductive metal wiring (1008). The metal reinforcing wiring pattern (1009) made of the same material is formed apart from each other.
[0059] 第一配線層 (1003)と第二配線層 (1007)との間に挟まれた層間絶縁膜 (1006) には、第一及び第二配線層（1003、 1007)中にそれぞれ設けられた導電性金属配 線（1004、 1008)を相互に電気的に接続する導電性金属ビア（1010)と、第一及び 第二配線層（1003、 1007)中にそれぞれ設けられた金属補強配線パターン（1005 、 1009)が重なり合う領域を相互に電気的に接続する金属補強ビアパターン（1011 )と、が形成されている。金属補強ビアパターン（1011)は導電性金属ビア（1010)と 同じ導電性物質で形成されて！、る。  The interlayer insulating film (1006) sandwiched between the first wiring layer (1003) and the second wiring layer (1007) is provided in the first and second wiring layers (1003, 1007), respectively. Conductive metal vias (1010) for electrically connecting the conductive metal wirings (1004, 1008) to each other, and metal reinforcing wirings provided in the first and second wiring layers (1003, 1007), respectively. A metal reinforcing via pattern (1011) for electrically connecting mutually overlapping areas of the patterns (1005, 1009) is formed. The metal reinforcing via pattern (1011) is made of the same conductive material as the conductive metal via (1010)! RU
[0060] 図 4に示す実施形態に係る半導体装置においては、本半導体装置の厚さ方向に 積み重ねられた導電性金属配線（1004、 1008)と、導電性金属ビア（1010)と、から 多層回路構造が形成されている。さらに、本半導体装置の厚さ方向に積み重ねられ た金属補強配線パターン（1005、 1009)と、これらを相互に連結する金属補強ビア パターン（1011)と、力も多層支持構造が形成されている。多層支持構造は、多層回 路構造が形成されている回路領域における間隙部に存在している。すなわち、多層 支持構造は、多層回路構造が形成されている回路領域の内部において、多層回路 構造と抵触しな!ヽように、多層回路構造が存在しな!ヽ領域に形成されて!ヽる。  In the semiconductor device according to the embodiment shown in FIG. 4, a multi-layer circuit includes conductive metal wirings (1004, 1008) and conductive metal vias (1010) stacked in the thickness direction of the semiconductor device. A structure is formed. Further, a metal reinforcing wiring pattern (1005, 1009) stacked in the thickness direction of the present semiconductor device, a metal reinforcing via pattern (1011) for interconnecting the metal reinforcing wiring patterns, and a multi-layer supporting structure are formed. The multilayer support structure exists in a gap in a circuit region where the multilayer circuit structure is formed. That is, the multilayer support structure is formed in the region where the multilayer circuit structure does not exist, just like the multilayer circuit structure does not conflict with the inside of the circuit region where the multilayer circuit structure is formed. .
[0061] 図 4に示す実施形態に係る半導体装置においては、多層支持構造を形成する補 強配線パターン（1005、 1009)と、同一の配線層に存在する導電性金属配線（100 4、 1008)とは同一の導電性材料で形成され、さらに、多層支持構造を形成する金 属補強ビアパターン（1011)と、同一の層間絶縁膜に存在する導電性金属ビア（10 10)とは同一の導電性材料で形成されているが、必ずしもこれには限定されない。補 強配線パターン（1005、 1009)と導電性金属配線（1004、 1008)は相互に異なる 材料によって形成されていても良ぐまた、同一の層間絶縁膜に存在する金属補強 ビアパターン（1011)と導電性金属ビア（1010)とは相互に異なる導電性材料によつ て形成されていても良い。し力しながら、同一の材料で形成することにより、製造プロ セスにおける工程数を少なくすることができるというメリットがある。 In the semiconductor device according to the embodiment shown in FIG. 4, the reinforcing wiring patterns (1005, 1009) forming the multilayer support structure and the conductive metal wirings (1004, 1008) existing in the same wiring layer Are formed of the same conductive material, and the metal reinforcing via pattern (1011) forming the multilayer support structure and the conductive metal via (1010) existing in the same interlayer insulating film are the same conductive material. Although it is formed of a conductive material, it is not necessarily limited to this. The reinforcing wiring pattern (1005, 1009) and the conductive metal wiring (1004, 1008) may be made of different materials. Also, metal reinforcement existing in the same interlayer insulating film The via pattern (1011) and the conductive metal via (1010) may be formed of mutually different conductive materials. However, by forming the same material with the same force, there is an advantage that the number of steps in the manufacturing process can be reduced.
[0062] 本発明の第 1の態様に係る半導体装置において、上記のような多層支持構造は、 半導体装置の厚さ方向において、半導体基板（1001)上に積層される複数の配線 層及び層間絶縁膜のうちの少なくとも 2層以上にわたって形成されていれば良い。  [0062] In the semiconductor device according to the first aspect of the present invention, the multilayer support structure as described above includes a plurality of wiring layers and interlayer insulating layers stacked on the semiconductor substrate (1001) in the thickness direction of the semiconductor device. It is sufficient that the film is formed over at least two layers of the film.
[0063] また、この多層支持構造は、導電性金属配線（1004、 1008)及び導電性金属ビア  [0063] Further, this multilayer support structure includes conductive metal wirings (1004, 1008) and conductive metal vias.
(1010)からなる多層回路構造力も電気的に絶縁されたものであってもよぐあるいは 、多層回路構造に電気的に接続されたものでもあっても良い。  The multilayer circuit structure composed of (1010) may also be electrically insulated, or may be electrically connected to the multilayer circuit structure.
[0064] 但し、多層回路構造に電気的に接続される場合であっても、多層支持構造は、そ の一端部のみにぉ 、て多層回路構造に接続され、他端部にお 、ては多層回路構造 とは電気的に隔離される、すなわち、電気的に開放される。  [0064] However, even when electrically connected to the multilayer circuit structure, the multilayer support structure is connected to the multilayer circuit structure only at one end thereof, and is electrically connected at the other end. The multilayer circuit structure is electrically isolated, that is, electrically open.
[0065] また、多層支持構造は、本半導体装置の最上層である第二配線層（1007)力も半 導体基板（1001)まで延長されたものであってもよぐあるいは、複数の配線層及び 層間絶縁膜からなる積層体の内部にぉ 、て終端して 、るものであってもよ!/、。  Further, the multi-layer support structure may be such that the force of the second wiring layer (1007), which is the uppermost layer of the present semiconductor device, is also extended to the semiconductor substrate (1001). It may be one that terminates inside the laminated body composed of the interlayer insulating film.
[0066] 図 5乃至図 8は本発明の第 1の態様に係る半導体装置の他の実施形態の構造を模 式的に示す断面図である。  FIGS. 5 to 8 are cross-sectional views schematically showing the structure of another embodiment of the semiconductor device according to the first aspect of the present invention.
[0067] 図 5乃至図 8に示す実施形態に係る半導体装置は、いずれも、図 4に示した実施形 態に係る半導体装置と同様に、半導体基板（1001)と、半導体基板（1001)上に形 成された複数個のトランジスタ（1101)と、隣接するトランジスタ（1101)間を電気的 に分離させるための素子分離領域 (絶縁層、 1016)と、トランジスタ（1101)を覆って 半導体基板（1001)上に形成された絶縁膜（1002)と、絶縁膜（1002)上に形成さ れた第一配線層 (1003)と、第一配線層 (1003)上に形成された第一層間絶縁膜 (1 006)と、第一層間絶縁膜 (1006)上に形成された第二配線層（1007)と、第二配線 層（1007)上に形成された第二層間絶縁膜 (1012)と、第二層間絶縁膜 (1012)上 に形成された第三配線層（1013)と、を備えている。  The semiconductor device according to the embodiment shown in FIGS. 5 to 8 is similar to the semiconductor device according to the embodiment shown in FIG. 4, and includes a semiconductor substrate (1001) and a semiconductor substrate (1001). A plurality of transistors (1101) formed in a semiconductor device, an element isolation region (insulating layer, 1016) for electrically isolating adjacent transistors (1101), and a semiconductor substrate (1101) covering the transistors (1101) 1001), an insulating film (1002) formed on the insulating film (1002), a first wiring layer (1003) formed on the insulating film (1002), and a first interlayer formed on the first wiring layer (1003). An insulating film (1006), a second wiring layer (1007) formed on the first interlayer insulating film (1006), and a second interlayer insulating film (1012) formed on the second wiring layer (1007). ) And a third wiring layer (1013) formed on the second interlayer insulating film (1012).
[0068] 第一配線層 (1003)は非導電性材料力もなり、第一配線層 (1003)には、回路配 線となる導電性金属配線（1004)と、導電性金属配線（1004)と同じ導電性物質から なる金属補強配線パターン（1005)とが相互に離間して形成されている。 The first wiring layer (1003) also becomes a non-conductive material, and the first wiring layer (1003) includes a conductive metal wiring (1004) serving as a circuit wiring and a conductive metal wiring (1004). From the same conductive material The metal reinforcing wiring pattern (1005) is formed apart from each other.
[0069] 第二配線層 (1007)は非導電性材料力もなり、第二配線層 (1007)には、回路配 線となる導電性金属配線（1008)と、導電性金属配線（1008)と同じ物質からなる金 属補強配線パターン（1009)とが相互に離間して形成されて!ヽる。  The second wiring layer (1007) also becomes a non-conductive material, and the second wiring layer (1007) includes a conductive metal wiring (1008) serving as a circuit wiring and a conductive metal wiring (1008). The metal reinforcing wiring pattern (1009) made of the same material is formed apart from each other.
[0070] 第一配線層 (1003)と第二配線層 (1007)との間に挟まれた層間絶縁膜 (1006) には、第一及び第二配線層（1003、 1007)中にそれぞれ設けられた導電性金属配 線（1004、 1008)を相互に電気的に接続する導電性金属ビア（1010)と、第一及び 第二配線層（1003、 1007)中にそれぞれ設けられた金属補強配線パターン（1005 、 1009)が重なり合う領域を相互に電気的に接続する金属補強ビアパターン（1011 )と、が形成されている。金属補強ビアパターン（1011)は導電性金属ビア（1010)と 同じ導電性物質で形成されて！、る。  The interlayer insulating film (1006) sandwiched between the first wiring layer (1003) and the second wiring layer (1007) is provided in the first and second wiring layers (1003, 1007), respectively. Conductive metal vias (1010) for electrically connecting the conductive metal wirings (1004, 1008) to each other, and metal reinforcing wirings provided in the first and second wiring layers (1003, 1007), respectively. A metal reinforcing via pattern (1011) for electrically connecting mutually overlapping areas of the patterns (1005, 1009) is formed. The metal reinforcing via pattern (1011) is made of the same conductive material as the conductive metal via (1010)! RU
[0071] 第三配線層 (1013)は非導電性材料カゝらなり、第三配線層 (1013)にはグローバ ル配線 (電源配線、 1015)が形成されている。  The third wiring layer (1013) is made of a non-conductive material, and global wiring (power supply wiring, 1015) is formed in the third wiring layer (1013).
[0072] ここで、グローバル配線（1015)とは、グローバル配線（1015)より下層に形成され たローカル配線である導電性金属配線（1004、 1008)よりも相対的に長い配線長を 有した配線である。半導体チップ上に形成された論理回路のうち、近接する論理回 路同士の配線は配線ピッチを細力くした下層のローカル配線（1004、 1008)によつ て行なわれ、離れた論理回路同士の配線は、上層のグローバル配線（1015)によつ て行なわれる。  Here, the global wiring (1015) is a wiring having a wiring length relatively longer than a conductive metal wiring (1004, 1008) which is a local wiring formed below the global wiring (1015). It is. Of the logic circuits formed on the semiconductor chip, the wiring between adjacent logic circuits is performed by lower-level local wiring (1004, 1008) with a finer wiring pitch, and the wiring between distant logic circuits is reduced. The wiring is performed by the global wiring (1015) in the upper layer.
[0073] 一般に、グローバル配線（1015)は、ローカル配線（1004、 1008)よりも配線膜厚 及び配線幅が大きぐかつ、配線間隔が広い。  In general, the global wiring (1015) has a larger wiring thickness and a wider wiring width than the local wiring (1004, 1008), and has a wider wiring interval.
[0074] 図 5乃至図 8に示す実施形態に係る半導体装置は上記のような共通の構造を有す る一方、以下のような相違点を有している。  The semiconductor devices according to the embodiments shown in FIGS. 5 to 8 have the above-described common structure, but have the following differences.
[0075] 図 5に示す実施形態に係る半導体装置においては、多層支持構造の金属補強配 線パターン（1009)には、第二層間絶縁膜（1012)中に設けられた金属補強ビアパ ターン（1014)が接続され、この補強ビアパターン（1014)を介して、多層支持構造 は、その一端部において、グローバル配線（1015)に電気的に接続されている。一 方、多層支持構造は、その他端部において、第一配線層 (1003)中に形成された金 属補強配線パターン（1005)を形成している。すなわち、多層支持構造は、半導体 基板上（1001)に形成された複数の配線層及び層間絶縁膜からなる積層体の内部 において終端している。 In the semiconductor device according to the embodiment shown in FIG. 5, the metal reinforcing wiring pattern (1009) of the multilayer support structure includes a metal reinforcing via pattern (1014) provided in the second interlayer insulating film (1012). ), And the multilayer support structure is electrically connected at one end to the global wiring (1015) via the reinforcing via pattern (1014). On the other hand, the multi-layer support structure, at the other end, has a metal layer formed in the first wiring layer (1003). A metal reinforcing wiring pattern (1005) is formed. That is, the multi-layer support structure terminates inside a stacked body composed of a plurality of wiring layers and an interlayer insulating film formed on the semiconductor substrate (1001).
[0076] 図 6に示す実施形態に係る半導体装置においても、図 5に示した実施形態係る半 導体装置と同様に、多層支持構造は一端部においてグローバル配線（1015)に接 続されている。ただし、図 5に示した実施形態係る半導体装置と異なり、多層支持構 造は、他端部において、第一配線層 (1003)中に形成された金属補強配線パターン (1005)が、絶縁膜（1002)中に設けられた補強ビアパターン（1017)に接続されて おり、多層支持構造は、この補強ビアパターン（1017)を介して、半導体基板（1001 )の素子分離領域 (絶縁層、 1016)に支持されている。  In the semiconductor device according to the embodiment shown in FIG. 6, similarly to the semiconductor device according to the embodiment shown in FIG. 5, the multilayer support structure is connected at one end to the global wiring (1015). However, unlike the semiconductor device according to the embodiment shown in FIG. 5, the multi-layer support structure has a metal reinforcing wiring pattern (1005) formed in the first wiring layer (1003) at the other end. 1002) are connected to the reinforcing via pattern (1017) provided in the semiconductor substrate (1001) through the reinforcing via pattern (1017). It is supported by.
[0077] 図 7に示す実施形態に係る半導体装置においては、多層支持構造は、グローバル 配線（1015)に接続されておらず、グローバル配線（1015)からは電気的に切り離さ れた構造体とされている。  In the semiconductor device according to the embodiment shown in FIG. 7, the multilayer support structure is a structure that is not connected to the global wiring (1015) and is electrically separated from the global wiring (1015). ing.
[0078] また、図 8に示す実施形態に係る半導体装置においても、多層支持構造は、グロ一 バル配線（1015)に接続されておらず、グローバル配線（1015)力もは電気的に切り 離された構造体とされているが、図 6に示す実施形態に係る半導体装置と同様に、 多層支持構造は、その他端部において、絶縁膜（1002)中に設けられた金属補強ビ ァパターン（1017)に接続されており、金属補強ビアパターン（1017)を介して、半導 体基板（1001)の素子分離領域 (絶縁層、 1016)に支持されている。  Also in the semiconductor device according to the embodiment shown in FIG. 8, the multilayer support structure is not connected to the global wiring (1015), and the power of the global wiring (1015) is electrically separated. As in the case of the semiconductor device according to the embodiment shown in FIG. 6, the multilayer support structure has a metal reinforcing via pattern (1017) provided in the insulating film (1002) at the other end. And is supported by an element isolation region (insulating layer, 1016) of the semiconductor substrate (1001) via a metal reinforcing via pattern (1017).
[0079] 図 9は、図 5及び図 6に示した実施形態に係る半導体装置におけるように、多層支 持構造が、一端部において、グローバル配線（1015)に接続された場合の等価回路 を示す回路図である。  FIG. 9 shows an equivalent circuit when the multilayer support structure is connected at one end to the global wiring (1015) as in the semiconductor device according to the embodiment shown in FIGS. 5 and 6. It is a circuit diagram.
[0080] ここで、多層支持構造は半導体基板（1001)または層間絶縁膜の間にキャパシタ ンスを形成するため、抵抗として示されるグローバル配線（1015)に対して、多層支 持構造はデカップリング容量（1112)として機能する。  Here, since the multilayer support structure forms a capacitance between the semiconductor substrate (1001) or the interlayer insulating film, the multilayer support structure has a decoupling capacitance with respect to the global wiring (1015) shown as a resistance. Functions as (1112).
[0081] 第 1の態様に係る半導体装置において、図 5及び図 6に示した実施形態に係る半 導体装置におけるように、多層支持構造が、その一端部において、グローバル配線（ 1015)に接続された場合、半導体装置の最上層が多層支持構造で補強されるため に、半導体装置の全体的な構造の強度がさらに高められることが期待できる。 In the semiconductor device according to the first embodiment, as in the semiconductor device according to the embodiment shown in FIGS. 5 and 6, one end of the multilayer support structure is connected to the global wiring (1015). The uppermost layer of the semiconductor device is reinforced with a multilayer support structure In addition, it can be expected that the strength of the entire structure of the semiconductor device is further enhanced.
[0082] また、図 9に示した等価回路からわ力るように、多層支持構造がデカップリング容量  Further, as shown by the equivalent circuit shown in FIG. 9, the multilayer support structure has a decoupling capacitance.
(1112)のような回路的役割を果たすため、電源ラインの安定を得ることができる。  Since the circuit plays the role of a circuit as in (1112), the power supply line can be stabilized.
[0083] また、図 6及び図 8に示した実施形態に係る半導体装置におけるように、多層支持 構造が半導体基板（1001)に設けられた素子分離領域（1016)に接続されると、多 層支持構造は、高強度の基板（1001)に支持されることになるため、高い構造強度 を有することとなり、半導体装置の全体的な構造の強度も高められることとなる。  When the multilayer support structure is connected to the element isolation region (1016) provided in the semiconductor substrate (1001) as in the semiconductor device according to the embodiment shown in FIGS. Since the supporting structure is supported by the high-strength substrate (1001), the supporting structure has high structural strength, and the strength of the overall structure of the semiconductor device is also increased.
[0084] なお、上記の実施形態においては、半導体装置の回路領域のみの構造を中心に 説明したが、第 1の態様に係る半導体装置は、電気的に外部と信号の送受信を行う ノ^ドを半導体基板（1001)上に有する構造もとり得る。このような構造においても、 回路領域には多層支持構造を形成することが可能であり、また、それに加えて、パッ ド下の領域にも、同様な多層支持構造を形成することができる。  In the above embodiment, the structure of only the circuit region of the semiconductor device has been mainly described. However, the semiconductor device according to the first embodiment electrically transmits and receives signals to and from the outside. On the semiconductor substrate (1001). In such a structure, a multilayer support structure can be formed in the circuit region, and in addition, a similar multilayer support structure can be formed in the region below the pad.
[0085] また、多層支持構造の一部を形成する金属補強ビアパターン（1011)の半導体装 置の厚さ方向における長さは、半導体装置の厚さ方向における導電性金属ビア（10 10)の長さよりも大きくすることが可能である。これによつて、多層支持構造における 金属補強配線パターン（1005、 1009)との密着性の向上や層間絶縁膜の強度を向 上することが可能となり、化学機械研磨 (CMP)プロセスの際やチップパッケージング 時に印加される衝撃や応力に起因する膜剥がれや膜破壊を防止することが可能とな る。  The length of the metal reinforcing via pattern (1011) forming a part of the multilayer support structure in the thickness direction of the semiconductor device is the same as that of the conductive metal via (1010) in the thickness direction of the semiconductor device. It can be larger than the length. This makes it possible to improve the adhesion to the metal reinforcing wiring patterns (1005, 1009) in the multi-layer support structure and the strength of the interlayer insulating film. It is possible to prevent film peeling and film destruction due to impact and stress applied during packaging.
[0086] また、半導体装置の横断面（図 5乃至図 8の紙面と直交する面）における金属補強 ビアパターン（1011)の形状は特に限定されるものではなぐ矩形、孔状、スリット状 等各種の形態をとり得る。例えば、金属補強ビアパターン（1011)の形状をスリット状 とすることにより、断面積を増やすことなぐ半導体装置の厚さ方向における導電性金 属ビア（1010)の長さを大き 、ものとすることができる。  [0086] The shape of the metal reinforcing via pattern (1011) in the cross section of the semiconductor device (the surface orthogonal to the paper surface in FIGS. 5 to 8) is not particularly limited, and may be various shapes such as a rectangle, a hole, and a slit. It can take the form of For example, by making the shape of the metal reinforcing via pattern (1011) into a slit shape, it is possible to increase the length of the conductive metal via (1010) in the thickness direction of the semiconductor device without increasing the cross-sectional area. Can be.
[0087] また、第 1の態様に係る半導体装置においては、層間絶縁膜の単位面積当たりに 占める導電性金属ビア（1010)と金属補強ビアパターン（1011)との総面積の割合 力 ％以上であることが好ましぐ 10%以上であることがより好ましい。このような条件 を満たすように導電性金属ビア（1010)及び金属補強ビアパターン（1011)を形成 することにより、化学機械研磨 (CMP)プロセスの際の欠陥の発生を低減することが できる。 Further, in the semiconductor device according to the first embodiment, the ratio of the total area of the conductive metal via (1010) and the metal reinforcing via pattern (1011) to the unit area of the interlayer insulating film is not less than power%. More preferably, it is more preferably 10% or more. Form conductive metal vias (1010) and metal reinforcing via patterns (1011) to satisfy these conditions. By doing so, the occurrence of defects during the chemical mechanical polishing (CMP) process can be reduced.
[0088] なお、第 1の態様に係る半導体装置において、層間絶縁膜（1006、 1012)の材料 は特に限定されない。例えば、 SiN、 SiOC、 SiC、 SiCN、 SiO等の無機材料及び  [0088] In the semiconductor device according to the first embodiment, the material of the interlayer insulating films (1006, 1012) is not particularly limited. For example, inorganic materials such as SiN, SiOC, SiC, SiCN, SiO
2  2
これらの組合せを用いることができる。特に、低誘電率膜と呼ばれる膜、すなわち、 Si oより誘電率が低い材料力 なる膜を用いることが好ましい。組合せの例としては、 These combinations can be used. In particular, it is preferable to use a film called a low dielectric constant film, that is, a film having a material strength lower than that of SiO. Examples of combinations are:
2 2
例えば、ローカル配線を低誘電率膜、グローバル配線を低誘電率膜よりも膜強度が 高い SiO等の膜で構成される。  For example, the local wiring is formed of a low-dielectric-constant film, and the global wiring is formed of a film of SiO or the like having higher film strength than the low-dielectric-constant film.
2  2
[0089] 低誘電率膜としては、具体的には、例えば、 CVD法や塗布法により形成される各 種有機ポリマー、 MSQ、 HSQ、炭素含有シリコン酸ィ匕膜 (SiOCH)等を例示するこ とができる力 これらに特に限定されるものではない。有機ポリマーとしては、例えば、 ポリイミド、ポリテトラフルォロエチレン、ポリアリルエーテル、ポリべンゾォキサゾール、 ポリオレフイン、ポリアミドを用いることができる力 これらに限定されるものではない。  [0089] Specific examples of the low dielectric constant film include various organic polymers, MSQ, HSQ, and carbon-containing silicon oxide film (SiOCH) formed by a CVD method or a coating method. The force that can be achieved is not particularly limited to these. As the organic polymer, for example, polyimide, polytetrafluoroethylene, polyallyl ether, polybenzoxazole, polyolefin, and polyamide can be used. However, the organic polymer is not limited thereto.
[0090] また、導電性金属配線（1004、 1008)、導電性金属ビア（1010)、金属補強配線 パターン（1005、 1009)及び金属補強ビアパターン（1011)を構成する導体として は、 Cuまたは Cu合金を用いることが好ましいが、これらに限定されるわけではなぐ Aほたは A1合金、その他、 W、 Ni、 Cr、 Ti、 Ag等の金属あるいはこれらの合金、例え ば、 W— Ti、 A1— W、 Al— Ni等の金属間化合物、シリサイド化合物などを用いること ができる。  [0090] Further, as conductors constituting the conductive metal wiring (1004, 1008), conductive metal via (1010), metal reinforcing wiring pattern (1005, 1009) and metal reinforcing via pattern (1011), Cu or Cu It is preferable to use an alloy, but it is not limited to these. A is an A1 alloy, and other metals such as W, Ni, Cr, Ti, and Ag or alloys thereof, for example, W—Ti, A1 — Intermetallic compounds such as —W, Al—Ni, and silicide compounds can be used.
[0091] 半導体基板（1001)としても、例えば、シリコン単結晶基板、各種化合物半導体基 板等を用いることができる。  [0091] As the semiconductor substrate (1001), for example, a silicon single crystal substrate, various compound semiconductor substrates, or the like can be used.
[0092] また、第 1の態様に係る半導体装置において、導電性金属配線（1004、 1008)、 導電性金属ビア（1010)、金属補強配線パターン（1005、 1009)及び金属補強ビア パターン（1011)のそれぞれの配置位置や形状その他のファクタ一は、特に限定さ れるものではなぐ種々の態様を含み得るものである。例えば、導電性金属配線（10 04、 1008)の各配線層における大きさ、形状、配線数その他のファクタ一は任意の ちのとすることがでさる。  In the semiconductor device according to the first embodiment, the conductive metal wiring (1004, 1008), the conductive metal via (1010), the metal reinforcing wiring pattern (1005, 1009), and the metal reinforcing via pattern (1011) Each of the arrangement positions, shapes, and other factors may include various modes which are not particularly limited. For example, the size, shape, number of wirings, and other factors of the conductive metal wirings (1004, 1008) in each wiring layer can be arbitrary.
[0093] 第 1の態様に係る半導体装置の製造方法は特に限定されない。例えば、ダマシン 法を用いて形成することが可能である。図 10乃至図 19は、図 6に示した半導体装置 の製造方法としてのダマシン法における各工程を示す断面図である。以下、図 6に示 した半導体装置の製造方法の一例を図 10乃至図 19を参照して説明する。 [0093] The method for manufacturing the semiconductor device according to the first embodiment is not particularly limited. For example, Damascene It can be formed using a method. 10 to 19 are cross-sectional views showing respective steps in a damascene method as a method for manufacturing the semiconductor device shown in FIG. Hereinafter, an example of a method for manufacturing the semiconductor device shown in FIG. 6 will be described with reference to FIGS.
[0094] まず、図 10に示すように、半導体基板（1001)の表面に素子分離領域（1016)を 形成する。 First, as shown in FIG. 10, an element isolation region (1016) is formed on the surface of a semiconductor substrate (1001).
[0095] 次いで、半導体基板（1001)上にトランジスタ（1101)を搭載する。  Next, the transistor (1101) is mounted on the semiconductor substrate (1001).
[0096] この後、半導体基板（1001)上に、例えば、 CVD法または塗布法により、絶縁膜（1 [0096] Thereafter, the insulating film (1) is formed on the semiconductor substrate (1001) by, for example, a CVD method or a coating method.
002)を形成する。絶縁膜（1002)を形成した後、絶縁膜（1002)の内部に補強ビア ノターン（ 1017)及び導電性金属ビア（1113)を形成する。 002). After forming the insulating film (1002), a reinforcing via turn (1017) and a conductive metal via (1113) are formed inside the insulating film (1002).
[0097] 次いで、絶縁膜（1002)上に、例えば、 CVD法または塗布法により、第一配線層 (Next, on the insulating film (1002), for example, the first wiring layer (
1003)を形成する。 1003).
[0098] 次いで、図 11に示すように、第一配線層 (1003)の所定部位を、例えば、 RIE法等 の方法によりエッチングして、第一配線層（1003)に配線溝（1018)を形成する。ここ で、配線溝（1018)は、導電性金属配線（1004)及び補強配線パターン（1005)の 形成位置に対応して形成されて 、る。  Next, as shown in FIG. 11, a predetermined portion of the first wiring layer (1003) is etched by a method such as the RIE method to form a wiring groove (1018) in the first wiring layer (1003). Form. Here, the wiring groove (1018) is formed corresponding to the formation position of the conductive metal wiring (1004) and the reinforcing wiring pattern (1005).
[0099] 次いで、図 12に示すように、配線溝（1018)が埋め込まれるように、金属を、例えばNext, as shown in FIG. 12, the metal is removed, for example, so that the wiring groove (1018) is buried.
、スパッタ法などにより堆積させる。その後、化学機械研磨 (CMP)法等により余剰の 金属分を除去し、第一配線層 (1003)中に導電性金属配線（1004)及び補強配線 パターン（1005)を形成する。 , By a sputtering method or the like. Then, excess metal is removed by a chemical mechanical polishing (CMP) method or the like, and a conductive metal wiring (1004) and a reinforcing wiring pattern (1005) are formed in the first wiring layer (1003).
[0100] 次いで、図 13に示すように、導電性金属配線（1004)及び補強配線パターン（100Next, as shown in FIG. 13, the conductive metal wiring (1004) and the reinforcing wiring pattern (100
5)を形成した第一配線層 (1003)上に、第一層間絶縁膜 (1006)を堆積させる。 A first interlayer insulating film (1006) is deposited on the first wiring layer (1003) on which 5) is formed.
[0101] 次いで、図 14に示すように、第一層間絶縁膜（1006)を、上記と同様にエッチング し、第一層間絶縁膜（1006)にビア孔（1019)を形成する。 Next, as shown in FIG. 14, the first interlayer insulating film (1006) is etched in the same manner as above to form a via hole (1019) in the first interlayer insulating film (1006).
[0102] 次いで、図 15に示すように、ビア孔（1019)に金属を堆積させ、 CMP法にて余剰 の金属を除去して、導電性金属ビア（1010)及び補強ビアパターン（1011)を形成 する。 Next, as shown in FIG. 15, a metal is deposited in the via hole (1019), and excess metal is removed by a CMP method to form a conductive metal via (1010) and a reinforcing via pattern (1011). Form.
[0103] 次いで、図 16に示すように、第一層間絶縁膜（1006)上に第二配線層（1007)を 形成する。 [0104] 次いで、図 17に示すように、第二配線層 (1007)の所定部位を、例えば、 RIE法等 の方法によりエッチングして、第二配線層（1007)に配線溝（1020)を形成する。ここ で、配線溝（1020)は、導電性金属ビア（1010)及び補強ビアパターン（1011)の形 成位置に対応して形成されて!、る。 Next, as shown in FIG. 16, a second wiring layer (1007) is formed on the first interlayer insulating film (1006). Next, as shown in FIG. 17, a predetermined portion of the second wiring layer (1007) is etched by a method such as the RIE method to form a wiring groove (1020) in the second wiring layer (1007). Form. Here, the wiring groove (1020) is formed corresponding to the formation position of the conductive metal via (1010) and the reinforcing via pattern (1011).
[0105] 次いで、図 18に示すように、配線溝（1020)が埋め込まれるように、金属を、例えば 、スパッタ法などにより堆積させる。その後、化学機械研磨 (CMP)法等により余剰の 金属分を除去し、第二配線層 (1007)中に導電性金属配線（1008)及び補強配線 パターン（1009)を形成する。  Next, as shown in FIG. 18, a metal is deposited by, for example, a sputtering method so that the wiring groove (1020) is filled. Then, excess metal is removed by a chemical mechanical polishing (CMP) method or the like, and a conductive metal wiring (1008) and a reinforcing wiring pattern (1009) are formed in the second wiring layer (1007).
[0106] 次いで、図 19に示すように、第二配線層（1007)上に第二層間絶縁膜（1012)を 形成する。  Next, as shown in FIG. 19, a second interlayer insulating film (1012) is formed on the second wiring layer (1007).
[0107] 次いで、第二層間絶縁膜 (1012)を、上記と同様にエッチングし、第二層間絶縁膜  [0107] Next, the second interlayer insulating film (1012) is etched in the same manner as described above, and the second interlayer insulating film (1012) is etched.
(1012)にビア孔を形成する。  A via hole is formed in (1012).
[0108] 次いで、このビア孔に金属を堆積させ、 CMP法にて余剰の金属を除去して、第二 層間絶縁膜（ 1012)中に補強ビアパターン（1014)を形成する。 Next, a metal is deposited in the via hole, and a surplus metal is removed by a CMP method to form a reinforcing via pattern (1014) in the second interlayer insulating film (1012).
[0109] 次いで、第二層間絶縁膜（1012)上に第三配線層（1013)を形成する。 Next, a third wiring layer (1013) is formed on the second interlayer insulating film (1012).
[0110] 次いで、第三配線層 (1013)の所定部位を、例えば、 RIE法によりエッチングして、 第三配線層 (1013)に配線溝を形成する。 Next, a predetermined portion of the third wiring layer (1013) is etched by, eg, RIE to form a wiring groove in the third wiring layer (1013).
[0111] 次いで、この配線溝に金属を堆積させ、化学機械研磨 (CMP)法により余剰の金属 分を除去し、第三配線層 (1013)中にグローバル配線（1015)を形成する。 [0111] Next, a metal is deposited in the wiring groove, and a surplus metal is removed by a chemical mechanical polishing (CMP) method to form a global wiring (1015) in the third wiring layer (1013).
[0112] このようにして、図 6に示した半導体装置が形成される。 Thus, the semiconductor device shown in FIG. 6 is formed.
[0113] なお、図 10乃至図 19において示した製造方法においては、導電性金属ビア（101 0)と導電性金属配線（1006、 1008)を別々に形成するシングルダマシンプロセスを 採用している力 シングルダマシンプロセスに代えて、デュアルダマシンプロセスを採 用することも可能である。デュアルダマシンプロセスにおいては、例えば、第一層間 絶縁膜（1006)と第二配線層 (1007)とを成膜した後、ビア孔（1019)及び配線溝（1 020)を形成し、ビア孔（1019)及び配線溝（1020)に金属膜を堆積させ、 CMP法 にて余剰の金属を除去し、導電性金属ビア（1010)と導電性金属配線（1008)とが 一括で形成される。 (パッド下領域における導電性金属配線） In the manufacturing method shown in FIGS. 10 to 19, a single damascene process in which the conductive metal via (1010) and the conductive metal wiring (1006, 1008) are separately formed is adopted. Instead of a single damascene process, a dual damascene process can be employed. In the dual damascene process, for example, after a first interlayer insulating film (1006) and a second wiring layer (1007) are formed, a via hole (1019) and a wiring groove (1020) are formed. A metal film is deposited in (1019) and the wiring groove (1020), and excess metal is removed by a CMP method, so that a conductive metal via (1010) and a conductive metal wiring (1008) are formed at a time. (Conductive metal wiring under pad area)
次に、本発明の第 2の態様に係る半導体装置は、半導体基板と、半導体基板上に 形成された少なくとも一つの層間絶縁膜と、層間絶縁膜を介して積層された複数の 配線層と、複数の配線層のうちの最上層上に形成されたパッドと、を備え、複数の配 線層の各々に形成された回路配線と、層間絶縁膜を貫通し、上下方向に隣接する回 路配線を相互に接続する導電性金属ビアと、からなる多層回路構造が形成されてい る半導体装置であって、複数の配線層の各々に設けられた補強配線パターンと、層 間絶縁膜に設けられ、上下方向に隣接する補強配線パターンを相互に接続する補 強ビアパターンと、力もなる多層支持構造を備え、パッドの下方の領域には、多層回 路構造の少なくとも一部が配置されており、パッドの下方には、多層支持構造が、多 層回路構造と抵触しな ヽ領域に形成されて ヽることを特徴とするものである。  Next, a semiconductor device according to a second aspect of the present invention includes a semiconductor substrate, at least one interlayer insulating film formed on the semiconductor substrate, and a plurality of wiring layers stacked with the interlayer insulating film interposed therebetween. A pad formed on the uppermost layer of the plurality of wiring layers; a circuit wiring formed on each of the plurality of wiring layers; and a circuit wiring penetrating through the interlayer insulating film and vertically adjacent to the wiring layer. A conductive metal via interconnecting the conductive metal vias, a multi-layer circuit structure comprising: a reinforcing wiring pattern provided on each of a plurality of wiring layers; and an inter-layer insulating film; A reinforcing via pattern for interconnecting reinforcing wiring patterns adjacent to each other in the vertical direction, and a multilayer supporting structure that provides a strong force. At least a part of the multilayer circuit structure is arranged in a region below the pad. Below, is a multilayer support structure Are formed in a region that does not conflict with the multilayer circuit structure.
[0114] 図 20は、本発明の第 2の態様に係る半導体装置の一実施形態を示す模式的断面 図である。 FIG. 20 is a schematic cross-sectional view showing one embodiment of a semiconductor device according to the second aspect of the present invention.
[0115] 図 20に示す本実施形態に係る半導体装置は、半導体基板（1021)と、半導体基 板（1021)上に形成されたトランジスタ（1101)と、トランジスタ（1101)を覆って半導 体基板（1021)上に形成された絶縁膜（1022)と、絶縁膜（1022)上に形成された 第一配線層 (1023)と、第一配線層 (1023)上に形成された層間絶縁膜 (1026)と、 層間絶縁膜 (1026)上に形成された第二配線層（1027)と、第二配線層（1027)上 に形成され、チップ外部と電気信号の送受信を行う金属ワイヤボンディングパッド（1 040)と、を備えている。  The semiconductor device according to the present embodiment shown in FIG. 20 includes a semiconductor substrate (1021), a transistor (1101) formed on the semiconductor substrate (1021), and a semiconductor covering the transistor (1101). An insulating film (1022) formed on the substrate (1021), a first wiring layer (1023) formed on the insulating film (1022), and an interlayer insulating film formed on the first wiring layer (1023) (1026), a second wiring layer (1027) formed on the interlayer insulating film (1026), and a metal wire bonding pad formed on the second wiring layer (1027) for transmitting and receiving electric signals to and from the outside of the chip (1 040).
[0116] 第一配線層 (1023)は非導電性材料カゝらなり、第一配線層 (1023)には、回路配 線となる導電性金属配線（1024)と、導電性金属配線（1024)と同じ導電性物質から なる金属補強配線パターン（1025)とが相互に離間して形成されている。  [0116] The first wiring layer (1023) is made of a non-conductive material, and the first wiring layer (1023) includes a conductive metal wiring (1024) serving as a circuit wiring and a conductive metal wiring (1024). ) And a metal reinforcing wiring pattern (1025) made of the same conductive material as that of (1) are formed apart from each other.
[0117] 第二配線層 (1027)は非導電性材料カゝらなり、第二配線層 (1027)には、回路配 線となる導電性金属配線（1028)と、導電性金属配線（1028)と同じ物質からなる金 属補強配線パターン（1029)とが相互に離間して形成されて!ヽる。  [0117] The second wiring layer (1027) is made of a non-conductive material. The second wiring layer (1027) has a conductive metal wiring (1028) serving as a circuit wiring and a conductive metal wiring (1028). ) And a metal reinforcing wiring pattern (1029) made of the same material as that of (1) are formed apart from each other.
[0118] 第一配線層 (1023)と第二配線層 (1027)との間に挟まれた層間絶縁膜 (1026) には、第一及び第二配線層（1023、 1027)中にそれぞれ設けられた導電性金属配 線（1024、 1028)を相互に電気的に接続する導電性金属ビア（1030)と、第一及び 第二配線層（1023、 1027)中にそれぞれ設けられた金属補強配線パターン（1025 、 1029)が重なり合う領域を相互に電気的に接続する金属補強ビアパターン（1031 )と、が形成されている。金属補強ビアパターン（1031)は導電性金属ビア（1030)と 同じ導電性物質で形成されて！、る。 [0118] The interlayer insulating film (1026) sandwiched between the first wiring layer (1023) and the second wiring layer (1027) is provided in the first and second wiring layers (1023, 1027), respectively. Conductive metal wiring A conductive metal via (1030) for electrically connecting the lines (1024, 1028) to each other, and metal reinforcing wiring patterns (1025, 1029) provided in the first and second wiring layers (1023, 1027), respectively. And a metal reinforcing via pattern (1031) for electrically connecting mutually overlapping regions to each other. The metal reinforcing via pattern (1031) is made of the same conductive material as the conductive metal via (1030)! RU
[0119] 図 20に示す実施形態に係る半導体装置においては、本半導体装置の厚さ方向に 積み重ねられた導電性金属配線（1024、 1028)と、導電性金属ビア（1030)と、から 多層回路構造が形成されている。さらに、本半導体装置の厚さ方向に積み重ねられ た金属補強配線パターン（1025、 1029)と、これらを相互に連結する金属補強ビア パターン（1031)と、力も多層支持構造が形成されている。多層支持構造は、多層回 路構造が形成されている回路領域における間隙部に存在している。すなわち、多層 支持構造は、多層回路構造が形成されている回路領域の内部において、多層回路 構造と抵触しな!ヽように、多層回路構造が存在しな!ヽ領域に形成されて!ヽる。  [0119] In the semiconductor device according to the embodiment shown in Fig. 20, a multilayer circuit includes conductive metal wirings (1024, 1028) and conductive metal vias (1030) stacked in the thickness direction of the semiconductor device. A structure is formed. Further, a metal reinforcing wiring pattern (1025, 1029) stacked in the thickness direction of the present semiconductor device, a metal reinforcing via pattern (1031) for interconnecting the metal reinforcing wiring patterns (1025, 1029), and a multilayer supporting structure are formed. The multilayer support structure exists in a gap in a circuit region where the multilayer circuit structure is formed. That is, the multilayer support structure is formed in the region where the multilayer circuit structure does not exist, just like the multilayer circuit structure does not conflict with the inside of the circuit region where the multilayer circuit structure is formed. .
[0120] さらに、図 20に示す実施形態に係る半導体装置においては、多層支持構造は、金 属ワイヤボンディングパッド（1040)の下方の領域に形成されているとともに、多層回 路構造の一部も金属ワイヤボンディングパッド（1040)の下方の領域に形成されてい る。また、複数個のトランジスタ（1101)のうちのいくつかは金属ワイヤボンディングパ ッド（1040)の下方の領域に配置されている。  Further, in the semiconductor device according to the embodiment shown in FIG. 20, the multilayer support structure is formed in a region below the metal wire bonding pad (1040), and a part of the multilayer circuit structure is also provided. It is formed in a region below the metal wire bonding pad (1040). Some of the plurality of transistors (1101) are arranged in a region below the metal wire bonding pad (1040).
[0121] ボンディングワイヤ（1041)を金属ワイヤボンディングパッド（1040)に接続する際 には、非常に大きな衝撃または応力が金属ワイヤボンディングパッド（1040)に作用 する。その衝撃または応力は金属ワイヤボンディングパッド（1040)の下方に位置す る多層回路構造にも伝播する。し力しながら、本実施形態に係る半導体装置におい ては、金属ワイヤボンディングパッド（1040)の下方の領域に多層支持構造が存在す るため、層間絶縁膜（1026)における強度及び密着性が増大されており、ボンディン グワイヤ（1041)のボンディング時の衝撃や応力による膜剥がれや膜破壊を防止す ることが可能である。  When connecting the bonding wire (1041) to the metal wire bonding pad (1040), a very large impact or stress acts on the metal wire bonding pad (1040). The impact or stress propagates to the multilayer circuit structure located below the metal wire bonding pad (1040). However, in the semiconductor device according to the present embodiment, since the multilayer support structure exists in the region below the metal wire bonding pad (1040), the strength and adhesion in the interlayer insulating film (1026) increase. Thus, it is possible to prevent film peeling and film destruction due to impact and stress during bonding of the bonding wire (1041).
[0122] また、多層支持構造は、第一及び第二配線層（1023、 1027)の金属補強配線パ ターン（1025、 1029)が相互に重なり合う領域を相互に金属補強ビアパターン（103 1)を介して接続するものであるため、多層支持構造によって占有される領域の面積 が少なくてすみ、金属ワイヤボンディングパッド（1040)の下方の領域にも、他の回路 領域と同様に、導電性金属配線（1024、 1028)及び導電性金属ビア（1030)、ある いは、さらに、トランジスタ（1101)を配置させることが可能である。このため、多層支 持構造によるプロセス耐性、ワイヤボンディング耐性、榭脂封入耐性等を向上させる ことができるとともに、より小さな面積に所定の電気回路を配置することが可能になり、 生産コストを向上させることができる。 [0122] In addition, the multilayer support structure includes a region where the metal reinforcing wiring patterns (1025, 1029) of the first and second wiring layers (1023, 1027) overlap with each other and a metal reinforcing via pattern (103). 1), the area occupied by the multilayer support structure can be reduced, and the area under the metal wire bonding pad (1040) can be electrically conductive like the other circuit areas. It is possible to dispose a conductive metal wiring (1024, 1028) and a conductive metal via (1030), or a transistor (1101). For this reason, it is possible to improve the process resistance, wire bonding resistance, resin encapsulation resistance, and the like of the multilayer support structure, and it is possible to arrange a predetermined electric circuit in a smaller area, thereby increasing production costs. be able to.
[0123] 図 20に示す実施形態に係る半導体装置においては、多層支持構造を形成する補 強配線パターン（1025、 1029)と、同一の配線層に存在する導電性金属配線（102 4、 1028)とは同一の導電性材料で形成され、さらに、多層支持構造を形成する金 属補強ビアパターン（1031)と、同一の層間絶縁膜に存在する導電性金属ビア（10 30)とは同一の導電性材料で形成されているが、必ずしもこれには限定されない。補 強配線パターン（1025、 1029)と導電性金属配線（1024、 1028)は相互に異なる 材料によって形成されていても良ぐまた、同一の層間絶縁膜に存在する金属補強 ビアパターン（1031)と導電性金属ビア（1030)とは相互に異なる導電性材料によつ て形成されていても良い。し力しながら、同一の材料で形成することにより、製造プロ セスにおける工程数を少なくすることができるというメリットがある。  In the semiconductor device according to the embodiment shown in FIG. 20, the reinforcing wiring patterns (1025, 1029) forming the multilayer support structure and the conductive metal wirings (1024, 1028) existing in the same wiring layer Are formed of the same conductive material, and the metal reinforcing via pattern (1031) forming the multilayer support structure and the conductive metal via (1030) existing in the same interlayer insulating film are formed of the same conductive material. Although it is formed of a conductive material, it is not necessarily limited to this. The reinforcing wiring pattern (1025, 1029) and the conductive metal wiring (1024, 1028) may be formed of mutually different materials. Also, the metal reinforcing via pattern (1031) existing in the same interlayer insulating film may be used. The conductive metal via (1030) may be formed of a conductive material different from the conductive metal via (1030). However, by forming the same material with the same force, there is an advantage that the number of steps in the manufacturing process can be reduced.
[0124] 本発明の第 2の態様に係る半導体装置においても、本発明の第 1の態様に係る半 導体装置と同様に、上記のような多層支持構造は、半導体装置の厚さ方向において 、半導体基板（1001)上に積層される複数の配線層及び層間絶縁膜のうちの少なく とも 2層以上にわたって形成されていれば良い。  [0124] In the semiconductor device according to the second embodiment of the present invention, similarly to the semiconductor device according to the first embodiment of the present invention, the multilayer support structure as described above has the following features in the thickness direction of the semiconductor device: It is sufficient that at least two or more of a plurality of wiring layers and interlayer insulating films stacked on the semiconductor substrate (1001) are formed.
[0125] また、この多層支持構造は、導電性金属配線（1024、 1028)及び導電性金属ビア  [0125] Further, this multilayered support structure includes conductive metal wiring (1024, 1028) and conductive metal via.
(1030)からなる多層回路構造または金属ワイヤボンディングパッド（1040)力も電気 的に絶縁されたものであってもよぐあるいは、多層回路構造または金属ワイヤボン デイングパッド（1040)に電気的に接続されたものでもあっても良い。  The multilayer circuit structure consisting of (1030) or metal wire bonding pads (1040) may also be electrically insulated or electrically connected to the multilayer circuit structure or metal wire bonding pads (1040) It may be something.
[0126] 但し、多層回路構造に電気的に接続される場合であっても、多層支持構造は、そ の一端部のみにぉ 、て多層回路構造に接続され、他端部にお 、ては多層回路構造 とは電気的に隔離される、すなわち、電気的に接地される。 [0127] また、多層支持構造は、本半導体装置の最上層である第二配線層（1027)から半 導体基板（1021)まで延長されたものであってもよぐあるいは、多層回路構造の内 部にお 、て終端して 、るものであってもよ 、。 However, even when electrically connected to the multilayer circuit structure, the multilayer support structure is connected to the multilayer circuit structure only at one end thereof, and is electrically connected to the other end thereof. The multilayer circuit structure is electrically isolated, that is, electrically grounded. The multilayer support structure may extend from the second wiring layer (1027), which is the uppermost layer of the semiconductor device, to the semiconductor substrate (1021), or may be a multilayer circuit structure. It may be terminated at the department.
[0128] また、金属ワイヤボンディングパッド（1040)の下方の領域にぉ 、ても、半導体基板  [0128] Further, even in the region below the metal wire bonding pad (1040), the semiconductor substrate
(1021)に素子分離領域（1016) (図 5参照）が設けられている場合には、図 6に示し た実施形態と同様に、多層支持構造は素子分離領域（1016)に接続させることも可 能である。  When the element isolation region (1016) (see FIG. 5) is provided in (1021), the multilayer support structure can be connected to the element isolation region (1016), similarly to the embodiment shown in FIG. It is possible.
[0129] 図 21及び図 22は、多層支持構造の存在領域の一例を模式的に示す平面図であ る。  FIG. 21 and FIG. 22 are plan views schematically showing an example of an existing area of the multilayer support structure.
[0130] 図 21及び図 22に示すように、多層支持構造は、ボンディングパッド（351、 352)の 下方の領域のみならず、ボンディングパッド（351、 352)の外周よりも外側の所定距 離の範囲（350)の下方の領域にも形成することができる。  [0130] As shown in Figs. 21 and 22, the multi-layer support structure has a predetermined distance outside the outer periphery of the bonding pad (351, 352) as well as the area below the bonding pad (351, 352). It can also be formed in the area below the range (350).
[0131] ボンディングパッド（351、 352)の外周よりも外側の所定距離の範囲（350)は特に 限定されない。後述するように、多層支持構造がボンディングパッドの外周よりも外側 の領域にまで広がっている場合における、ボンディングパッドの外縁から多層支持構 造の最外周までの距離と、ボンディングパッドとボンディングワイヤとの間の密着強度 との関係を調べたところ、 10 m程度の距離範囲までに多層支持構造を配置するこ とにより、ボンディングパッドの下方の領域のみに多層支持構造を形成した場合と比 較して、良好な密着強度の向上が観察されている。このため、所定距離の範囲（350 )として約 10 mを設定することにより、ボンディングパッドとボンディングワイヤとの間 の密着強度を向上させることができる。  [0131] The range (350) of the predetermined distance outside the outer periphery of the bonding pads (351, 352) is not particularly limited. As will be described later, when the multilayer support structure extends to a region outside the outer periphery of the bonding pad, the distance from the outer edge of the bonding pad to the outermost periphery of the multilayer support structure, and the distance between the bonding pad and the bonding wire. Investigation of the relationship with the adhesion strength between them revealed that the multilayer support structure was arranged within a distance range of about 10 m, compared to the case where the multilayer support structure was formed only in the area below the bonding pad. , Good improvement in adhesion strength has been observed. For this reason, by setting the range of the predetermined distance (350) to about 10 m, the adhesion strength between the bonding pad and the bonding wire can be improved.
[0132] なお、図 21は、隣接するボンディングパッド（351)間の間隔が 20 μ mである場合に 、ボンディングパッド（351)の外側 10 μ mの距離までの範囲（350)内に多層回線構 造を配置する例を示して ヽる。  FIG. 21 shows a case where the distance between adjacent bonding pads (351) is 20 μm, and the number of multilayer circuits within a range (350) of a distance of 10 μm outside the bonding pads (351) is increased. An example of arranging structures is shown.
[0133] 図 22は、隣接するボンディングパッド（352)間の間隔が 10 m未満である場合に 、ボンディングパッド（352)の外側 10 μ mの距離までの範囲（350)内に多層回線構 造を配置する例を示して ヽる。  [0133] FIG. 22 shows that, when the distance between adjacent bonding pads (352) is less than 10 m, a multilayer circuit structure within a range (350) up to a distance of 10 μm outside the bonding pads (352). An example of arranging is shown below.
[0134] また、多層支持構造の一部を形成する金属補強ビアパターン（1031)の半導体装 置の厚さ方向における長さは、半導体装置の厚さ方向における導電性金属ビア（10 30)の長さよりも大きくすることが可能である。これによつて、多層支持構造における 金属補強配線パターン（1025、 1029)との密着性の向上や層間絶縁膜の強度を向 上することが可能となり、ワイヤボンディング時の衝撃や応力に起因する膜剥がれや 膜破壊を防止することが可能となる。 [0134] Further, the semiconductor device of the metal reinforcing via pattern (1031) forming a part of the multilayer support structure is provided. The length of the device in the thickness direction can be larger than the length of the conductive metal via (1030) in the thickness direction of the semiconductor device. This makes it possible to improve the adhesion to the metal reinforcing wiring patterns (1025, 1029) in the multilayer support structure and improve the strength of the interlayer insulating film. Peeling and film destruction can be prevented.
[0135] また、半導体装置の横断面（図 20の紙面と直交する面）における金属補強ビアバタ ーン（1031)の形状は特に限定されるものではなぐ矩形、孔状、スリット状等各種の 形態をとり得る。例えば、金属補強ビアパターン（1031)の形状をスリット状とすること により、断面積を増やすことなぐ半導体装置の厚さ方向における導電性金属ビア（1 030)の長さを大き 、ものとすることができる。  [0135] The shape of the metal reinforcing via pattern (1031) in the cross section of the semiconductor device (the surface orthogonal to the paper surface of FIG. 20) is not particularly limited, and may be various shapes such as a rectangle, a hole, and a slit. Can be taken. For example, by making the shape of the metal reinforcing via pattern (1031) into a slit shape, it is possible to increase the length of the conductive metal via (1030) in the thickness direction of the semiconductor device without increasing the cross-sectional area. Can be.
[0136] また、第 2の態様に係る半導体装置においては、層間絶縁膜の単位面積当たりに 占める導電性金属ビア（1030)と金属補強ビアパターン（1031)との総面積の割合 力 ％以上であることが好ましぐ 10%以上であることがより好ましい。このような条件 を満たすように導電性金属ビア（1030)及び金属補強ビアパターン（1031)を形成 することにより、ボンディングワイヤとボンディングパッドとの間の密着強度を高めるこ とがでさる。  In the semiconductor device according to the second embodiment, the ratio of the total area of the conductive metal via (1030) and the metal reinforcing via pattern (1031) to the unit area of the interlayer insulating film is not less than power%. More preferably, it is more preferably 10% or more. By forming the conductive metal via (1030) and the metal reinforcing via pattern (1031) so as to satisfy such conditions, the adhesion strength between the bonding wire and the bonding pad can be increased.
[0137] なお、第 2の態様に係る半導体装置においても、層間絶縁膜材料、導電性金属配 線 (回路配線)、導電性金属ビア、補強配線パターン及び補強ビアを構成する導電 性材料、並びに、半導体基板の材料は何ら限定されるものではなぐ第 1の態様に係 る半導体装置において挙げたものと同様のものを用いることができる。  Note that also in the semiconductor device according to the second aspect, the interlayer insulating film material, the conductive metal wiring (circuit wiring), the conductive metal via, the reinforcing wiring pattern and the conductive material forming the reinforcing via, and The material of the semiconductor substrate is not limited at all, and the same materials as those described in the semiconductor device according to the first embodiment can be used.
[0138] また、第 2の態様に係る半導体装置において、導電性金属配線（1024、 1028)、 導電性金属ビア（1010)、金属補強配線パターン（1005、 1009)及び金属補強ビア パターン（1031)のそれぞれの配置位置や形状その他のファクタ一は、特に限定さ れるものではなぐ種々の態様を含み得るものである。例えば、導電性金属配線（10 24、 1028)の各配線層における大きさ、形状、配線数その他のファクタ一は任意の ちのとすることがでさる。  In the semiconductor device according to the second embodiment, the conductive metal wiring (1024, 1028), the conductive metal via (1010), the metal reinforcing wiring pattern (1005, 1009), and the metal reinforcing via pattern (1031) Each of the arrangement positions, shapes, and other factors may include various modes which are not particularly limited. For example, the size, shape, number of wirings, and other factors in each wiring layer of the conductive metal wirings (1024, 1028) can be arbitrary.
[0139] 例えば、図 20に示した実施形態に係る半導体装置においては、半導体装置の最 上層である第二配線層 (1027)には、ワイヤボンディングパッド（1040)の下方にお いては大面積の配線は存在しないが、ワイヤボンディングパッド（1040)の下方の領 域において、半導体装置の最上層、あるいは、上層のうちの複数層に、導電性金属 配線と同一材料で形成された大面積の配線層パッドを形成し、ボンディングパッド（ 1 040)を支持するよう〖こ構成することもできる。 For example, in the semiconductor device according to the embodiment shown in FIG. 20, the second wiring layer (1027), which is the uppermost layer of the semiconductor device, is provided below the wire bonding pad (1040). In the area below the wire bonding pad (1040), the uppermost layer of the semiconductor device, or a plurality of upper layers, is formed of the same material as the conductive metal wiring. A large-area wiring layer pad may be formed to support the bonding pad (104).
[0140] 第 2の態様に係る半導体装置の製造方法は、第 1の態様に係る半導体装置の場合 と同様に、特に限定されない。例えば、ダマシン法を用いて形成することが可能であ る。 [0140] The method for manufacturing the semiconductor device according to the second aspect is not particularly limited, as in the case of the semiconductor device according to the first aspect. For example, it can be formed using a damascene method.
(スクライブ領域における多層支持構造）  (Multilayer support structure in scribe area)
次に、本発明の第 3の態様に係る半導体装置は、半導体基板と、半導体基板上に 形成された少なくとも一つの層間絶縁膜と、層間絶縁膜を介して積層された複数の 配線層と、を備え、複数の配線層の各々に形成された回路配線と、層間絶縁膜を貫 通し、上下方向に隣接する回路配線を相互に接続する導電性金属ビアと、からなる 多層回路構造が形成されている半導体装置であって、半導体装置は、複数の配線 層の各々に設けられた補強配線パターンと、層間絶縁膜に設けられ、上下方向に隣 接する前記補強配線パターンを相互に接続する補強ビアパターンと、からなる多層 支持構造を備え、半導体装置は、多層回路構造が形成されている回路領域と、回路 領域の周囲の領域であって、回路が形成されていないスクライブ領域と、を有してお り、多層支持構造は前記スクライブ領域に形成されていることを特徴とする。  Next, a semiconductor device according to a third aspect of the present invention includes a semiconductor substrate, at least one interlayer insulating film formed on the semiconductor substrate, and a plurality of wiring layers stacked with the interlayer insulating film interposed therebetween. A multilayer circuit structure is formed, comprising: a circuit wiring formed in each of a plurality of wiring layers; and a conductive metal via penetrating an interlayer insulating film and interconnecting vertically adjacent circuit wirings. A reinforcing via provided on each of a plurality of wiring layers and a reinforcing via provided on an interlayer insulating film and interconnecting the reinforcing wiring patterns adjacent to each other in the up-down direction. The semiconductor device includes a circuit region in which the multilayer circuit structure is formed, and a scribe region which is a region around the circuit region and in which no circuit is formed. hand Here, the multilayer support structure is formed in the scribe area.
[0141] 図 23は、本発明の第 3の態様に係る半導体装置の一実施形態を示す模式的断面 図である。 FIG. 23 is a schematic cross-sectional view showing one embodiment of a semiconductor device according to the third aspect of the present invention.
[0142] 図 23に示す本実施形態に係る半導体装置は、半導体基板（1061)と、半導体基 板（1061)上に形成されたトランジスタ（1101)と、トランジスタ（1101)を覆って半導 体基板（1061)上に形成された絶縁膜（1062)と、絶縁膜（1062)上に形成された 第一配線層 (1063)と、第一配線層 (1063)上に形成された第一層間絶縁膜 (1064 )と、第一層間絶縁膜 (1064)上に形成された第二配線層（1065)と、第二配線層（1 065)上に形成された第二層間絶縁膜 (1066)と、第二層間絶縁膜 (1066)上に形 成された第三配線層 (1067)と、第三配線層 (1067)上に形成され、チップ外部と電 気信号の送受信を行う金属ワイヤボンディングパッド（1040)と、を備えている。 [0143] 第一配線層 (1063)は非導電性材料カゝらなり、第一配線層 (1063)には、回路領 域（1200)内において、回路配線となる導電性金属配線（1091)と、導電性金属配 線（1091)と同じ導電性物質力もなる金属補強配線パターン（1081、 1086)とが相 互に離間して形成されている。 The semiconductor device according to the present embodiment shown in FIG. 23 includes a semiconductor substrate (1061), a transistor (1101) formed on the semiconductor substrate (1061), and a semiconductor covering the transistor (1101). An insulating film (1062) formed on the substrate (1061), a first wiring layer (1063) formed on the insulating film (1062), and a first layer formed on the first wiring layer (1063) An interlayer insulating film (1064), a second wiring layer (1065) formed on the first interlayer insulating film (1064), and a second interlayer insulating film (1065) formed on the second wiring layer (1065). 1066), a third wiring layer (1067) formed on the second interlayer insulating film (1066), and a metal formed on the third wiring layer (1067) for transmitting and receiving electric signals to and from the outside of the chip. And a wire bonding pad (1040). The first wiring layer (1063) is made of a non-conductive material, and the first wiring layer (1063) has a conductive metal wiring (1091) serving as a circuit wiring in the circuit area (1200). And metal reinforcing wiring patterns (1081, 1086) having the same conductive material strength as the conductive metal wiring (1091) are formed apart from each other.
[0144] また、第一配線層 (1063)には、スクライブ領域（1300)内において、導電性金属 配線（1091)と同じ導電性物質力もなる金属補強配線パターン（1071)が形成され ている。  In the first wiring layer (1063), a metal reinforcing wiring pattern (1071) having the same conductive material strength as the conductive metal wiring (1091) is formed in the scribe region (1300).
[0145] 第二配線層 (1065)は非導電性材料カゝらなり、第二配線層 (1065)には、回路領 域（1200)内において、回路配線となる導電性金属配線（1093)と、導電性金属配 線（1093)と同じ物質力もなる金属補強配線パターン（1083、 1088)とが相互に離 間して形成されている。  The second wiring layer (1065) is made of a non-conductive material, and the second wiring layer (1065) has a conductive metal wiring (1093) serving as a circuit wiring in the circuit area (1200). And metal reinforcing wiring patterns (1083, 1088) having the same material strength as the conductive metal wiring (1093) are formed apart from each other.
[0146] また、第二配線層 (1065)には、スクライブ領域（1300)内において、導電性金属 配線（1093)と同じ導電性物質力もなる金属補強配線パターン（1073)が形成され ている。  In the second wiring layer (1065), a metal reinforcing wiring pattern (1073) having the same conductive material strength as that of the conductive metal wiring (1093) is formed in the scribe region (1300).
[0147] 第三配線層 (1067)は非導電性材料カゝらなり、第三配線層 (1067)には、回路領 域（1200)内において、回路配線となる導電性金属配線（1095)と、導電性金属配 線（1095)と同じ物質力もなる金属補強配線パターン（1085)とが相互に離間して形 成されている。  [0147] The third wiring layer (1067) is made of a non-conductive material, and the third wiring layer (1067) has a conductive metal wiring (1095) serving as a circuit wiring in the circuit area (1200). And a metal reinforcing wiring pattern (1085) having the same material strength as the conductive metal wiring (1095) are formed apart from each other.
[0148] また、第三配線層 (1067)には、スクライブ領域（1300)内において、導電性金属 配線（1095)と同じ導電性物質力もなる金属補強配線パターン（1075)が形成され ている。  In the third wiring layer (1067), a metal reinforcing wiring pattern (1075) having the same conductive material strength as the conductive metal wiring (1095) is formed in the scribe region (1300).
[0149] また、本実施形態に係る半導体装置においては、最上層の第三配線層 (1067)に 形成された導電性金属配線（1095)の一部が大面積のものとされ、大面積配線層パ ッド（1095B)を形成して！/、る。ワイヤボンディングパッド（1040)は大面積配線層パッ ド（1095B)の上部に形成されている。  In the semiconductor device according to the present embodiment, a part of the conductive metal wiring (1095) formed in the uppermost third wiring layer (1067) has a large area, and the large area wiring Form a layer pad (1095B)! / The wire bonding pad (1040) is formed above the large area wiring layer pad (1095B).
[0150] 第一配線層 (1063)と第二配線層 (1065)との間に挟まれた第一層間絶縁膜 (10 64)には、回路領域（1200)内において、第一及び第二配線層（1063、 1065)中に それぞれ設けられた導電性金属配線（1091、 1093)を相互に電気的に接続する導 電性金属ビア（1092)と、第一及び第二配線層（1063、 1065)中にそれぞれ設けら れた金属補強配線パターン（1081、 1083)が重なり合う領域を相互に電気的に接 続する金属補強ビアパターン（1082、 1087)と、が形成されている。金属補強ビアパ ターン（1082、 1087)は導電性金属ビア（1092)と同じ導電性物質で形成されてい る。 [0150] The first interlayer insulating film (1064) sandwiched between the first wiring layer (1063) and the second wiring layer (1065) has first and second layers in the circuit region (1200). Conductors for electrically connecting the conductive metal wires (1091, 1093) provided in the two wiring layers (1063, 1065), respectively. A metal that electrically connects an electrically conductive metal via (1092) and a region where the metal reinforcing wiring patterns (1081, 1083) provided in the first and second wiring layers (1063, 1065) respectively overlap each other. A reinforcing via pattern (1082, 1087) is formed. The metal reinforcing via patterns (1082, 1087) are formed of the same conductive material as the conductive metal via (1092).
[0151] また、第一層間絶縁膜（1064)には、スクライブ領域（1300)内において、第一及 び第二配線層（1063、 1065)中にそれぞれ設けられた金属補強配線パターン（10 71、 1073)が重なり合う領域を相互に電気的に接続する金属補強ビアパターン（10 72)が形成されている。  [0151] In the first interlayer insulating film (1064), the metal reinforcing wiring patterns (1010) provided in the first and second wiring layers (1063, 1065) in the scribe region (1300), respectively. A metal reinforcing via pattern (1072) for electrically connecting mutually overlapping regions with each other (71, 1073) is formed.
[0152] 第二配線層 (1065)と第三配線層 (1067)との間に挟まれた第二層間絶縁膜 (10 66)には、回路領域（1200)内において、第二及び第三配線層（1065、 1067)中に それぞれ設けられた導電性金属配線（1093、 1095)を相互に電気的に接続する導 電性金属ビア（1094)と、第二及び第三配線層（1065、 1067)中にそれぞれ設けら れた金属補強配線パターン（1083、 1085)が重なり合う領域を相互に電気的に接 続する金属補強ビアパターン（1084、 1089)と、が形成されている。金属補強ビアパ ターン（1084、 1089)は導電性金属ビア（1094)と同じ導電性物質で形成されてい る。  [0152] The second interlayer insulating film (1066) sandwiched between the second wiring layer (1065) and the third wiring layer (1067) has the second and third wiring layers in the circuit region (1200). A conductive metal via (1094) for electrically connecting the conductive metal wirings (1093, 1095) provided in the wiring layers (1065, 1067) to each other; and second and third wiring layers (1065, 1065). 1067) are provided with metal reinforcing via patterns (1084, 1089) for electrically connecting mutually overlapping regions provided with metal reinforcing wiring patterns (1083, 1085). The metal reinforcing via patterns (1084, 1089) are formed of the same conductive material as the conductive metal via (1094).
[0153] また、第二層間絶縁膜（1066)には、スクライブ領域（1300)内において、第二及 び第三配線層（1065、 1067)中にそれぞれ設けられた金属補強配線パターン（10 73、 1075)が重なり合う領域を相互に電気的に接続する金属補強ビアパターン（10 74)が形成されている。  In the second interlayer insulating film (1066), the metal reinforcing wiring patterns (10 73) provided in the second and third wiring layers (1065, 1067) in the scribe region (1300), respectively. , 1075) are formed with a metal reinforcing via pattern (1074) for electrically connecting mutually overlapping regions to each other.
[0154] 図 23に示す実施形態に係る半導体装置においては、回路領域（1200)内のワイ ャボンディングパッド（1040)の下方において、本半導体装置の厚さ方向に積み重 ねられた導電性金属配線（1091、 1093、 1095)と、導電性金属ビア（1092、 1094 )と、力 多層回路構造が形成されている。  In the semiconductor device according to the embodiment shown in FIG. 23, the conductive metal stacked in the thickness direction of the semiconductor device below the wire bonding pad (1040) in the circuit region (1200) Wirings (1091, 1093, 1095), conductive metal vias (1092, 1094), and a multi-layer circuit structure are formed.
[0155] さらに、回路領域（1200)内において、本半導体装置の厚さ方向に積み重ねられ た金属補強配線パターン（1081、 1083、 1085)と、これらを相互に連結する金属補 強ビアパターン（1082、 1084)と、力も多層支持構造が形成されている。多層支持 構造は、多層回路構造が形成されている回路領域における間隙部に存在している。 すなわち、多層支持構造は、多層回路構造が形成されている回路領域（1200)の内 部において、多層回路構造と抵触しないように、多層回路構造が存在しない領域に 形成されている。 Further, in the circuit region (1200), the metal reinforcing wiring patterns (1081, 1083, 1085) stacked in the thickness direction of the semiconductor device and the metal reinforcing via patterns (1082) interconnecting them. , 1084), the force also forms a multilayer support structure. Multi-layer support The structure exists in a gap in a circuit region where the multilayer circuit structure is formed. That is, the multilayer support structure is formed in a region where the multilayer circuit structure does not exist so as not to conflict with the multilayer circuit structure inside the circuit region (1200) where the multilayer circuit structure is formed.
[0156] また、スクライブ領域（1300)内においても、本半導体装置の厚さ方向に積み重ね られた金属補強配線パターン（1071、 1073、 1075)と、これらを相互に連結する金 属補強ビアパターン（1072、 1074)と、によっても多層支持構造が形成されている。  In the scribe area (1300), the metal reinforcing wiring patterns (1071, 1073, 1075) stacked in the thickness direction of the semiconductor device and the metal reinforcing via patterns (107, 1073, 1075) interconnecting the metal reinforcing wiring patterns (1071, 1073, 1075) are also provided. 1072, 1074) also form a multilayer support structure.
[0157] さらに、回路領域（1200)内におけるワイヤボンディングパッド（1040)の下方の領 域においても、第一及び第二配線層（1063、 1065)にそれぞれ設けられた金属補 強配線パターン（1086、 1088)と、第一層間絶縁膜（1064)に設けられ、金属補強 配線パターン（1086、 1088)が相互に重なり合った領域を電気的に接続する金属 補強ビアパターン（1087)と、第二層間絶縁膜 (1066)に設けられ、金属補強配線パ ターン（1088)を上部の大面積配線層パッド（1095B)に支持する金属補強ビアバタ ーン（1089)と、力もなる多層支持構造が設けられている。  [0157] Further, also in a region below the wire bonding pad (1040) in the circuit region (1200), the metal reinforcing wiring pattern (1086) provided on the first and second wiring layers (1063, 1065) respectively. , 1088), a metal reinforcing via pattern (1087) provided on the first interlayer insulating film (1064), and electrically connecting regions where the metal reinforcing wiring patterns (1086, 1088) overlap each other; A metal reinforced via pattern (1089) is provided on the interlayer insulating film (1066) and supports the metal reinforced wiring pattern (1088) on the large area wiring layer pad (1095B) on the top, and a multi-layered support structure is provided. ing.
[0158] ここで、図 24は、図 23に示す実施形態に係る半導体装置における回路領域（120 0)とスクライブ領域（1300)との位置関係を模式的に示す平面図であり、図 25は、図 24に示した領域 Bの拡大平面図である。  Here, FIG. 24 is a plan view schematically showing a positional relationship between the circuit region (1200) and the scribe region (1300) in the semiconductor device according to the embodiment shown in FIG. 23, and FIG. 25 is an enlarged plan view of a region B shown in FIG.
[0159] 図 23、図 24及び図 25に示すように、半導体装置におけるスクライブ領域（1300)と は、導電性金属配線（1091、 1093、 1095)、及び導電性金属ビア（1092、 1094) によって形成される多層回路構造が存在する回路領域（ 1200) (ワイヤボンディング ノッド（1040)の下方の領域を含む)よりも外側に位置し、回路領域（ 1200)の外周 縁と半導体チップの周縁端部 Eとの間の領域を指す。一般に、スクライブ領域（1300 )には回路は存在しない。  As shown in FIG. 23, FIG. 24 and FIG. 25, the scribe region (1300) in the semiconductor device is defined by the conductive metal wiring (1091, 1093, 1095) and the conductive metal via (1092, 1094). It is located outside the circuit area (1200) (including the area below the wire bonding nod (1040)) where the multilayer circuit structure to be formed exists, and the outer peripheral edge of the circuit area (1200) and the peripheral edge of the semiconductor chip. Refers to the area between E and Generally, there are no circuits in the scribe area (1300).
[0160] なお、図 25にお ヽて、半導体チップの一角に存在する符合 Xで示される部位は「十 字マーク」を表すものである。この十字マーク Xは、図 26に模式的に示すように、チッ プ切断前のウェハ上においては、文字通り、十字形をなすものであって、ウェハをダ イシングする際のァライメント（目合わせ）に用いられるマークである。ダイシング後の 各半導体チップ（半導体装置）においては、図 25に示すようなほぼ L形の形状として 、半導体チップの四隅に残存する。 [0160] In FIG. 25, the portion indicated by the symbol X existing in one corner of the semiconductor chip represents a "cross-shaped mark". As schematically shown in FIG. 26, the cross mark X has a cross shape literally on the wafer before chip cutting, and is used for alignment when dicing the wafer. This is the mark used. Each semiconductor chip (semiconductor device) after dicing has an almost L-shaped shape as shown in FIG. , And remain at the four corners of the semiconductor chip.
[0161] 図 23、図 24及び図 25に示す本実施形態に係る半導体装置においては、このよう な回路領域（1200)よりも外側の領域であるスクライブ領域（1300)において、第一 乃至第三配線層（1063、 1065、 1067)にそれぞれ形成された金属補強配線バタ ーン（1071、 1073、 1075)と、第一及び第二層間絶縁膜（1064、 1066)中にそれ ぞれ形成され、金属補強配線パターン（1071、 1073、 1075)を相互に電気的に接 続する金属補強ビアパターン（1072、 1074)と、からなる多層支持構造が形成され ている。 In the semiconductor device according to the present embodiment shown in FIGS. 23, 24, and 25, the first to third scribe regions (1300) outside the circuit region (1200) are located. Metal reinforcing wiring patterns (1071, 1073, 1075) formed on the wiring layers (1063, 1065, 1067), and first and second interlayer insulating films (1064, 1066), respectively; A multi-layered support structure composed of metal reinforcing via patterns (1072, 1074) for electrically connecting the metal reinforcing wiring patterns (1071, 1073, 1075) to each other is formed.
[0162] 本実施形態に係る半導体装置にお!ヽては、多層支持構造を形成する補強配線パ ターン（1071、 1073、 1075)と、同一の配線層に存在する導電性金属配線（1091 、 1093、 1095)とは同一の導電性材料で形成され、さらに、多層支持構造を形成す る金属補強ビアパターン（1072、 1074)と、同一の層間絶縁膜に存在する導電性金 属ビア（1092、 1094)とは同一の導電性材料で形成されている力 必ずしもこれに は限定されない。補強配線パターン（1071、 1073、 1075)と導電性金属配線（109 1、 1093、 1095)は相互に異なる材料によって形成されていても良ぐまた、同一の 層間絶縁膜に存在する金属補強ビアパターン（1072、 1074)と導電性金属ビア（10 92、 1094)とは相互に異なる導電性材料によって形成されていても良い。し力しなが ら、同一の材料で形成することにより、製造プロセスにおける工程数を少なくすること ができるというメリットがある。  In the semiconductor device according to the present embodiment, the reinforcing wiring patterns (1071, 1073, 1075) forming the multilayer support structure and the conductive metal wirings (1091, 1093, 1095) are formed of the same conductive material, and furthermore, the metal reinforcing via patterns (1072, 1074) forming the multilayer support structure and the conductive metal vias (1092) existing in the same interlayer insulating film are formed. , 1094) is not necessarily limited to the force formed of the same conductive material. The reinforcing wiring pattern (1071, 1073, 1075) and the conductive metal wiring (1091, 1093, 1095) may be formed of mutually different materials. Also, metal reinforcing via patterns existing in the same interlayer insulating film The (1072, 1074) and the conductive metal vias (1092, 1094) may be formed of mutually different conductive materials. However, there is an advantage in that the number of steps in the manufacturing process can be reduced by forming the same material while using force.
[0163] また、本実施形態に係る半導体製造装置において、スクライブ領域（1300)におけ る多層支持構造の配置位置は特に限定されるわけではなぐスクライブ領域（1300) 内の任意の位置に配置することができる力 半導体チップの各角部、すなわち、図 2 5に示すように、十字マーク Xの下方の領域に多層支持構造を配置することが望まし い。  In the semiconductor manufacturing apparatus according to the present embodiment, the position of the multilayer support structure in the scribe region (1300) is not particularly limited, and is arranged at an arbitrary position in the scribe region (1300). Possible Force It is desirable to dispose the multilayer support structure at each corner of the semiconductor chip, that is, in the region below the cross mark X as shown in FIG.
[0164] このような十字マーク Xの下方の領域は半導体チップの角部になるため、応力が最 も集中しやすぐ例えば、榭脂封入時等に膜剥がれが発生しやすい。このため、十字 マーク Xの下方の領域に多層支持構造を形成することによって、半導体チップの角 部における強度及び密着性を高めることが可能となり、信頼性の高い半導体装置を 提供することが可能となる。 [0164] Since the area below the cross mark X is the corner of the semiconductor chip, the stress is most concentrated and the film is likely to be peeled off immediately when, for example, resin is sealed. For this reason, by forming a multilayer support structure in the region below the cross mark X, it is possible to increase the strength and adhesion at the corners of the semiconductor chip, and to achieve a highly reliable semiconductor device. Can be provided.
[0165] 図 27は、本発明の第 3の態様に係る半導体装置の別の実施形態を示す模式的断 面図であり、図 28は、図 27に示す半導体装置における回路領域とスクライブ領域と の位置関係を模式的に示す平面図であり、図 29は、図 28に示した領域 Eの拡大平 面図である。 FIG. 27 is a schematic cross-sectional view showing another embodiment of the semiconductor device according to the third aspect of the present invention. FIG. 28 shows a circuit region and a scribe region in the semiconductor device shown in FIG. 29 is a plan view schematically showing the positional relationship of FIG. 29, and FIG. 29 is an enlarged plan view of a region E shown in FIG.
[0166] 図 27に示す実施形態に係る半導体装置は、図 23、図 24及び図 25に示す実施形 態に係る半導体装置と比較して、ワイヤボンディングパッド（1040)が形成されている 位置よりもチップ外周縁側の回路領域、すなわち、ワイヤボンディングパッド（1040) の外側とスクライブ領域（1300)との間にシールド（1100)が形成されている点が異 なる。  The semiconductor device according to the embodiment shown in FIG. 27 differs from the semiconductor devices according to the embodiment shown in FIGS. 23, 24 and 25 from the position where the wire bonding pad (1040) is formed. The difference is also that a shield (1100) is formed between a circuit region on the outer peripheral side of the chip, that is, the outside of the wire bonding pad (1040) and the scribe region (1300).
[0167] シールド（1100)は、金属補強配線パターンと金属補強ビアパターンとが積層され た積層体力 なる。  [0167] The shield (1100) has a laminated body strength in which a metal reinforcing wiring pattern and a metal reinforcing via pattern are stacked.
[0168] シールド（1100)は、図 29に示すように、半導体チップの外周縁に沿って全周にわ たって連続的に配置されている。このため、半導体装置の外部から回路領域（1200 )への水分の侵入を有効に阻止することができる。さらに、シールド（1100)は金属補 強配線パターンと金属補強ビアパターンとからなる多層支持構造でもあるため、半導 体チップの外周縁部における強度及び密着性を高める作用も併せて発揮する。  [0168] As shown in FIG. 29, the shield (1100) is arranged continuously over the entire periphery along the outer peripheral edge of the semiconductor chip. Therefore, it is possible to effectively prevent moisture from entering the circuit region (1200) from outside the semiconductor device. Further, since the shield (1100) is also a multilayer support structure including a metal reinforcing wiring pattern and a metal reinforcing via pattern, it also exerts an effect of increasing the strength and adhesion at the outer peripheral edge of the semiconductor chip.
[0169] 本発明の第 3の態様に係る半導体装置においては、多層支持構造は少なくともスク ライブ領域（1300)に設けられていればよぐこの条件を満足する限りにおいて、多 層支持構造の形成領域に関しては、次のような実施形態をとり得る。  [0169] In the semiconductor device according to the third aspect of the present invention, the multilayer support structure may be formed at least in the scribe region (1300) as long as the condition is satisfied. Regarding the area, the following embodiment can be adopted.
(1)スクライブ領域（1300)、回路領域（1200)及びワイヤボンディングパッド（1040) の下方の領域のすべてに多層支持構造を形成する実施形態  (1) An embodiment in which a multilayer support structure is formed in all of the area under the scribe area (1300), the circuit area (1200), and the wire bonding pad (1040).
(2)スクライブ領域（1300)のみに多層支持構造が形成され、回路領域（1200)及び ワイヤボンディングパッド（1040)の下方の領域には多層支持構造が形成されていな い実施形態  (2) An embodiment in which the multilayer support structure is formed only in the scribe area (1300) and the multilayer support structure is not formed in the area below the circuit area (1200) and the wire bonding pad (1040).
(3)スクライブ領域（1300)及びワイヤボンディングパッド（1040)の下方の領域に多 層支持構造が形成され、回路領域（1200)には多層支持構造が形成されていない 実施形態 (4)スクライブ領域（1300)及び回路領域（1200)に多層支持構造が形成され、ワイ ャボンディングパッド（1040)の下方の領域には多層支持構造が形成されていない 実施形態。 (3) A multilayer support structure is formed in a region below the scribe region (1300) and the wire bonding pad (1040), and a multilayer support structure is not formed in the circuit region (1200). (4) An embodiment in which a multi-layer support structure is formed in the scribe area (1300) and the circuit area (1200), and the multi-layer support structure is not formed in a region below the wire bonding pad (1040).
[0170] 本発明の第 1の態様に係る半導体装置において、前述の本発明の第 1及び第 2の 態様に係る半導体装置と同様に、多層支持構造は、半導体装置の厚さ方向におい て、半導体基板（1061)上に積層される複数の配線層及び層間絶縁膜のうちの少な くとも 2層以上にわたって形成されていれば良い。  [0170] In the semiconductor device according to the first aspect of the present invention, like the semiconductor devices according to the above-described first and second aspects of the present invention, the multilayer support structure has a structure in the thickness direction of the semiconductor device. It is sufficient that at least two or more of a plurality of wiring layers and interlayer insulating films stacked on the semiconductor substrate (1061) are formed.
[0171] また、この多層支持構造は、導電性金属配線（1091、 1093、 1095)及び導電性 金属ビア（1092、 1094)力もなる多層回路構造またはワイヤボンディングパッド（104 0)から電気的に絶縁されたものであってもよぐあるいは、多層回路構造またはワイ ャボンディングパッド（1040)に電気的に接続されたものでもあっても良い。  [0171] Further, the multilayer support structure is electrically insulated from the multilayer circuit structure or the wire bonding pad (1040) that also has the force of the conductive metal wiring (1091, 1093, 1095) and the conductive metal via (1092, 1094). It may be one that is electrically connected to a multilayer circuit structure or a wire bonding pad (1040).
[0172] 但し、多層回路構造に電気的に接続される場合であっても、多層支持構造は、そ の一端部のみにぉ 、て多層回路構造に接続され、他端部にお 、ては多層回路構造 とは電気的に隔離される、すなわち、電気的に接地される。また、スクライブ領域（13 00)においても、半導体基板（1061)に素子分離領域（1016)が設けられている場 合には、本発明の第 1の態様に係る半導体装置と同様に、多層支持構造は素子分 離領域（1016)に接続させることができる。  [0172] However, even when electrically connected to the multilayer circuit structure, the multilayer support structure is connected to the multilayer circuit structure only at one end thereof, and is electrically connected at the other end. The multilayer circuit structure is electrically isolated, that is, electrically grounded. Also in the scribe region (1300), when the element isolation region (1016) is provided in the semiconductor substrate (1061), similarly to the semiconductor device according to the first embodiment of the present invention, the multi-layer support is provided. The structure can be connected to the element isolation region (1016).
[0173] また、多層支持構造は、本半導体装置の最上層である第三配線層（1067)力も半 導体基板（1061)まで延長されたものであってもよぐあるいは、複数の配線層及び 層間絶縁膜からなる積層体の内部にぉ 、て終端して 、るものであってもよ!/、。  [0173] Further, the multilayer support structure may be configured such that the force of the third wiring layer (1067), which is the uppermost layer of the present semiconductor device, is also extended to the semiconductor substrate (1061), or a plurality of wiring layers and It may be one that terminates inside the laminated body composed of the interlayer insulating film.
[0174] また、本発明の第 1及び第 2の態様に係る半導体装置と同様に、多層支持構造の 一部を形成する金属補強ビアパターン（1082、 1084)の半導体装置の厚さ方向に おける長さは、半導体装置の厚さ方向における導電性金属ビア（1092、 1094)の長 さよりも大きくすることが可能である。これによつて、多層支持構造における金属補強 配線パターン（1081、 1083、 1085)との密着性の向上や層間絶縁膜の強度を向上 することが可能となり、ダイシング時ゃワイヤボンディング時の衝撃や応力に起因する 膜剥がれや膜破壊を防止することが可能となる。  Further, similarly to the semiconductor device according to the first and second embodiments of the present invention, the metal reinforcing via pattern (1082, 1084) forming a part of the multilayer support structure in the thickness direction of the semiconductor device. The length can be larger than the length of the conductive metal via (1092, 1094) in the thickness direction of the semiconductor device. This makes it possible to improve the adhesion to the metal-reinforced wiring patterns (1081, 1083, 1085) and the strength of the interlayer insulating film in the multi-layered support structure. It is possible to prevent film peeling and film destruction due to the above.
[0175] また、半導体装置の横断面（図 23、図 27の紙面と直交する面）における金属補強 ビアパターン（1082、 1084)の形状は特に限定されるものではなぐ矩形、孔状、ス リット状等各種の形態をとり得る。例えば、金属補強ビアパターン（1082、 1084)の 形状をスリット状とすることにより、断面積を増やすことなぐ半導体装置の厚さ方向に おける導電性金属ビア（1092、 1094)の長さを大きいものとすることができる。 [0175] Further, the metal reinforcement in the cross section of the semiconductor device (the surface orthogonal to the paper surface in FIGS. 23 and 27) The shape of the via pattern (1082, 1084) is not particularly limited, and may take various forms such as a rectangle, a hole, and a slit. For example, by making the shape of the metal reinforcing via pattern (1082, 1084) into a slit shape, it is possible to increase the length of the conductive metal via (1092, 1094) in the thickness direction of the semiconductor device without increasing the cross-sectional area. It can be.
[0176] また、第 3の態様に係る半導体装置においては、スクライブ領域（1300)における 層間絶縁膜の単位面積当たりに占める金属補強ビアパターン（1072、 1074)の総 面積の割合が 5%以上であることが好ましぐ 10%以上であることがより好ましい。こ のような条件を満たすように金属補強ビアパターン（1072、 1074)を形成することに より、ボンディングワイヤとボンディングパッドとの間の密着強度を高めることができる。  In the semiconductor device according to the third aspect, the ratio of the total area of the metal reinforcing via patterns (1072, 1074) to the unit area of the interlayer insulating film in the scribe region (1300) is 5% or more. More preferably, it is more preferably 10% or more. By forming the metal reinforcing via pattern (1072, 1074) so as to satisfy such a condition, the adhesion strength between the bonding wire and the bonding pad can be increased.
[0177] なお、第 3の態様に係る半導体装置においても、層間絶縁膜材料、導電性金属配 線 (回路配線)、導電性金属ビア、補強配線パターン及び補強ビアを構成する導電 性材料、並びに、半導体基板の材料は何ら限定されるものではなぐ第 1の態様に係 る半導体装置において挙げたものと同様のものを用いることができる。  The semiconductor device according to the third aspect also includes an interlayer insulating film material, a conductive metal wiring (circuit wiring), a conductive metal via, a reinforcing wiring pattern, a conductive material forming a reinforcing via, and The material of the semiconductor substrate is not limited at all, and the same materials as those described in the semiconductor device according to the first embodiment can be used.
[0178] 第 3の態様に係る半導体装置の製造方法は、第 1の態様に係る半導体装置の場合 と同様に、特に限定されない。例えば、ダマシン法を用いて形成することが可能であ る。  The method for manufacturing a semiconductor device according to the third embodiment is not particularly limited, as in the case of the semiconductor device according to the first embodiment. For example, it can be formed using a damascene method.
実施例  Example
[0179] 以下、本発明の具体的構成を実施例に基づいて、より詳細に説明するが、本発明 はこれらの実施例に何ら限定されるものではない。  [0179] Hereinafter, specific configurations of the present invention will be described in more detail based on examples, but the present invention is not limited to these examples.
(実施例 1)  (Example 1)
図 30は上述の本発明の第 1の態様に係る半導体装置の一実施例の断面図である  FIG. 30 is a sectional view of one embodiment of the semiconductor device according to the first aspect of the present invention described above.
[0180] 以下、図 30を参照して、本発明の第 1の態様に係る半導体装置の一実施例を説明 する。 Hereinafter, an example of the semiconductor device according to the first embodiment of the present invention will be described with reference to FIG.
[0181] 図 30に示すように、本実施例に係る半導体装置は、半導体基板（111)と、半導体 基板（ 111)上に形成された絶縁膜 (112)とを備えて!/、る。  As shown in FIG. 30, the semiconductor device according to this example includes a semiconductor substrate (111) and an insulating film (112) formed on the semiconductor substrate (111).
[0182] 本実施例にお!、ては、半導体基板（111)は単結晶シリコン基板である。 In this example, the semiconductor substrate (111) is a single crystal silicon substrate.
[0183] また、絶縁膜（112)はボロフォスフオシリケート'ガラス（BPSG : borophosphosilic ate glass)、フォスフオシリケート'ガラス（PSG： phosphosilicate glass)、酸ィ匕シリ コン（SiO )、窒化シリコン（SiN)、酸窒化シリコン（SiON)、酸弗化シリコン（SiOF)、 [0183] The insulating film (112) is made of borophosphosilicate 'glass (BPSG: borophosphosilic). ate glass), phosphosilicate glass (PSG: phosphosilicate glass), silicon oxide silicon (SiO 2), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxyfluoride (SiOF),
2  2
炭化シリコン (SiC)、炭窒化シリコン（SiCN)等の絶縁材料またはそれらの組み合わ せから構成されている。  It is composed of insulating materials such as silicon carbide (SiC) and silicon carbonitride (SiCN) or a combination thereof.
[0184] 絶縁膜（112)上には、第一配線層（113)が形成されている。 [0184] A first wiring layer (113) is formed on the insulating film (112).
[0185] 本実施例においては、第一配線層 (113)は低誘電率材料の有機ポリマー、 MSQIn this embodiment, the first wiring layer (113) is made of an organic polymer of a low dielectric constant material, MSQ
、 HSQまたは炭素含有シリコン酸ィ匕膜である力 エッチングストッパー及びノヽードマ スクをなす SiN、 SiOC、 SiC、 SiCN, SiO等との積層膜力も構成することもできる。 , HSQ or a carbon-containing silicon oxide film. A stacked film strength with SiN, SiOC, SiC, SiCN, SiO, etc. forming an etching stopper and a node mask can also be formed.
2  2
[0186] 第一配線層 (113)には、回路を電気的に接続する金属回路配線 (または、導電性 金属配線）（115)と、回路とは電気的な接続を持たない金属補強配線パターン（116 )と、が形成されている。  [0186] The first wiring layer (113) includes a metal circuit wiring (or a conductive metal wiring) (115) for electrically connecting a circuit and a metal reinforcing wiring pattern having no electrical connection to the circuit. (116) are formed.
[0187] 第一配線層（113)上には、第一層間絶縁膜（117)が形成されている。  [0187] On the first wiring layer (113), a first interlayer insulating film (117) is formed.
[0188] 第一層間絶縁膜（117)中には、上下の金属回路配線（115、 121)を相互に電気 的に接続する導電性金属ビア（118)と、上下の金属補強配線パターンを接続する金 属補強ビアパターン（119)と、が形成されている。  In the first interlayer insulating film (117), a conductive metal via (118) for electrically connecting the upper and lower metal circuit wirings (115, 121) to each other, and an upper and lower metal reinforcing wiring pattern are provided. A metal reinforcing via pattern (119) to be connected is formed.
[0189] 本実施例においては、第一層間絶縁膜（117)は低誘電率材料の有機ポリマー、 MSQ、 HSQまたは炭素含有シリコン酸ィ匕膜である力 エッチングストッパー及びノヽ ードマスクをなす SiC、 SiCN, SiO等との積層膜から構成することもできる。  In this embodiment, the first interlayer insulating film (117) is made of an organic polymer of low dielectric constant material, MSQ, HSQ, or a silicon-containing film containing carbon. It can also be composed of a laminated film of SiCN, SiO, etc.
2  2
[0190] 第一層間絶縁膜（117)上には、第二配線層（120)が形成されている。  [0190] On the first interlayer insulating film (117), a second wiring layer (120) is formed.
[0191] 第二配線層（120)中には、金属回路配線（121)と、金属補強配線パターン（122) と、が形成されている。 [0191] In the second wiring layer (120), a metal circuit wiring (121) and a metal reinforcing wiring pattern (122) are formed.
[0192] 本実施例においては、第二配線層 (120)は低誘電率材料の有機ポリマー、 MSQ 、 HSQまたは炭素含有シリコン酸ィ匕膜である力 エッチングストッパー及びノヽードマ スクをなす SiN、 SiOC、 SiC、 SiCN, SiO等との積層膜力も構成することもできる。  In the present embodiment, the second wiring layer (120) is made of an organic polymer of a low dielectric constant material, MSQ, HSQ, or a silicon-oxide film containing carbon. Etching stopper and SiN, SiOC forming a node mask. , SiC, SiCN, SiO, etc. can also be configured.
2  2
[0193] このように、配線層と層間絶縁膜とが交互に積層されることにより、多層回路構造が 形成されている。  [0193] As described above, a multilayer circuit structure is formed by alternately stacking the wiring layers and the interlayer insulating films.
[0194] 金属補強ビアパターン（119)は第一及び第二配線層（113、 120)の金属補強配 線パターン（116、 122)を相互に接続することにより、多層支持構造を形成している [0195] 図 31は、本実施例に係る半導体装置の平面図である。 The metal reinforcing via pattern (119) forms a multilayer support structure by connecting the metal reinforcing wiring patterns (116, 122) of the first and second wiring layers (113, 120) to each other. FIG. 31 is a plan view of the semiconductor device according to the present embodiment.
[0196] 図 31に示すように、第一及び第二配線層（113、 120)において金属補強配線バタ ーン（116、 122)の形状や位置が異なる場合には、金属補強ビアパターン（119)は 金属補強配線パターン（ 116、 122)が重なり合う領域（ 123)のみを接続するように配 置される。このため、従来力も形成されている CMP用ダミーパターンの寸法、形状を 変化させることなぐすなわち、チップの面積を増大させることなぐ金属補強ビアバタ ーン（ 119)を導入することができる。  As shown in FIG. 31, when the shapes and positions of the metal reinforcing wiring patterns (116, 122) are different in the first and second wiring layers (113, 120), the metal reinforcing via patterns (119 ) Are arranged so as to connect only the region (123) where the metal reinforcing wiring patterns (116, 122) overlap. For this reason, it is possible to introduce a metal reinforcing via pattern (119) that does not change the size and shape of the CMP dummy pattern, which is also conventionally formed, that is, does not increase the chip area.
[0197] 図 30に示すような構造を用いることにより、模擬的に、 LSIの強度、密着性を増大さ せることが可能となり、化学機械研磨（CMP)プロセスの際やチップパッケージング時 に印加される衝撃や応力に起因して生じる膜剥がれや膜破壊を防止することが可能 となる。  [0197] By using the structure as shown in Fig. 30, it is possible to simulate the increase in the strength and adhesion of the LSI, and to apply it during the chemical mechanical polishing (CMP) process and during chip packaging. It is possible to prevent film peeling and film destruction caused by the applied shock and stress.
[0198] 図 32は、低誘電率膜を層間絶縁膜に用いた場合の金属補強ビアパターンの面積 占有率 (半導体装置の単位面積に対する金属補強ビアパターンの面積が占める割 合）と CMP時の膜剥がれの割合との関係を示すグラフである。  [0198] FIG. 32 shows the area occupancy of the metal-reinforced via pattern (the ratio of the area of the metal-reinforced via pattern to the unit area of the semiconductor device) when the low-dielectric-constant film is used as the interlayer insulating film, and the CMP occupancy. It is a graph which shows the relationship with the rate of film peeling.
[0199] 金属補強ビアパターンが存在しない場合 (ビア占有率 =0%)には膜剥がれが 100 %の割合で発生しているのに対して、金属補強ビアパターンがチップ内に 5%以上 存在することにより、膜剥がれの割合を大幅に減少させることが可能となる。  [0199] When there is no metal reinforcing via pattern (via occupancy = 0%), film peeling occurs at a rate of 100%, whereas metal reinforcing via patterns exist in the chip at 5% or more. By doing so, it is possible to greatly reduce the rate of film peeling.
[0200] なお、図 30に示した半導体装置においては、導電性金属ビア（118)と導電性金属 配線（115、 121)を別々に形成するシングルダマシンプロセスを用いている力 導電 性金属ビア（118)と導電性金属配線（121)とを同時に形成するデュアルダマシンプ 口セスを用いることも可能である。  [0200] In the semiconductor device shown in FIG. 30, the force conductive metal via (118) and the conductive metal via (115, 121) formed separately using a single damascene process are used. It is also possible to use a dual damascene process for simultaneously forming 118) and the conductive metal wiring (121).
(実施例 2)  (Example 2)
図 33は上述の本発明の第 2の態様に係る半導体装置の一実施例の断面図である  FIG. 33 is a cross-sectional view of one embodiment of the semiconductor device according to the second aspect of the present invention described above.
[0201] 以下、図 33を参照して、本発明の第 2の態様に係る半導体装置の一実施例を説明 する。 Hereinafter, an example of the semiconductor device according to the second embodiment of the present invention will be described with reference to FIG.
[0202] 図 33に示すように、本実施例に係る半導体装置は、半導体基板 (211)と、半導体 基板 (211)上に形成された絶縁膜 (212)とを備えている。 As shown in FIG. 33, the semiconductor device according to this example includes a semiconductor substrate (211) and a semiconductor substrate (211). An insulating film (212) formed on a substrate (211).
[0203] 本実施例にお!、ては、半導体基板 (211)は単結晶シリコン基板である。 In this embodiment, the semiconductor substrate (211) is a single crystal silicon substrate.
[0204] 絶縁膜（212)は、ボロフォスフオシリケート'ガラス（BPSG :borophosphosilicate glass)、フォスフオシリケート'ガラス（PSG： phosphosilicate glass)、酸ィ匕シリコ ン（SiO )、窒化シリコン（SiN)、酸窒化シリコン（SiON)、酸弗化シリコン（SiOF)、[0204] The insulating film (212) is made of borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), phosphosilicate glass (PSG), silicon oxide (SiO 2), silicon nitride (SiN), Silicon oxynitride (SiON), silicon oxyfluoride (SiOF),
2 2
炭化シリコン (SiC)、炭窒化シリコン（SiCN)等の絶縁膜またはそれらの組み合わせ から構成されている。  It is composed of insulating films such as silicon carbide (SiC) and silicon carbonitride (SiCN), or a combination thereof.
[0205] 絶縁膜 (212)上に第一配線層 (213)が形成されている。 [0205] The first wiring layer (213) is formed on the insulating film (212).
[0206] 本実施例においては、第一配線層 (213)は低誘電率材料の有機ポリマー、 MSQ 、 HSQまたは炭素含有シリコン酸ィ匕膜である力 エッチングストッパー及びノヽードマ スクをなす SiN、 SiOC、 SiC、 SiCN, SiO等との積層膜力も構成することもできる。  In this embodiment, the first wiring layer (213) is made of an organic polymer of low dielectric constant material, MSQ, HSQ, or a silicon-containing silicon oxide film. Etching stopper and SiN, SiOC forming a node mask are used. , SiC, SiCN, SiO, etc. can also be configured.
2  2
[0207] 第一配線層 (213)には、回路を電気的に接続する金属回路配線 (または、導電性 金属配線）（215)と、回路とは電気的な接続を持たない金属ダミー配線 (216)と、が 形成されている。  The first wiring layer (213) includes a metal circuit wiring (or a conductive metal wiring) (215) for electrically connecting a circuit and a metal dummy wiring ( 216) is formed.
[0208] 第一配線層（213)上には、第一層間絶縁膜 (217)が形成されている。  [0208] On the first wiring layer (213), a first interlayer insulating film (217) is formed.
[0209] 第一層間絶縁膜 (217)中には、上下の金属回路配線（215、 219)を相互に電気 的に接続する導電性金属ビア（224)と、上下の金属補強配線パターンを接続する金 属補強ビアパターン (225)と、が形成されている。  In the first interlayer insulating film (217), a conductive metal via (224) for electrically connecting the upper and lower metal circuit wirings (215, 219) to each other, and an upper and lower metal reinforcing wiring pattern are provided. A metal reinforcing via pattern (225) to be connected is formed.
[0210] 本実施例においては、第一層間絶縁膜 (217)は低誘電率材料の有機ポリマー、In this embodiment, the first interlayer insulating film (217) is an organic polymer of a low dielectric constant material,
MSQ、 HSQまたは炭素含有シリコン酸ィ匕膜である力 エッチングストッパー及びノヽ ードマスクをなす SiC、 SiCN, SiO等との積層膜から構成することもできる。 It can be composed of a laminated film of SiC, SiCN, SiO or the like forming a force etching stopper and a node mask which is MSQ, HSQ or carbon-containing silicon oxide film.
2  2
[0211] 第一層間絶縁膜 (217)上には、第二配線層（218)が形成されている。  [0211] On the first interlayer insulating film (217), a second wiring layer (218) is formed.
[0212] 第二配線層（218)中には、金属回路配線（219)と、金属補強配線パターン（220) と、が形成されている。 [0212] In the second wiring layer (218), a metal circuit wiring (219) and a metal reinforcing wiring pattern (220) are formed.
[0213] 本実施例においては、第二配線層 (218)は低誘電率材料の有機ポリマー、 MSQ 、 HSQまたは炭素含有シリコン酸ィ匕膜である力 エッチングストッパー及びノヽードマ スクをなす SiN、 SiOC、 SiC、 SiCN, SiO等との積層膜力も構成することもできる。  In this embodiment, the second wiring layer (218) is made of an organic polymer of low dielectric constant material, MSQ, HSQ, or a silicon-containing silicon oxide film. , SiC, SiCN, SiO, etc. can also be configured.
2  2
[0214] このように、配線層と層間絶縁膜とが交互に積層されることにより、多層回路構造が 形成されている。 [0214] As described above, the multilayer circuit structure is formed by alternately laminating the wiring layers and the interlayer insulating films. Is formed.
[0215] 多層回路構造上には、チップ外部と電気信号の送受信を行う金属ボンディングパッ ド（221)が形成されている。この金属ボンディングパッド（221)は最上層の第二配線 層（218)に形成された金属回路配線（219)と電気的に接続されている。  [0215] On the multilayer circuit structure, a metal bonding pad (221) for transmitting and receiving electric signals to and from the outside of the chip is formed. The metal bonding pad (221) is electrically connected to the metal circuit wiring (219) formed on the uppermost second wiring layer (218).
[0216] また、金属ボンディングパッド（221)の下方の領域においても、金属ボンディングパ ッド（221)が無 ヽ領域（回路領域)と同様に、トランジスタ（2211)、金属回路配線 (2 15)、金属導電性金属ビア（224)が存在する。  [0216] Also in the region below the metal bonding pad (221), the transistor (2211) and the metal circuit wiring (215) have the metal bonding pad (221) in the same manner as the non-metal region (circuit region). There is a metal conductive metal via (224).
[0217] また、本実施例においては、金属ボンディングパッド（221)の下方の領域にのみ、 上下層の金属補強配線パターン（216、 220)が相互に重なり合う領域を接続する金 属補強ビアパターン (225)が存在する。  Further, in this embodiment, only in the region below the metal bonding pad (221), the metal reinforcing via patterns (216, 220) connecting the regions where the upper and lower metal reinforcing wiring patterns (216, 220) overlap each other are connected. 225) exists.
[0218] ボンディングワイヤ（227)を金属ボンディングパッド（221)に接続する際には、非常 に大きな衝撃または応力が金属ボンディングパッド（221)に加えられ、その衝撃は金 属ボンディングパッド (221)の下方の金属回路配線や金属導電性金属ビアにも伝播 する。本実施例においては、金属補強ビアパターン（225)が存在することにより、層 間絶縁膜における強度や密着性を増大させることが可能となり、ボンディング時の衝 撃や応力に起因する膜剥がれや膜破壊を防止することが可能となる。  [0218] When connecting the bonding wire (227) to the metal bonding pad (221), a very large impact or stress is applied to the metal bonding pad (221), and the impact is applied to the metal bonding pad (221). It propagates to the lower metal circuit wiring and metal conductive metal vias. In the present embodiment, the presence of the metal reinforcing via pattern (225) makes it possible to increase the strength and adhesion of the inter-layer insulating film, resulting in film peeling or film peeling due to impact or stress during bonding. Destruction can be prevented.
[0219] 図 34は、図 33に示した実施例に係る半導体装置の平面図である。  FIG. 34 is a plan view of the semiconductor device according to the example shown in FIG.
[0220] 金属ボンディングパッド（221)の下方に存在する金属補強配線パターン（216、 22 0)が相互に重なり合う領域を接続する金属補強ビアパターン (225)が存在するため 、金属回路配線または導電性金属ビアへの電気的な影響やチップ面積の増大を発 生することなぐワイヤボンディングに対する強度を増大させることが可能になる。  [0220] Since there is a metal reinforcing via pattern (225) that connects areas where the metal reinforcing wiring patterns (216, 220) existing below the metal bonding pad (221) overlap each other, the metal circuit wiring or the conductive pattern is formed. It is possible to increase the strength for wire bonding without causing an electrical effect on metal vias and an increase in chip area.
[0221] 図 35は、図 33に示した実施例に係る半導体装置において、低誘電率膜を層間絶 縁膜に用いた場合の金属ボンディングパッドの下方の領域における金属補強ビアパ ターンの面積割合 (ビア占有率（％) )とワイヤボンディング時の膜剥がれの割合 (ボン デイング不良割合（％) )との関係を示すグラフである。  FIG. 35 shows the area ratio of the metal reinforcing via pattern in the region below the metal bonding pad when the low dielectric constant film is used as the interlayer insulating film in the semiconductor device according to the example shown in FIG. 7 is a graph showing a relationship between a via occupation ratio (%)) and a film peeling ratio during wire bonding (bonding defect ratio (%)).
[0222] 図 35から明らかであるように、金属補強ビアパターン（225)が金属ボンディングパ ッド（221)の下方に存在しない場合 (ビア占有率 =0%)には、膜剥がれが発生して V、るのに対して (ボンディング不良割合 = 100%)、金属補強ビアパターン（225)が 金属ボンディングパッド（221)の下方に 10%以上存在することにより膜剥がれの割 合を大幅に減少させることが可能となる（ボンディング不良割合く 6%)。 [0222] As is clear from Fig. 35, when the metal reinforcing via pattern (225) does not exist below the metal bonding pad (221) (via occupancy = 0%), film peeling occurs. In contrast to V, (bonding failure rate = 100%), the metal reinforcement via pattern (225) The presence of 10% or more below the metal bonding pad (221) can greatly reduce the rate of film peeling (bonding failure rate is 6%).
[0223] 本実施例においては、金属ボンディングパッド（221)の下方の領域に回路領域を なすトランジスタ（2211)と、金属回路配線（215、 219)及び導電性金属ビア（224) からなる多層回路構造が存在する場合につ!ヽて述べたが、金属ボンディングパッド（ 221)の下方の領域には、トランジスタ（2211)並びに多層回路構造を形成する金属 回路配線及び導電性金属ビアの何れか一つのみが配置されて 、てもよ 、。あるいは 、トランジスタ（2211)及び多層回路構造の何れもが金属ボンディングパッド（221)の 下方の領域には配置されておらず、金属ボンディングパッド（221)の下方の領域に は、金属補強配線パターン（216、 220)と金属補強ビアパターン（225)とからなる多 層支持構造のみが配置されて 、てもよ 、。 In the present embodiment, a transistor (2211) forming a circuit area below the metal bonding pad (221), and a multilayer circuit including metal circuit wirings (215, 219) and conductive metal vias (224) As described above when the structure exists, the region below the metal bonding pad (221) includes one of the transistor (2211) and one of the metal circuit wiring and the conductive metal via forming the multilayer circuit structure. Only one is arranged. Alternatively, neither the transistor (2211) nor the multilayer circuit structure is disposed in the region below the metal bonding pad (221), and the region below the metal bonding pad (221) is provided with a metal reinforcing wiring pattern ( 216, 220) and a metal reinforcing via pattern (225) alone may be arranged.
[0224] 図 36は、上記の実施例を応用したハイスペック LSIの断面図である。 FIG. 36 is a cross-sectional view of a high-spec LSI to which the above embodiment is applied.
[0225] 図 36に示すように、ハイスペック LSIの場合には、低誘電率材料からなる多層ロー カル配線層 (228)と、多層ローカル配線層（228)の上方にグローバル配線層（231 )と、が形成される。 [0225] As shown in FIG. 36, in the case of a high-spec LSI, a multilayer local wiring layer (228) made of a low dielectric constant material and a global wiring layer (231) above the multilayer local wiring layer (228). And are formed.
[0226] グローバル配線層 (231)は、多層ローカル配線層 (228)を構成する低誘電率材料 よりも誘電率と膜強度が高い絶縁膜であるビア層間絶縁膜 (230)と、ビア層間絶縁 膜 (230)の上方に形成され、多層ローカル配線層 (228)を構成する低誘電率材料 よりも誘電率と膜強度が高い絶縁膜からなる配線層 (229)と、力 なる。  [0226] The global wiring layer (231) includes a via interlayer insulating film (230), which is an insulating film having a higher dielectric constant and film strength than the low dielectric constant material constituting the multilayer local wiring layer (228), and a via interlayer insulating film. The wiring layer (229) formed of an insulating film having a higher dielectric constant and a higher film strength than the low dielectric constant material forming the multilayer local wiring layer (228) is formed above the film (230).
[0227] また、ローカル配線（236)とグローバル配線（237)力 なる多層配線の上方には、 チップ外部と電気信号の送受信を行う金属ボンディングパッド（232)が配置されて 、 る。  A metal bonding pad (232) for transmitting and receiving an electric signal to / from the outside of the chip is arranged above the local wiring (236) and the global wiring (237).
[0228] 本実施例においては、配線層（229)及びビア層間絶縁膜 (230)はそれぞれ SiO  In the present embodiment, the wiring layer (229) and the via interlayer insulating film (230) are each made of SiO 2.
2 2
、 SiOF力らなる。 , SiOF forces.
[0229] 強度及び密着性が高いグローバル配線層 (231)中のビア層間絶縁膜 (230)内に は金属補強ビアパターンは存在せず、配線層 (229)内にのみ CMP平坦用ダミー配 線パターン（235)が存在する。  [0229] There is no metal reinforcing via pattern in the via interlayer insulating film (230) in the global wiring layer (231) having high strength and adhesion, and the dummy wiring for CMP flattening is only in the wiring layer (229). There is a pattern (235).
[0230] そして、低誘電率層間絶縁膜からなるローカル配線層 (228)中の金属ボンディン グパッド（232)の下方の領域にのみ、上下層の金属補強配線パターン（238)を相互 に接続する金属補強ビアパターン（233)が形成されて!ヽる。 [0230] Then, the metal bond in the local wiring layer (228) made of a low dielectric constant interlayer insulating film is formed. A metal reinforcing via pattern (233) for connecting the metal reinforcing wiring patterns (238) of the upper and lower layers to each other is formed only in a region below the bonding pad (232).
[0231] ここで、ボンディング時の衝撃に対して、グローバル配線層（231)は、配線層（229 )及びビア層間絶縁膜 (230)の膜強度及び密着性が高いため、ボンディング時の衝 撃または応力に対して耐えることが可能となる。また、ローカル配線層（228)には金 属補強ビアパターン (233)が存在することにより、層間絶縁膜における強度及び密 着性を増大させることが可能となり、ボンディング時の衝撃や応力に起因する膜剥が れゃ膜破壊を防止することが可能となる。  [0231] Here, the global wiring layer (231) has high film strength and adhesion of the wiring layer (229) and the via interlayer insulating film (230) against the shock at the time of bonding. Alternatively, it is possible to withstand stress. In addition, the presence of the metal reinforcing via pattern (233) in the local wiring layer (228) makes it possible to increase the strength and adhesion of the interlayer insulating film, resulting in the impact and stress during bonding. It is possible to prevent film peeling and film destruction.
[0232] なお、図 36に示した半導体装置においては、導電性金属ビアと導電性金属配線と を別々に形成するシングルダマシンプロセスが用いられている力 導電性金属ビアと 導電性金属配線とを同時に形成するデュアルダマシンプロセスを用いることも可能で ある。  In the semiconductor device shown in FIG. 36, a single damascene process in which a conductive metal via and a conductive metal wiring are formed separately is used. It is also possible to use a dual damascene process formed at the same time.
[0233] 図 37は、図 36に示した実施例に対する第一の変形例の断面図である。  FIG. 37 is a cross-sectional view of a first modification of the embodiment shown in FIG.
[0234] 図 37に示す半導体装置においては、図 33に示した半導体装置と同様に、トランジ スタ（2211)が形成された半導体基板 (211)上に、絶縁膜 (212)、第一配線層（21 3)、第一層間絶縁膜 (217)、第二配線層（218)、第二層間絶縁膜 (240)、第三配 線層 (241)がこの順番に積層されている。 In the semiconductor device shown in FIG. 37, similarly to the semiconductor device shown in FIG. 33, an insulating film (212) and a first wiring layer are formed on a semiconductor substrate (211) on which a transistor (2211) is formed. (213), a first interlayer insulating film (217), a second wiring layer (218), a second interlayer insulating film (240), and a third wiring layer (241) are stacked in this order.
[0235] 第三配線層（241)上には、金属ボンディングパッド（221)が配置されている。 [0235] On the third wiring layer (241), a metal bonding pad (221) is arranged.
[0236] 最上層の第三配線層 (241)には、金属ボンディングパッド（221)の直下の位置に おいて、大面積配線層パッド（242)が形成されており、この大面積配線層パッド（24 2)がその上方に積載される金属ボンディングパッド (221)を支持する構造となってい る。 In the uppermost third wiring layer (241), a large-area wiring layer pad (242) is formed immediately below the metal bonding pad (221). (242) has a structure for supporting the metal bonding pad (221) stacked thereon.
[0237] なお、大面積配線層パッド（242)は、第三配線層 (241)の回路領域に設けられた 金属回路配線 (243)と同一材質によって形成されている。  The large-area wiring layer pad (242) is formed of the same material as the metal circuit wiring (243) provided in the circuit region of the third wiring layer (241).
[0238] このような大面積配線層パッド（242)を有する本半導体装置においても、大面積配 線層パッド（242)の下方の領域には、金属ボンディングパッド（221)が無い領域（回 路領域)と同様に、トランジスタ（2211)と、金属回路配線 (215)、金属導電性金属ビ ァ（224)及び金属回路配線 (219)からなる多層回路構造と、が存在し、さらに、金属 補強配線パターン（216、 220)及びこれらが相互に重なり合う領域を接続する金属 補強ビアパターン (225)からなる多層支持構造が存在する。 In the present semiconductor device having such a large-area wiring layer pad (242), the area below the large-area wiring layer pad (242) does not include the metal bonding pad (221) (the circuit). As in the case of (region), there is a transistor (2211) and a multilayer circuit structure including a metal circuit wiring (215), a metal conductive metal via (224), and a metal circuit wiring (219). There is a multi-layer support structure consisting of reinforced wiring patterns (216, 220) and metal reinforced via patterns (225) connecting the areas where they overlap.
[0239] 図 38は、図 36に示した実施例に対する第二の変形例の断面図である。  FIG. 38 is a sectional view of a second modification of the embodiment shown in FIG.
[0240] 図 38に示す半導体装置は、図 37に示した半導体装置における最上層の第三配 線層 (241)が単層構造であるのに対して、最上層の第三配線層 (245)が複数層の 積層構造力 構成されている点が図 37に示した半導体装置と異なっている。  In the semiconductor device shown in FIG. 38, the uppermost third wiring layer (241) in the semiconductor device shown in FIG. 37 has a single-layer structure, whereas the uppermost third wiring layer (245) 37) is different from the semiconductor device shown in FIG.
[0241] すなわち、図 38に示す半導体装置においては、第二層間絶縁膜 (240)の上には 、複数個の配線層が積層された積層体 (245)が第三配線層として形成されており、 この積層体（245)には、金属ボンディングパッド（221)の直下の位置において、大 面積配線層パッド（246)が形成されている。この大面積配線層パッド（246)も複数 層の積層体から構成されており、大面積配線層パッド（246)がその上部に積載され る金属ボンディングパッド（221)を支持する構造となって！/、る。  [0241] That is, in the semiconductor device shown in FIG. 38, a laminate (245) in which a plurality of wiring layers are stacked is formed as a third wiring layer on the second interlayer insulating film (240). A large area wiring layer pad (246) is formed on the laminate (245) immediately below the metal bonding pad (221). This large-area wiring layer pad (246) is also composed of a laminate of a plurality of layers, and has a structure in which the large-area wiring layer pad (246) supports the metal bonding pad (221) mounted thereon! /
[0242] なお、大面積配線層パッド（246)は、積層体（245)の回路領域に設けられた金属 回路配線 (247)と同一材質によって形成されて 、る。  [0242] The large-area wiring layer pad (246) is formed of the same material as the metal circuit wiring (247) provided in the circuit region of the multilayer body (245).
[0243] このような大面積配線層パッド（246)を有する本半導体装置においても、大面積配 線層パッド（246)の下方の領域には、金属ボンディングパッド（221)が無い領域（回 路領域)と同様に、トランジスタ（2211)と、金属回路配線 (215)、金属導電性金属ビ ァ（224)及び金属回路配線 (240)からなる多層回路構造と、が存在し、さらに、金属 補強配線パターン（216、 220)及びこれらが相互に重なり合う領域を接続する金属 補強ビアパターン (225)からなる多層支持構造が存在する。  [0243] In the present semiconductor device having such a large-area wiring layer pad (246), the area below the large-area wiring layer pad (246) does not include the metal bonding pad (221) (the circuit). As in the case of (area), there is a transistor (2211) and a multilayer circuit structure including a metal circuit wiring (215), a metal conductive metal via (224), and a metal circuit wiring (240). There is a multi-layer support structure consisting of wiring patterns (216, 220) and metal reinforced via patterns (225) connecting the areas where they overlap.
[0244] 図 38に示す半導体装置においては、図 37に示す半導体装置と同様に、金属ボン デイングパッド（221)を強度の高い大面積配線層パッド（246)によって支持しており 、かつ、大面積配線層パッド（246)の下部に位置する第二層間絶縁膜 (240)は、図 36に示したグロ一ノ レ配線層 (231)中のビア層間絶縁膜 (230)と同様〖こ、強度及 び密着性の高いものとできるため、第二層間絶縁膜 (240)内には金属補強ビアバタ ーンを形成する必要はなぐ第二層間絶縁膜 (240)より下方の配線層及び層間絶縁 膜にお ヽてのみ、 CMP平坦用ダミー配線パターン及び金属補強ビアパターンから なる多層支持構造が存在して ヽる。 [0245] ここで、ボンディング時の衝撃に対して、大面積配線層パッド（246)を有する第三 配線層 (245)は膜強度及び密着性が高いため、ボンディング時の衝撃または応力 に対して耐性を有することが可能となり、一方、第三配線層（245)よりも下方の層に は多層支持構造が存在することにより、層間絶縁膜における強度、密着性を増大さ せることが可能となり、ボンディング時の衝撃や応力に起因する膜剥がれや膜破壊を 防止することが可能となる。 In the semiconductor device shown in FIG. 38, similar to the semiconductor device shown in FIG. 37, a metal bonding pad (221) is supported by a large-strength large-area wiring layer pad (246). The second interlayer insulating film (240) located under the area wiring layer pad (246) is the same as the via interlayer insulating film (230) in the green wiring layer (231) shown in FIG. It is not necessary to form a metal reinforcing via pattern in the second interlayer insulating film (240) because it can have high strength and high adhesion. Wiring layers and interlayer insulation below the second interlayer insulating film (240) Only in the film, there is a multilayer support structure including a dummy wiring pattern for CMP flattening and a metal reinforcing via pattern. Here, the third wiring layer (245) having the large-area wiring layer pad (246) has high film strength and high adhesion to the impact during bonding. On the other hand, the layer below the third wiring layer (245) has a multilayer support structure, so that the strength and adhesion of the interlayer insulating film can be increased. It is possible to prevent film peeling and film destruction due to shock and stress during bonding.
[0246] なお、図 37及び図 38に示す半導体装置においては、金属ボンディングパッド（22 1)の下方の領域に回路領域をなすトランジスタ、金属回路配線及び金属導電性金 属ビアが存在する場合について述べた力 金属ボンディングパッド（221)の下方の 領域には、トランジスタ（2211)または多層回路構造の何れか一方のみが配置されて いてもよい。あるいは、トランジスタ（2211)及び多層回路構造の何れもが金属ボンデ イングパッド（221)の下方の領域には配置されておらず、金属ボンディングパッド（22 1)の下方の領域には、金属補強配線パターンと金属補強ビアパターンとからなる多 層支持構造のみが配置されて 、てもよ 、。  In the semiconductor device shown in FIGS. 37 and 38, the case where a transistor, a metal circuit wiring, and a metal conductive metal via forming a circuit region exist in a region below the metal bonding pad (221) is described. In the region below the force metal bonding pad (221) described above, only one of the transistor (2211) and the multilayer circuit structure may be arranged. Alternatively, neither the transistor (2211) nor the multilayer circuit structure is arranged in the area below the metal bonding pad (221), and the area below the metal bonding pad (221) is a metal reinforcing wiring. Only a multi-layer support structure composed of a pattern and a metal reinforcing via pattern may be arranged.
[0247] 図 39及び図 40は、図 37及び図 38に示した半導体装置における大面積配線層パ ッド（242、 246)の形状の一例を示す平面図である。  FIGS. 39 and 40 are plan views showing examples of the shape of the large-area wiring layer pads (242, 246) in the semiconductor device shown in FIGS. 37 and 38.
[0248] 大面積配線層パッド（242、 246)は、例えば、図 39に示すように、全体が金属 Rか らなる矩形形状とすることができる。  The large-area wiring layer pads (242, 246) can be formed in a rectangular shape entirely made of metal R, as shown in FIG. 39, for example.
[0249] あるいは、図 40に示すように、外形を金属 Rからなる矩形形状とし、その中に、絶縁 膜からなる矩形状の島 Iを形成することも可能である。この場合、島 Iの数は 1個または 複数個とすることができる（図 40に示す例においては 4個)。また、島 Iを複数個設け る場合の島 Iの配置も任意である。  Alternatively, as shown in FIG. 40, the outer shape may be a rectangular shape made of metal R, and a rectangular island I made of an insulating film may be formed therein. In this case, the number of islands I can be one or more (four in the example shown in FIG. 40). In addition, when a plurality of islands I are provided, the arrangement of the islands I is optional.
[0250] さらに、大面積配線層パッド（242、 246)は、図 36に示したグローバル配線層（23 1)を有する半導体装置、あるいは、グローバル配線層 231)を有しない半導体装置 の 、ずれに対しても適用可能である。  Furthermore, the large-area wiring layer pads (242, 246) are more likely to be displaced than the semiconductor device having the global wiring layer (231) shown in FIG. 36 or the semiconductor device having no global wiring layer 231). It is also applicable.
(実施例 3)  (Example 3)
図 41は、本発明の第 2の態様に係る半導体装置の他の実施例の断面図である。以 下、図 41を参照して、本実施例に係る半導体装置を説明する。 [0251] 図 41に示すように、本実施例に係る半導体装置は、半導体基板 (311)と、半導体 基板 (311)上に形成された絶縁膜 (312)とを備えている。 FIG. 41 is a cross-sectional view of another example of the semiconductor device according to the second embodiment of the present invention. Hereinafter, the semiconductor device according to the present embodiment will be described with reference to FIG. As shown in FIG. 41, the semiconductor device according to the present example includes a semiconductor substrate (311) and an insulating film (312) formed on the semiconductor substrate (311).
[0252] 本実施例にお!、ては、半導体基板 (311)は単結晶シリコン基板である。 In this embodiment, the semiconductor substrate (311) is a single crystal silicon substrate.
[0253] また、絶縁膜（312)はボロフォスフォシリケート'ガラス（8?30 :1)01：0 1105 110511 ate glass)、フォスフオシリケート'ガラス（PSG： phosphosilicate glass)、酸ィ匕シリ コン（SiO )、窒化シリコン（SiN)、酸窒化シリコン（SiON)、酸弗化シリコン（SiOF)、 The insulating film (312) is made of borophosphosilicate 'glass (8-30: 1) 01: 0 1105 110511 ate glass), phosphosilicate glass (PSG: phosphosilicate glass), silicon oxide silicon (SiO 2), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxyfluoride (SiOF),
2  2
炭化シリコン (SiC)、炭窒化シリコン（SiCN)等の絶縁材料またはそれらの組み合わ せから構成されている。  It is composed of insulating materials such as silicon carbide (SiC) and silicon carbonitride (SiCN) or a combination thereof.
[0254] 絶縁膜 (312)上には、第一配線層（313)が形成されている。 [0254] The first wiring layer (313) is formed on the insulating film (312).
[0255] 本実施例においては、第一配線層 (313)は低誘電率材料の有機ポリマー、 MSQIn this embodiment, the first wiring layer (313) is made of an organic polymer of a low dielectric constant material, MSQ
、 HSQまたは炭素含有シリコン酸ィ匕膜である力 エッチングストッパー及びノヽードマ スクをなす SiN、 SiOC、 SiC、 SiCN, SiO等との積層膜力も構成することもできる。 , HSQ or a carbon-containing silicon oxide film. A stacked film strength with SiN, SiOC, SiC, SiCN, SiO, etc. forming an etching stopper and a node mask can also be formed.
2  2
[0256] 第一配線層 (313)には、回路を電気的に接続する金属回路配線 (または、導電性 金属配線）（315)と、回路とは電気的な接続を持たない金属補強配線パターン (316 )と、が形成されている。  [0256] The first wiring layer (313) includes a metal circuit wiring (or a conductive metal wiring) (315) for electrically connecting the circuit and a metal reinforcing wiring pattern having no electrical connection to the circuit. (316) is formed.
[0257] 第一配線層（313)上には、第一層間絶縁膜 (317)が形成されている。  [0257] On the first wiring layer (313), a first interlayer insulating film (317) is formed.
[0258] 第一層間絶縁膜 (317)中には、上下の金属回路配線 (319、 315)を相互に電気 的に接続する導電性金属ビア（324)と、上下の金属補強配線パターンを接続する金 属補強ビアパターン (325)と、が形成されている。  In the first interlayer insulating film (317), a conductive metal via (324) for electrically connecting the upper and lower metal circuit wirings (319, 315) to each other, and an upper and lower metal reinforcing wiring pattern are provided. A metal reinforcing via pattern (325) to be connected is formed.
[0259] 本実施例においては、第一層間絶縁膜 (317)は低誘電率材料の有機ポリマー、 MSQ、 HSQまたは炭素含有シリコン酸ィ匕膜である力 エッチングストッパー及びノヽ ードマスクをなす SiC、 SiCN, SiO等との積層膜から構成することもできる。  In the present embodiment, the first interlayer insulating film (317) is made of an organic polymer of low dielectric constant material, MSQ, HSQ or a silicon-containing film containing carbon. It can also be composed of a laminated film of SiCN, SiO, etc.
2  2
[0260] 第一層間絶縁膜 (317)上には、第二配線層（318)が形成されている。  [0260] On the first interlayer insulating film (317), a second wiring layer (318) is formed.
[0261] 第二配線層（318)中には、金属回路配線（319)と、金属補強配線パターン（320) と、が形成されている。 [0261] In the second wiring layer (318), a metal circuit wiring (319) and a metal reinforcing wiring pattern (320) are formed.
[0262] 本実施例においては、第二配線層 (318)は低誘電率材料の有機ポリマー、 MSQ 、 HSQまたは炭素含有シリコン酸ィ匕膜である力 エッチングストッパー及びノヽードマ スクをなす SiN、 SiOC、 SiC、 SiCN, SiO等との積層膜力も構成することもできる。 [0263] このように、配線層と層間絶縁膜とが交互に積層されることにより、多層回路構造が 形成されている。 In this embodiment, the second wiring layer (318) is made of an organic polymer of low dielectric constant material, MSQ, HSQ, or a silicon-containing film containing carbon. Etching stopper and SiN, SiOC forming a node mask. , SiC, SiCN, SiO, etc. can also be configured. As described above, a multilayer circuit structure is formed by alternately stacking the wiring layers and the interlayer insulating films.
[0264] 金属補強ビアパターン (325)は第一及び第二配線層（313、 318)の金属補強配 線パターン（316、 320)を相互に接続することにより、多層支持構造を形成している  [0264] The metal reinforcing via pattern (325) forms a multilayer support structure by connecting the metal reinforcing wiring patterns (316, 320) of the first and second wiring layers (313, 318) to each other.
[0265] 多層回路構造上には、チップ外部と電気信号の送受信を行う金属ボンディングパッ ド（321)が形成されている。この金属ボンディングパッド（321)は最上層の第二配線 層（318)に形成された金属回路配線 (319)と電気的に接続されて!ヽる。 On the multilayer circuit structure, a metal bonding pad (321) for transmitting and receiving electric signals to and from the outside of the chip is formed. The metal bonding pad (321) is electrically connected to the metal circuit wiring (319) formed on the uppermost second wiring layer (318).
[0266] また、金属ボンディングパッド（321)の下方の領域にぉ 、ても、金属ボンディングパ ッド（321)が無い領域（回路領域)と同様に、トランジスタ（3211)、金属回路配線 (3 15)、金属導電性金属ビア（324)が存在する。  [0266] Even in the region below the metal bonding pad (321), the transistor (3211) and the metal circuit wiring (3) as in the region (circuit region) where the metal bonding pad (321) is not provided. 15), there is a metal conductive metal via (324).
[0267] ワイヤボンディング時の衝撃または応力は金属ボンディングパッド（321)の下方の みでなぐ金属ボンディングパッド（321)の外側の領域にも拡散する可能性がある。 このため、本実施例においては、金属ボンディングパッド（321)の下方の領域のみで なぐ図 41に示すように、金属ボンディングパッド（321)の外縁から一定の距離（325 1)以内に存在する上下に隣接する金属補強配線パターン（316、 320)が相互に重 なり合う領域を接続する金属補強ビアパターン (325)が形成されて!ヽる。  [0267] The impact or stress at the time of wire bonding may also diffuse to a region outside the metal bonding pad (321), which can be seen only below the metal bonding pad (321). For this reason, in the present embodiment, as shown in FIG. 41, which is formed only in the region below the metal bonding pad (321), the upper and lower portions existing within a predetermined distance (3251) from the outer edge of the metal bonding pad (321) are formed. A metal reinforcing via pattern (325) for connecting a region where the metal reinforcing wiring patterns (316, 320) adjacent to each other overlap each other is formed.
[0268] ここで、金属ボンディングパッド（321)の外縁から一定の距離（3251)は低誘電率 材料の強度や密着性に応じて変化する。チップ全面に金属補強ビアパターン (325) を形成することが必要となる場合もある。  Here, the fixed distance (3251) from the outer edge of the metal bonding pad (321) changes according to the strength and adhesion of the low dielectric constant material. It may be necessary to form a metal reinforced via pattern (325) over the entire chip.
[0269] ボンディングワイヤ（3250)を金属ボンディングパッド（321)に接続する際、非常に 大きな衝撃または応力が金属ボンディングパッド（321)に作用する。その衝撃または 応力は金属ボンディングパッド（321)の真下や、金属ボンディングパッド（321)よりも 外側の領域の下層に存在する金属回路配線及び金属導電性金属ビアにも伝播する  When connecting the bonding wire (3250) to the metal bonding pad (321), a very large impact or stress acts on the metal bonding pad (321). The impact or stress propagates to the metal circuit wiring and the metal conductive metal via located immediately below the metal bonding pad (321) and under the region outside the metal bonding pad (321).
[0270] 本実施例においては、金属ボンディングパッド（321)の真下のみならず、金属ボン デイングパッド (321)の外縁から所定の距離 (3251)の範囲内にも、金属補強ビアパ ターン（325)が存在することにより、金属ボンディングパッド（321)及びその周囲にま で層間絶縁膜の強度及び密着性を増大させることが可能となり、ワイヤボンディング 時の衝撃や応力による膜剥がれや膜破壊を防止することが可能となる。 [0270] In this embodiment, the metal reinforcing via pattern (325) is located not only immediately below the metal bonding pad (321) but also within a predetermined distance (3251) from the outer edge of the metal bonding pad (321). The metal bonding pad (321) and its surroundings This makes it possible to increase the strength and adhesion of the interlayer insulating film, and to prevent film peeling and film destruction due to impact and stress during wire bonding.
[0271] 図 42は、層間絶縁膜を低誘電率膜で構成した場合において、多層支持構造が金 属ボンディングパッド（321)の下方力も外側に広がっている場合の、多層支持構造 が存在する領域の金属ボンディングパッド（321)の外縁からの距離と、ボールシェア 法で測定したボンディング部の密着強度との関係を示すグラフである。  [0271] FIG. 42 shows a region where the multilayer support structure exists when the interlayer support film is formed of a low dielectric constant film and the downward force of the metal bonding pad (321) is also spread outward. 7 is a graph showing the relationship between the distance from the outer edge of the metal bonding pad (321) and the adhesion strength of the bonding portion measured by the ball shear method.
[0272] 図 42から明らかであるように、金属ボンディングパッド（321)の外縁力も約 10 m の範囲内にも多層支持構造を存在させることにより、金属ボンディングパッド（321) の下方の領域のみに多層支持構造を存在させた場合よりも、ワイヤボンディングに対 する強度を力なり増大させることが可能である。  [0272] As is apparent from Fig. 42, the outer peripheral force of the metal bonding pad (321) is also within a range of about 10 m by providing the multilayer support structure, so that only the area below the metal bonding pad (321) is provided. It is possible to significantly increase the strength for wire bonding as compared to the case where a multilayer support structure is present.
[0273] 図 43は、図 41に示した半導体装置の平面図である。  FIG. 43 is a plan view of the semiconductor device shown in FIG.
[0274] 本実施例に係る半導体装置においては、金属ボンディングパッド（321)の下方及 び金属ボンディングパッド（321)の外縁から一定の距離（3251)内に存在する下層 の金属補強配線パターン間を接続するような金属補強ビアパターン (325)が存在す る場合においても、上下に隣接する金属補強配線パターンが相互に重なり合う領域 ( 326)にのみ金属補強ビアパターン（325)は存在するため、金属回路配線または導 電性金属ビアへの電気的な影響やチップ面積の増大を発生することなく、ワイヤボン デイングに対する強度を増大させることが可能になる。  In the semiconductor device according to the present embodiment, the space between the lower metal reinforcing wiring patterns existing under the metal bonding pad (321) and within a certain distance (3251) from the outer edge of the metal bonding pad (321) is reduced. Even when there is a metal reinforcing via pattern (325) for connection, the metal reinforcing via pattern (325) exists only in the region (326) where the metal reinforcing wiring patterns vertically adjacent to each other overlap with each other. It is possible to increase the strength against wire bonding without causing an electrical effect on circuit wiring or conductive metal vias or an increase in chip area.
[0275] 本実施例においては、金属ボンディングパッド（321)の下方の領域に回路領域を なすトランジスタ（3211)と、金属回路配線（315、 319)及び導電性金属ビア（324) からなる多層回路構造が存在する場合につ!ヽて述べたが、金属ボンディングパッド（ 321)の下方の領域には、トランジスタ（3211)並びに多層回路構造を形成する金属 回路配線及び導電性金属ビアの何れか一つのみが配置されて 、てもよ 、。あるいは 、トランジスタ（3211)及び多層回路構造の何れもが金属ボンディングパッド（321)の 下方の領域には配置されておらず、金属ボンディングパッド（321)の下方の領域に は、金属補強配線パターン（316、 320)と金属補強ビアパターン（325)とからなる多 層支持構造のみが配置されて 、てもよ 、。  In the present example, a transistor (3211) forming a circuit area below the metal bonding pad (321), a multilayer circuit including metal circuit wirings (315, 319) and conductive metal vias (324) As described above when the structure exists, the region below the metal bonding pad (321) includes one of the transistor (3211) and one of the metal circuit wiring and the conductive metal via forming the multilayer circuit structure. Only one is arranged. Alternatively, neither the transistor (3211) nor the multilayer circuit structure is arranged in the region below the metal bonding pad (321), and the region below the metal bonding pad (321) is provided with a metal reinforcing wiring pattern ( 316, 320) and a metal reinforcing via pattern (325) alone may be arranged.
[0276] 図 44は、上記の実施例を応用したハイスペック LSIの断面図である。 [0277] 図 44に示すように、ハイスペック LSIの場合には、低誘電率材料からなる多層ロー カル配線層 (328)と、多層ローカル配線層（328)の上方にグローバル配線層（331 )と、が形成される。 FIG. 44 is a cross-sectional view of a high-spec LSI to which the above embodiment is applied. As shown in FIG. 44, in the case of a high-spec LSI, a multilayer local wiring layer (328) made of a low dielectric constant material and a global wiring layer (331) above the multilayer local wiring layer (328). And are formed.
[0278] グローバル配線層 (331)は、多層ローカル配線層 (328)を構成する低誘電率材料 よりも誘電率と膜強度が高い絶縁膜であるビア層間絶縁膜 (330)と、ビア層間絶縁 膜 (330)の上方に形成され、多層ローカル配線層 (328)を構成する低誘電率材料 よりも誘電率と膜強度が高い絶縁膜からなる配線層 (329)と、力 なる。  [0278] The global wiring layer (331) includes a via interlayer insulating film (330), which is an insulating film having higher dielectric constant and film strength than the low dielectric constant material constituting the multilayer local wiring layer (328), and a via interlayer insulating film. The wiring layer (329) formed of an insulating film having a higher dielectric constant and a higher film strength than the low dielectric constant material forming the multilayer local wiring layer (328) is formed above the film (330).
[0279] また、ローカル配線（336)とグローバル配線（337)力 なる多層配線の上方には、 チップ外部と電気信号の送受信を行う金属ボンディングパッド（332)が配置されて 、 る。  [0279] A metal bonding pad (332) for transmitting and receiving electric signals to and from the outside of the chip is arranged above the multi-layer wiring that acts as the local wiring (336) and the global wiring (337).
[0280] 本実施例においては、配線層（329)及びビア層間絶縁膜 (330)はそれぞれ SiO  In this embodiment, the wiring layer (329) and the via interlayer insulating film (330) are each made of SiO 2.
2 2
、 SiOF力らなる。 , SiOF forces.
[0281] 強度及び密着性が高いグローバル配線層 (331)中のビア層間絶縁膜 (330)内に は金属補強ビアパターンは存在せず、配線層 (329)内にのみ CMP平坦用ダミー配 線パターン（335)が存在する。  [0281] There is no metal reinforcing via pattern in the via interlayer insulating film (330) in the global wiring layer (331) having high strength and adhesion, and the dummy wiring for CMP flattening is only in the wiring layer (329). There is a pattern (335).
[0282] そして、低誘電率層間絶縁膜からなるローカル配線層 (328)中の金属ボンディン グパッド（332)の下方の領域と、金属ボンディングパッド（332)の外縁から一定の距 離（3251)以内の領域とには、上下層の金属補強配線パターン（338)を相互に接続 する金属補強ビアパターン (333)が形成されて!、る。  [0282] Then, within a certain distance (3251) from the region below the metal bonding pad (332) in the local wiring layer (328) made of a low dielectric constant interlayer insulating film and the outer edge of the metal bonding pad (332). A metal reinforcing via pattern (333) for connecting the metal reinforcing wiring patterns (338) of the upper and lower layers to each other is formed in the region (1).
[0283] ここで、ボンディング時の衝撃に対して、グローバル配線層（331)は、配線層（329 )及びビア層間絶縁膜 (330)の膜強度及び密着性が高いため、ボンディング時の衝 撃または応力に対して耐えることが可能となる。また、ローカル配線層（328)には金 属補強ビアパターン (333)が存在することにより、層間絶縁膜における強度及び密 着性を増大させることが可能となり、ボンディング時の衝撃や応力に起因する膜剥が れゃ膜破壊を防止することが可能となる。  Here, the global wiring layer (331) has high film strength and adhesion of the wiring layer (329) and the via interlayer insulating film (330) against the shock at the time of bonding. Alternatively, it is possible to withstand stress. In addition, the presence of the metal reinforcing via pattern (333) in the local wiring layer (328) makes it possible to increase the strength and adhesion of the interlayer insulating film, resulting in the impact and stress during bonding. It is possible to prevent film peeling and film destruction.
(実施例 4)  (Example 4)
図 45は、本発明の第一の態様に係る半導体装置の他の実施例の断面図である。 以下、図 45を参照して、本実施例に係る半導体装置を説明する。 [0284] 図 45に示すように、本実施例に係る半導体装置は、半導体基板 (411)と、半導体 基板 (411)上に形成された絶縁膜 (412)とを備えている。 FIG. 45 is a cross-sectional view of another example of the semiconductor device according to the first embodiment of the present invention. Hereinafter, the semiconductor device according to the present embodiment will be described with reference to FIG. As shown in FIG. 45, the semiconductor device according to the present example includes a semiconductor substrate (411) and an insulating film (412) formed on the semiconductor substrate (411).
[0285] 本実施例にお!、ては、半導体基板 (411)は単結晶シリコン基板である。 In this embodiment, the semiconductor substrate (411) is a single crystal silicon substrate.
[0286] また、絶縁膜 (412)はボロフォスフオシリケート'ガラス（BPSG :borophosphosilic ate glass)、フォスフオシリケート'ガラス（PSG： phosphosilicate glass)、酸ィ匕シリ コン（SiO )、窒化シリコン（SiN)、酸窒化シリコン（SiON)、酸弗化シリコン（SiOF)、 The insulating film (412) is made of borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), phosphosilicate glass (PSG), silicon nitride (SiO 2), silicon nitride (SiN ), Silicon oxynitride (SiON), silicon oxyfluoride (SiOF),
2  2
炭化シリコン (SiC)、炭窒化シリコン（SiCN)等の絶縁材料またはそれらの組み合わ せから構成されている。  It is composed of insulating materials such as silicon carbide (SiC) and silicon carbonitride (SiCN) or a combination thereof.
[0287] 絶縁膜 (412)上には、第一配線層（413)が形成されている。 [0287] On the insulating film (412), a first wiring layer (413) is formed.
[0288] 本実施例においては、第一配線層 (413)は低誘電率材料の有機ポリマー、 MSQIn this embodiment, the first wiring layer (413) is made of an organic polymer of a low dielectric constant material, MSQ
、 HSQまたは炭素含有シリコン酸ィ匕膜である力 エッチングストッパー及びノヽードマ スクをなす SiN、 SiOC、 SiC、 SiCN, SiO等との積層膜力も構成することもできる。 , HSQ or a carbon-containing silicon oxide film. A stacked film strength with SiN, SiOC, SiC, SiCN, SiO, etc. forming an etching stopper and a node mask can also be formed.
2  2
[0289] 第一配線層 (413)には、回路を電気的に接続する金属回路配線 (または、導電性 金属配線）（415)と、回路とは電気的な接続を持たない金属補強配線パターン (416 )と、が形成されている。  [0289] The first wiring layer (413) includes a metal circuit wiring (or a conductive metal wiring) (415) for electrically connecting the circuit and a metal reinforcing wiring pattern having no electrical connection to the circuit. (416) are formed.
[0290] 第一配線層（413)上には、第一層間絶縁膜 (417)が形成されている。  [0290] On the first wiring layer (413), a first interlayer insulating film (417) is formed.
[0291] 第一層間絶縁膜 (417)中には、上下の金属回路配線 (415、 421)を相互に電気 的に接続する導電性金属ビア (418)と、上下の金属補強配線パターン (422、 416) を接続する金属補強ビアパターン (419)と、が形成されている。  [0291] In the first interlayer insulating film (417), a conductive metal via (418) for electrically connecting the upper and lower metal circuit wirings (415, 421) to each other, and an upper and lower metal reinforcing wiring pattern ( 422, 416) and a metal reinforcing via pattern (419).
[0292] さらに、本半導体装置の厚さ方向における金属補強ビアパターン (419)の長さは 同層に形成されている導電性金属ビア (418)の同方向における長さよりも大きく設定 されている。  Further, the length of the metal reinforcing via pattern (419) in the thickness direction of the present semiconductor device is set to be longer than the length of the conductive metal via (418) formed in the same layer in the same direction. .
[0293] 本実施例においては、第一層間絶縁膜 (417)は低誘電率材料の有機ポリマー、 MSQ、 HSQまたは炭素含有シリコン酸ィ匕膜である力 エッチングストッパー及びノヽ ードマスクをなす SiC、 SiCN, SiO等との積層膜から構成することもできる。  In this embodiment, the first interlayer insulating film (417) is a low dielectric constant material organic polymer, MSQ, HSQ or a carbon-containing silicon oxide film. It can also be composed of a laminated film of SiCN, SiO, etc.
2  2
[0294] 第一層間絶縁膜 (417)上には、第二配線層（420)が形成されている。  [0294] On the first interlayer insulating film (417), a second wiring layer (420) is formed.
[0295] 第二配線層 (420)中には、金属回路配線 (421)と、金属補強配線パターン (422) と、が形成されている。 [0296] 本実施例にお!、ては、第二配線層 (420)は低誘電率材料の有機ポリマー、 MSQ 、 HSQまたは炭素含有シリコン酸ィ匕膜である力 エッチングストッパー及びノヽードマ スクをなす SiN、 SiOC、 SiC、 SiCN、 SiO等との積層膜力も構成することもできる。 [0295] In the second wiring layer (420), a metal circuit wiring (421) and a metal reinforcing wiring pattern (422) are formed. In this embodiment, the second wiring layer (420) is formed of an organic polymer of a low dielectric constant material, MSQ, HSQ or a carbon-containing silicon oxide film. An etching stopper and a node mask are used. The laminated film strength with SiN, SiOC, SiC, SiCN, SiO, or the like can be configured.
2  2
[0297] このように、配線層と層間絶縁膜とが交互に積層されることにより、多層回路構造が 形成されている。  [0297] As described above, a multilayer circuit structure is formed by alternately stacking the wiring layers and the interlayer insulating films.
[0298] 金属補強ビアパターン (419)は第一及び第二配線層（413、 420)の金属補強配 線パターン (416、 422)を相互に接続することにより、多層支持構造を形成している  [0298] The metal reinforcing via pattern (419) forms a multi-layer support structure by connecting the metal reinforcing wiring patterns (416, 422) of the first and second wiring layers (413, 420) to each other.
[0299] 図 46は、図 45に示した実施例に係る半導体装置の平面図である。 FIG. 46 is a plan view of the semiconductor device according to the example shown in FIG.
[0300] 図 46に示すように、第一及び第二配線層（413、 420)において金属補強配線パタ ーン (416、 422)の形状や位置が異なる場合には、金属補強ビアパターン (419)は 金属補強配線パターン (または、ダミー配線）（416、 422)が重なり合う領域 (423)の みを接続するように配置される。このため、従来力も形成されている CMP用ダミーパ ターンの寸法、形状を変化させることなぐすなわち、チップの面積を増大させること なぐ金属補強ビアパターン (または、ダミービア）（419)を導入することができる。  As shown in FIG. 46, when the shapes and positions of the metal reinforcing wiring patterns (416, 422) are different in the first and second wiring layers (413, 420), the metal reinforcing via patterns (419 ) Are arranged so as to connect only the region (423) where the metal reinforcing wiring pattern (or dummy wiring) (416, 422) overlaps. For this reason, it is possible to introduce a metal reinforcing via pattern (or dummy via) (419) that does not change the dimensions and shape of the dummy pattern for CMP in which the conventional force is also formed, that is, does not increase the chip area. .
[0301] 図 47、図 48及び図 49は、図 45に示した半導体装置における金属補強ビアパター ン (419)の形状の例を示す平面図である。  FIG. 47, FIG. 48 and FIG. 49 are plan views showing examples of the shape of the metal reinforcing via pattern (419) in the semiconductor device shown in FIG.
[0302] 前述のように、半導体装置の厚さ方向における金属補強ビアパターン (419)の長さ は、同層に形成された導電性金属ビア (418)の半導体装置の厚さ方向における長さ よりも大きく設定されている。  [0302] As described above, the length of the metal reinforcing via pattern (419) in the thickness direction of the semiconductor device is the length of the conductive metal via (418) formed in the same layer in the thickness direction of the semiconductor device. It is set larger than.
[0303] この金属補強ビアパターン (419)は、例えば、図 47に示すように、導電性金属ビア  [0303] The metal reinforcing via pattern (419) is, for example, as shown in FIG.
(418)よりも直径が大きい円筒状ビア (424)として形成することができる。この場合、 円筒状ビア (424)は 1個または複数個を形成することができる。  It can be formed as a cylindrical via (424) having a larger diameter than (418). In this case, one or more cylindrical vias (424) can be formed.
[0304] また、金属補強ビアパターン (419)は、図 48に示すように、スリット状の、または、横 断面が矩形状のビア (425)として形成することができる。この場合、矩形状ビア (425 )は 1個または複数個を形成することができる。  As shown in FIG. 48, the metal reinforcing via pattern (419) can be formed as a slit-shaped via or a via (425) having a rectangular cross section. In this case, one or more rectangular vias (425) can be formed.
[0305] あるいは、金属補強ビアパターン (419)は、図 49に示すように、第一及び第二配 線層（413、 420)における金属補強配線パターン (416、 422)が相互に重なり合う 領域の全てにぉ ヽて形成されて ヽるビア（426)として形成することも可能である。 Alternatively, as shown in FIG. 49, the metal reinforcing via patterns (419) are such that the metal reinforcing wiring patterns (416, 422) in the first and second wiring layers (413, 420) overlap each other. It is also possible to form a via (426) that is formed entirely in the region.
[0306] このように、導電性金属ビア (418)よりも寸法が大きい金属補強ビアパターン (419 )を用いることにより、金属補強ビアパターン (419)におけるビアエッチング時のエツ チング速度が導電性金属ビア (418)のエッチング速度よりも速くなるため、図 45に示 すように、下層の金属補強配線パターン (416)に対する金属補強ビアパターン (419 )の食 、込み量が金属回路配線 (415)に対する導電性金属ビア (418)の食 、込み 量よりも大きくなる。 As described above, by using the metal reinforcing via pattern (419) having a size larger than that of the conductive metal via (418), the etching speed at the time of via etching in the metal reinforcing via pattern (419) can be reduced. Since the etching rate of the via (418) is higher than that of the via (418), as shown in FIG. In this case, the conductive metal via (418) eats more than the amount of food.
[0307] このように、金属補強ビアパターン (419)の食い込み量が大きくなる構造を用いるこ とにより、導電性金属ビア (418)と金属補強ビアパターン (419)との寸法が等しい場 合よりも、さらに、下層の金属強度配線パターン (416)との密着性や層間絶縁膜 (41 7)の強度を向上することが可能となり、化学機械研磨 (CMP)プロセスの際やチップ ノ ッケージング時に印加される衝撃や応力に起因する膜剥がれや膜破壊を防止す ることが可能となる。  As described above, by using the structure in which the metal reinforcement via pattern (419) is deepened, the conductive metal via (418) and the metal reinforcement via pattern (419) have the same dimensions. In addition, it is possible to improve the adhesiveness with the underlying metal strength wiring pattern (416) and the strength of the interlayer insulating film (417), and to apply it during the chemical mechanical polishing (CMP) process and during chip knocking. It is possible to prevent film peeling and film destruction due to the applied shock and stress.
[0308] なお、図 45に示した半導体装置においては、導電性金属ビア (418)と導電性金属 配線 (421)を別々に形成するシングルダマシンプロセスを用いている力 導電性金 属ビア (418)と導電性金属配線 (421)とを同時に形成するデュアルダマシンプロセ スを用いることも可能である。  In the semiconductor device shown in FIG. 45, a conductive metal via (418) using a single damascene process of separately forming a conductive metal via (418) and a conductive metal wiring (421) is used. ) And the conductive metal wiring (421) can be formed at the same time.
(実施例 5)  (Example 5)
図 50は、本発明の第 2の態様に係る半導体装置の他の実施例の断面図である。以 下、図 50を参照して、本実施例に係る半導体装置を説明する。  FIG. 50 is a cross-sectional view of another example of the semiconductor device according to the second embodiment of the present invention. Hereinafter, the semiconductor device according to the present embodiment will be described with reference to FIG.
[0309] 図 50に示すように、本実施例に係る半導体装置は、半導体基板 (511)と、半導体 基板 (511)上に形成されたトランジスタ（5221)と、トランジスタ（5221)を覆うように 半導体基板 (511)上に形成された絶縁膜 (512)とを備えている。 As shown in FIG. 50, the semiconductor device according to this example includes a semiconductor substrate (511), a transistor (5221) formed on the semiconductor substrate (511), and a transistor (5221). An insulating film (512) formed on a semiconductor substrate (511).
[0310] 本実施例においては、半導体基板（511)は単結晶シリコン基板である。 [0310] In this embodiment, the semiconductor substrate (511) is a single crystal silicon substrate.
[0311] また、絶縁膜（512)はボロフォスフォシリケート'ガラス（8?30 :1)01：0 1105 110511 ate glass)、フォスフオシリケート'ガラス（PSG： phosphosilicate glass)、酸ィ匕シリ コン（SiO )、窒化シリコン（SiN)、酸窒化シリコン（SiON)、酸弗化シリコン（SiOF)、 [0311] The insulating film (512) is made of borophosphosilicate 'glass (8-30: 1) 01: 0 1105 110511ate glass), phosphosilicate' glass (PSG: phosphosilicate glass), silicon oxide silicon (SiO 2), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxyfluoride (SiOF),
2  2
炭化シリコン (SiC)、炭窒化シリコン（SiCN)等の絶縁材料またはそれらの組み合わ せから構成されている。 Insulating materials such as silicon carbide (SiC) and silicon carbonitride (SiCN), or a combination thereof It is composed of
[0312] 絶縁膜 (512)上には、第一配線層（513)が形成されている。 [0312] The first wiring layer (513) is formed on the insulating film (512).
[0313] 本実施例においては、第一配線層 (513)は低誘電率材料の有機ポリマー、 MSQ 、 HSQまたは炭素含有シリコン酸ィ匕膜である力 エッチングストッパー及びノヽードマ スクをなす SiN、 SiOC、 SiC、 SiCN、 SiO等との積層膜力も構成することもできる。 In this embodiment, the first wiring layer (513) is made of an organic polymer of low dielectric constant material, MSQ, HSQ, or a silicon-containing silicon oxide film. Etching stopper and SiN, SiOC forming a node mask are used. , SiC, SiCN, SiO and the like can also be formed.
2  2
[0314] 第一配線層 (513)には、回路を電気的に接続する金属回路配線 (または、導電性 金属配線）（515)と、回路とは電気的な接続を持たない金属補強配線パターン (516 )と、が形成されている。  [0314] The first wiring layer (513) includes a metal circuit wiring (or a conductive metal wiring) (515) for electrically connecting the circuit and a metal reinforcing wiring pattern having no electrical connection to the circuit. (516) are formed.
[0315] 第一配線層（513)上には、第一層間絶縁膜 (517)が形成されている。  [0315] On the first wiring layer (513), a first interlayer insulating film (517) is formed.
[0316] 第一層間絶縁膜 (517)中には、上下の金属回路配線（515、 519)を相互に電気 的に接続する導電性金属ビア（524)と、上下の金属補強配線パターン（516、 520) を接続する金属補強ビアパターン (525)と、が形成されている。  [0316] In the first interlayer insulating film (517), conductive metal vias (524) for electrically connecting the upper and lower metal circuit wirings (515, 519) to each other, and upper and lower metal reinforcing wiring patterns (515) are provided. 516, 520) and a metal reinforcing via pattern (525).
[0317] 本実施例においては、第一層間絶縁膜 (517)は低誘電率材料の有機ポリマー、 MSQ、 HSQまたは炭素含有シリコン酸ィ匕膜である力 エッチングストッパー及びノヽ ードマスクをなす SiC、 SiCN、 SiO等との積層膜から構成することもできる。  In this embodiment, the first interlayer insulating film (517) is made of an organic polymer of a low dielectric constant material, MSQ, HSQ, or a silicon-containing silicon oxide film. It can also be composed of a laminated film of SiCN, SiO, etc.
2  2
[0318] 第一層間絶縁膜 (517)上には、第二配線層（518)が形成されている。  [0318] On the first interlayer insulating film (517), a second wiring layer (518) is formed.
[0319] 第二配線層（518)中には、金属回路配線（519)と、金属補強配線パターン（520) と、が形成されている。 [0319] In the second wiring layer (518), a metal circuit wiring (519) and a metal reinforcing wiring pattern (520) are formed.
[0320] 本実施例においては、第二配線層 (518)は低誘電率材料の有機ポリマー、 MSQ 、 HSQまたは炭素含有シリコン酸ィ匕膜である力 エッチングストッパー及びノヽードマ スクをなす SiN、 SiOC、 SiC、 SiCN、 SiO等との積層膜力も構成することもできる。  In the present embodiment, the second wiring layer (518) is made of an organic polymer of a low dielectric constant material, MSQ, HSQ or a silicon-containing silicon oxide film. , SiC, SiCN, SiO and the like can also be formed.
2  2
[0321] このように、配線層と層間絶縁膜とが交互に積層されることにより、多層回路構造が 形成されている。  [0321] As described above, a multilayer circuit structure is formed by alternately stacking the wiring layers and the interlayer insulating films.
[0322] 多層回路構造上には、チップ外部と電気信号の送受信を行う金属ボンディングパッ ド（521)が形成されている。この金属ボンディングパッド（521)は最上層の第二配線 層（518)に形成された金属回路配線 (519)と電気的に接続されて!ヽる。  [0322] A metal bonding pad (521) for transmitting and receiving electric signals to and from the outside of the chip is formed on the multilayer circuit structure. The metal bonding pad (521) is electrically connected to the metal circuit wiring (519) formed on the uppermost second wiring layer (518).
[0323] また、金属ボンディングパッド（521)の下方の領域にぉ 、ても、金属ボンディングパ ッド（521)が無い領域（回路領域)と同様に、トランジスタ（5211)、金属回路配線 (5 23)、金属導電性金属ビア（524)が存在する。 [0323] Even in the region below the metal bonding pad (521), similarly to the region (circuit region) where the metal bonding pad (521) is not provided, the transistor (5211) and the metal circuit wiring (5 23), there are metal conductive metal vias (524).
[0324] 本実施例においては、金属ボンディングパッド（521)の下方の領域にのみ、上下 方向に隣接する金属補強配線パターン (516、 520)が相互に重なり合う領域を接続 する金属補強ビアパターン（525)が形成されて!、る。 [0324] In this embodiment, the metal reinforcing via pattern (525) connecting the areas where the vertically adjacent metal reinforcing wiring patterns (516, 520) overlap each other only in the area below the metal bonding pad (521). ) Is formed!
[0325] さらに、本半導体装置の厚さ方向における金属補強ビアパターン（525)の長さは 同層に形成されている導電性金属ビア（524)の同方向における長さよりも大きく設定 されている。 Further, the length of the metal reinforcing via pattern (525) in the thickness direction of the semiconductor device is set to be longer than the length of the conductive metal via (524) formed in the same layer in the same direction. .
[0326] 図 51は、図 50に示した実施例に係る半導体装置の平面図である。  FIG. 51 is a plan view of the semiconductor device according to the example shown in FIG.
[0327] 図 51に示すように、金属補強ビアパターン（525)は、金属ボンディングパッド（521 As shown in FIG. 51, the metal reinforcing via pattern (525) is connected to the metal bonding pad (521).
)の下方に存在する金属補強配線パターン（516、 520)が相互に重なり合う領域を 接続するものとして形成されている。このため、回路をなす配線、ビアへの電気的な 影響やチップ面積の増大を発生することなぐワイヤボンディングに対する強度を増 大させることが可會 になる。 The metal reinforcing wiring patterns (516, 520) existing under () are formed so as to connect the mutually overlapping regions. For this reason, it is possible to increase the strength against wire bonding without causing an electrical influence on wirings and vias forming a circuit and an increase in chip area.
[0328] 図 52、図 53及び図 54は、図 50に示した半導体装置における金属補強ビアパター ン（525)の形状の例を示す平面図である。 FIGS. 52, 53 and 54 are plan views showing examples of the shape of the metal reinforcing via pattern (525) in the semiconductor device shown in FIG.
[0329] 前述のように、半導体装置の厚さ方向における金属補強ビアパターン (525)の長さ は、同層に形成された導電性金属ビア（524)の半導体装置の厚さ方向における長さ よりも大きく設定されている。 [0329] As described above, the length of the metal reinforcing via pattern (525) in the thickness direction of the semiconductor device is equal to the length of the conductive metal via (524) formed in the same layer in the thickness direction of the semiconductor device. It is set larger than.
[0330] この金属補強ビアパターン（525)は、例えば、図 52に示すように、導電性金属ビア The metal reinforcing via pattern (525) is, for example, as shown in FIG.
(524)よりも直径が大き 、円筒状ビア（528A)として形成することができる。この場合 The diameter is larger than (524) and can be formed as a cylindrical via (528A). in this case
、円筒状ビア（528A)は 1個または複数個を形成することができる。 One or more cylindrical vias (528A) can be formed.
[0331] また、金属補強ビアパターン（525)は、図 53に示すように、スリット状の、または、横 断面が矩形状のビア（528B)として形成することができる。この場合、矩形状ビア（52As shown in FIG. 53, the metal reinforcing via pattern (525) can be formed as a slit-shaped via or a via (528B) having a rectangular cross section. In this case, a rectangular via (52
8B)は 1個または複数個を形成することができる。 8B) can form one or a plurality.
[0332] あるいは、金属補強ビアパターン（525)は、図 54に示すように、第一及び第二配 線層（513、 518)における金属補強配線パターン（516、 520)が相互に重なり合う 領域の全てにおいて形成されているビア（528C)として形成することも可能である。 [0332] Alternatively, as shown in FIG. 54, the metal reinforcing via pattern (525) is formed in an area where the metal reinforcing wiring patterns (516, 520) in the first and second wiring layers (513, 518) overlap each other. It is also possible to form as a via (528C) formed in all.
[0333] このように、導電性金属ビア（524)よりも寸法が大き!/、金属補強ビアパターン（525 )を用いることにより、金属補強ビアパターン（525)におけるビアエッチング時のエツ チング速度が導電性金属ビア（524)のエッチング速度よりも速くなるため、図 50に示 すように、下層の金属補強配線パターン（516)に対する金属補強ビアパターン（525 )の食 、込み量が金属回路配線 (515)に対する導電性金属ビア（524)の食 、込み 量よりも大きくなる。 As described above, the dimensions are larger than the conductive metal vias (524)! / ), The etching speed at the time of via etching in the metal reinforcing via pattern (525) becomes faster than the etching speed of the conductive metal via (524), and as shown in FIG. The amount of penetration of the metal reinforcing via pattern (525) with respect to the wiring pattern (516) becomes larger than the amount of penetration of the conductive metal via (524) with respect to the metal circuit wiring (515).
[0334] このように、金属補強ビアパターン（525)の食 、込み量が大きくなる構造を用いるこ とにより、導電性金属ビア（524)と金属補強ビアパターン（525)との寸法が等しい場 合よりも、さらに、下層の金属強度配線パターン (516)との密着性や層間絶縁膜 (51 7)の強度を向上することが可能となり、ワイヤボンディング時に印加される衝撃ゃ応 力に起因する膜剥がれや膜破壊を防止することが可能となる。  [0334] As described above, by using a structure in which the metal reinforcement via pattern (525) has a large bite, the conductive metal via (524) and the metal reinforcement via pattern (525) have the same dimensions. It is possible to further improve the adhesion with the metal strength wiring pattern (516) of the lower layer and the strength of the interlayer insulating film (517) as compared with the case, and this is caused by the impact stress applied during wire bonding. It is possible to prevent film peeling and film destruction.
[0335] 本実施例においては、金属ボンディングパッド（521)の下方の領域に回路領域を なすトランジスタ（5211)と、金属回路配線（515、 519)及び導電性金属ビア（524) からなる多層回路構造が存在する場合につ!ヽて述べたが、金属ボンディングパッド（ 521)の下方の領域には、トランジスタ（5211)並びに多層回路構造を形成する金属 回路配線及び導電性金属ビアの何れか一つのみが配置されて 、てもよ 、。あるいは 、トランジスタ（5211)及び多層回路構造の何れもが金属ボンディングパッド（521)の 下方の領域には配置されておらず、金属ボンディングパッド（521)の下方の領域に は、金属補強配線パターン（516、 520)と金属補強ビアパターン（525)とからなる多 層支持構造のみが配置されて 、てもよ 、。  In the present embodiment, a transistor (5211) forming a circuit area below the metal bonding pad (521), a multilayer circuit including metal circuit wirings (515, 519) and conductive metal vias (524) As described in the case where the structure exists, the region below the metal bonding pad (521) includes one of the transistor (5211) and one of the metal circuit wiring and the conductive metal via forming the multilayer circuit structure. Only one is arranged. Alternatively, neither the transistor (5211) nor the multilayer circuit structure is disposed in the region below the metal bonding pad (521), and the region below the metal bonding pad (521) is provided with a metal reinforcing wiring pattern ( 516, 520) and a metal supporting via pattern (525) alone.
[0336] 図 55は、上記の実施例を応用したハイスペック LSIの断面図である。  FIG. 55 is a cross-sectional view of a high-spec LSI to which the above embodiment is applied.
[0337] 図 55に示すように、ハイスペック LSIの場合には、低誘電率材料からなる多層ロー カル配線層 (528)と、多層ローカル配線層（528)の上方にグローバル配線層（531 )と、が形成される。  As shown in FIG. 55, in the case of a high-spec LSI, a multilayer local wiring layer (528) made of a low dielectric constant material and a global wiring layer (531) above the multilayer local wiring layer (528) And are formed.
[0338] グローバル配線層 (531)は、多層ローカル配線層 (528)を構成する低誘電率材料 よりも誘電率と膜強度が高い絶縁膜であるビア層間絶縁膜 (530)と、ビア層間絶縁 膜 (530)の上方に形成され、多層ローカル配線層 (528)を構成する低誘電率材料 よりも誘電率と膜強度が高い絶縁膜からなる配線層 (529)と、力 なる。  [0338] The global wiring layer (531) includes a via interlayer insulating film (530), which is an insulating film having a higher dielectric constant and film strength than the low dielectric constant material constituting the multilayer local wiring layer (528), and a via interlayer insulating film. The wiring layer (529) formed of an insulating film having a higher dielectric constant and a higher film strength than the low dielectric constant material forming the multilayer local wiring layer (528) is formed above the film (530).
[0339] また、ローカル配線（536)とグローバル配線（537)力 なる多層配線の上方には、 チップ外部と電気信号の送受信を行う金属ボンディングパッド（532)が配置されて 、 る。 [0339] Further, above the local wiring (536) and the global wiring (537), A metal bonding pad (532) for transmitting and receiving electric signals to and from the outside of the chip is arranged.
[0340] 本実施例においては、配線層（529)及びビア層間絶縁膜 (530)はそれぞれ SiO  In this embodiment, the wiring layer (529) and the via interlayer insulating film (530) are each made of SiO
2 2
、 SiOF力らなる。 , SiOF forces.
[0341] 強度及び密着性が高いグローバル配線層 (531)中のビア層間絶縁膜 (530)内に は金属補強ビアパターンは存在せず、配線層 (529)内にのみ CMP平坦用ダミー配 線パターン（535)が存在する。  [0341] There is no metal reinforcing via pattern in the via interlayer insulating film (530) in the global wiring layer (531) having high strength and adhesion, and the dummy wiring for CMP flattening is only in the wiring layer (529). There is a pattern (535).
[0342] また、グローバル配線層 (531)には金属補強ビアパターンは存在せず、金属ボン デイングパッド（532)の下方の領域にのみ、低誘電率層間膜からなるローカル配線 層（528)における上下方向に隣接する金属補強配線パターン相互間を接続する金 属補強ビアパターン (533)が形成されて!、る。 [0342] Further, the metal wiring via pattern does not exist in the global wiring layer (531), and only in the region below the metal bonding pad (532), the local wiring layer (528) made of a low dielectric constant interlayer film is formed. A metal reinforcing via pattern (533) for connecting the metal reinforcing wiring patterns adjacent to each other in the vertical direction is formed.
[0343] さらに、本半導体装置の厚さ方向における金属補強ビアパターン（533)の長さは 同層の導電性金属ビア（524)の本半導体装置の厚さ方向における長さよりも大きく 設定されている。 Further, the length of the metal reinforcing via pattern (533) in the thickness direction of the present semiconductor device is set to be longer than the length of the conductive metal via (524) in the same layer in the thickness direction of the present semiconductor device. I have.
[0344] ここで、ボンディング時の衝撃に対して、グローバル配線層（531)は、配線層（529 )及びビア層間絶縁膜 (530)の膜強度及び密着性が高いため、ボンディング時の衝 撃または応力に対して耐えることが可能となる。また、ローカル配線層（528)には金 属補強ビアパターン (533)が存在することにより、層間絶縁膜における強度及び密 着性を増大させることが可能となり、ボンディング時の衝撃や応力に起因する膜剥が れゃ膜破壊を防止することが可能となる。  [0344] Here, the global wiring layer (531) has high film strength and adhesion of the wiring layer (529) and the via interlayer insulating film (530) due to the bonding shock. Alternatively, it is possible to withstand stress. In addition, the presence of the metal reinforcing via pattern (533) in the local wiring layer (528) makes it possible to increase the strength and adhesion of the interlayer insulating film, resulting in impact and stress during bonding. It is possible to prevent film peeling and film destruction.
[0345] なお、図 55に示した半導体装置においては、導電性金属ビアと導電性金属配線と を別々に形成するシングルダマシンプロセスが用いられている力 導電性金属ビアと 導電性金属配線とを同時に形成するデュアルダマシンプロセスを用いることも可能で ある。  [0345] In the semiconductor device shown in FIG. 55, a single damascene process in which a conductive metal via and a conductive metal wiring are separately formed is used. It is also possible to use a dual damascene process formed at the same time.
(実施例 6)  (Example 6)
図 56は、本発明の第 2の態様に係る半導体装置の他の実施例の断面図である。以 下、図 56を参照して、本実施例に係る半導体装置を説明する。  FIG. 56 is a sectional view of another example of the semiconductor device according to the second embodiment of the present invention. Hereinafter, the semiconductor device according to the present embodiment will be described with reference to FIG.
[0346] 図 56に示すように、本実施例に係る半導体装置は、半導体基板 (611)と、半導体 基板 (611)上に形成されたトランジスタ（6221)と、トランジスタ（6221)を覆うように 半導体基板 (611)上に形成された絶縁膜 (612)とを備えている。 As shown in FIG. 56, the semiconductor device according to this example includes a semiconductor substrate (611) and a semiconductor The semiconductor device includes a transistor (6221) formed on a substrate (611) and an insulating film (612) formed on a semiconductor substrate (611) so as to cover the transistor (6221).
[0347] 本実施例にお!、ては、半導体基板 (611)は単結晶シリコン基板である。 In this embodiment, the semiconductor substrate (611) is a single crystal silicon substrate.
[0348] また、絶縁膜（612)はボロフォスフォシリケート'ガラス（8?30 :1)01：0 1105 110511 ate glass)、フォスフオシリケート'ガラス（PSG： phosphosilicate glass)、酸ィ匕シリ コン（SiO )、窒化シリコン（SiN)、酸窒化シリコン（SiON)、酸弗化シリコン（SiOF)、 [0348] The insulating film (612) is made of borophosphosilicate 'glass (8-30: 1) 01: 0 1105 110511ate glass), phosphosilicate glass (PSG: phosphosilicate glass), silicon oxide silicon (SiO 2), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxyfluoride (SiOF),
2  2
炭化シリコン (SiC)、炭窒化シリコン（SiCN)等の絶縁材料またはそれらの組み合わ せから構成されている。  It is composed of insulating materials such as silicon carbide (SiC) and silicon carbonitride (SiCN) or a combination thereof.
[0349] 絶縁膜 (612)上には、第一配線層（613)が形成されている。 [0349] On the insulating film (612), a first wiring layer (613) is formed.
[0350] 本実施例においては、第一配線層 (613)は低誘電率材料の有機ポリマー、 MSQIn this embodiment, the first wiring layer (613) is made of an organic polymer of a low dielectric constant material, MSQ
、 HSQまたは炭素含有シリコン酸ィ匕膜である力 エッチングストッパー及びノヽードマ スクをなす SiN、 SiOC、 SiC、 SiCN, SiO等との積層膜力も構成することもできる。 , HSQ or a carbon-containing silicon oxide film. A stacked film strength with SiN, SiOC, SiC, SiCN, SiO, etc. forming an etching stopper and a node mask can also be formed.
2  2
[0351] 第一配線層 (613)には、回路を電気的に接続する金属回路配線 (または、導電性 金属配線）（615)と、回路とは電気的な接続を持たない金属補強配線パターン (616 )と、が形成されている。  [0351] The first wiring layer (613) includes a metal circuit wiring (or a conductive metal wiring) (615) for electrically connecting a circuit and a metal reinforcing wiring pattern having no electrical connection to the circuit. (616) is formed.
[0352] 第一配線層（613)上には、第一層間絶縁膜 (617)が形成されている。  [0352] On the first wiring layer (613), a first interlayer insulating film (617) is formed.
[0353] 第一層間絶縁膜 (617)中には、上下の金属回路配線 (615、 619)を相互に電気 的に接続する導電性金属ビア（624)と、上下の金属補強配線パターン (616、 620) を接続する金属補強ビアパターン (625)と、が形成されている。  In the first interlayer insulating film (617), conductive metal vias (624) for electrically connecting the upper and lower metal circuit wirings (615, 619) to each other, and upper and lower metal reinforcing wiring patterns ( 616, 620) are formed.
[0354] 本実施例においては、第一層間絶縁膜 (617)は低誘電率材料の有機ポリマー、 MSQ、 HSQまたは炭素含有シリコン酸ィ匕膜である力 エッチングストッパー及びノヽ ードマスクをなす SiC、 SiCN, SiO等との積層膜から構成することもできる。  In this embodiment, the first interlayer insulating film (617) is made of an organic polymer of a low dielectric constant material, MSQ, HSQ or SiC forming a force etching stopper and a node mask, which is a carbon-containing silicon oxide film. It can also be composed of a laminated film of SiCN, SiO, etc.
2  2
[0355] 第一層間絶縁膜 (617)上には、第二配線層（618)が形成されている。  [0355] On the first interlayer insulating film (617), a second wiring layer (618) is formed.
[0356] 第二配線層（618)中には、金属回路配線 (619)と、金属補強配線パターン (620) と、が形成されている。 In the second wiring layer (618), a metal circuit wiring (619) and a metal reinforcing wiring pattern (620) are formed.
[0357] 本実施例においては、第二配線層 (618)は低誘電率材料の有機ポリマー、 MSQ 、 HSQまたは炭素含有シリコン酸ィ匕膜である力 エッチングストッパー及びノヽードマ スクをなす SiN、 SiOC、 SiC、 SiCN, SiO等との積層膜力も構成することもできる。 [0358] このように、配線層と層間絶縁膜とが交互に積層されることにより、多層回路構造が 形成されている。 In this embodiment, the second wiring layer (618) is made of an organic polymer of low dielectric constant material, MSQ, HSQ, or a silicon-containing silicon-containing film. Etching stopper and SiN, SiOC forming a node mask. , SiC, SiCN, SiO, etc. can also be configured. [0358] As described above, a multilayer circuit structure is formed by alternately laminating the wiring layers and the interlayer insulating films.
[0359] 多層回路構造上には、チップ外部と電気信号の送受信を行う金属ボンディングパッ ド（621)が形成されている。この金属ボンディングパッド (621)は最上層の第二配線 層（618)に形成された金属回路配線 (619)と電気的に接続されて!ヽる。  [0359] On the multilayer circuit structure, a metal bonding pad (621) for transmitting and receiving an electric signal to and from the outside of the chip is formed. The metal bonding pad (621) is electrically connected to the metal circuit wiring (619) formed on the uppermost second wiring layer (618).
[0360] また、金属ボンディングパッド（621)の下方の領域にぉ 、ても、金属ボンディングパ ッド (621)が無い領域（回路領域)と同様に、トランジスタ (6221)、金属回路配線 (6 23)、金属導電性金属ビア（624)が存在する。  [0360] Further, even in the region below the metal bonding pad (621), the transistor (6221) and the metal circuit wiring (6) as in the region (circuit region) without the metal bonding pad (621). 23), there is a metal conductive metal via (624).
[0361] ワイヤボンディング時の衝撃または応力は金属ボンディングパッド（621)の下方の みでなぐ金属ボンディングパッド (621)の外側の領域にも拡散する可能性がある。 このため、本実施例においては、金属ボンディングパッド（621)の下方の領域のみで なぐ図 57に示すように、金属ボンディングパッド（621)の外縁から一定の距離（623 1)以内に存在する上下に隣接する金属補強配線パターン (616、 620)が相互に重 なり合う領域を接続する金属補強ビアパターン (625)が形成されて!ヽる。  [0361] The impact or stress at the time of wire bonding may also diffuse to a region outside the metal bonding pad (621), which can be seen only below the metal bonding pad (621). For this reason, in the present embodiment, as shown in FIG. 57, which is formed only in the region below the metal bonding pad (621), the upper and lower portions existing within a certain distance (6231) from the outer edge of the metal bonding pad (621) are formed. A metal reinforcing via pattern (625) connecting regions where the metal reinforcing wiring patterns (616, 620) adjacent to each other overlap each other is formed.
[0362] さらに、本半導体装置の厚さ方向における金属補強ビアパターン (625)の長さは 同層の導電性金属ビア (624)の本半導体装置の厚さ方向における長さよりも大きく 設定されている。  Further, the length of the metal reinforcing via pattern (625) in the thickness direction of the present semiconductor device is set to be larger than the length of the conductive metal via (624) of the same layer in the thickness direction of the present semiconductor device. I have.
[0363] ここで、金属ボンディングパッド（621)の外縁から一定の距離（6231)は低誘電率 材料の強度や密着性に応じて変化する。チップ全面に金属補強ビアパターン (625) を形成することが必要となる場合もある。  Here, the fixed distance (6231) from the outer edge of the metal bonding pad (621) changes according to the strength and adhesion of the low dielectric constant material. It may be necessary to form a metal reinforced via pattern (625) over the entire chip.
[0364] 図 42に示したように、低誘電率膜を層間絶縁膜に用いた半導体装置においては、 金属ボンディングパッドの外縁から約 10 μ mの範囲内にも多層支持構造を存在させ ることにより、金属ボンディングパッドの下方の領域のみに多層支持構造を存在させ た場合よりも、ワイヤボンディングに対する強度をかなり増大させることが可能となった ことが示された。  [0364] As shown in Fig. 42, in a semiconductor device using a low dielectric constant film as an interlayer insulating film, a multilayer support structure must exist within a range of about 10 µm from the outer edge of the metal bonding pad. Thus, it was shown that the strength for wire bonding can be considerably increased as compared with the case where the multilayer support structure exists only in the region below the metal bonding pad.
[0365] 図 57は、図 56に示した半導体装置の平面図である。  FIG. 57 is a plan view of the semiconductor device shown in FIG.
[0366] 図 57に示すように、金属ボンディングパッド（621)の下方及び金属ボンディングパ ッド（621)の外縁から一定の距離 (6231)内に存在する下層の金属補強配線パター ン（616、 620)間を接続する金属補強ビアパターン (625)が存在する場合において も、上下方向に隣接する金属補強配線パターン (616、 620)が相互に重なり合う領 域 (626)にのみ金属補強ビアパターン (625)は存在するため、回路をなす配線や 導電性金属ビアへの電気的な影響やチップ面積の増大を発生することなく、ワイヤボ ンデイングに対する強度を増大させることが可能になる。 [0366] As shown in FIG. 57, the lower metal reinforcing wiring pattern located below the metal bonding pad (621) and within a certain distance (6231) from the outer edge of the metal bonding pad (621). Even if there is a metal reinforcing via pattern (625) that connects between the metal reinforcing wires (616, 620), the metal only in the area (626) where the vertically adjacent metal reinforcing wiring patterns (616, 620) overlap each other. The presence of the reinforcing via pattern (625) makes it possible to increase the strength against wire bonding without causing an electrical influence on the wiring forming the circuit or the conductive metal via or an increase in the chip area.
[0367] 図 58、図 59及び図 60は、図 56に示した半導体装置における金属補強ビアパター ン（625)の形状の例を示す平面図である。  FIG. 58, FIG. 59 and FIG. 60 are plan views showing examples of the shape of the metal reinforcing via pattern (625) in the semiconductor device shown in FIG.
[0368] 前述のように、半導体装置の厚さ方向における金属補強ビアパターン (625)の長さ は、同層に形成された導電性金属ビア (624)の半導体装置の厚さ方向における長さ よりも大きく設定されている。  [0368] As described above, the length of the metal reinforcing via pattern (625) in the thickness direction of the semiconductor device is equal to the length of the conductive metal via (624) formed in the same layer in the thickness direction of the semiconductor device. It is set larger than.
[0369] この金属補強ビアパターン（625)は、例えば、図 58に示すように、導電性金属ビア  The metal reinforcing via pattern (625) is, for example, as shown in FIG.
(624)よりも直径が大き 、円筒状ビア（628)として形成することができる。この場合、 円筒状ビア（628)は 1個または複数個を形成することができる。  It has a larger diameter than (624) and can be formed as a cylindrical via (628). In this case, one or more cylindrical vias (628) can be formed.
[0370] また、金属補強ビアパターン (625)は、図 59に示すように、スリット状の、または、横 断面が矩形状のビア (629)として形成することができる。この場合、矩形状ビア（629 )は 1個または複数個を形成することができる。  As shown in FIG. 59, the metal reinforcing via pattern (625) can be formed as a slit-shaped via or a via (629) having a rectangular cross section. In this case, one or more rectangular vias (629) can be formed.
[0371] あるいは、金属補強ビアパターン (625)は、図 60に示すように、第一及び第二配 線層（613、 618)における金属補強配線パターン（616、 620)が相互に重なり合う 領域の全てにぉ 、て形成されて 、るビア（630)として形成することも可能である。  [0371] Alternatively, as shown in FIG. 60, the metal reinforcing via pattern (625) is formed in an area where the metal reinforcing wiring patterns (616, 620) in the first and second wiring layers (613, 618) overlap each other. All of them can be formed as a via (630).
[0372] このように、導電性金属ビア（624)よりも寸法が大き 、金属補強ビアパターン (625 )を用いることにより、金属補強ビアパターン（625)におけるビアエッチング時のエツ チング速度が導電性金属ビア（624)のエッチング速度よりも速くなるため、図 56に示 すように、下層の金属補強配線パターン (616)に対する金属補強ビアパターン（625 )の食 、込み量が金属回路配線 (615)に対する導電性金属ビア（624)の食 、込み 量よりも大きくなる。  [0372] As described above, by using the metal reinforcing via pattern (625) which is larger in size than the conductive metal via (624), the etching speed at the time of via etching in the metal reinforcing via pattern (625) becomes conductive. Since the etching speed of the metal via (624) is faster than that of the metal circuit wiring (615) as shown in FIG. ) Of the conductive metal via (624) with respect to).
[0373] このように、金属補強ビアパターン (625)の食 、込み量が大きくなる構造を用いるこ とにより、導電性金属ビア（624)と金属補強ビアパターン (625)との寸法が等しい場 合よりも、さらに、下層の金属強度配線パターン (616)との密着性や層間絶縁膜 (61 7)の強度を向上することが可能となり、ワイヤボンディング時の衝撃や応力に起因す る膜剥がれや膜破壊を防止することが可能となる。 [0373] As described above, by using a structure in which the metal reinforcement via pattern (625) has a large bite, the conductive metal via (624) and the metal reinforcement via pattern (625) have the same dimensions. Furthermore, the adhesion to the lower metal strength wiring pattern (616) and the interlayer insulation film (61 It is possible to improve the strength of 7), and it is possible to prevent film peeling and film destruction due to impact and stress during wire bonding.
[0374] 以上のように、本実施例に係る半導体装置においては、金属ボンディングパッド（6 21)の外縁から一定の距離（6231)の範囲内に金属補強ビアパターン（625)が形成 され、かつ、金属補強ビアパターン (625)の長さを導電性金属ビア（624)の長さより も大きくすることにより、下層の金属補強配線パターン (616)との密着性や層間絶縁 膜 (617)の強度を向上することが可能となり、ワイヤボンディング時の衝撃や応力に 起因する膜剥がれや膜破壊を防止することが可能となる。  As described above, in the semiconductor device according to the present example, the metal reinforcing via pattern (625) is formed within a certain distance (6231) from the outer edge of the metal bonding pad (621), and By making the length of the metal reinforcing via pattern (625) longer than the length of the conductive metal via (624), the adhesion to the underlying metal reinforcing wiring pattern (616) and the strength of the interlayer insulating film (617) are increased. This makes it possible to prevent film peeling and film destruction caused by impact and stress during wire bonding.
[0375] 本実施例においては、金属ボンディングパッド (621)の下方の領域に回路領域を なすトランジスタ（6221)と、金属回路配線 (615、 619)及び導電性金属ビア（624) からなる多層回路構造が存在する場合につ!ヽて述べたが、金属ボンディングパッド（ 621)の下方の領域には、トランジスタ（6221)並びに多層回路構造を構成する金属 回路配線及び導電性金属ビアの何れか一つのみが配置されて 、てもよ 、。あるいは 、トランジスタ（6221)及び多層回路構造の何れもが金属ボンディングパッド (621)の 下方の領域には配置されておらず、金属ボンディングパッド (621)の下方の領域に は、金属補強配線パターン（616、 620)と金属補強ビアパターン（625)と力もなる多 層支持構造のみが配置されて 、てもよ 、。  In the present example, a transistor (6221) forming a circuit area below the metal bonding pad (621) and a multilayer circuit including metal circuit wirings (615, 619) and conductive metal vias (624) As described in the case where the structure exists, the region below the metal bonding pad (621) includes one of the transistor (6221) and one of the metal circuit wiring and the conductive metal via constituting the multilayer circuit structure. Only one is arranged. Alternatively, neither the transistor (6221) nor the multilayer circuit structure is arranged in the area below the metal bonding pad (621), and the area below the metal bonding pad (621) is provided with a metal reinforcing wiring pattern ( 616, 620) and the metal reinforcing via pattern (625), and only a multi-layered support structure that is powerful.
[0376] 図 61は、上記の実施例を応用したハイスペック LSIの断面図である。  FIG. 61 is a cross-sectional view of a high-spec LSI to which the above embodiment is applied.
[0377] 図 61に示すように、ハイスペック LSIの場合には、低誘電率材料からなる多層ロー カル配線層 (631)と、多層ローカル配線層（631)の上方にグローバル配線層（634 )と、が形成される。  As shown in FIG. 61, in the case of a high-spec LSI, a multilayer local wiring layer (631) made of a low dielectric constant material and a global wiring layer (634) above the multilayer local wiring layer (631). And are formed.
[0378] グローバル配線層 (634)は、多層ローカル配線層 (631)を構成する低誘電率材料 よりも誘電率と膜強度が高い絶縁膜であるビア層間絶縁膜 (633)と、ビア層間絶縁 膜 (633)の上方に形成され、多層ローカル配線層 (631)を構成する低誘電率材料 よりも誘電率と膜強度が高い絶縁膜からなる配線層 (632)と、力 なる。  [0378] The global wiring layer (634) includes a via interlayer insulating film (633), which is an insulating film having a higher dielectric constant and film strength than the low dielectric constant material forming the multilayer local wiring layer (631), and a via interlayer insulating film. The wiring layer (632) formed of an insulating film having a higher dielectric constant and a higher film strength than the low dielectric constant material forming the multilayer local wiring layer (631) is formed above the film (633).
[0379] また、ローカル配線（638)とグローバル配線（639)力 なる多層配線の上方には、 チップ外部と電気信号の送受信を行う金属ボンディングパッド（635)が配置されて 、 る。 [0380] 本実施例においては、配線層（632)及びビア層間絶縁膜 (633)はそれぞれ SiO [0379] A metal bonding pad (635) for transmitting and receiving an electric signal to and from the outside of the chip is arranged above the multi-layer wiring which serves as the local wiring (638) and the global wiring (639). In this embodiment, the wiring layer (632) and the via interlayer insulating film (633) are each made of SiO 2.
2 2
、 SiOF力らなる。 , SiOF forces.
[0381] 強度及び密着性が高いグローバル配線層 (634)中のビア層間絶縁膜 (633)内に は金属補強ビアパターンは存在せず、配線層 (632)内にのみ CMP平坦用ダミー配 線パターン (640)が存在する。  [0381] There is no metal reinforcing via pattern in the via interlayer insulating film (633) in the global wiring layer (634) having high strength and adhesion, and the dummy wiring for CMP flattening is only in the wiring layer (632). There is a pattern (640).
[0382] また、グローバル配線層 (634)には金属補強ビアパターンは存在せず、金属ボン デイングパッド（635)の下方の領域と、金属ボンディングパッド（635)の外縁から一 定の距離 (6331)内の領域とに、低誘電率層間膜からなるローカル配線層 (631)に おける上下方向に隣接する金属補強配線パターン相互間を接続する金属補強ビア パターン（636)が形成されて!、る。  [0382] Also, there is no metal reinforcing via pattern in the global wiring layer (634), and a certain distance (6331) from the area below the metal bonding pad (635) and the outer edge of the metal bonding pad (635). Metal reinforcing via patterns (636) connecting between vertically adjacent metal reinforcing wiring patterns in the local wiring layer (631) made of a low dielectric constant interlayer film are formed in the region in parentheses. .
[0383] さらに、本半導体装置の厚さ方向における金属補強ビアパターン（636)の長さは 同層の導電性金属ビア (637)の本半導体装置の厚さ方向における長さよりも大きく 設定されている。  Further, the length of the metal reinforcing via pattern (636) in the thickness direction of the present semiconductor device is set to be longer than the length of the conductive metal via (637) in the same layer in the thickness direction of the present semiconductor device. I have.
[0384] ここで、ボンディング時の衝撃に対して、グローバル配線層（634)は、配線層（632 )及びビア層間絶縁膜 (633)の膜強度及び密着性が高いため、ボンディング時の衝 撃または応力に対して耐えることが可能となる。また、ローカル配線層（631)には金 属補強ビアパターン (636)が存在することにより、層間絶縁膜における強度及び密 着性を増大させることが可能となり、ボンディング時の衝撃や応力に起因する膜剥が れゃ膜破壊を防止することが可能となる。  [0384] Here, the global wiring layer (634) has a high film strength and adhesion of the wiring layer (632) and the via interlayer insulating film (633) against the shock at the time of bonding. Alternatively, it is possible to withstand stress. In addition, the presence of the metal reinforcing via pattern (636) in the local wiring layer (631) makes it possible to increase the strength and adhesion of the interlayer insulating film, resulting in the impact and stress during bonding. It is possible to prevent film peeling and film destruction.
(実施例 7)  (Example 7)
本発明の第 1の態様に係る半導体装置の他の実施例を説明する。  Another embodiment of the semiconductor device according to the first aspect of the present invention will be described.
[0385] 本実施例に係る半導体装置は、実施例 1に係る半導体装置と同様にして形成した The semiconductor device according to this example was formed in the same manner as the semiconductor device according to Example 1.
[0386] 図 30に示した半導体装置と同様に、本実施例に係る半導体装置の形成において は、半導体基板（111)上に形成された絶縁膜（112)を形成し、さらに、絶縁膜（112 )上に第一配線層 (113)を形成する。 As in the case of the semiconductor device shown in FIG. 30, in forming the semiconductor device according to the present example, an insulating film (112) formed on a semiconductor substrate (111) is formed, and further, an insulating film (112) is formed. A first wiring layer (113) is formed on (112).
[0387] 第一配線層 (113)には、回路を電気的に接続する金属回路配線 (または、導電性 金属配線）（115)と、回路とは電気的な接続を持たない金属補強配線パターン（116 )と、が形成される。 [0387] The first wiring layer (113) includes a metal circuit wiring (or conductive metal wiring) (115) for electrically connecting the circuit and a metal reinforcing wiring pattern having no electrical connection to the circuit. (116 ) Is formed.
[0388] 第一配線層（113)上には、第一層間絶縁膜 (117)が形成される。  [0388] On the first wiring layer (113), a first interlayer insulating film (117) is formed.
[0389] 第一層間絶縁膜（117)中には、上下の金属回路配線（115、 121)を相互に電気 的に接続する導電性金属ビア（118)と、上下の金属補強配線パターンを接続する金 属補強ビアパターン（119)と、を形成する。  [0389] In the first interlayer insulating film (117), a conductive metal via (118) for electrically connecting the upper and lower metal circuit wirings (115, 121) to each other, and an upper and lower metal reinforcing wiring pattern are provided. A metal reinforcing via pattern (119) to be connected is formed.
[0390] さらに、第一層間絶縁膜（117)上には、第二配線層（120)を形成する。 [0390] Further, a second wiring layer (120) is formed on the first interlayer insulating film (117).
[0391] 第二配線層（120)中には、金属回路配線（121)と、金属補強配線パターン（122) と、を形成する。 [0391] In the second wiring layer (120), a metal circuit wiring (121) and a metal reinforcing wiring pattern (122) are formed.
[0392] このように、配線層と層間絶縁膜とが交互に積層されることにより、多層回路構造が 形成されている。  [0392] As described above, a multilayer circuit structure is formed by alternately stacking the wiring layers and the interlayer insulating films.
[0393] 金属補強ビアパターン（119)は第一及び第二配線層 (113, 120)の金属補強配 線パターン（116、 122)を相互に接続することにより、多層支持構造を形成している  [0393] The metal reinforced via pattern (119) forms a multilayer support structure by connecting the metal reinforced wiring patterns (116, 122) of the first and second wiring layers (113, 120) to each other.
[0394] 以上のような構成を有する本実施例に係る半導体装置において、本半導体装置の 単位面積当たりに存在するビアの総面積の割合、すなわち、導電性金属ビア（118) の面積と金属補強ビアパターン（119)の面積との和が本半導体装置の単位面積に 占める割合を変動させた。 [0394] In the semiconductor device according to the present embodiment having the above configuration, the ratio of the total area of the vias per unit area of the semiconductor device, that is, the area of the conductive metal via (118) and the metal reinforcement The ratio of the sum of the area of the via pattern (119) and the unit area of the semiconductor device was varied.
[0395] 図 62は、低誘電率膜を層間絶縁膜に用いた半導体装置の単位面積に対するビア  [0395] FIG. 62 shows vias per unit area of a semiconductor device using a low dielectric constant film as an interlayer insulating film.
(導電性金属ビア及び金属補強ビアパターン)の総面積の割合と、 2psiの荷重にて C u—CMPを行った場合に、層間絶縁膜の剥がれに起因して発生する欠陥数を光学 欠陥モニタ装置で測定した個数との関係を示すグラフである。  The optical defect monitor monitors the ratio of the total area of the (conductive metal via and metal reinforcing via pattern) and the number of defects that occur due to peeling of the interlayer insulating film when Cu-CMP is performed under a load of 2 psi. It is a graph which shows the relationship with the number measured with the apparatus.
[0396] 図 62に示すように、半導体装置の単位面積当たりのビア (導電性金属ビア及び金 属補強ビアパターン)の総面積の割合が 10%以上になると、 CMP時における欠陥 の個数が大きく低下し、膜剥がれの割合を減少させることが可能となることがわかる。 (実施例 8)  As shown in FIG. 62, when the ratio of the total area of vias (conductive metal vias and metal reinforcing via patterns) per unit area of the semiconductor device is 10% or more, the number of defects during CMP increases. It can be seen that it is possible to reduce the rate of film peeling. (Example 8)
本発明の第 2の態様に係る半導体装置の他の実施例を説明する。  Another embodiment of the semiconductor device according to the second aspect of the present invention will be described.
[0397] 本実施例に係る半導体装置は、実施例 2に係る半導体装置と同様にして形成した [0398] 図 33に示した半導体装置と同様に、本実施例に係る半導体装置の形成において は、まず、トランジスタ（2211)が形成された半導体基板 (211)上に絶縁膜 (212)を 形成し、この絶縁膜 (212)上に第一配線層 (213)を形成した。 [0397] The semiconductor device according to this example was formed in the same manner as the semiconductor device according to Example 2. As in the case of the semiconductor device shown in FIG. 33, in forming the semiconductor device according to this example, first, an insulating film (212) is formed on a semiconductor substrate (211) on which a transistor (2211) is formed. Then, a first wiring layer (213) was formed on the insulating film (212).
[0399] 第一配線層 (213)には、回路を電気的に接続する金属回路配線 (または、導電性 金属配線）（215)と、回路とは電気的な接続を持たない金属ダミー配線 (216)と、が 形成されている。  [0399] The first wiring layer (213) includes a metal circuit wiring (or a conductive metal wiring) (215) for electrically connecting a circuit and a metal dummy wiring (215) having no electrical connection to the circuit. 216) is formed.
[0400] 第一配線層（213)上には、第一層間絶縁膜 (217)が形成される。  [0400] A first interlayer insulating film (217) is formed on the first wiring layer (213).
[0401] 第一層間絶縁膜 (217)中には、上下の金属回路配線 (223、 219)を相互に電気 的に接続する導電性金属ビア（224)と、上下の金属補強配線パターンを接続する金 属補強ビアパターン (225)と、が形成されている。  [0401] In the first interlayer insulating film (217), conductive metal vias (224) for electrically connecting the upper and lower metal circuit wirings (223, 219) to each other, and upper and lower metal reinforcing wiring patterns are provided. A metal reinforcing via pattern (225) to be connected is formed.
[0402] 第一層間絶縁膜 (217)上には、第二配線層（218)が形成されている。 [0402] On the first interlayer insulating film (217), a second wiring layer (218) is formed.
[0403] 第二配線層（218)中には、金属回路配線（219)と、金属補強配線パターン（220) と、が形成されている。 [0403] In the second wiring layer (218), a metal circuit wiring (219) and a metal reinforcing wiring pattern (220) are formed.
[0404] このように、配線層と層間絶縁膜とが交互に積層されることにより、多層回路構造が 形成されている。  [0404] As described above, a multilayer circuit structure is formed by alternately stacking the wiring layers and the interlayer insulating films.
[0405] 多層回路構造上には、チップ外部と電気信号の送受信を行う金属ボンディングパッ ド（221)が形成されている。この金属ボンディングパッド（221)は最上層の第二配線 層（218)に形成された金属回路配線（219)と電気的に接続されている。  [0405] On the multilayer circuit structure, a metal bonding pad (221) for transmitting and receiving electric signals to and from the outside of the chip is formed. The metal bonding pad (221) is electrically connected to the metal circuit wiring (219) formed on the uppermost second wiring layer (218).
[0406] また、金属ボンディングパッド（221)の下方の領域にぉ 、ても、金属ボンディングパ ッド（221)が無 ヽ領域（回路領域)と同様に、トランジスタ（2211)、金属回路配線 (2 15)、金属導電性金属ビア（224)が存在する。  [0406] Further, even in the region below the metal bonding pad (221), the transistor (2211) and the metal circuit wiring ( 2 15), there is a metal conductive metal via (224).
[0407] また、本実施例においては、金属ボンディングパッド（221)の下方の領域にのみ、 上下層の金属補強配線パターン（216、 220)が相互に重なり合う領域を接続する金 属補強ビアパターン (225)が存在する。  In this embodiment, the metal reinforcing via patterns (216, 220) connecting the areas where the upper and lower metal reinforcing wiring patterns (216, 220) overlap each other are formed only in the area below the metal bonding pad (221). 225) exists.
[0408] 以上のような構成を有する本実施例に係る半導体装置において、金属ボンディン グパッド（221)の下方の領域の本半導体装置の単位面積当たりに存在するビアの総 面積の割合、すなわち、導電性金属ビア（224)の面積と金属補強ビアパターン (22 5)の面積との和が本半導体装置の単位面積に占める割合を変動させた。 [0409] 図 63は、低誘電率膜を層間絶縁膜に用いた半導体装置の金属ボンディングパッド の下方の領域の単位面積に対するビア (導電性金属ビア及び金属補強ビアパターン )の総面積の割合と、ボールシェア法により測定した金属ボンディングパッドとボンデ イングワイヤとの間の密着硬度との関係を示すグラフである。 In the semiconductor device according to the present embodiment having the above-described configuration, the ratio of the total area of vias existing per unit area of the semiconductor device in the region below the metal bonding pad (221), The ratio of the sum of the area of the conductive metal via (224) and the area of the metal reinforcing via pattern (225) to the unit area of the semiconductor device was changed. [0409] FIG. 63 shows the ratio of the total area of vias (conductive metal vias and metal reinforcing via patterns) to the unit area of the region below the metal bonding pad of a semiconductor device using a low dielectric constant film as an interlayer insulating film. 4 is a graph showing the relationship between the adhesion hardness between a metal bonding pad and a bonding wire measured by a ball shear method.
[0410] 図 63に示すように、金属ボンディングパッドの下方の領域における半導体装置の 単位面積当たりのビア (導電性金属ビア及び金属補強ビアパターン)の総面積の割 合が 10%以上になると、金属ボンディングパッドとボンディングワイヤとの間の密着硬 度を大きく高めることが可能であることが判明した。  [0410] As shown in Fig. 63, when the ratio of the total area of the vias (conductive metal vias and metal reinforcing via patterns) per unit area of the semiconductor device in the region below the metal bonding pad becomes 10% or more, It has been found that the adhesion hardness between the metal bonding pad and the bonding wire can be greatly increased.
(実施例 9)  (Example 9)
図 64及び図 65は、いずれも本発明の第 3の態様に係る半導体装置の他の実施例 の断面図である。  FIGS. 64 and 65 are cross-sectional views of another example of the semiconductor device according to the third embodiment of the present invention.
[0411] 以下、図 64及び図 65を参照して、本発明の第 3の態様に係る半導体装置の他の 実施例を説明する。まず、双方の実施例に係る半導体装置に共通する構造につい て説明する。  [0411] Hereinafter, another embodiment of the semiconductor device according to the third aspect of the present invention will be described with reference to FIGS. First, a structure common to the semiconductor devices according to both embodiments will be described.
[0412] 図 64及び図 65に示すように、本実施例に係る半導体装置は、半導体基板（711) と、半導体基板 (711)上に形成されたトランジスタ（7221)と、トランジスタ（7221)を 覆って、半導体基板 (711)上に形成された絶縁膜 (712)と、を備えている。  As shown in FIGS. 64 and 65, the semiconductor device according to the present example includes a semiconductor substrate (711), a transistor (7221) formed on the semiconductor substrate (711), and a transistor (7221). And an insulating film (712) formed on the semiconductor substrate (711).
[0413] 本実施例における半導体基板（711)は単結晶シリコン基板力もなる。 [0413] The semiconductor substrate (711) in this embodiment also has a single crystal silicon substrate strength.
[0414] また、絶縁膜（712)はボロフォスフオシリケート'ガラス（BPSG :borophosphosilic ate glass)、フォスフオシリケート'ガラス（PSG： phosphosilicate glass)、酸ィ匕シリ コン（SiO )、窒化シリコン（SiN)、酸窒化シリコン（SiON)、酸弗化シリコン（SiOF)、 [0414] The insulating film (712) is made of borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), phosphosilicate glass (PSG), silicon dioxide (SiO 2), silicon nitride (SiN ), Silicon oxynitride (SiON), silicon oxyfluoride (SiOF),
2  2
炭化シリコン (SiC)、炭窒化シリコン（SiCN)等の絶縁材料またはそれらの組み合わ せから構成されている。  It is composed of insulating materials such as silicon carbide (SiC) and silicon carbonitride (SiCN) or a combination thereof.
[0415] 絶縁膜 (712)上には、第一配線層（713)が形成されている。 [0415] The first wiring layer (713) is formed on the insulating film (712).
[0416] 本実施例においては、第一配線層 (713)は低誘電率材料の有機ポリマー、 MSQ[0416] In this embodiment, the first wiring layer (713) is made of an organic polymer of low dielectric constant material, MSQ
、 HSQまたは炭素含有シリコン酸ィ匕膜である力 エッチングストッパー及びノヽードマ スクをなす SiN、 SiOC、 SiC、 SiCN, SiO等との積層膜力も構成することもできる。 , HSQ or a carbon-containing silicon oxide film. A stacked film strength with SiN, SiOC, SiC, SiCN, SiO, etc. forming an etching stopper and a node mask can also be formed.
2  2
[0417] 第一配線層（713)には、回路を電気的に接続する金属回路配線 (715)と、回路と は電気的な接続を持たな 、金属補強配線パターン (716)と、が形成されて!、る。 [0417] In the first wiring layer (713), a metal circuit wiring (715) for electrically connecting circuits, and a circuit Has no electrical connection, a metal reinforced wiring pattern (716) is formed!
[0418] 第一配線層（713)上には、第一層間絶縁膜 (717)が形成されている。 [0418] On the first wiring layer (713), a first interlayer insulating film (717) is formed.
[0419] 第一層間絶縁膜 (717)には、第一及び第二配線層（713、 718)中にそれぞれ設 けられた導電性金属配線 (715、 719)を相互に電気的に接続する導電性金属ビア（ 725)と、第一及び第二配線層（713、 718)中にそれぞれ設けられた金属補強配線 パターン（716、 720)を相互に接続する金属補強ビアパターン（726)と、が形成され ている。 [0419] The first interlayer insulating film (717) is electrically connected to conductive metal wirings (715, 719) provided in the first and second wiring layers (713, 718), respectively. And a metal reinforcing via pattern (726) interconnecting the metal reinforcing wiring patterns (716, 720) provided in the first and second wiring layers (713, 718), respectively. Are formed.
[0420] 本実施例においては、第一層間絶縁膜 (717)は低誘電率材料の有機ポリマー、 MSQ、 HSQまたは炭素含有シリコン酸ィ匕膜である力 エッチングストッパー及びノヽ ードマスクをなす SiC、 SiCN、 SiO等との積層膜から構成することもできる。  In this embodiment, the first interlayer insulating film (717) is an organic polymer of a low dielectric constant material, MSQ, HSQ or a silicon-containing film containing carbon. It can also be composed of a laminated film of SiCN, SiO, etc.
2  2
[0421] 第一層間絶縁膜 (717)上には、第二配線層（718)が形成されている。  [0421] On the first interlayer insulating film (717), a second wiring layer (718) is formed.
[0422] 第二配線層 (718)には、金属回路配線 (719)と金属補強配線パターン (720)とが 形成されている。 [0422] In the second wiring layer (718), a metal circuit wiring (719) and a metal reinforcing wiring pattern (720) are formed.
[0423] 本実施例においては、第二配線層 (718)は低誘電率材料の有機ポリマー、 MSQ 、 HSQまたは炭素含有シリコン酸ィ匕膜である力 エッチングストッパー及びノヽードマ スクをなす SiN、 SiOC、 SiC、 SiCN、 SiO等との積層膜力も構成することもできる。  In the present embodiment, the second wiring layer (718) is made of an organic polymer of low dielectric constant material, MSQ, HSQ or a silicon-containing film containing carbon. The etching stopper and the SiN, SiOC forming the node mask are used. , SiC, SiCN, SiO and the like can also be formed.
2  2
[0424] 第二配線層（718)上には、第二層間絶縁膜 (721)が形成されている。  [0424] On the second wiring layer (718), a second interlayer insulating film (721) is formed.
[0425] 第二層間絶縁膜 (721)は第一層間絶縁膜 (717)と同じ材質力も形成されている。 [0425] The second interlayer insulating film (721) has the same material strength as the first interlayer insulating film (717).
[0426] 第二層間絶縁膜 (721)上には、第 3配線層（722)が形成されている。 [0426] On the second interlayer insulating film (721), a third wiring layer (722) is formed.
[0427] 第 3配線層 (722)は第二配線層 (718)と同じ材質カゝら形成されている。 [0427] The third wiring layer (722) is formed of the same material as the second wiring layer (718).
[0428] このように、配線層と層間絶縁膜とが交互に積層されることにより、多層回路構造が 形成されている。 [0428] As described above, a multilayer circuit structure is formed by alternately stacking the wiring layers and the interlayer insulating films.
[0429] 多層回路構造上には、チップ外部と電気信号の送受信を行う金属ボンディングパッ ド（723)が形成されている。この金属ボンディングパッド（723)は最上層の第 3配線 層（722)に形成された金属回路配線（724)と電気的に接続されている。  [0429] On the multilayer circuit structure, a metal bonding pad (723) for transmitting and receiving an electric signal to and from the outside of the chip is formed. The metal bonding pad (723) is electrically connected to the metal circuit wiring (724) formed on the uppermost third wiring layer (722).
[0430] また、金属ボンディングパッド（723)の下方の領域にぉ 、ても、金属ボンディングパ ッド（723)が無い領域（回路領域)と同様に、トランジスタ（7221)、金属回路配線 (7 15、 719)、金属導電性金属ビア（725)が存在する。 [0431] 図 64及び図 65に示す実施例に係る半導体装置においては、回路領域（1200)内 の金属ボンディングパッド（723)の下方において、本半導体装置の厚さ方向に積み 重ねられた金属回路配線（724、 719、 715)と、導電性金属ビア（727、 725)と、力 ら多層回路構造が形成されて ヽる。 [0430] Even in the region below the metal bonding pad (723), similarly to the region (circuit region) where the metal bonding pad (723) is not provided, the transistor (7221) and the metal circuit wiring (7 15, 719), metal conductive metal vias (725) are present. In the semiconductor device according to the embodiment shown in FIGS. 64 and 65, the metal circuits stacked in the thickness direction of the semiconductor device below the metal bonding pad (723) in the circuit region (1200) Wirings (724, 719, 715), conductive metal vias (727, 725), and a multilayer circuit structure are formed by force.
[0432] さらに、回路領域（1200)内において、本半導体装置の厚さ方向に積み重ねられ た金属補強配線パターン（729、 720、 716)と、これらを相互に連結する金属補強ビ ァパターン (728、 726)と、力も多層支持構造が形成されている。多層支持構造は、 多層回路構造が形成されている回路領域における間隙部に存在している。すなわち 、多層支持構造は、多層回路構造が形成されている回路領域（1200)の内部にお いて、多層回路構造と抵触しないように、多層回路構造が存在しない領域に形成さ れている。  [0432] Further, in the circuit area (1200), the metal reinforcing wiring patterns (729, 720, 716) stacked in the thickness direction of the semiconductor device and the metal reinforcing via patterns (728, 726), the force also forms a multilayer support structure. The multilayer support structure is present in a gap in a circuit area where the multilayer circuit structure is formed. That is, the multilayer support structure is formed in a region where the multilayer circuit structure does not exist so as not to conflict with the multilayer circuit structure inside the circuit region (1200) where the multilayer circuit structure is formed.
[0433] また、回路領域（1200) (金属ボンディングパッド（723)の下方の領域を含む）の外 側の領域であるスクライブ領域（1300)内においても、本半導体装置の厚さ方向に 積み重ねられた金属補強配線パターン（729、 720、 716)と、これらを相互に連結す る金属補強ビアパターン (728、 726)と、によっても多層支持構造が形成されている  [0433] Also, in the scribe region (1300), which is the region outside the circuit region (1200) (including the region below the metal bonding pad (723)), the semiconductor device is stacked in the thickness direction. Metal supporting wiring patterns (729, 720, 716) and metal reinforcing via patterns (728, 726) interconnecting them form a multilayer support structure.
[0434] スクライブ領域（1300)に形成された金属補強配線パターン（716、 720、 729)及 び金属補強ビアパターン（726、 728)からなる多層支持構造は、図 24及び図 25ある いは図 28及び図 28に示したように、スクライブ領域（1300)の全体にわたつて均一 に配されており、半導体チップの四つの角部、すなわち、十字マーク Xの下方の領域 にも形成されている。 [0434] The multilayer support structure including the metal reinforcing wiring patterns (716, 720, 729) and the metal reinforcing via patterns (726, 728) formed in the scribe area (1300) is shown in Figs. As shown in FIG. 28 and FIG. 28, the scribe area (1300) is uniformly distributed over the entire area, and is also formed in the four corners of the semiconductor chip, that is, in the area below the cross mark X. .
[0435] このため、半導体チップの周縁の近傍及び角部における多層回路構造の強度及 び密着性を高めることができ、信頼性の高 、半導体装置を提供することができる。  [0435] Therefore, the strength and adhesion of the multilayer circuit structure in the vicinity and at the corners of the periphery of the semiconductor chip can be increased, and a highly reliable semiconductor device can be provided.
[0436] ただし、多層支持構造の平面的配置は上記の例に限定されるものではなぐ例え ば、十字マーク Xの下方の領域のみに形成してもよぐあるいは、半導体チップの角 部を除く周縁辺に沿った領域にのみ形成することもできる。 [0436] However, the planar arrangement of the multilayer support structure is not limited to the above example. For example, the multilayer support structure may be formed only in the region below the cross mark X or excluding the corners of the semiconductor chip. It can also be formed only in the region along the peripheral edge.
[0437] 図 65に示す実施例に係る半導体装置は、図 64に示す実施例に係る半導体装置と 比較して、金属ボンディングパッド（723)が形成されている位置よりもチップ外周縁 側の回路領域、すなわち、金属ボンディングパッド (723)の外側とスクライブ領域（13 00)との間にシールド（730)が形成されている点が異なる。 The semiconductor device according to the embodiment shown in FIG. 65 is different from the semiconductor device according to the embodiment shown in FIG. 64 in that the outer peripheral edge of the chip is located at a position closer to the position where the metal bonding pad (723) is formed. The difference lies in that a shield (730) is formed between the circuit region on the side, that is, the outside of the metal bonding pad (723) and the scribe region (1300).
[0438] シールド（730)は、金属補強配線パターンと金属補強ビアパターンとが積層された 積層体力もなる。すなわち、シールド (730)は多層支持構造と同様の構造を有して いる。 [0438] The shield (730) also has a laminated body strength in which the metal reinforcing wiring pattern and the metal reinforcing via pattern are stacked. That is, the shield (730) has the same structure as the multilayer support structure.
[0439] シールド（730)は、図 29に示したように、半導体チップの外周縁に沿って全周にわ たって連続的に配置されている。このため、半導体装置の外部から回路領域（1200 )への水分の侵入を有効に阻止することができる。  [0439] As shown in FIG. 29, the shield (730) is arranged continuously over the entire periphery along the outer peripheral edge of the semiconductor chip. Therefore, it is possible to effectively prevent moisture from entering the circuit region (1200) from outside the semiconductor device.
[0440] さらに、シールド（730)は金属補強配線パターンと金属補強ビアパターンと力もな る多層支持構造でもあるため、金属ボンディングパッド (723)の外側とスクライブ領域 (1300)との間において、積層体を構成する各層の間の密着性を高める作用も併せ て発揮する。  [0440] Further, since the shield (730) is also a multi-layered support structure that also acts as a metal reinforcing wiring pattern and a metal reinforcing via pattern, a layer is formed between the outside of the metal bonding pad (723) and the scribe area (1300). It also exerts the effect of increasing the adhesion between the layers constituting the body.
[0441] また、図 64及び図 65に示す実施例に係る半導体装置においては、いずれも、回 路領域（1200) (金属ボンディングパッド（723)の下方の領域を含む）にも、スクライ ブ領域（1300)と同様に、金属補強配線パターン（716、 720、 729)及び金属補強 ビアパターン（726、 728)からなる多層支持構造が形成されて!、る。  In the semiconductor device according to the embodiment shown in FIGS. 64 and 65, both the circuit region (1200) (including the region below the metal bonding pad (723)) and the scribe region Similarly to (1300), a multi-layer support structure composed of metal reinforcing wiring patterns (716, 720, 729) and metal reinforcing via patterns (726, 728) is formed.
[0442] このため、第 1の態様の実施例に係る半導体装置において述べたような、 LSIの強 度や密着性を増大させることができ、化学機械研磨 (CMP)プロセスの際やチップパ ッケージング時に印加される衝撃や応力によって膜剥がれや膜破壊を防止すること ができる。その結果として、金属ボンディングパッド（723)の下方の領域におけるワイ ャボンディング時の衝撃や応力に起因する膜剥がれや膜破壊を防止することができ る。  [0442] For this reason, as described in the semiconductor device according to the example of the first aspect, the strength and adhesion of the LSI can be increased, so that it can be used during a chemical mechanical polishing (CMP) process or chip packaging. Film peeling and film destruction can be prevented by the applied impact and stress. As a result, it is possible to prevent film peeling and film destruction due to impact and stress during wire bonding in a region below the metal bonding pad (723).
[0443] なお、図 64及び図 65に示す実施例に係る半導体装置においては、回路領域（12 00) (金属ボンディングパッド（723)の下方の領域を含む）に多層支持構造が形成さ れて 、ることは必ずしも必要ではな!/、。  In the semiconductor device according to the embodiment shown in FIGS. 64 and 65, a multilayer support structure is formed in the circuit region (12000) (including the region below the metal bonding pad (723)). It is not necessary!
[0444] 図 64及び図 65に示す実施例に係る半導体装置においては、金属ボンディングパ ッド（723)の下方の領域に回路領域をなすトランジスタ（7221)と、金属回路配線 (7 15、 719、 724)及び導電性金属ビア（724、 727)からなる多層回路構造が存在す る場合について述べた力 金属ボンディングパッド（723)の下方の領域には、トラン ジスタ（7221)並びに多層回路構造を形成する金属回路配線及び導電性金属ビア の何れか一つのみが配置されていてもよい。あるいは、トランジスタ（7221)及び多層 回路構造の何れもが金属ボンディングパッド（723)の下方の領域には配置されてお らず、金属ボンディングパッド（723)の下方の領域には、金属補強配線パターン（71 6、 720、 729)と金属補強ビアパターン（726、 728)とからなる多層支持構造のみが 配置されていてもよい。 In the semiconductor device according to the embodiment shown in FIGS. 64 and 65, a transistor (7221) forming a circuit area below the metal bonding pad (723) and a metal circuit wiring (715, 719) 724) and conductive metal vias (724, 727). In the region below the metal bonding pad (723), only the transistor (7221) and one of the metal circuit wiring and the conductive metal via forming the multilayer circuit structure are arranged. Is also good. Alternatively, neither the transistor (7221) nor the multilayer circuit structure is arranged in the region below the metal bonding pad (723), and the region below the metal bonding pad (723) is formed in the metal reinforcing wiring pattern. Only a multi-layer support structure consisting of (716, 720, 729) and metal reinforcing via patterns (726, 728) may be arranged.
[0445] なお、図 64及び図 65に示す実施例に係る半導体装置においては、導電性金属ビ ァと導電性金属配線とを別々に形成するシングルダマシンプロセスが用いられて!/、る 力 導電性金属ビアと導電性金属配線とを同時に形成するデュアルダマシンプロセ スを用いることも可能である。  In the semiconductor device according to the embodiment shown in FIGS. 64 and 65, a single damascene process for separately forming a conductive metal via and a conductive metal wiring is used. It is also possible to use a dual damascene process for simultaneously forming conductive metal vias and conductive metal wiring.
図面の簡単な説明  Brief Description of Drawings
[0446] [図 1]従来の半導体装置の断面図である。 FIG. 1 is a cross-sectional view of a conventional semiconductor device.
[図 2]従来の半導体装置におけるボンディング時のパッド剥がれを示す図である。  FIG. 2 is a diagram showing pad peeling during bonding in a conventional semiconductor device.
[図 3]従来のボンディングパッド構造の一例を示す断面図である。  FIG. 3 is a cross-sectional view showing one example of a conventional bonding pad structure.
[図 4]本発明の第 1の態様に係る半導体装置の一実施形態を示す模式的断面図で ある。  FIG. 4 is a schematic sectional view showing one embodiment of the semiconductor device according to the first aspect of the present invention.
[図 5]本発明の第 1の態様に係る半導体装置の他の実施形態を示す模式的断面図 である。  FIG. 5 is a schematic sectional view showing another embodiment of the semiconductor device according to the first aspect of the present invention.
[図 6]本発明の第 1の態様に係る半導体装置の他の実施形態を示す模式的断面図 である。  FIG. 6 is a schematic sectional view showing another embodiment of the semiconductor device according to the first aspect of the present invention.
[図 7]本発明の第 1の態様に係る半導体装置の他の実施形態を示す模式的断面図 である。  FIG. 7 is a schematic sectional view showing another embodiment of the semiconductor device according to the first aspect of the present invention.
[図 8]本発明の第 1の態様に係る半導体装置の他の実施形態を示す模式的断面図 である。  FIG. 8 is a schematic sectional view showing another embodiment of the semiconductor device according to the first aspect of the present invention.
[図 9]本発明の第 1の態様に係る半導体装置の等価回路を示す回路図である。  FIG. 9 is a circuit diagram showing an equivalent circuit of the semiconductor device according to the first embodiment of the present invention.
[図 10]本発明の第 1の態様に係る半導体装置の製造方法における一製造工程を示 す断面図である。 圆 11]本発明の第 1の態様に係る半導体装置の製造方法における一製造工程を示 す断面図である。 FIG. 10 is a cross-sectional view showing one manufacturing step in the method for manufacturing a semiconductor device according to the first embodiment of the present invention. [11] FIG. 11 is a cross-sectional view showing one manufacturing step in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
圆 12]本発明の第 1の態様に係る半導体装置の製造方法における一製造工程を示 す断面図である。 [12] FIG. 12 is a cross-sectional view showing one manufacturing step in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
圆 13]本発明の第 1の態様に係る半導体装置の製造方法における一製造工程を示 す断面図である。 [13] FIG. 13 is a cross-sectional view showing one manufacturing step in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
圆 14]本発明の第 1の態様に係る半導体装置の製造方法における一製造工程を示 す断面図である。 [14] FIG. 14 is a cross-sectional view showing one manufacturing step in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
圆 15]本発明の第 1の態様に係る半導体装置の製造方法における一製造工程を示 す断面図である。 [15] FIG. 15 is a cross-sectional view showing one manufacturing step in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
圆 16]本発明の第 1の態様に係る半導体装置の製造方法における一製造工程を示 す断面図である。 [16] FIG. 16 is a cross-sectional view showing one manufacturing step in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
圆 17]本発明の第 1の態様に係る半導体装置の製造方法における一製造工程を示 す断面図である。 [17] FIG. 17 is a cross-sectional view showing one manufacturing step in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
圆 18]本発明の第 1の態様に係る半導体装置の製造方法における一製造工程を示 す断面図である。 [18] FIG. 18 is a cross-sectional view showing one manufacturing step in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
圆 19]本発明の第 1の態様に係る半導体装置の製造方法における一製造工程を示 す断面図である。 [19] FIG. 19 is a cross-sectional view showing one manufacturing step in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
[図 20]本発明の第 2の態様に係る半導体装置の一実施形態を示す模式的断面図で ある。  FIG. 20 is a schematic cross-sectional view showing one embodiment of a semiconductor device according to a second aspect of the present invention.
圆 21]本発明の第 2の態様に係る半導体装置における多層支持構造の存在領域の 一例を模式的に示す平面図である。 [21] FIG. 21 is a plan view schematically showing an example of a region where a multilayer support structure exists in a semiconductor device according to a second embodiment of the present invention.
圆 22]本発明の第 2の態様に係る半導体装置における多層支持構造の存在領域の 一例を模式的に示す平面図である。 [22] FIG. 22 is a plan view schematically showing an example of a region where a multilayer support structure exists in a semiconductor device according to a second embodiment of the present invention.
圆 23]本発明の第 3の態様に係る半導体装置の一実施形態を示す模式的断面図で ある。 [23] FIG. 23 is a schematic sectional view showing one embodiment of a semiconductor device according to a third aspect of the present invention.
圆 24]本発明の第 3の態様に係る半導体装置における回路領域とスクライブ領域と の位置関係を模式的に示す平面図である。 [図 25]図 24に示した領域 Bの拡大平面図である。 [24] FIG. 24 is a plan view schematically showing a positional relationship between a circuit region and a scribe region in a semiconductor device according to a third embodiment of the present invention. 25 is an enlarged plan view of a region B shown in FIG. 24.
[図 26]半導体チップのコーナーに設けられた十字マークの形状を示す平面図である  FIG. 26 is a plan view showing the shape of a cross mark provided at a corner of a semiconductor chip.
[図 27]本発明の第 3の態様に係る半導体装置の別の実施形態を示す模式的断面図 である。 FIG. 27 is a schematic sectional view showing another embodiment of the semiconductor device according to the third aspect of the present invention.
圆 28]図 27に示す半導体装置における回路領域とスクライブ領域との位置関係を模 式的に示す平面図である。 [28] FIG. 28 is a plan view schematically showing a positional relationship between a circuit region and a scribe region in the semiconductor device shown in FIG. 27.
[図 29]図 28に示した領域 Eの拡大平面図である。  FIG. 29 is an enlarged plan view of a region E shown in FIG. 28.
圆 30]本発明の第 1の態様に係る半導体装置の一実施例の断面図である。 FIG. 30 is a cross-sectional view of one example of the semiconductor device according to the first embodiment of the present invention.
[図 31]図 30に示した実施例に係る半導体装置の平面図である。  FIG. 31 is a plan view of the semiconductor device according to the embodiment shown in FIG. 30.
圆 32]低誘電率膜を層間絶縁膜に用 、た場合の金属補強ビアパターンの面積占有 率 (半導体装置の単位面積に対する金属補強ビアパターンの面積が占める割合)と圆 32] When the low dielectric constant film is used as the interlayer insulating film, the area occupation ratio of the metal reinforcing via pattern (the ratio of the area of the metal reinforcing via pattern to the unit area of the semiconductor device) and
CMP時の膜剥がれの割合との関係を示すグラフである。 6 is a graph showing a relationship with a rate of film peeling during CMP.
圆 33]本発明の第 2の態様に係る半導体装置の一実施例の断面図である。 [33] FIG. 33 is a sectional view of an example of a semiconductor device according to a second embodiment of the present invention.
[図 34]図 33に示した実施例に係る半導体装置の平面図である。  FIG. 34 is a plan view of the semiconductor device according to the embodiment shown in FIG. 33.
圆 35]図 33に示した実施例に係る半導体装置において、低誘電率膜を層間絶縁膜 に用いた場合の金属ボンディングパッドの下方の領域における金属補強ビアパター ンの面積割合 (ビア占有率（％) )とワイヤボンディング時の膜剥がれの割合 (ボンディ ング不良割合 (％) )との関係を示すグラフである。 [35] In the semiconductor device according to the embodiment shown in FIG. 33, when the low dielectric constant film is used as the interlayer insulating film, the area ratio of the metal reinforcing via pattern in the region below the metal bonding pad (via occupancy (% 3 is a graph showing the relationship between the percentage of film peeling during wire bonding (bonding failure rate (%)).
圆 36]本発明の第 2の態様に係る半導体装置の一実施例を応用したハイスペック LS Iの断面図である。 [36] FIG. 36 is a cross-sectional view of a high-spec LSI to which an example of the semiconductor device according to the second embodiment of the present invention is applied.
圆 37]図 36に示した実施例に対する第一の変形例の断面図である。 FIG. 37 is a sectional view of a first modification of the embodiment shown in FIG. 36.
[図 38]図 36に示した実施例に対する第二の変形例の断面図である。  FIG. 38 is a sectional view of a second modification of the embodiment shown in FIG. 36.
[図 39]図 37及び図 38に示した半導体装置における大面積配線層パッドの形状の一 例を示す平面図である。  FIG. 39 is a plan view showing an example of the shape of a large-area wiring layer pad in the semiconductor device shown in FIGS. 37 and 38.
[図 40]図 37及び図 38に示した半導体装置における大面積配線層パッドの形状の一 例を示す平面図である。  FIG. 40 is a plan view showing an example of the shape of a large-area wiring layer pad in the semiconductor device shown in FIGS. 37 and 38.
圆 41]本発明の第 2の態様に係る半導体装置の他の実施例の断面図である。 圆 42]多層支持構造が存在する領域の金属ボンディングパッドの外縁からの距離と、 ボールシェア法で測定したボンディング部の密着強度との関係を示すグラフである。 [41] FIG. 41 is a cross-sectional view of another example of the semiconductor device according to the second embodiment of the present invention. 圆 42] A graph showing the relationship between the distance from the outer edge of the metal bonding pad in the region where the multilayer support structure exists and the adhesion strength of the bonding portion measured by the ball shear method.
[図 43]図 41に示した半導体装置の平面図である。  FIG. 43 is a plan view of the semiconductor device shown in FIG. 41.
[図 44]図 41に示した実施例を応用したノヽイスペック LSIの断面図である。  FIG. 44 is a sectional view of a noise-spec LSI to which the embodiment shown in FIG. 41 is applied.
圆 45]本発明の第一の態様に係る半導体装置の他の実施例の断面図である。 [45] FIG. 45 is a cross-sectional view of another example of the semiconductor device according to the first embodiment of the present invention.
[図 46]図 45に示した実施例に係る半導体装置の平面図である。  FIG. 46 is a plan view of the semiconductor device according to the embodiment shown in FIG. 45.
圆 47]図 45に示した半導体装置における金属補強ビアパターンの形状の一例を示 す平面図である。 [47] FIG. 47 is a plan view showing an example of the shape of a metal reinforcing via pattern in the semiconductor device shown in FIG. 45.
圆 48]図 45に示した半導体装置における金属補強ビアパターンの形状の一例を示 す平面図である。 [48] FIG. 48 is a plan view showing an example of the shape of a metal reinforcing via pattern in the semiconductor device shown in FIG. 45.
圆 49]図 45に示した半導体装置における金属補強ビアパターンの形状の一例を示 す平面図である。 [49] FIG. 45 is a plan view showing an example of the shape of a metal reinforcing via pattern in the semiconductor device shown in FIG. 45.
圆 50]本発明の第 2の態様に係る半導体装置の他の実施例の断面図である。 FIG. 50 is a cross-sectional view of another example of the semiconductor device according to the second embodiment of the present invention.
[図 51]図 50に示した実施例に係る半導体装置の平面図である。 FIG. 51 is a plan view of the semiconductor device according to the embodiment shown in FIG. 50.
圆 52]図 50に示した半導体装置における金属補強ビアパターンの形状の一例を示 す平面図である。 [52] FIG. 52 is a plan view showing an example of the shape of the metal reinforcing via pattern in the semiconductor device shown in FIG. 50.
圆 53]図 50に示した半導体装置における金属補強ビアパターンの形状の一例を示 す平面図である。 FIG. 53 is a plan view showing an example of the shape of a metal reinforcing via pattern in the semiconductor device shown in FIG. 50.
圆 54]図 50に示した半導体装置における金属補強ビアパターンの形状の一例を示 す平面図である。 [54] FIG. 54 is a plan view showing an example of the shape of a metal reinforcing via pattern in the semiconductor device shown in FIG. 50.
[図 55]図 50に示した実施例を応用したノ、イスペック LSIの断面図である。  FIG. 55 is a cross-sectional view of a Nos. Ispec LSI to which the embodiment shown in FIG. 50 is applied.
圆 56]本発明の第 2の態様に係る半導体装置の他の実施例の断面図である。 [56] FIG. 56 is a cross-sectional view of another example of the semiconductor device according to the second embodiment of the present invention.
[図 57]図 56に示した半導体装置の平面図である。 FIG. 57 is a plan view of the semiconductor device shown in FIG. 56.
圆 58]図 56に示した半導体装置における金属補強ビアパターンの形状の一例を示 す平面図である。 [58] FIG. 58 is a plan view showing an example of the shape of a metal reinforcing via pattern in the semiconductor device shown in FIG. 56.
圆 59]図 56に示した半導体装置における金属補強ビアパターンの形状の一例を示 す平面図である。 [59] FIG. 59 is a plan view showing an example of the shape of the metal reinforcing via pattern in the semiconductor device shown in FIG. 56.
圆 60]図 56に示した半導体装置における金属補強ビアパターンの形状の一例を示 す平面図である。 [60] shows an example of the shape of a metal reinforcing via pattern in the semiconductor device shown in FIG. FIG.
[図 61]図 56に示した実施例を応用したノヽイスペック LSIの断面図である。  FIG. 61 is a cross-sectional view of a noise-spec LSI to which the embodiment shown in FIG. 56 is applied.
圆 62]低誘電率膜を層間絶縁膜に用いた半導体装置の単位面積に対するビア (導 電性金属ビア及び金属補強ビアパターン)の総面積の割合と、 2psiの荷重にて Cu — CMPを行った場合に、層間絶縁膜の剥がれに起因して発生する欠陥数を光学欠 陥モニタ装置で測定した個数との関係を示すグラフである。 [62] Cu-CMP is performed with the ratio of the total area of vias (conductive metal vias and metal reinforcing via patterns) to the unit area of a semiconductor device using a low dielectric constant film as an interlayer insulating film, and a load of 2 psi. 4 is a graph showing a relationship between the number of defects generated due to peeling of an interlayer insulating film and the number measured by an optical defect monitoring device when the optical insulating film is removed.
圆 63]低誘電率膜を層間絶縁膜に用いた半導体装置の金属ボンディングパッドの下 方の領域の単位面積に対するビア (導電性金属ビア及び金属補強ビアパターン)の 総面積の割合と、ボールシェア法により測定した金属ボンディングパッドとボンディン グワイヤとの間の密着硬度との関係を示すグラフである。 圆 63] The ratio of the total area of the vias (conductive metal vias and metal reinforcing via patterns) to the unit area of the area under the metal bonding pad of the semiconductor device using the low dielectric constant film as the interlayer insulating film, and the ball share 6 is a graph showing the relationship between the adhesion hardness between a metal bonding pad and a bonding wire measured by a method.
圆 64]本発明の第 3の態様に係る半導体装置の他の実施例の断面図である。 FIG. 64 is a cross-sectional view of another example of the semiconductor device according to the third embodiment of the present invention.
圆 65]本発明の第 3の態様に係る半導体装置の他の実施例の断面図である。 [65] FIG. 65 is a cross-sectional view of another example of the semiconductor device according to the third embodiment of the present invention.
符号の説明 Explanation of symbols
1001 半導体基板 1001 Semiconductor substrate
1002 絶縁膜  1002 insulation film
1003 第一配線層  1003 1st wiring layer
1004、 1008 導電性金属配線  1004, 1008 conductive metal wiring
1005、 1009 金属補強配線パターン  1005, 1009 Metal reinforced wiring pattern
1006 第一層間絶縁膜  1006 First interlayer insulating film
1007 第二配線層  1007 Second wiring layer
1010 導電性金属ビア  1010 Conductive metal via
1011、 1014、 1017 金属補強ビアパターン  1011, 1014, 1017 Metal reinforced via pattern
1012 第二層間絶縁膜  1012 Second interlayer insulating film
1013 第三配線層  1013 Third wiring layer
1015 グローバル配線  1015 Global wiring
1016 素子分離領域  1016 Isolation area
1018、 1020 配線溝  1018, 1020 Wiring groove
1019 ビア孔 1021 半導体基板 1019 Via hole 1021 Semiconductor substrate
1022 絶縁膜  1022 insulating film
1023 第一配線層  1023 First wiring layer
1024、 1028 導電性金属配線  1024, 1028 conductive metal wiring
1025、 1029 金属補強配線パターン  1025, 1029 Metal reinforced wiring pattern
1026 第一層間絶縁膜  1026 First interlayer insulating film
1027 第二配線層  1027 Second wiring layer
1030 導電性金属ビア  1030 Conductive metal via
1031 金属補強ビアパターン  1031 Metal reinforced via pattern
1040 金属ワイヤボンディングパッド  1040 Metal wire bonding pad
1042 ボンディングワイヤ  1042 Bonding wire
1061 半導体基板  1061 Semiconductor substrate
1062 絶縁膜  1062 insulating film
1063 第一配線層  1063 First wiring layer
1064 第一層間絶縁膜  1064 First interlayer insulating film
1065 第二配線層  1065 Second wiring layer
1066 第二層間絶縁膜  1066 Second interlayer insulating film
1067 第三配線層  1067 Third wiring layer
1091、 1093、 1095 導電性金属配線  1091, 1093, 1095 Conductive metal wiring
1092、 1094 導電性金属ビア  1092, 1094 Conductive metal via
1095B 大面積配線層パッド  1095B Large area wiring layer pad
1100 シールド 1100 shield
6221 トランジスタ 6221 transistor
6231、 6331金属ボンディングパッドの外縁から一定の距離 7221 トランジスタ  6231, 6331 Constant distance from outer edge of metal bonding pad 7221 Transistor
111 半導体基板 111 Semiconductor substrate
112 絶縁膜 112 Insulating film
113 第一配線層 115、 121 金属回路配線 113 1st wiring layer 115, 121 Metal circuit wiring
116、 122 金属補強配線パターン 117 層間絶縁膜  116, 122 Metal reinforced wiring pattern 117 Interlayer insulating film
118 導電性金属ビア  118 Conductive metal via
119 金属補強ビアパターン 119 Metal Reinforced Via Pattern
120 第二配線層 120 Second wiring layer
123 導電性金属ビアが重なり合う領域 211 半導体基板  123 Area where conductive metal via overlaps 211 Semiconductor substrate
212 絶縁膜 212 insulating film
213 第一配線層 213 First wiring layer
215、 219 金属回路配線  215, 219 metal circuit wiring
216、 220 金属補強配線パターン 217 層間絶縁膜  216, 220 Metal reinforced wiring pattern 217 Interlayer insulating film
218 第二配線層  218 Second wiring layer
221 金属ボンディングパッド 221 Metal bonding pad
2211 トランジスタ 2211 transistor
223 金属回路配線 223 metal circuit wiring
224 金属導電性金属ビア 224 metal conductive metal via
225 金属補強ビアパターン 225 Metal Reinforced Via Pattern
228 多層ローカル配線層 228 multilayer local wiring layers
229 配線層 229 Wiring layer
230 ビア層間絶縁膜 230 Via interlayer insulating film
231 グロ一パル配線層 231 Global wiring layer
232 金属ボンディングパッド 232 metal bonding pad
233 金属補強ビアパターン 233 Metal Reinforced Via Pattern
235 CMP平坦用ダミー配線パターン 235 Dummy wiring pattern for CMP flattening
236 ローカル配線 236 local wiring
237 グローバル配線 611 半導体基板 237 Global Wiring 611 Semiconductor substrate
612 絶縁膜 612 insulating film
613 第一配線層 613 First wiring layer
615、 619、 623 金属回路配線または導電性金属配線 615, 619, 623 metal circuit wiring or conductive metal wiring
616、 620 金属補強配線パターン 616, 620 Metal reinforced wiring pattern
617 第一層間絶縁膜 617 First interlayer insulating film
618 第二配線層  618 Second wiring layer
621、 635 金属ボンディングパッド  621, 635 metal bonding pad
624、 637 導電性金属ビア  624, 637 conductive metal via
625、 636 金属補強ビアパターン  625, 636 Metal reinforced via pattern
626 金属補強配線パターンが相互に重なり合う領域 628 円筒状ビア  626 Area where metal reinforcing wiring patterns overlap each other 628 Cylindrical via
629 矩形状のビア 629 rectangular via
630 ビア 630 via
631 多層ローカル配線層  631 Multi-layer local wiring layer
632 配線層  632 Wiring layer
633 ビア層間絶縁膜  633 Via interlayer insulating film
634 グローバル配線層  634 Global Wiring Layer
638 ローカル配線  638 Local Wiring
639 グローバル配線  639 Global Wiring
640 CMP平坦用ダミー配線パターン  640 Dummy wiring pattern for CMP flattening
711 半導体基板  711 Semiconductor substrate
712 絶縁膜  712 insulating film
713 第一配線層  713 First wiring layer
715、 719、 724 金属回路配線または導電性金属配線 716 金属補強配線パターン  715, 719, 724 Metal circuit wiring or conductive metal wiring 716 Metal reinforcement wiring pattern
717 第一層間絶縁膜 717 First interlayer insulating film
718 第二配線層 720 金属補強配線パターン718 Second wiring layer 720 Metal reinforced wiring pattern
721 第二層間絶縁膜721 Second interlayer insulating film
722 第 3配線層 722 Third wiring layer
723 金属ボンディングパッド 723 Metal bonding pad
725、 727 導電性金属ビア725, 727 conductive metal via
726 金属補強ビアパターン726 Metal Reinforced Via Pattern
728 金属補強ビアパターン728 Metal reinforced via pattern
729 金属補強配線パターン729 Metal reinforced wiring pattern
730 シールド 730 shield
E 半導体チップ周縁端部 E Edge of semiconductor chip
X 十字マーク X cross mark

Claims

請求の範囲 The scope of the claims
[1] 半導体基板と、  [1] a semiconductor substrate,
前記半導体基板上に形成された少なくとも一つの層間絶縁膜と、  At least one interlayer insulating film formed on the semiconductor substrate,
前記層間絶縁膜を介して積層された複数の配線層と、を備え、  A plurality of wiring layers laminated via the interlayer insulating film,
前記複数の配線層の各々に形成された回路配線と、前記層間絶縁膜を貫通し、上 下方向に隣接する前記回路配線を相互に接続する導電性金属ビアと、からなる多層 回路構造が形成されて ヽる半導体装置であって、  A multilayer circuit structure including a circuit wiring formed in each of the plurality of wiring layers, and a conductive metal via penetrating the interlayer insulating film and interconnecting the circuit wirings adjacent to each other in a vertical direction is formed. A semiconductor device,
前記複数の配線層の各々に設けられた補強配線パターンと、前記層間絶縁膜に 設けられ、上下方向に隣接する前記補強配線パターンを相互に接続する補強ビア ノ《ターンと、力らなる多層支持構造を備え、  A reinforcing wiring pattern provided on each of the plurality of wiring layers, a reinforcing via pattern provided on the interlayer insulating film and interconnecting the reinforcing wiring patterns vertically adjacent to each other, With structure,
前記多層支持構造は、前記多層回路構造が存在する前記半導体装置の回路領 域にぉ 、て、前記多層回路構造と抵触しな 、領域に形成されて 、ることを特徴とする 半導体装置。  The semiconductor device is characterized in that the multilayer support structure is formed in a region that does not conflict with the multilayer circuit structure in a circuit region of the semiconductor device in which the multilayer circuit structure exists.
[2] 最上層上に形成され、外部と電気的に信号の送受信を行なうパッドをさらに有する ものであることを特徴とする請求項 1に記載の半導体装置。  [2] The semiconductor device according to claim 1, further comprising a pad formed on an uppermost layer and configured to electrically transmit and receive signals to and from the outside.
[3] 前記多層支持構造は前記パッドの下方の領域にも存在していることを特徴とする請 求項 2に記載の半導体装置。 3. The semiconductor device according to claim 2, wherein said multilayer support structure is also present in a region below said pad.
[4] 半導体基板と、 [4] a semiconductor substrate;
前記半導体基板上に形成された少なくとも一つの層間絶縁膜と、  At least one interlayer insulating film formed on the semiconductor substrate,
前記層間絶縁膜を介して積層された複数の配線層と、  A plurality of wiring layers stacked via the interlayer insulating film,
前記複数の配線層のうちの最上層上に形成されたパッドと、を備え、  A pad formed on an uppermost layer of the plurality of wiring layers,
前記複数の配線層の各々に形成された回路配線と、前記層間絶縁膜を貫通し、上 下方向に隣接する前記回路配線を相互に接続する導電性金属ビアと、からなる多層 回路構造が形成されて ヽる半導体装置であって、  A multilayer circuit structure including a circuit wiring formed in each of the plurality of wiring layers, and a conductive metal via penetrating the interlayer insulating film and interconnecting the circuit wirings adjacent to each other in a vertical direction is formed. A semiconductor device,
前記複数の配線層の各々に設けられた補強配線パターンと、前記層間絶縁膜に 設けられ、上下方向に隣接する前記補強配線パターンを相互に接続する補強ビア ノ《ターンと、力らなる多層支持構造を備え、  A reinforcing wiring pattern provided on each of the plurality of wiring layers, a reinforcing via pattern provided on the interlayer insulating film and interconnecting the reinforcing wiring patterns vertically adjacent to each other, With structure,
前記パッドの下方の領域には、前記多層回路構造の少なくとも一部が配置されて おり、 In a region below the pad, at least a part of the multilayer circuit structure is disposed. Yes,
前記パッドの下方には、前記多層支持構造が、前記多層回路構造と抵触しない領 域に形成されていることを特徴とする半導体装置。  The semiconductor device according to claim 1, wherein the multilayer support structure is formed below the pad in a region that does not conflict with the multilayer circuit structure.
[5] 前記半導体基板上に形成されたトランジスタをさらに備えており、 [5] The semiconductor device further includes a transistor formed on the semiconductor substrate,
前記トランジスタは、前記パッドの下方に配置されて ヽることを特徴とする請求項 4 に記載の半導体装置。  The semiconductor device according to claim 4, wherein the transistor is arranged below the pad.
[6] 前記多層支持構造は、前記パッドの下方の領域のみならず、前記パッドの外周より も外側の所定距離の範囲の下方の領域にも形成されていることを特徴とする請求項 [6] The multi-layer support structure is formed not only in a region below the pad but also in a region below a predetermined distance outside the outer periphery of the pad.
4または 5に記載の半導体装置。 6. The semiconductor device according to 4 or 5.
[7] 前記所定距離は 10 μ mであることを特徴とする請求項 6に記載の半導体装置。 7. The semiconductor device according to claim 6, wherein the predetermined distance is 10 μm.
[8] 半導体基板と、 [8] a semiconductor substrate;
前記半導体基板上に形成された少なくとも一つの層間絶縁膜と、  At least one interlayer insulating film formed on the semiconductor substrate,
前記層間絶縁膜を介して積層された複数の配線層と、を備え、  A plurality of wiring layers laminated via the interlayer insulating film,
前記複数の配線層の各々に形成された回路配線と、前記層間絶縁膜を貫通し、上 下方向に隣接する前記回路配線を相互に接続する導電性金属ビアと、からなる多層 回路構造が形成されて ヽる半導体装置であって、  A multilayer circuit structure including a circuit wiring formed in each of the plurality of wiring layers, and a conductive metal via penetrating the interlayer insulating film and interconnecting the circuit wirings adjacent to each other in a vertical direction is formed. A semiconductor device,
前記半導体装置は、前記複数の配線層の各々に設けられた補強配線パターンと、 前記層間絶縁膜に設けられ、上下方向に隣接する前記補強配線パターンを相互に 接続する補強ビアパターンと、力もなる多層支持構造を備え、  The semiconductor device also has a reinforcing wiring pattern provided on each of the plurality of wiring layers, and a reinforcing via pattern provided on the interlayer insulating film and interconnecting the reinforcing wiring patterns that are vertically adjacent to each other. Equipped with a multilayer support structure,
前記半導体装置は、前記多層回路構造が形成されている回路領域と、前記回路 領域の周囲の領域であって、回路が形成されていないスクライブ領域と、を有してお り、  The semiconductor device has a circuit region in which the multilayer circuit structure is formed, and a scribe region surrounding the circuit region, in which no circuit is formed,
前記多層支持構造は前記スクライブ領域に形成されていることを特徴とする半導体 装置。  The semiconductor device according to claim 1, wherein the multilayer support structure is formed in the scribe region.
[9] 前記多層支持構造は、前記回路領域において、前記多層回路構造と抵触しない 領域に形成されていることを特徴とする請求項 8に記載の半導体装置。  9. The semiconductor device according to claim 8, wherein the multilayer support structure is formed in a region of the circuit region that does not conflict with the multilayer circuit structure.
[10] 最上層上に形成され、外部と電気的に信号の送受信を行なうパッドをさらに有する ものであることを特徴とする請求項 8または 9に記載の半導体装置。 10. The semiconductor device according to claim 8, further comprising a pad formed on the uppermost layer and configured to electrically transmit and receive signals to and from the outside.
[11] 前記パッドの下方の領域にも前記多層支持構造が形成されているものであることを 特徴とする請求項 8乃至 10のいずれか 1項に記載の半導体装置。 11. The semiconductor device according to claim 8, wherein the multilayer support structure is formed also in a region below the pad.
[12] 前記パッドの外側と前記スクライブ領域との間にも前記多層支持構造が形成されて V、るものであることを特徴とする請求項 8乃至 11の 、ずれか 1項に記載の半導体装 置。  12. The semiconductor according to claim 8, wherein the multilayer support structure is formed between the outer side of the pad and the scribe region, and the multilayer support structure is formed. Equipment.
[13] 前記補強ビアパターンの前記半導体装置の厚さ方向における長さは前記導電性 金属ビアの前記半導体装置の厚さ方向における長さよりも大きいものであることを特 徴とする請求項 1乃至 12のいずれか 1項に記載の半導体装置。  13. The semiconductor device according to claim 1, wherein a length of the reinforcing via pattern in a thickness direction of the semiconductor device is larger than a length of the conductive metal via in a thickness direction of the semiconductor device. 13. The semiconductor device according to any one of 12.
[14] 前記補強ビアパターンの前記半導体装置の横断面における形状力スリット状である ことを特徴とする請求項 1乃至 13のいずれか 1項に記載の半導体装置。  14. The semiconductor device according to claim 1, wherein the reinforcing via pattern has a slit shape in a cross section of the semiconductor device.
[15] 前記多層支持構造は前記回路配線及び前記導電性金属ビアから電気的に独立し て形成されているものであることを特徴とする請求項 1乃至 14のいずれか 1項に記載 の半導体装置。  15. The semiconductor according to claim 1, wherein the multilayer support structure is formed independently of the circuit wiring and the conductive metal via. apparatus.
[16] 前記多層支持構造は、前記回路配線、前記導電性金属ビア及び前記パッドから電 気的に独立して形成されているものであることを特徴とする請求項 2乃至 7及び 10の いずれか 1項に記載の半導体装置。  16. The multi-layer support structure according to claim 2, wherein the multi-layer support structure is formed electrically independent of the circuit wiring, the conductive metal via, and the pad. Or the semiconductor device according to item 1.
[17] 前記多層支持構造は前記半導体基板中に設けられた素子分離領域に接続されて いるものであることを特徴とする請求項 1乃至 16のいずれか 1項に記載の半導体装 置。 17. The semiconductor device according to claim 1, wherein the multi-layer support structure is connected to an element isolation region provided in the semiconductor substrate.
[18] 前記半導体装置は、その最上層において、グロ一ノ レ配線をさらに備えており、 前記回路領域に形成された前記多層支持構造は、その一端部において、前記グロ 一バル配線部に接続され、他端部においては、前記回路配線及び前記導電性金属 ビアとは隔離されているものであることを特徴とする請求項 1乃至 17のいずれ力 1項 に記載の半導体装置。  [18] The semiconductor device further includes a global wiring in an uppermost layer thereof, and the multilayer support structure formed in the circuit region is connected at one end thereof to the global wiring portion. 18. The semiconductor device according to claim 1, wherein the other end is separated from the circuit wiring and the conductive metal via.
[19] 前記パッドの下方の領域に形成された多層支持構造は、前記パッド及び他の回路 と接続されて 、るものであることを特徴とする請求項 2乃至 7及び 10の 、ずれか 1項 に記載の半導体装置。  [19] The multi-layered support structure formed in a region below the pad is connected to the pad and another circuit, and the multi-layered support structure is connected to the pad and another circuit. 13. The semiconductor device according to item 13.
[20] 前記補強配線パターン及び前記補強ビアパターンと、それらと同一層に存在する 前記回路配線及び前記導電性金属ビアとはそれぞれ同一の材料で形成されている ものである請求項 1乃至 19にいずれか 1項に記載の半導体装置。 [20] The reinforcing wiring pattern and the reinforcing via pattern exist in the same layer as the reinforcing wiring pattern and the reinforcing via pattern. 20. The semiconductor device according to claim 1, wherein the circuit wiring and the conductive metal via are each formed of the same material.
[21] 前記層間絶縁膜の単位面積当たりに占める、前記導電性金属ビアと前記補強ビア パターンとの総面積の割合が 5%以上とされているものであることを特徴とする請求 項 1乃至 20のいずれか 1項に記載の半導体装置。 21. The method according to claim 1, wherein a ratio of a total area of the conductive metal via and the reinforcing via pattern to a unit area of the interlayer insulating film is 5% or more. 21. The semiconductor device according to any one of 20.
[22] 前記パッドの下方の領域において、前記層間絶縁膜の単位面積当たりに占める、 前記導電性金属ビアと前記補強ビアパターンとの総面積の割合が 5%以上とされて いるものであることを特徴とする請求項 2乃至 7及び 10のいずれか 1項に記載の半導 体装置。 [22] In a region below the pad, a ratio of a total area of the conductive metal via and the reinforcing via pattern to a unit area of the interlayer insulating film is 5% or more. The semiconductor device according to claim 2, wherein the semiconductor device is characterized in that:
[23] 前記スクライブ領域にぉ 、て、前記層間絶縁膜の単位面積当たりに占める前記補 強ビアパターンの総面積の割合が 5%以上とされているものであることを特徴とする 請求項 8乃至 22のいずれか 1項に記載の半導体装置。  [23] The ratio of the total area of the reinforcing via pattern per unit area of the interlayer insulating film to the scribe region may be 5% or more. 23. The semiconductor device according to any one of to 22.
[24] 前記補強ビアパターンは前記補強配線パターンが相互に重なり合う領域のみを接 続するものであることを特徴とする請求項 1乃至 23のいずれか 1項に記載の半導体 装置。 24. The semiconductor device according to claim 1, wherein the reinforcing via pattern connects only areas where the reinforcing wiring patterns overlap each other.
[25] 請求項 1乃至 24のいずれか 1項に記載の半導体装置の製造方法であって、 前記多層支持構造を形成する前記補強配線パターンと前記補強ビアパターンと、 それらと同一層に存在する前記回路配線及び前記導電性金属ビアとをそれぞれ同 一の材料で形成する過程を備える、  [25] The method of manufacturing a semiconductor device according to any one of claims 1 to 24, wherein the reinforcing wiring pattern and the reinforcing via pattern forming the multilayer support structure are present in the same layer as the reinforcing wiring pattern and the reinforcing via pattern. Forming the circuit wiring and the conductive metal via with the same material, respectively.
ことを特徴とする半導体装置の製造方法。  A method for manufacturing a semiconductor device, comprising:
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