JP2006019312A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device Download PDF

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JP2006019312A
JP2006019312A JP2004192394A JP2004192394A JP2006019312A JP 2006019312 A JP2006019312 A JP 2006019312A JP 2004192394 A JP2004192394 A JP 2004192394A JP 2004192394 A JP2004192394 A JP 2004192394A JP 2006019312 A JP2006019312 A JP 2006019312A
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insulating film
reinforcing
interlayer insulating
bonding
integrated circuit
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Yasunori Asano
恭典 浅野
Katsuya Murakami
克也 村上
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Toshiba Corp
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Toshiba Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the separation of a film, such as an interlayer insulating film, and to improve bonding properties. <P>SOLUTION: A semiconductor integrated circuit device comprises a plurality of wires formed in the interlayer insulating film laminated on a semiconductor substrate; a via for connecting the plurality of wires in the upper and lower directions; a bonding pad that is connected to at least one of the plurality of wires and has a bonding area for connecting a bonding wire for electrical connection to the outside; a plurality of reinforcing patterns that are formed in the interlayer insulating film at the lower section of the bonding pad and are not electrically connected to the bonding pad; and a via for reinforcement for connecting the reinforcement patterns arranged vertically in the plurality of reinforcement patterns. The reinforcement pattern is made of the same member as the plurality of wires, and at least one portion of the member directly below the bonding area has a part in which no member exist. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体集積回路装置に関するものである。   The present invention relates to a semiconductor integrated circuit device.

従来、半導体集積回路装置の層間絶縁膜として、誘電率が低い（k≦３．０）絶縁膜であるいわゆるlow-k膜が用いられるようになってきた。しかし、このlow-k膜は、密度が低いため、層間絶縁膜の下部層、例えば拡散防止膜等との密着強度が弱く、ダイシング時等に発生するダメージによりlow-k膜の膜剥がれが生じるといった問題が発生していた。   Conventionally, a so-called low-k film which is an insulating film having a low dielectric constant (k ≦ 3.0) has been used as an interlayer insulating film of a semiconductor integrated circuit device. However, since this low-k film has a low density, the adhesion strength with the lower layer of the interlayer insulating film, such as a diffusion prevention film, is weak, and the low-k film peels off due to damage that occurs during dicing or the like Such a problem has occurred.

このlow-k膜の膜剥がれ対策としては、ボンディングパッドの下部にダミー配線を配設した半導体集積回路装置が知られている（例えば、特許文献１参照。）。   As a countermeasure against the film peeling of the low-k film, a semiconductor integrated circuit device in which a dummy wiring is disposed under the bonding pad is known (for example, see Patent Document 1).

この特許文献１の半導体集積回路装置によれば、ボンディングパッドの下部に配線層と同じ材料からなるダミー配線及び、ビアを配してダイシング時のダメージをダミー配線及びビアにより防止しようとするものである。   According to the semiconductor integrated circuit device disclosed in Patent Document 1, dummy wirings and vias made of the same material as the wiring layer are arranged under the bonding pads to prevent damage during dicing by the dummy wirings and vias. is there.

しかし、上記半導体集積回路装置では、ボンディングパッドに、ボンディングワイヤを超音波と熱加重を併用して押し付け接着する場合に以下のような問題がある。   However, the semiconductor integrated circuit device has the following problems when the bonding wire is pressed and bonded to the bonding pad using both ultrasonic waves and heat load.

配線材料として、例えば銅（Ｃｕ）が用いられたとき、ボンディングパッドの下部に、銅をダミー配線として配置すると、ボンディングパッドにボンディングワイヤを加重して接続する際に、ボンディングパッドにボンディングワイヤを接続することが困難である。
特開2001-267323号公報 For example, when copper (Cu) is used as the wiring material, if copper is placed under the bonding pad as a dummy wiring, the bonding wire is connected to the bonding pad when the bonding wire is weighted and connected to the bonding pad. Difficult to do.
JP 2001-267323 A

本発明は、半導体集積回路装置内の層間絶縁膜等の膜剥がれを防止し、かつボンディング性を向上させることが可能な半導体集積回路装置を提供することを目的とする。   An object of the present invention is to provide a semiconductor integrated circuit device capable of preventing film peeling of an interlayer insulating film or the like in the semiconductor integrated circuit device and improving bonding properties.

本発明の一態様の半導体集積回路装置は、半導体基板上に積層された層間絶縁膜内にそれぞれ形成された複数の配線と、前記複数の配線を上下方向に接続するビアと、前記複数の配線のうちの少なくとも１つの配線と接続され、外部との電気的接続のためのボンディングワイヤを接続するボンディングエリアを有するボンディングパッドと、前記ボンディングパッドの下部の前記層間絶縁膜内に形成され、前記ボンディングパッドとは電気的に接続されない複数の強化パターンと、複数の前記強化パターンのうち、上下に配置された前記強化パターン同士を接続する強化用ビアとを有し、前記強化パターンは、前記複数の配線と同一の部材から構成されており、かつ、前記ボンディングエリアの直下部分における前記部材のうち、その少なくとも一部に前記部材が存在しない部位を有していることを特徴としている。   A semiconductor integrated circuit device according to one embodiment of the present invention includes a plurality of wirings formed in an interlayer insulating film stacked over a semiconductor substrate, vias that connect the plurality of wirings in the vertical direction, and the plurality of wirings. A bonding pad connected to at least one of the wirings and having a bonding area for connecting a bonding wire for electrical connection to the outside; and formed in the interlayer insulating film below the bonding pad, A plurality of reinforcing patterns that are not electrically connected to the pad; and a reinforcing via that connects the reinforcing patterns arranged above and below among the plurality of reinforcing patterns. It is composed of the same member as the wiring, and among the members in the portion immediately below the bonding area, It is characterized by having a site which is not present the member part also.

本発明によれば、半導体集積回路装置の層間絶縁膜剥がれの防止及びボンディング性を高めることが可能である。   According to the present invention, it is possible to prevent peeling of an interlayer insulating film of a semiconductor integrated circuit device and to improve bonding properties.

以下、本発明の実施例について、図面を参照して説明する。   Embodiments of the present invention will be described below with reference to the drawings.

本発明の実施例に係る半導体集積回路装置を図１及び図２を用いて説明する。図１（ａ）は、本発明の実施例に係る半導体集積回路装置の構造を示す平面図であり、チップの上部付近の構成のみを示している。また、図１は必ずしも実際の寸法が反映されたものではない。   A semiconductor integrated circuit device according to an embodiment of the present invention will be described with reference to FIGS. FIG. 1A is a plan view showing the structure of a semiconductor integrated circuit device according to an embodiment of the present invention, and shows only the configuration near the top of the chip. Also, FIG. 1 does not necessarily reflect actual dimensions.

図１（ａ）に示すように、半導体集積回路装置の中央部には素子領域１が形成され、周辺部には、パッド領域２が形成される。素子領域１には、トランジスタ、ダイオード及びキャパシタ等の各種機能素子が形成され、この素子領域１の上部には各機能素子を接続する配線が多層構造に形成されている。一方、パッド領域２には、半導体集積回路装置の外部から半導体集積回路装置の内部に電気信号を入出力する端子となるボンディングパッド６０が形成され、そのボンディングパッド６０の直下部分には、強化パターン８０及び強化用ビア９０が形成されている。   As shown in FIG. 1A, an element region 1 is formed in the central portion of the semiconductor integrated circuit device, and a pad region 2 is formed in the peripheral portion. Various functional elements such as transistors, diodes, and capacitors are formed in the element region 1, and wirings for connecting the functional elements are formed in a multilayer structure on the element region 1. On the other hand, in the pad region 2, a bonding pad 60 is formed as a terminal for inputting / outputting an electric signal from the outside of the semiconductor integrated circuit device to the inside of the semiconductor integrated circuit device. 80 and reinforcing vias 90 are formed.

図１（b）は、図１（ａ）のＡ−Ａ’断面図である。図１（b）に示すように、半導体基板１０上に、第１の層間絶縁膜２０、拡散防止膜３０が積層状に形成されている。この第１の層間絶縁膜２０には、誘電率k＝２．２〜２．７の範囲程度の誘電率kの低いlow-k膜（例えば、ＳｉＯＣ膜）が用いられている。また、拡散防止膜３０は、配線４０として用いられる銅（Ｃｕ）が第１の層間絶縁膜２０に拡散するのを防止するために設けられたものであって、ＳｉＮ、ＳｉＣＮ等が用いられている。   FIG. 1B is a cross-sectional view taken along the line A-A ′ of FIG. As shown in FIG. 1B, a first interlayer insulating film 20 and a diffusion prevention film 30 are formed on the semiconductor substrate 10 in a laminated form. As the first interlayer insulating film 20, a low-k film (for example, SiOC film) having a low dielectric constant k in the range of dielectric constant k = 2.2 to 2.7 is used. The diffusion preventing film 30 is provided to prevent copper (Cu) used as the wiring 40 from diffusing into the first interlayer insulating film 20, and SiN, SiCN, or the like is used. Yes.

素子領域１の上部における積層状の第１の層間絶縁膜２０部分には、銅（Ｃｕ）等の金属導体からなる配線４０が多層構造に設けられ、下層の配線４０と上層の配線４０とがビア４５によって電気的接続されている。そして、この配線４０は、半導体基板１０等に形成された各種機能素子に電気的に接続されている。   A wiring 40 made of a metal conductor such as copper (Cu) is provided in a multilayer structure in the laminated first interlayer insulating film 20 portion in the upper part of the element region 1, and the lower wiring 40 and the upper wiring 40 are provided. The vias 45 are electrically connected. The wiring 40 is electrically connected to various functional elements formed on the semiconductor substrate 10 or the like.

そして、これらの配線４０及びビア４５が所定の数だけ繰り返し積み上げられて多層配線が形成され、最上層の拡散防止膜３０上には、ＳｉＮ、ＳｉＯ２等の絶縁材料からなる第２の層間絶縁膜５０が形成されている。第１の層間絶縁膜２０は、誘電率kが大きいと半導体集積回路装置の信号遅延を引き起こすため、誘電率k(k≦３．０)の低いlow-k膜を用いるが、第２の層間絶縁膜５０は、配線４０の信号遅延を及ぼす影響が小さいため、low-k膜に比べて誘電率kは高いが機械的強度が強いＳｉＮ、ＳｉＯ２等の絶縁材料を用いている。   A predetermined number of these wirings 40 and vias 45 are repeatedly stacked to form a multilayer wiring, and a second interlayer insulating film made of an insulating material such as SiN or SiO 2 is formed on the uppermost diffusion barrier film 30. 50 is formed. The first interlayer insulating film 20 uses a low-k film having a low dielectric constant k (k ≦ 3.0) because a signal delay of the semiconductor integrated circuit device is caused when the dielectric constant k is large. Since the insulating film 50 has little influence on the signal delay of the wiring 40, an insulating material such as SiN or SiO2 having a high dielectric constant k but high mechanical strength as compared with the low-k film is used.

第２の層間絶縁膜５０上のパッド領域２に、ＡｌやＣｕ等の金属からなるボンディングパッド６０が形成されている。そして、このボンディングパッド６０は最上層の配線４０にビア４５を介して電気的に接続されている。   A bonding pad 60 made of a metal such as Al or Cu is formed in the pad region 2 on the second interlayer insulating film 50. The bonding pad 60 is electrically connected to the uppermost layer wiring 40 through a via 45.

なお、このボンディングパッド６０は、配線４０及びビア４５と同一の材質であるＣｕを用いてもよいし、また、ボンディングパッド６０上に、バンプ用メッキ層を形成してもよい。   The bonding pad 60 may be made of Cu, which is the same material as the wiring 40 and the via 45, or a bump plating layer may be formed on the bonding pad 60.

第２の層間絶縁膜５０及びボンディングパッド６０の上部に、半導体集積回路装置の外部との電気信号の送受信のための金（Ａｕ）やアルミ合金からなるボンディングワイヤ（図示しない）が接続されるボンディングエリア６５を除いて、パッシベーション膜７０が形成されている。なお、ボンディングエリア６５は、ボンディングワイヤをボンディングパッド６０に加重して押し付けボンディングする際に、加重が集中する部分である。   Bonding in which bonding wires (not shown) made of gold (Au) or aluminum alloy for transmitting / receiving electric signals to / from the outside of the semiconductor integrated circuit device are connected to the upper portion of the second interlayer insulating film 50 and the bonding pad 60. Except for the area 65, a passivation film 70 is formed. The bonding area 65 is a portion where the weight is concentrated when the bonding wire is weighted and pressed against the bonding pad 60 for bonding.

そして、パッド領域２内であってボンディングパッド６０の下部には、配線４０と同一材料のＣｕを部材とし、かつ、配線４０とほぼ同一の多層構造を有する強化パターン８０が形成されている。この強化パターン８０は、配線４０と同一層に形成され、かつ、図１（c）に示すように、チップの外周部に、素子領域１を囲うようにリング状に形成され、配線４０及びビア４５と電気的に接続されず、独立して設けられている。   In the pad region 2 and below the bonding pad 60, a reinforcing pattern 80 is formed which uses Cu of the same material as the wiring 40 and has a multilayer structure substantially the same as the wiring 40. The reinforcing pattern 80 is formed in the same layer as the wiring 40 and, as shown in FIG. 1C, is formed in a ring shape so as to surround the element region 1 on the outer periphery of the chip. It is not electrically connected to 45 but is provided independently.

さらに、各強化パターン８０は、ビア４５と同一のＣｕを部材とする強化用ビア９０によって連結されている。この強化用ビア９０もまた、配線４０及びビア４５とは電気的に接続されていない。   Further, each reinforcing pattern 80 is connected by a reinforcing via 90 having the same Cu as that of the via 45 as a member. The reinforcing via 90 is also not electrically connected to the wiring 40 and the via 45.

これらの強化パターン８０及び強化用ビア９０は、配線４０及びビア４５と同様に所定の数だけ繰り返し積み上げて形成されている。   These reinforcing patterns 80 and reinforcing vias 90 are formed by repeatedly accumulating a predetermined number like the wirings 40 and vias 45.

ここで、上記強化パターン８０の形状について、図２を用いて説明する。図２における斜線部分が強化パターン８０である。図２（a）に示すように、強化パターン８０は、パッド領域２に形成され、かつ各ボンディングパッド６０のボンディングエリア６５の直下部分のうち、その中央部を中心とした四角形状の強化パターン８０の部材が存在しない部位を有している。   Here, the shape of the reinforcing pattern 80 will be described with reference to FIG. The hatched portion in FIG. As shown in FIG. 2A, the reinforcing pattern 80 is formed in the pad region 2, and the rectangular reinforcing pattern 80 centering on the central portion of the portion directly below the bonding area 65 of each bonding pad 60. It has a part where no member exists.

また、図２（b）に示すように、強化パターン８０は、パッド領域２に形成され、かつ各ボンディングパッド６０のボンディングエリア６５の直下部分のうち、その中央部を中心とした円状の強化パターン８０の部材が存在しない部位を有している。   Further, as shown in FIG. 2B, the reinforcing pattern 80 is formed in the pad region 2 and has a circular shape centering on the central portion of the portion directly below the bonding area 65 of each bonding pad 60. The pattern 80 has a portion where no member exists.

また、図２（c）に示すように、強化パターン８０は、各ボンディングパッド６０に対応して独立して設けられ、各ボンディングパッド６０のボンディングエリア６５の直下部分のうち、その中央部を中心とした四角形状の強化パターン８０の部材が存在しない部位を有している。   Further, as shown in FIG. 2C, the reinforcing pattern 80 is provided independently corresponding to each bonding pad 60, and the central portion of the portion directly below the bonding area 65 of each bonding pad 60 is centered. The portion of the rectangular reinforcing pattern 80 is not present.

さらに、図２（d）に示すように、強化パターン８０は、パッド領域２に形成され、かつ各ボンディングパッド６０のボンディングエリア６５の直下部分の全部分には強化パターン８０の部材が存在しない形状を有している。   Further, as shown in FIG. 2 (d), the reinforcing pattern 80 is formed in the pad region 2 and has a shape in which the members of the reinforcing pattern 80 do not exist in the entire portion immediately below the bonding area 65 of each bonding pad 60. have.

なお、図２（a）、図２（b）、図２（c）及び図２（d）に示したボンディングエリア６５の直下部分のうち、強化パターン８０の部材が存在しない部位には、第１の層間絶縁膜２０が充填されている。以上のようにして、本発明の本実施例に係る半導体集積回路装置は構成されている。   2A, FIG. 2B, FIG. 2C, and FIG. 2D, the portion directly below the bonding area 65 where the member of the reinforcing pattern 80 is not present One interlayer insulating film 20 is filled. As described above, the semiconductor integrated circuit device according to this embodiment of the present invention is configured.

以下、本発明の実施例に係る半導体集積回路装置の製造方法を図３を用いて説明する。まず、図３（a）に示すように、トランジスタ、ダイオード及びキャパシタ等の各種機能素子が作りこまれた半導体基板１０上に、最下層の第１の層間絶縁膜２０aを形成する。この第１の層間絶縁膜２０aは、ＳｉＯＣ等の誘電率kが低い（k≦３．０)、いわゆるlow-k膜であり、ＣＶＤ（chemical vapor deposition)法若しくはＳＯＧ（spin on glass）法等により形成する。以降、半導体基板１０及びその上層の形成物に対して、各種機能素子が形成された領域を素子領域１、各種機能素子が形成されていない領域をパッド領域２と呼ぶ。   A method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention will be described below with reference to FIG. First, as shown in FIG. 3A, a lowermost first interlayer insulating film 20a is formed on a semiconductor substrate 10 on which various functional elements such as transistors, diodes, and capacitors are formed. The first interlayer insulating film 20a is a so-called low-k film having a low dielectric constant k such as SiOC (k ≦ 3.0), such as a CVD (chemical vapor deposition) method or a SOG (spin on glass) method. To form. Hereinafter, with respect to the semiconductor substrate 10 and the formation formed thereon, a region where various functional elements are formed is referred to as an element region 1, and a region where various functional elements are not formed is referred to as a pad region 2.

次に、素子領域１の第１の層間絶縁膜２０aをドライエッチング技術を用いてパターニングして、溝２１a（配線４０aに対応する平面形状を有する）を形成する。その際、第１の層間絶縁膜２０aのパッド領域２にも溝２２a（強化パターン８０aに対応する平面形状を有する）を形成する。   Next, the first interlayer insulating film 20a in the element region 1 is patterned using a dry etching technique to form a trench 21a (having a planar shape corresponding to the wiring 40a). At this time, a groove 22a (having a planar shape corresponding to the reinforcing pattern 80a) is also formed in the pad region 2 of the first interlayer insulating film 20a.

この溝２１a及び溝２２a形成の際には、各溝２１a、２２aの底面から半導体基板１０が露出しないようにする。上記溝２１aの溝幅（配線４０aの幅に相当）は、例えば０．１〜１．０μｍ程度である。また、上記溝２２aの幅（強化パターン８０aの平面形状の寸法）は、例えば８０〜１００μｍ角程度である。   When the grooves 21a and 22a are formed, the semiconductor substrate 10 is not exposed from the bottom surfaces of the grooves 21a and 22a. The groove width of the groove 21a (corresponding to the width of the wiring 40a) is, for example, about 0.1 to 1.0 μm. The width of the groove 22a (planar dimension of the reinforcing pattern 80a) is, for example, about 80 to 100 μm square.

次に、図３（b）に示すように、第１の層間絶縁膜２０a、溝２１a及び溝２２aの全面に、導電性配線材料である銅（Ｃｕ）等の金属膜を形成し、溝２１aと溝２２aとを金属膜で埋め込む。   Next, as shown in FIG. 3B, a metal film such as copper (Cu), which is a conductive wiring material, is formed on the entire surface of the first interlayer insulating film 20a, the groove 21a, and the groove 22a, and the groove 21a. And the groove 22a are filled with a metal film.

次に、ＣＭＰ（chemical mechanical polishing）法を用いて金属膜を第１の層間絶縁膜２０aが露出するまで研磨して平坦化し、配線４０aと強化パターン８０aとを形成する。なお、この配線４０aは、プラグ（図示しない）を介して半導体基板１０等に形成された各種機能素子と電気的に接続されている。ここで、配線４０aと強化パターン８０aは、電気的に接続されないように形成する。   Next, the metal film is polished and planarized using a CMP (chemical mechanical polishing) method until the first interlayer insulating film 20a is exposed, thereby forming the wiring 40a and the reinforcing pattern 80a. The wiring 40a is electrically connected to various functional elements formed on the semiconductor substrate 10 or the like via a plug (not shown). Here, the wiring 40a and the reinforcing pattern 80a are formed so as not to be electrically connected.

次に、第１の層間絶縁膜２０a、配線４０a及び強化パターン８０a上の全面に、ＳｉＮ、ＳｉＣＮ等からなる拡散防止膜３０aをＳＯＧ法やＣＶＤ法により形成する。   Next, a diffusion prevention film 30a made of SiN, SiCN, or the like is formed on the entire surface of the first interlayer insulating film 20a, the wiring 40a, and the reinforcing pattern 80a by the SOG method or the CVD method.

続いて、拡散防止膜３０a上に、第１の層間絶縁膜２０aと同一の第１の層間絶縁膜２０bを堆積する。以降、同一のものを添え字のみを変えて表現する。   Subsequently, the same first interlayer insulating film 20b as the first interlayer insulating film 20a is deposited on the diffusion preventing film 30a. Thereafter, the same thing is expressed by changing only the subscript.

次に、図３（c）に示すように、第１の層間絶縁膜２０bにドライエッチング技術を用いてパターニングして、素子領域１に前記配線４０aに達するようなビアホール２４a（ビア４５aの形状に対応する）を形成し、パッド領域２には、前記強化パターン８０aに達するようなビアホール２５a（強化用ビア９０aの形状に対応する）を形成する。   Next, as shown in FIG. 3C, the first interlayer insulating film 20b is patterned using a dry etching technique to form a via hole 24a (via 45a shape) that reaches the wiring 40a in the element region 1. And a via hole 25a (corresponding to the shape of the reinforcing via 90a) is formed in the pad region 2 so as to reach the reinforcing pattern 80a.

また、素子領域１には、第１の層間絶縁膜２０bにドライエッチング技術を用いて、ビアホール２４aと接するように溝２１b（配線４０bに対応する平面形状を有する）を形成する。その際、パッド領域２には、前記溝２２aとほぼ同一の形状の溝２２b（強化パターン８０bに対応する平面形状を有する）を、ビアホール２５aと接するように、第１の層間絶縁膜２０bに形成する。   In the element region 1, a groove 21 b (having a planar shape corresponding to the wiring 40 b) is formed in the first interlayer insulating film 20 b by using a dry etching technique so as to be in contact with the via hole 24 a. At that time, in the pad region 2, a groove 22b having a shape substantially the same as the groove 22a (having a planar shape corresponding to the reinforcing pattern 80b) is formed in the first interlayer insulating film 20b so as to be in contact with the via hole 25a. To do.

次に、第１の層間絶縁膜２０b、溝２１b、溝２２b、ビアホール２４a及びビアホール２５aの全面に、溝２１b、溝２２b、ビアホール２４a及びビアホール２５aを埋め込むようにして、金属膜を形成する。続いて、金属膜を前記第１の層間絶縁膜２０bが露出するまで研磨し平坦化し、配線４０b及び強化パターン８０b、ビア４５aと強化用ビア９０aとを形成する。   Next, a metal film is formed so that the groove 21b, the groove 22b, the via hole 24a, and the via hole 25a are embedded in the entire surface of the first interlayer insulating film 20b, the groove 21b, the groove 22b, the via hole 24a, and the via hole 25a. Subsequently, the metal film is polished and planarized until the first interlayer insulating film 20b is exposed, thereby forming the wiring 40b, the reinforcing pattern 80b, the via 45a, and the reinforcing via 90a.

以下、配線４０、ビア４５、強化パターン８０及び強化用ビア９０の形成工程を繰り返し、図３(d)に示すように、多層の配線層を形成する。   Thereafter, the process of forming the wiring 40, the via 45, the reinforcing pattern 80, and the reinforcing via 90 is repeated to form a multilayer wiring layer as shown in FIG.

次に、最上層の拡散防止膜３０c、配線４０c及び強化用パターン８０c上に第２の層間絶縁膜５０を形成する。この第２の層間絶縁膜５０は、ＳｉＮ、ＳｉＯ２等の絶縁材料から形成されるものである。この第２の層間絶縁膜５０内に最上部の配線４０cに達するような所定の位置に溝を形成し、金属を堆積させ、ＣＭＰ法で平坦化し、ビア４５cを形成する。   Next, a second interlayer insulating film 50 is formed on the uppermost diffusion preventing film 30c, the wiring 40c, and the reinforcing pattern 80c. The second interlayer insulating film 50 is formed from an insulating material such as SiN or SiO2. A trench is formed at a predetermined position in the second interlayer insulating film 50 so as to reach the uppermost wiring 40c, a metal is deposited, and planarized by a CMP method to form a via 45c.

次に、第２の層間絶縁膜５０を介して、強化パターン８０a、８０b及び８０cの上部に、ボンディングパッド６０を形成する。このボンディングパッド６０は、ビア４５cを介して、配線４０cとは接続されているが、強化パターン８０a、８０b及び８０cとは、電気的に接続されていない。続いて、このボンディングパッド６０の一部であるボンディングエリア６５を除くようにして、パッシベーション膜７０を形成する。   Next, a bonding pad 60 is formed on the reinforcement patterns 80a, 80b and 80c via the second interlayer insulating film 50. The bonding pad 60 is connected to the wiring 40c through the via 45c, but is not electrically connected to the reinforcing patterns 80a, 80b, and 80c. Subsequently, a passivation film 70 is formed so as to remove the bonding area 65 which is a part of the bonding pad 60.

次に、ボンディングエリア６５に、半導体集積回路装置の外部との電気信号の送受信のための金（Ａｕ）やアルミ合金等からなるボンディングワイヤ（図示しない）を、超音波と熱加重を併用して押し付け、ボンディングパッド６０とボンディングワイヤの界面を金属共晶させて接続する。以上のようにして、本発明の本実施例に係る半導体集積回路装置は製造されている。   Next, a bonding wire (not shown) made of gold (Au), aluminum alloy or the like for transmitting / receiving an electrical signal to / from the outside of the semiconductor integrated circuit device is used in the bonding area 65 by using both ultrasonic waves and heat load. The interface between the bonding pad 60 and the bonding wire is metal eutectic and connected. As described above, the semiconductor integrated circuit device according to this embodiment of the present invention is manufactured.

このようにして、配線４０a、４０b、４０c及びビア４５a、４５bと同一の工程で、各強化パターン８０a、８０b、８０c及び強化用ビア９０a、９０bを形成することが可能となる。   In this manner, the reinforcing patterns 80a, 80b, 80c and the reinforcing vias 90a, 90b can be formed in the same process as the wirings 40a, 40b, 40c and the vias 45a, 45b.

本実施例に示すように、半導体集積回路装置内に強化パターン８０及び強化用ビア９０を配設することにより、ダイシング時等に発生する衝撃による、第１の層間絶縁膜２０の剥がれを防止することができる。   As shown in the present embodiment, by disposing the reinforcing pattern 80 and the reinforcing via 90 in the semiconductor integrated circuit device, the first interlayer insulating film 20 is prevented from being peeled off due to an impact generated during dicing or the like. be able to.

これは、半導体集積回路装置の外周部からダメージが発生し、外周部から第１の層間絶縁膜２０に膜剥がれが生じたとしても、強化パターン８０及び強化用ビア９０によって、第１の層間絶縁膜２０の膜剥がれが、素子領域１に進行することを防止可能となる。従って、素子領域１内部の配線４０及びビア４５が断線される等の半導体集積回路装置の故障を防ぐことが可能となる。   This is because even if damage is generated from the outer peripheral portion of the semiconductor integrated circuit device and the first interlayer insulating film 20 is peeled off from the outer peripheral portion, the first interlayer insulation is caused by the reinforcing pattern 80 and the reinforcing via 90. It is possible to prevent the film peeling of the film 20 from proceeding to the element region 1. Therefore, failure of the semiconductor integrated circuit device such as disconnection of the wiring 40 and the via 45 in the element region 1 can be prevented.

また、強化パターン８０及び強化用ビア９０が形成されているパッド領域２内の下部層は、通常の半導体集積回路装置においては、トランジスタ、ダイオード及びキャパシタ等の各種機能素子は形成されておらず、第１の層間絶縁膜２０が形成されているだけのデッドスペースである。このパッド領域２に本実施例による強化パターン８０及び強化用ビア９０を配置することにより、半導体集積回路装置のチップ面積を増大させることなく、層間絶縁膜２０の層間膜剥がれを抑止することが可能となる。   In the lower layer in the pad region 2 where the reinforcing pattern 80 and the reinforcing via 90 are formed, various functional elements such as transistors, diodes, and capacitors are not formed in a normal semiconductor integrated circuit device. This is a dead space where only the first interlayer insulating film 20 is formed. By disposing the reinforcing pattern 80 and the reinforcing via 90 according to this embodiment in the pad region 2, it is possible to suppress the interlayer film peeling of the interlayer insulating film 20 without increasing the chip area of the semiconductor integrated circuit device. It becomes.

さらに、強化パターン８０は、ボンディングパッド６０のボンディングエリア６５の直下部分のうち、少なくとも一部には強化パターン８０の部材が存在しない形状を有し、この強化パターン８０の部材が存在しない部分には、第１の層間絶縁膜２０が形成されている。   Further, the reinforcing pattern 80 has a shape in which the member of the reinforcing pattern 80 does not exist in at least a part of the portion directly below the bonding area 65 of the bonding pad 60. A first interlayer insulating film 20 is formed.

強化パターン８０が上記のような形状を有している理由は次の通りである。ボンディングエリア６５の直下に形成される第１の層間絶縁膜２０内に、Ｃｕ等の金属が形成されている半導体集積回路装置は、Ｃｕ等の金属が形成されていない半導体集積回路装置に比べてボンディングパッド６０にボンディングワイヤを接続しにくくなることを確認した。   The reason why the reinforcing pattern 80 has the shape as described above is as follows. A semiconductor integrated circuit device in which a metal such as Cu is formed in the first interlayer insulating film 20 formed immediately below the bonding area 65 is compared with a semiconductor integrated circuit device in which a metal such as Cu is not formed. It was confirmed that it was difficult to connect the bonding wire to the bonding pad 60.

そこで、本実施例に係る半導体集積回路装置においては、ボンディングエリア６５の直下部分のうち少なくとも一部に強化パターン８０の部材であるＣｕ等の金属が存在しない形状の強化パターン８０を有している。このように、ボンディングエリア６５直下の一部にはＣｕ等の金属が形成されていないので、超音波と熱加重を併用してボンディングパッド６０にボンディングワイヤを押し付け接続するときに、高いボンディング性を得ることが可能となる。   Therefore, the semiconductor integrated circuit device according to the present embodiment has the reinforcing pattern 80 having a shape in which a metal such as Cu that is a member of the reinforcing pattern 80 does not exist in at least a part of the portion directly below the bonding area 65. . As described above, since a metal such as Cu is not formed in a portion immediately below the bonding area 65, high bonding properties can be obtained when a bonding wire is pressed and connected to the bonding pad 60 using both ultrasonic waves and thermal load. Can be obtained.

ボンディングエリア６５の直下のうち少なくとも一部に強化パターン８０の部材が存在していなければ、ボンディングエリア６５の直下部分の全部分に強化パターン８０が形成されているものに比べて、ボンディング性を高めることが可能である。さらに、ボンディングエリア６５の直下の全部分に強化パターン８０の部材が存在しなければ、ボンディングエリア６５の直下の一部分のみに強化パターン８０の部材が存在しないものに比べ、ボンディング性を高めることが可能である。   If the member of the reinforcing pattern 80 is not present at least in a part directly below the bonding area 65, the bonding property is improved as compared with the case where the reinforcing pattern 80 is formed on the entire part immediately below the bonding area 65. It is possible. Furthermore, if the member of the reinforced pattern 80 does not exist in all the parts immediately below the bonding area 65, it is possible to improve the bondability as compared with the case where the member of the reinforced pattern 80 does not exist only in a part immediately below the bonding area 65. It is.

本実施例では、強化パターン８０及び強化用ビア９０は、図１（b）に示すように、半導体基板１０上の第１の層間絶縁膜２０から最上層の第１の層間絶縁膜２０に至るまで、全ての第１の層間絶縁膜２０及び拡散防止膜３０に配置されている。しかし、この強化パターン８０及び強化用ビア９０の配置は、これに限らず、最上層の第１の層間絶縁膜２０及び拡散防止膜３０にのみに配置する場合など、配線４０及びビア４５等の素子領域１内の多層配線形成の妨げにならない範囲で変更することが可能である。   In this embodiment, the reinforcing pattern 80 and the reinforcing via 90 extend from the first interlayer insulating film 20 on the semiconductor substrate 10 to the uppermost first interlayer insulating film 20 as shown in FIG. Up to all of the first interlayer insulating film 20 and the diffusion preventing film 30 are disposed. However, the arrangement of the reinforcing pattern 80 and the reinforcing via 90 is not limited to this, and when the wiring pattern 40 and the via 45 are arranged only in the uppermost first interlayer insulating film 20 and the diffusion prevention film 30. It is possible to change within a range that does not hinder the formation of the multilayer wiring in the element region 1.

本発明の実施例に係る半導体集積回路装置の構造を示す図。1 is a diagram showing a structure of a semiconductor integrated circuit device according to an embodiment of the present invention. 本発明の実施例に係る半導体集積回路装置の強化パターンの構造を示す概略図。Schematic which shows the structure of the reinforcement | strengthening pattern of the semiconductor integrated circuit device based on the Example of this invention. 本発明の実施例に係る半導体集積回路装置の製造方法を示す製造工程断面図。FIG. 5 is a manufacturing process sectional view showing the method of manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention.

符号の説明Explanation of symbols

１ 素子領域
２ パッド領域
１０ 半導体基板
２０、２０a、２０b 第１の層間絶縁膜
２１a、２１b、２２a、２２b 溝
２４a、２５a ビアホール
３０、３０a、３０b、３０c 拡散防止膜
４０、４０a、４０b、４０c 配線
４５、４５a、４５b、４５c ビア
５０ 第２の層間絶縁膜
６０ ボンディングパッド
６５ ボンディングエリア
７０ パッシベーション膜
８０、８０a、８０b、８０c 強化パターン
９０、９０a、９０b 強化用ビア DESCRIPTION OF SYMBOLS 1 Element area | region 2 Pad area | region 10 Semiconductor substrate 20, 20a, 20b 1st interlayer insulation film 21a, 21b, 22a, 22b Groove 24a, 25a Via hole 30, 30a, 30b, 30c Diffusion prevention film 40, 40a, 40b, 40c Wiring 45, 45a, 45b, 45c Via 50 Second interlayer insulating film 60 Bonding pad 65 Bonding area 70 Passivation films 80, 80a, 80b, 80c Reinforcement patterns 90, 90a, 90b Reinforcement vias

Claims (5)

半導体基板上に積層された層間絶縁膜内にそれぞれ形成された複数の配線と、
前記複数の配線を上下方向に接続するビアと、
前記複数の配線のうちの少なくとも１つの配線と接続され、外部との電気的接続のためのボンディングワイヤを接続するボンディングエリアを有するボンディングパッドと、
前記ボンディングパッドの下部の前記層間絶縁膜内に形成され、前記ボンディングパッドとは電気的に接続されない複数の強化パターンと、
複数の前記強化パターンのうち、上下に配置された前記強化パターン同士を接続する強化用ビアとを有し、
前記強化パターンは、前記複数の配線と同一の部材から構成されており、かつ、前記ボンディングエリアの直下部分における前記部材のうち、その少なくとも一部に前記部材が存在しない部位を有していることを特徴とする半導体集積回路装置。 A plurality of wirings each formed in an interlayer insulating film laminated on a semiconductor substrate;
Vias connecting the plurality of wirings in the vertical direction;
A bonding pad connected to at least one of the plurality of wirings and having a bonding area for connecting a bonding wire for electrical connection with the outside;
A plurality of reinforcing patterns formed in the interlayer insulating film below the bonding pad and not electrically connected to the bonding pad;
Among the plurality of reinforcing patterns, having reinforcing vias that connect the reinforcing patterns arranged above and below,
The reinforcing pattern is composed of the same member as the plurality of wirings, and has a portion where the member does not exist in at least a part of the member in a portion immediately below the bonding area. A semiconductor integrated circuit device. 前記強化パターンは、前記ボンディングエリアの直下部分における前記部材のうち、その中央部に前記部材が存在しない部位を有していることを特徴とする請求項１記載の半導体集積回路装置。 2. The semiconductor integrated circuit device according to claim 1, wherein the reinforcing pattern has a portion where the member does not exist in a central portion of the member in a portion immediately below the bonding area. 前記強化パターンは、前記ボンディングエリアの直下部分における前記部材のうち、その全部分に前記部材が存在しないことを特徴とする請求項１記載の半導体集積回路装置。 2. The semiconductor integrated circuit device according to claim 1, wherein the reinforcing pattern does not exist in all of the members in the portion immediately below the bonding area. 前記強化パターンの前記ボンディングエリアの直下部分における前記部材が存在しない部位には、前記層間絶縁膜が形成されていることを特徴とする請求項１乃至３のいずれか一項に記載の半導体集積回路装置。 4. The semiconductor integrated circuit according to claim 1, wherein the interlayer insulating film is formed at a portion where the member does not exist in a portion immediately below the bonding area of the reinforcing pattern. 5. apparatus. 前記強化パターンは、前記複数の配線のうちの１つの配線と同一の層に形成され、前記強化用ビアは、前記ビアと同一の層に形成されていることを特徴とする請求項１乃至４のいずれか一項に記載の半導体集積回路装置。 5. The reinforcing pattern is formed in the same layer as one of the plurality of wirings, and the reinforcing via is formed in the same layer as the via. The semiconductor integrated circuit device according to any one of the above.
JP2004192394A 2004-06-30 2004-06-30 Semiconductor integrated circuit device Pending JP2006019312A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005142553A (en) * 2003-10-15 2005-06-02 Toshiba Corp Semiconductor device
JP2007250965A (en) * 2006-03-17 2007-09-27 Nec Electronics Corp Semiconductor integrated circuit device
JP2007263650A (en) * 2006-03-28 2007-10-11 Dainippon Printing Co Ltd Tool for electrical signal measurement and its manufacturing method
WO2007116463A1 (en) * 2006-03-31 2007-10-18 Fujitsu Limited Semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005142553A (en) * 2003-10-15 2005-06-02 Toshiba Corp Semiconductor device
JP2007250965A (en) * 2006-03-17 2007-09-27 Nec Electronics Corp Semiconductor integrated circuit device
US8399954B2 (en) 2006-03-17 2013-03-19 Renesas Electronics Corporation Semiconductor integrated circuit device
JP2007263650A (en) * 2006-03-28 2007-10-11 Dainippon Printing Co Ltd Tool for electrical signal measurement and its manufacturing method
JP4703456B2 (en) * 2006-03-28 2011-06-15 大日本印刷株式会社 Electric signal measuring jig
WO2007116463A1 (en) * 2006-03-31 2007-10-18 Fujitsu Limited Semiconductor device

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