JP4703456B2 - Electric signal measuring jig - Google Patents

Description

  The present invention relates to an electric signal measuring jig and a method of manufacturing the electric signal measuring jig, and more particularly to an electric signal measuring jig provided with an electric signal measuring pad that can be electrically connected to a terminal of an electronic device, and such an electric signal. The present invention relates to a manufacturing method for manufacturing a measuring jig.

With recent high performance and downsizing of electronic devices, electronic devices used are becoming increasingly dense, large-scale, and complicated. Furthermore, with the increase in the drive clock speed of electronic devices, in addition to the above-mentioned high density, the importance of high speed and high frequency is increasing.
Against this background, jigs for inspecting and measuring electronic devices are also required to have a narrow pitch corresponding to an increase in the number of terminals and a low loss structure corresponding to a high-frequency signal. Specifically, measurement jigs for detecting open and short of printed circuit boards, jigs for inspecting various glass display electrodes, jigs for inspecting semiconductor packages with solder balls and evaluating electrical characteristics And a jig for determining the quality of a semiconductor device, a measurement jig for evaluating signal responsiveness of a desired module at a high frequency, and the like.
JP 2000-304770 A

  However, conventional jigs require a certain degree of rigidity and strength, and because they are easy to manufacture and process, tape-type jigs or printed boards that use plastic substrates are used. Has been. Therefore, in the conventional jig, the inner diameter of the through hole is limited to 100 μm, and the formation pitch of the through hole is limited to about 200 μm. To deal with the narrow pitch and the multi-pin (pad) of the electronic device to be inspected An increase in the size of the electric signal measuring jig was inevitable. In addition, since the resin substrate has low hardness, it is difficult to perform high-definition patterning. From this point of view, it is difficult to reduce the size of the electric signal measuring jig.

On the other hand, in parallel inspection in which a plurality of terminals arranged at high density in a wafer state are inspected at the same time, it is essential to reduce the size of the electric signal measuring jig. The limit was a major obstacle to improving the efficiency of parallel inspection.
In addition, when inspecting an electronic device in a heated state, it is important that the heat resistance of the jig, in particular, the thermal expansion coefficient of the jig is close to the thermal expansion coefficient of the electronic device. However, the conventional jig has a problem that it hinders the inspection of an electronic device having terminals at a narrow pitch.
The present invention has been made in view of the above circumstances, and an electric signal measuring jig for reliably and efficiently inspecting an electronic device, and such an electric signal measuring jig can be simply used. It aims at providing the manufacturing method for manufacturing.

In order to achieve such an object, an electric signal measuring jig according to the present invention includes a silicon substrate, a plurality of through holes formed in the silicon substrate, and an inner wall surface of the through hole. An insulating film formed at a predetermined part on the back surface and two or more surface side silicon dioxide layers laminated at a predetermined part on the surface of the silicon substrate, wherein a plurality of wirings are embedded so as to form the same surface The surface-side silicon dioxide layer provided, the conductive material layer filled in the through-hole, and the wiring embedded in any one of the surface-side silicon dioxide layers and the surface to connect the desired conductive material layer A plurality of conductive via portions disposed through the side silicon dioxide layer and the wiring embedded in the uppermost surface side silicon dioxide layer and are flush with the surface side silicon dioxide layer Multiple electric power A plurality of electrical signal measurements that are not connected to the signal measurement pad and the wiring embedded in the uppermost surface-side silicon dioxide layer and are embedded in the same plane as the surface-side silicon dioxide layer The surface side silicon dioxide layer is connected so as to connect the pad for electric signal measurement, which is not connected to the wiring, and the wiring embedded in any surface side silicon dioxide layer lower than the uppermost layer. And a plurality of electrode vias disposed on the back surface of the silicon substrate and connected to each conductive material layer, and the thickness of the silicon substrate is 100 to 600 μm The inner diameter of the through hole is in the range of 10 to 100 μm.

  In the electric signal measuring jig of the present invention, since the substrate is made of a silicon substrate, sufficient rigidity and strength can be obtained even when the thickness is about 100 to 600 μm, and the coefficient of thermal expansion is the object to be inspected. Since the thermal expansion coefficient of the electronic device is close to that of the electronic device and the electronic device having terminals at a narrow pitch can be reliably inspected in a heated state, and since it has a through hole with a small diameter of 10 to 100 μm, wiring In the case of a multi-layer structure, further downsizing is possible, and parallel inspection for simultaneously inspecting a plurality of terminals arranged at high density in a wafer state becomes easier.

  Further, in the manufacturing method of the present invention, the electrical signal measurement pad and the wiring are formed so as to fill the electrolytic plating site in the high-definition grooves for the electrical signal measurement pad and the wiring formed on the surface side silicon dioxide layer. Therefore, it is possible to form a high-definition electric signal measuring pad and wiring, and also to form a conductive material layer in the through hole and to form an electric signal measuring pad and wiring in the surface side silicon dioxide layer. Can be carried out simultaneously, and the production efficiency is high. Furthermore, fine through holes having an inner diameter of 10 to 100 μm can be formed at a narrow pitch of about 20 to 200 μm. Further, by repeating the second layer forming step as many times as necessary, a small electric signal measuring jig having a multilayer structure can be easily manufactured.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[Electric signal measuring jig]
FIG. 1 is a plan view showing an embodiment of the electric signal measuring jig of the present invention, and FIG. 2 is a schematic cross-sectional view of the electric signal measuring jig shown in FIG. is there. 1 and 2, an electric signal measuring jig 1 according to the present invention is formed on a silicon substrate 2, a plurality of through holes 3 formed in the silicon substrate 2, and the surface 2a side of the silicon substrate 2. The surface side silicon dioxide layer 5 is provided. A plurality of electric signal measuring pads 6 and wirings 7 are embedded in the surface-side silicon dioxide layer 5 with the surface exposed. The wiring 7 connects the conductive material layer 8 disposed in each through-hole 3 and each electric signal measuring pad 6. Further, a silicon dioxide film 4 is provided on the inner wall surface of the through hole 3 and the back surface 2b of the silicon substrate 2, and the conductive material layer 8 disposed in each through hole 3 is a silicon dioxide film on the back surface 2b of the silicon substrate 2. 4 has an end face that is flush with the electrode pad 9. In the illustrated example, in order to avoid the drawing from becoming complicated, a case is shown in which ten electric signal measuring pads 6 arranged in two rows of five are provided for convenience.

In the electric signal measuring jig 1 of the present invention having the above-described structure, the terminals of the electronic device 31 (indicated by imaginary lines in FIG. 2) to be inspected are electrically connected to the plurality of electric signal measuring pads 6. The electronic device 31 is inspected by connecting the input / output signal terminal and the power supply terminal to the electrode pad 9 on the back surface of the electric signal measuring jig 1 and supplying the input / output signal and power.
The silicon substrate 2 constituting the electric signal measuring jig 1 has a thickness in the range of 100 to 600 μm, preferably 300 to 500 μm. When the thickness of the silicon substrate 2 is less than 100 μm, the strength is insufficient, the durability when the through holes 3 are provided at a narrow pitch is lowered, and warpage is likely to occur. On the other hand, if the thickness exceeds 600 μm, it is difficult to form the through hole 3 of the electric signal measuring jig, which is not preferable.

The through hole 3 provided in such a silicon substrate 2 has an inner diameter in the range of 10 to 100 μm, preferably in the range of 10 to 50 μm, and a pitch (distance L between opening centers of adjacent through holes as shown in FIG. 1). It is in the range of 20 to 1000 μm, preferably 30 to 300 μm. Further, at least part of the through holes 3 may have a pitch in the range of 20 to 200 μm. In the present invention, all the inner diameters and pitches of the through holes 3 may be within the above range, and among the plurality of through holes 3, the desired through hole 3 has an inner diameter and a pitch within the above range. There may be. Of course, all the through holes 3 may have, for example, an inner diameter of 10 μm and a formation pitch of 20 μm.
The silicon dioxide film 4 formed on the silicon substrate 2 has a thickness of about 0.1 to 5 μm, preferably about 0.8 to 4.5 μm. The surface-side silicon dioxide layer 5 has a thickness of about 0.1 to 5 μm, preferably about 0.8 to 4.5 μm. If the thickness of the silicon dioxide film 4 and the surface-side silicon dioxide layer 5 is less than the above range, poor insulation is likely to occur, and if it exceeds the above range, stress control during film formation becomes difficult and warpage and distortion are likely to occur. It is not preferable.

  The electric signal measuring pad 6 constituting the electric signal measuring jig 1 is for electrically connecting the terminals of the electronic device, and the shape thereof is not particularly limited, and is continuous with the wiring 7 as shown in the illustrated example. It may be a rectangular shape, a circular shape, a rectangular shape wider than the wiring 7, an elliptical shape, or the like. The electric signal measuring pad 6 is embedded in the surface side silicon dioxide layer 5 with the surface exposed. In the illustrated example, the surface of the electric signal measuring pad 6 is the same as the surface of the surface side silicon dioxide layer 5. It has a surface. The dimensions, formation pitch, arrangement state, and number of the electrical signal measurement pads 6 can be set in consideration of the pitch, arrangement, number, etc. of the terminals of the electronic device to be inspected. Further, the electric signal measuring pad 6 may be protruded from the surface or a protrusion may be provided on the electric signal measuring pad 6 in accordance with the inspection object. In the case where the protrusion is provided, for example, a material such as gold or nickel can be used.

The wiring 7 connects the electric signal measuring pad 6 and the conductive material layer 8 in the corresponding through hole 3 and is embedded in the surface-side silicon dioxide layer 5 with the surface exposed. In the illustrated example, the surface of the wiring 7 is flush with the surface of the surface-side silicon dioxide layer 5. In the illustrated example, the plurality of wirings 7 are linearly arranged in parallel. However, the present invention is not limited to this, and the arrangement and number of electric signal measurement pads 6 and the arrangement of through holes 3 are not limited thereto. , And can be appropriately designed according to the number.
The conductive material layer 8 is formed on the silicon dioxide film 4 of each through hole 3 to fill the through hole 3, and one end thereof is connected to the wiring 7 on the surface 2 a side of the silicon substrate 2. The other end is exposed to the back surface 2b side of the silicon substrate 2 to form an electrode pad 9. In the illustrated example, the conductive material layer 8 is disposed so as to fill the through-hole 3, but may be disposed on the inner wall surface of the through-hole 3 so as to leave a through hole.

  The material of the electric signal measuring pad 6, the wiring 7, the conductive material layer 8, and the electrode pad 9 as described above can be, for example, copper, silver, gold, or the like. Further, when the electric signal measuring pad 6, the wiring 7, the conductive material layer 8, and the electrode pad 9 are made of a material that may cause corrosion such as copper, the exposed electric signal measuring pad 6 and the wiring are exposed. 7. A gold thin film, a nickel thin film, or the like may be disposed on the surface of the electrode pad 9 to provide corrosion resistance.

FIG. 3 is a plan view showing another embodiment of the electric signal measuring jig of the present invention, and FIG. 4 is a schematic cross-sectional view of the electric signal measuring jig shown in FIG. It is. 3 and 4, the electric signal measuring jig 11 of the present invention is laminated on the silicon substrate 12, a plurality of through holes 13 formed in the silicon substrate 12, and the surface 12 a side of the silicon substrate 12. The surface side silicon dioxide layers 15a, 15b and 15c, and a plurality of electric signal measuring pads 16a, 16b and 16c formed on the surface side silicon dioxide layer 15c which is the uppermost layer. In the illustrated example, in order to avoid the drawing from becoming complicated, a case is shown in which 30 electrical signal measurement pads arranged in 6 rows of 5 are provided for convenience.
On the other hand, a silicon dioxide film 14 is provided on the inner wall surface of each through hole 13 and the back surface 12 b of the silicon substrate 12, and each through hole 13 is filled with a conductive material layer 18.

  In addition, wiring layers 17a and 17b are embedded in the laminated surface-side silicon dioxide layers 15a and 15b so that the surfaces are the same, and the surface is exposed in the surface-side silicon dioxide layer 15c. The wiring layer 17c is embedded in the state. Of these wiring layers 17a, 17b, and 17c, the wiring layer 17a is connected to the conductive material layer 18 of the corresponding through hole 13 and is disposed through the front-side silicon dioxide layers 15b and 15c. It is connected to the electric signal measuring pad 16a through the via portion 21a. In addition, the wiring layer 17b is connected to the conductive material layer 18 of the corresponding through hole 13 through the conductive via portion 20a disposed through the surface side silicon dioxide layer 15a, and the surface side silicon dioxide layer 15c. Is connected to the electric signal measuring pad 16b through a wiring via portion 21b disposed so as to penetrate therethrough. Further, the wiring layer 17c is connected to the electric signal measuring pad 16c and is electrically conductive material of the corresponding through hole 13 through the conductive via portion 20b disposed through the surface side silicon dioxide layers 15a and 15b. Connected to layer 18.

The conductive material layer 18 disposed in each through hole 13 has an end surface that is flush with the silicon dioxide film 14 on the back surface 12 b of the silicon substrate 12, and this end surface serves as an electrode pad 19.
In the electric signal measuring jig 11 of the present invention having the above-described structure, the terminals of the electronic device 41 (indicated by imaginary lines in FIG. 4) to be inspected are placed on the plurality of electric signal measuring pads 16a, 16b and 16c. Are electrically connected, and the terminals of the electronic device tester or the like are brought into contact with the electrode pads 19 on the back surface of the electric signal measuring jig 11 to supply input / output signals and power, whereby the electronic device 41 is inspected. .
The silicon substrate 12 constituting the electric signal measuring jig 11 has a thickness in the range of 100 to 600 μm, preferably 300 to 500 μm. When the thickness of the silicon substrate 12 is less than 100 μm, the strength is insufficient, the durability when the through holes 13 are provided at a narrow pitch is lowered, and warping is likely to occur. On the other hand, if the thickness exceeds 600 μm, it is difficult to form the through hole 13 of the electric signal measuring jig, which is not preferable.

  The through holes 13 provided in the silicon substrate 12 are formed so as to correspond to the plurality of electric signal measurement pads 16a, 16b, and 16c, and have an inner diameter of 10 to 100 μm, preferably 10 to 50 μm, and a pitch ( As shown in FIG. 3, the distance L) between the opening centers of adjacent through holes is in the range of 20 to 1000 μm, preferably 30 to 300 μm. Further, at least part of the through holes 13 may have a pitch in the range of 20 to 200 μm. In the present invention, all the inner diameters and pitches of the through holes 13 may be within the above range, and among the plurality of through holes 13, the desired through hole 13 has an inner diameter and a pitch within the above range. There may be. Of course, all the through holes 13 may have, for example, an inner diameter of 10 μm and a formation pitch of 20 μm.

  The silicon dioxide film 14 formed on the silicon substrate 12 has a thickness of about 0.1 to 5 μm, preferably about 0.8 to 4.5 μm. Moreover, the thickness of each laminated | stacked surface side silicon dioxide layer 15a, 15b, 15c can be 0.1-5 micrometers, Preferably it is about 0.8-4.5 micrometers. If the thickness of the silicon dioxide film 14 and the surface-side silicon dioxide layers 15a, 15b, and 15c is less than the above range, insulation failure is likely to occur. If the thickness exceeds the above range, stress control during film formation becomes difficult and warping may occur. Distortion tends to occur and is not preferable.

  The electric signal measuring pads 16a, 16b, and 16c constituting the electric signal measuring jig 11 are for electrically connecting terminals of the electronic device, and the shape is not particularly limited, as shown in the illustrated example. It may be circular, or may be square, elliptical or the like. The electric signal measuring pads 16a, 16b, and 16c are embedded in the outermost surface side silicon dioxide layer 15c with the surface exposed, and in the illustrated example, the surfaces of the electric signal measuring pads 16a, 16b, and 16c are embedded. Is flush with the surface of the surface-side silicon dioxide layer 15c. The dimensions, formation pitch, arrangement state, and number of the electric signal measurement pads 16a, 16b, and 16c can be set in consideration of the pitch, arrangement, number, and the like of the terminals of the electronic device to be inspected. Further, the electrical signal measurement pads 16a, 16b, and 16c may be protruded from the surface or projections may be provided on the electrical signal measurement pads 16a, 16b, and 16c in accordance with the inspection target. In the case where the protrusion is provided, for example, a material such as gold or nickel can be used.

  Further, the wirings 17a, 17b, and 17c are formed by connecting the electrical signal measuring pads 16a, 16b, and 16c and the conductive material layer 18 in the corresponding through hole 13 to the conductive via portions 20a and 20b, the wiring via portion 21a, It connects via 21b. The wirings 17a and 17b are embedded in the surface-side silicon dioxide layers 15a and 15b so as to form the same surface, and the wiring 17c is embedded in the surface-side silicon dioxide layer 15c with the surface exposed. Then, the surface of the wiring 17c is flush with the surface of the uppermost surface side silicon dioxide layer 15c. In the illustrated example, the plurality of wirings 17a, 17b, and 17c are linear shapes arranged in parallel in a multilayer structure, but are not limited to this, and the electrical signal measurement pads 16a, 16b, and 16c are not limited thereto. It is possible to design appropriately according to the arrangement and number of the through holes 13 and the arrangement and number of the through holes 13.

The conductive material layer 18 is formed on the silicon dioxide film 14 in each through hole 13 and fills the through hole 13. One end of the conductive material layer 18 on the surface 12a side of the silicon substrate 12 is electrically connected to the wiring 17a. The other end portion is connected to the via portions 20 a and 20 b and is exposed to the back surface 12 b side of the silicon substrate 12 to form an electrode pad 19.
The electric signal measuring pads 16a, 16b, 16c, the wirings 17a, 17b, 17c, the conductive material layer 18, the electrode pads 19, the conductive via portions 20a, 20b, and the wiring via portions 21a, 21b as described above are, for example, It can be copper, silver, gold or the like. Further, when a material that may cause corrosion, such as copper, is used, a gold thin film, a nickel thin film, or the like is formed on the surface of the exposed electric signal measuring pads 16a, 16b, 16c, the wiring 17c, and the electrode pad 19. To prevent corrosion.

  Since the electric signal measuring jig of the present invention as described above uses a silicon substrate as the substrate, sufficient rigidity and strength can be obtained even when the substrate thickness is in the range of 100 to 600 μm. In addition, since the thermal expansion coefficient of the silicon substrate is close to the thermal expansion coefficient of the electronic device that is the object to be inspected, it is possible to reliably inspect the electronic device having terminals at a narrow pitch in a heated state. Further, since the inner diameter and pitch of the through holes can be set to the minimum inner diameter of 10 μm and the pitch of 20 μm, the electric signal measuring jig can be easily downsized. Further, by using a multilayer structure such as the electric signal measuring jig 11, it becomes possible to further reduce the size, and parallel inspection for simultaneously inspecting a plurality of electronic devices in a wafer state becomes easier.

  The embodiment of the electric signal measuring jig described above is an example, and the electric signal measuring jig of the present invention is not limited to this. For example, the electrode pads 9 and 19 may protrude from the back surfaces 2b and 12b of the silicon substrates 2 and 12 and are formed at desired positions (positions different from the through holes 3 and 13) via wiring. May be. Further, a barrier metal layer such as a titanium nitride film may be provided on the silicon dioxide films 4 and 14 and the surface side silicon dioxide layers 5 and 15c. Further, in the electric signal measuring jig 11, the surface side silicon dioxide layer has a three-layer structure, but the number of the surface side silicon dioxide layers is not limited to three.

[Method for manufacturing jig for measuring electric signal]
Next, a method for manufacturing an electric signal measuring jig according to the present invention will be described with reference to the drawings.
5 to 7 are process diagrams for explaining an embodiment of the method for manufacturing an electric signal measuring jig according to the present invention, using the electric signal measuring jig 1 as an example.
In the method for manufacturing an electric signal measuring jig of the present invention, first, the surface-side silicon dioxide layer 5 is formed on the surface 2a of the silicon substrate 2 (FIG. 5A). The surface-side silicon dioxide layer 5 can be formed by a vacuum film-forming method such as a plasma CVD method, a coating method using a silicon oxide precursor solution, or the like.

  Next, a mask pattern 51 having a predetermined opening is formed on the surface-side silicon dioxide layer 5 (FIG. 5B), and a plurality of grooves 52 are formed by etching or sandblasting using the mask pattern 51 as a mask. Is formed on the surface-side silicon dioxide layer 5 (FIG. 5C). The mask pattern 51 can be formed using a conventionally known photosensitive resist. For example, by setting the thickness of the mask pattern 51 to about 5 to 50 μm, the opening width (the electric signal measurement pad 6 to be formed 6 is formed. The mask pattern 51 having a fine opening having a width of the wiring 7 of about 5 μm can be formed. Etching can be performed, for example, by dry etching by ICP-RIE (Inductively Coupled Plasma-Reactive Ion Etching) method or wet etching. As shown in FIG. 5D, the shape of the formed groove 52 corresponds to the shape of the electric signal measurement pad 6 and the wiring 7 to be formed, the opening width W is about 5 μm, and the pitch P is A fine shape of about 10 μm can be formed.

Next, a mask pattern 53 having a predetermined opening is formed on the surface-side silicon dioxide layer 5 so as to cover the groove 52 (FIG. 6A), and a plurality of etching processes are performed by using the mask pattern 53 as a mask. The through hole 3 is formed (FIG. 6B). Each formed through hole is positioned so as to hang over a part of each groove 52. The etching process can be performed by, for example, dry etching by ICP-RIE method or wet etching. Further, the through hole 3 may be formed by sandblasting.
The inner diameter of the through-hole 3 to be formed can be appropriately set within the range of 10 to 100 μm, preferably 5 to 50 μm, the formation pitch can be set within the range of 20 to 1000 μm, preferably 30 to 300 μm, and at least a part of the formation pitch can be set. They are set in the range of 20 to 200 μm, and these can be adjusted according to the size and position of the opening of the mask pattern.

A mask pattern may also be formed on the back surface 2b of the silicon substrate 2, and the through holes 3 may be formed from both surfaces by sandblasting. Also, any one of the above-mentioned may be applied to the silicon substrate 2 from the surface side silicon dioxide layer 5 side. The through hole 3 may be formed by forming a microhole with a predetermined depth by a method and then polishing the back surface 2b of the silicon substrate 2 to expose the microhole.
Next, a silicon dioxide film 4 is formed on the back surface 2b of the silicon substrate 2 including the inner wall surface of the through hole 3 (FIG. 6C). The silicon dioxide film 4 can be formed by a vacuum film forming method such as a plasma CVD method, a coating method using a precursor solution of silicon oxide or the like, a method of thermally oxidizing the silicon substrate 2 or the like.

Next, a base conductive thin film 55 is formed on the silicon dioxide film 4 and the surface-side silicon dioxide layer 5 (FIG. 7A). It is difficult for the silicon dioxide film 4 and the surface-side silicon dioxide layer 5 to provide a catalyst for electroless plating, and the underlying conductive thin film is also reliably formed on the silicon dioxide film 4 inside the fine through-hole 3. In order to form it, in this invention, the base conductive thin film 55 is formed without using an electroless plating method. For example, first, a titanium nitride film is provided on the silicon dioxide film 4 and the surface-side silicon dioxide layer 5 by MOCVD (Metal Organic-Chemical Vapor Deposition) using plasma to form a barrier metal layer. Next, a base conductive thin film 55 is formed on the titanium nitride film by forming a thin film such as copper by sputtering or CVD.
Note that an insulating film may be formed on the titanium nitride film, and then the base conductive thin film 55 may be formed. In this case, a silicon dioxide film can be formed as the insulating film by a plasma CVD method.

Next, desired resist patterns 56 are formed on both surfaces (on the underlying conductive thin film 55) of the silicon substrate 2, and the inner wall surface and the surface side of the through hole 3 are formed by electrolytic plating using the underlying conductive thin film 55 as a power feeding layer. Electrolytic plating sites 57 are formed in the grooves 52 of the silicon dioxide layer 5 (FIG. 7B). The resist pattern 56 can be formed, for example, by laminating a photosensitive dry film resist on the silicon substrate 2 and exposing and developing it through a desired photomask. Electrolytic plating can be performed by electrolytic copper plating, electrolytic silver plating, electrolytic gold plating, or the like.
Next, the resist pattern 56 is removed, and thereafter, the electrolytic plating site 57 and the exposed underlying conductive thin film 55 are removed by polishing so that the electrolytic plating site 57 remains only in the groove 52. As a result, the electrical signal measuring pad 6 and the wiring 7 are formed in the groove 52, and the electroplating portion 57 filled in the through hole 3 becomes the conductive material layer 8, thereby conducting conduction on the front and back sides. An electric signal measuring jig 1 having an electrode pad 9 with the end of 8 being flush with the silicon dioxide film 4 is obtained (FIG. 7C). Polishing of the electroplating site 57 and the exposed underlying conductive thin film 55 can be performed by, for example, chemical mechanical polishing (CMP) or the like.

In the present invention, the above-described electrical signal measurement pad 6, wiring 7 and conductive material layer 8 may be formed as follows. That is, polishing (for example, CMP) is performed with the resist pattern 56 left without being removed, so that the electrolytic plating portion 57 and the resist pattern 56 are flush with each other. Next, the resist pattern 56 is removed, and the exposed underlying conductive thin film 55 is removed by wet etching, thereby forming the electric signal measuring pad 6, the wiring 7, and the conductive material layer 8. Further, after removing the underlying conductive thin film 55 by wet etching, the electric signal measuring pad 6 and the wiring 7 may be polished (for example, CMP).
When the base conductive thin film 55 is formed through the titanium nitride film as described above, the titanium nitride film is also removed together with the base conductive thin film 55. Further, as described above, the electric signal measuring jig of the present invention may be provided with a barrier metal layer such as a titanium nitride film on the silicon dioxide film 4 or the surface side silicon dioxide layer 5, as described above. In the case of manufacturing an electric signal measuring jig having such a form, only the base conductive thin film 55 is removed, and the titanium nitride film is left.

  In such a method for manufacturing an electric signal measuring jig according to the present invention, the electric signal measuring pad 6 and the wiring 7 are formed so that the plurality of grooves 52 formed in the surface-side silicon dioxide layer 5 are filled with the electrolytic plating portion 57. As described above, the groove 52 can be formed to have a fine shape with an opening width of about 5 μm and a pitch of about 10 μm. Therefore, it is possible to form a high-definition electric signal measuring pad 6 and wiring 7. is there. In addition, the formation of the conductive material layer 8 in the through hole 3 and the formation of the electric signal measuring pad 6 and the wiring 7 on the surface-side silicon dioxide layer 5 can be performed simultaneously, and the manufacturing efficiency is high. Further, fine through holes 3 having an inner diameter of 10 to 100 μm can be formed at a narrow pitch of about 20 to 200 μm. Furthermore, the conductive material layer 8 can be formed without causing defects in these fine through holes. In the present invention, the electric signal measuring pads 6 and the wirings 7 can be formed in a high-definition pattern on the surface-side silicon dioxide layer 5 where film formation by electroless plating is impossible.

8 to 9 are process diagrams for explaining another embodiment of the method for manufacturing an electric signal measuring jig according to the present invention, using the electric signal measuring jig 11 as an example.
In the method for manufacturing an electric signal measuring jig of the present invention, first, in the same manner as the method for manufacturing the electric signal measuring jig 1, the plurality of through holes 13 formed in the silicon substrate 12 and the silicon substrate are formed. 12 on the surface 12a side of the surface 12, a plurality of electric signal measuring pads 16a, wirings 17a embedded in the surface side silicon dioxide layer 15a so that the surface is exposed, and each through hole A basic structure 11A including a silicon dioxide film 14 formed on the inner wall surface 13 and the back surface 12b of the silicon substrate 12 and a conductive material layer 18 filled in each through hole 13 is produced (FIG. 8A). .

Next, a second surface-side silicon dioxide layer 15b is laminated on the surface-side silicon dioxide layer 15a of the basic structure 11A (FIG. 8B). The surface-side silicon dioxide layer 15b can also be formed by a vacuum film-forming method such as a plasma CVD method, a coating method using a silicon oxide precursor solution, or the like, similarly to the surface-side silicon dioxide layer 5 described above. .
Next, a plurality of grooves 62 are formed in the surface-side silicon dioxide layer 15b (FIG. 8C). The formation of the groove 62 can be performed in the same manner as the formation of the groove 52 in the surface-side silicon dioxide layer 5 described above. The groove 62 formed in this way is located outside the wiring 17a of the lower surface side silicon dioxide layer 15a.
Next, fine holes having a predetermined size are formed in the surface-side silicon dioxide layer 15b so that the electrical signal measuring pad 16a formed on the surface-side silicon dioxide layer 15a, which is the lower layer, is exposed. A hole 64 is formed, and a new through hole 13 is formed in the surface-side silicon dioxide layer 15a, the surface-side silicon dioxide layer 15b, and the silicon substrate 12 in the stacked state (FIG. 8D). Each formed through hole 13 is positioned so as to hang over a part of each groove 62.

The formation of the new through hole 13 can be performed in the same manner as the formation of the through hole 3 in the surface side silicon dioxide layer 5 and the silicon substrate 2 described above. The via hole 64 is formed by, for example, forming a mask pattern having a predetermined opening on the surface-side silicon dioxide layer 15b so as to cover the groove 62, and etching the mask pattern as a mask. can do. As the etching process, for example, dry etching by ICP-RIE method or wet etching can be used. Alternatively, the via hole 64 may be formed by sandblasting. The order of forming the through hole 13 and the via hole 64 is not particularly limited.
The inner diameter of the through-hole 13 to be formed can be appropriately set in the range of 10 to 100 μm, preferably in the range of 5 to 50 μm, and the formation pitch can be set in the range of 20 to 1000 μm, preferably in the range of 30 to 300 μm. It sets in the range of 20-200 micrometers. The inner diameter of the via hole 64 can be appropriately set within a range of 10 to 100 μm, preferably 5 to 50 μm.

Next, the silicon dioxide film 14 is formed on the inner wall surface of the newly formed through hole 13, and then the underlying conductive thin film is formed on the silicon dioxide film 14, the surface-side silicon dioxide layer 15 b, and the via hole 64. 65 is formed (FIG. 9A). The silicon dioxide film 14 and the base conductive thin film 65 can be formed in the same manner as the method for forming the silicon dioxide film 4 and the base conductive thin film 55 described above.
Next, a desired resist pattern 66 is formed on both surfaces (on the base conductive thin film 65) of the silicon substrate 12, and the inner wall surface of the through hole 13 and the via hole are formed by electrolytic plating using the base conductive thin film 65 as a power feeding layer. The electroplating site | part 67 is formed in the groove part 62 in 64 and the surface side silicon dioxide layer 15b (FIG. 9 (B)). The formation of the resist pattern 66 and the formation of the electrolytic plating portion 67 by electrolytic plating can be performed in the same manner as the above-described method of forming the resist pattern 56 and the method of forming the electrolytic plating portion 57.

Next, the resist pattern 66 is removed, and then the electrolytic plating site 67 and the exposed underlying conductive thin film 65 are removed by polishing so that the electrolytic plating site 67 remains only in the groove 62 and the via hole 64. Thus, the electrical signal measurement pad 16b and the wiring 17b are formed in the groove 62, the wiring via 21a is formed in the via hole 64, and the electroplating site 67 filled in the through hole 13 is electrically conductive. The material layer 18 becomes conductive on the front and back sides, and the end thereof is flush with the silicon dioxide film 14 to form an electrode pad 19 (FIG. 9C). Polishing of the electroplating site 67 and the exposed underlying conductive thin film 65 can be performed by, for example, chemical mechanical polishing (CMP).
Next, in the same manner as in the above-described steps shown in FIGS. 8B to 9C, the electrical signal measuring pads 16a, 16b, and 16c and the wiring 17c are embedded so that the surface is exposed. The silicon dioxide layer 15c can be formed on the surface-side silicon dioxide layer 15b, and the electric signal measuring jig 11 of the present invention can be obtained (FIG. 9D).

  For example, when the base conductive thin film 65 is formed via a titanium nitride film, the titanium nitride film is also removed together with the base conductive thin film 65. Further, as described above, the electric signal measuring jig of the present invention may be provided with a barrier metal layer such as a titanium nitride film on the silicon dioxide film 14 or the surface side silicon dioxide layer 15c. In the case of manufacturing an electric signal measuring jig having such a form, only the base conductive thin film 65 is removed, leaving a titanium nitride film.

  Such a method for manufacturing an electric signal measuring jig of the present invention can easily manufacture a small electric signal measuring jig having a multilayer structure by repeating the second layer forming step as many times as necessary. . Further, the electric signal measuring pads 16a, 16b, 16c and the wirings 17a, 17b, 17c are formed so as to fill the electrolytic plating site 67 in the plurality of grooves 62 formed in the surface side silicon dioxide layers 15a, 15b, 15c of the respective layers. Therefore, it is possible to form a high-definition electric signal measuring pad and wiring. Further, the formation of the conductive material layer 18 in the through hole 13 and the formation of the electric signal measuring pads 16a, 16b, 16c and the wirings 17a, 17b, 17c on the surface side silicon dioxide layers 15a, 15b, 15c can be performed simultaneously. Can be produced and has high production efficiency. Further, fine through holes 13 having an inner diameter of 10 to 100 μm can be formed at a narrow pitch of about 20 to 200 μm. Furthermore, the conductive material layer 18 can be formed without causing defects in these fine through holes. Further, in the present invention, electrical signal measuring pads and wirings can be formed in a high-definition pattern on the surface-side silicon dioxide layers 15a, 15b, and 15c where film formation by electroless plating is impossible.

  The manufacturing method of the electric signal measuring jig of the present invention is not limited to the one shown in the above embodiment. For example, the electrical signal measurement pad 6, the electrical signal measurement pads 16a, 16b, 16c exposed on the surface side silicon dioxide layer 15c, the wiring 17c exposed on the surface side silicon dioxide layer 15c, and the electrode pads 9, 19 Alternatively, a gold thin film, a nickel thin film, or the like may be formed by electroless plating. In particular, as described above, the electrical signal measurement jig manufactured so that the silicon dioxide films 4 and 14 and the surface-side silicon dioxide layers 5 and 15c are exposed except the portions where the electrical signal measurement pads, wirings, and electrode pads are formed. In the tool, it is difficult to apply a catalyst for electroless plating to the silicon dioxide film and the surface-side silicon dioxide layer. Therefore, without forming a mask pattern, the electroless plating catalyst is attached only to the electric signal measurement pad, wiring, and electrode pad, and a gold thin film, nickel thin film, etc. are formed only by electroless plating on these parts. can do.

Next, the present invention will be described in more detail with specific examples.
[Example 1]
A silicon substrate having a thickness of 625 μm was prepared, and the surface of this silicon substrate was subjected to thermal oxidation (1050 ° C., 40 minutes) to form a surface-side silicon dioxide layer (thickness 2 μm).
Next, a silicon nitride film (thickness: 5 μm) was formed on the surface silicon dioxide layer by plasma CVD. Next, a positive photoresist (OFPR-800 manufactured by Tokyo Ohka Kogyo Co., Ltd.) is applied on the silicon nitride film, and exposed and developed through a photomask for forming electric signal measuring pads and wirings. A resist pattern was formed. Next, the silicon nitride film exposed from the resist pattern was dry-etched using CF ₄ as an etching gas, and then the resist pattern was stripped with a dedicated stripping solution to form a mask pattern made of silicon nitride. In this mask pattern, 100 circular openings for forming an electric signal measuring pad having a diameter of 100 μm were arranged in a line at a pitch of 200 μm, and this array was formed in parallel at a distance of 3 mm. It was. Further, from the arranged two rows of circular openings, line-shaped openings each having a width of 10 μm were continuously provided with a length of 15 mm in opposite directions (outward directions).

Next, the surface side silicon dioxide layer exposed from the mask pattern was dry-etched using SF ₆ as an etching gas by an ICP-RIE apparatus to form a groove. The groove portion was composed of a circular groove portion having an opening diameter of 50 μm and a line-shaped groove portion having a width of 10 μm provided continuously to the groove portion, and the depth was about 1 μm.
Next, after removing the mask pattern using acetone, a silicon nitride film (thickness 5 μm) was formed again by plasma CVD so as to cover the groove formed in the surface-side silicon dioxide layer. Next, a positive photoresist (OFPR-800 manufactured by Tokyo Ohka Kogyo Co., Ltd.) was applied onto the silicon nitride film, and a resist pattern was formed by exposure and development through a photomask for forming a through hole. . Next, the silicon nitride film exposed from the resist pattern was dry-etched using CF ₄ as an etching gas, and then the resist pattern was stripped with a dedicated stripping solution to form a mask pattern made of silicon nitride. This mask pattern has a circular opening having a diameter of 50 μm at each tip portion of the above-mentioned line-shaped groove, and the end of the line-shaped groove is exposed to about 10 μm in each circular opening. there were.

Next, by using an ICP-RIE apparatus, the surface side silicon dioxide layer exposed from the mask pattern and the underlying silicon substrate were dry-etched using SF ₆ as an etching gas to form through holes. The through holes have a tapered shape in which one opening diameter is 55 μm and the other opening diameter is 50 μm, and 100 pieces are arranged in a row at a pitch of 200 μm. In the through holes, the line-shaped groove portions described above are arranged. The end was exposed.
Next, the mask pattern was removed using acetone. Next, a thermal oxidation treatment (1050 ° C., 20 minutes) was performed on the silicon substrate on which the through hole was formed, and a silicon dioxide film was formed on the back surface of the silicon substrate including the inner wall surface of the through hole.
Next, a titanium nitride film is formed by MOCVD on the surface side silicon dioxide layer and the silicon dioxide film, and a copper thin film (thickness 0.2 μm) is formed by vapor deposition from the surface side silicon dioxide layer side. A conductive thin film was obtained.

Next, a dry film resist (APR manufactured by Asahi Kasei Co., Ltd.) was laminated on both sides of the silicon substrate. Then, the dry film resist on the surface side silicon dioxide layer side was exposed and developed through the photomask for exposing the groove and the through hole, thereby forming a resist pattern (thickness: 15 μm). The dry film resist on the other side was exposed and developed through a photomask for forming electrode pads to form a resist pattern (thickness 15 μm).
Next, electrolytic copper plating was performed using these resist patterns as a mask and the above-mentioned underlying conductive thin film as a power feeding layer. Thereby, the electrolytic plating site | part which filled the through hole and filled the groove part formed in the surface side silicon dioxide layer was formed.

  Next, the resist pattern is removed using acetone, and then the electroplating site, the underlying conductive thin film, and the titanium nitride film exposed on both surfaces of the silicon substrate are removed by chemical mechanical polishing, and the inside of the through hole and the groove portion are removed. The electrolytic plating site was left only inside. Thus, an electric signal measuring jig of the present invention as shown in FIGS. 1 and 2 was obtained. In this electric signal measuring jig, 100 circular electric signal measuring pads having a diameter of 50 μm are embedded in a line at a pitch of 150 μm with the surface exposed in the surface-side silicon dioxide layer. There are two parallel wires across the distance, and 10 μm wide line-like wiring is buried outside each electric signal measuring pad, with the surface exposed, and the tip of these wires has a conductive material layer in the through hole. It was connected to the electrode pad on the back surface. The electrode pad was an exposed surface of the conductive material layer filled in the through hole, and had a circular shape with a diameter of 50 μm and the same surface as the silicon dioxide film. 50 such electrode pads were arranged in a line at a pitch of 150 μm, and two lines were formed in parallel through a distance of 30 mm.

[Example 2]
In the same manner as in Example 1, the electric signal measuring jig of the present invention was produced and used as a basic structure.
Next, a second surface-side silicon dioxide layer was formed on the surface-side silicon dioxide layer of this basic structure in the same manner as the formation of the surface-side silicon dioxide layer of Example 1.
Next, grooves were formed in the second surface-side silicon dioxide layer by the same method as in Example 1. This groove part was located outside the two through-hole rows included in the basic structure. That is, a circular groove having an opening diameter of 50 μm and a line-shaped groove having a width of 10 μm connected to the circular groove, the depth is about 1 μm, and 100 circular grooves are arranged in a row at a pitch of 200 μm. Two such arrays were formed in parallel via a distance of 30 mm. And the line-shaped groove part was extended in the outer side direction of each circular groove part.

Next, a silicon nitride film (thickness 5 μm) was formed on the second surface-side silicon dioxide layer by plasma CVD. Next, a positive type photoresist (OFPR-800 manufactured by Tokyo Ohka Kogyo Co., Ltd.) was applied onto the silicon nitride film, and exposed and developed through a photomask for forming vias to form a resist pattern. Next, the silicon nitride film exposed from the resist pattern was dry-etched using CF ₄ as an etching gas, and then the resist pattern was stripped with a dedicated stripping solution to form a mask pattern made of silicon nitride. Next, by using an ICP-RIE apparatus, the second surface side silicon dioxide layer exposed from the mask pattern was dry-etched using SF ₆ as an etching gas to form via holes. The via hole had an opening diameter of 60 μm, and the electric signal measurement pad provided in the basic structure was exposed.

Next, through holes penetrating the surface-side silicon dioxide layer composed of two layers and the silicon substrate were formed in the same manner as in Example 1. The through holes have a tapered shape in which one opening diameter is 65 μm and the other opening diameter is 60 μm, and 50 through holes are arranged in a line at a pitch of 200 μm. This through hole was an exposed end of a line-shaped groove formed in the second surface-side silicon dioxide layer.
Next, the silicon substrate was subjected to thermal oxidation (1050 ° C., 20 minutes) to form a silicon dioxide film on the inner wall surface of a new through hole.
Next, a titanium nitride film is formed by MOCVD on the second surface side silicon dioxide layer and silicon dioxide film, and a copper thin film (thickness 0.2 μm) is formed on one side of the silicon substrate by sputtering. A thin film was formed.

Next, a dry film resist (APR manufactured by Asahi Kasei Co., Ltd.) was laminated on both sides of the silicon substrate. Then, the dry film resist having the second surface side silicon dioxide layer is exposed through a photomask for exposing the groove, the via hole, and the through hole formed in the second surface side silicon dioxide layer. And developed to form a resist pattern (thickness 15 μm). The dry film resist on the other side was exposed and developed through a photomask for forming electrode pads to form a resist pattern (thickness 15 μm).
Next, electrolytic copper plating was performed using these resist patterns as a mask and the above-mentioned underlying conductive thin film as a power feeding layer. As a result, an electrolytic plating site was formed that filled the through hole and filled the groove and via hole formed in the second surface-side silicon dioxide layer.

  Next, the resist pattern is removed using acetone, and then the electroplating site, the underlying conductive thin film, and the titanium nitride film exposed on both surfaces of the silicon substrate are removed by chemical mechanical polishing, and the inside of the through hole and the groove portion are removed. Inside, the electrolytic plating site was left only in the via hole. Thereby, the electric signal measuring jig of the present invention having a multilayer structure was obtained. This electric signal measuring jig includes 50 circular electric signal measuring pads having a diameter of 100 μm embedded in a line at a pitch of 200 μm with the surface exposed in the surface-side silicon dioxide layer, Two rows of electric signal measuring pads were provided in parallel with a distance of 0.5 mm, and one row of electric signal measuring pads was further provided in parallel with a distance of 30 mm on the outside. Of the four rows of electric signal measurement pads, the outer two rows of electric signal measurement pads are embedded in a line-like wiring having a width of 10 μm in the outer direction with their surfaces exposed. The tip of the wiring was connected to the electrode pad on the back surface through the conductive material layer in the through hole. The electrode pad is an exposed surface of the conductive material layer filled in the through hole, has a circular shape with a diameter of 50 μm, and has a surface flush with the silicon dioxide film, and is arranged in a row at a pitch of 200 μm. It is a thing. The arrangement of the electrode pads was such that two rows exist in parallel with a distance of 0.1 mm, and one more electrode pad exists in parallel on the outer side with a distance of 30 mm.

  The present invention can be used for inspection of electronic devices.

It is a top view which shows one Embodiment of the jig | tool for an electric signal measurement of this invention. It is a schematic sectional drawing of the AA arrow of the electric signal measurement jig | tool shown by FIG. It is a top view which shows other embodiment of the jig | tool for an electrical signal measurement of this invention. It is a schematic sectional drawing of the BB line arrow of the electric signal measurement jig | tool shown by FIG. It is process drawing which shows one Embodiment of the manufacturing method of the jig | tool for an electric signal measurement of this invention. It is process drawing which shows one Embodiment of the manufacturing method of the jig | tool for an electric signal measurement of this invention. It is process drawing which shows one Embodiment of the manufacturing method of the jig | tool for an electric signal measurement of this invention. It is process drawing which shows other embodiment of the manufacturing method of the jig | tool for an electric signal measurement of this invention. It is process drawing which shows other embodiment of the manufacturing method of the jig | tool for an electric signal measurement of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,11 ... Electric signal measuring jig 2,12 ... Silicon substrate 3,13 ... Through hole 4,14 ... Silicon dioxide film 5,15a, 15b, 15c ... Surface side silicon dioxide layer 6,16a, 16b, 16c ... Electrical signal measuring pads 7, 17a, 17b, 17c ... Wiring 8, 18 ... Conductive layer 9, 19 ... Electrode pad 20a, 20b ... Conductive via portion 21a, 21b ... Wiring via portion 52, 62 ... Groove portion 55, 65 ... Base Conductive thin film 57, 67 ... Electrolytic plating part 64 ... Hole for via

Claims (1)

A silicon substrate, a plurality of through holes formed in the silicon substrate, and an insulating film formed at a predetermined portion of the back surface of the silicon substrate including the inner wall surface of the through hole;
Two or more surface-side silicon dioxide layers laminated at a predetermined site on the surface of the silicon substrate, and a surface-side silicon dioxide layer provided with a plurality of wirings embedded so as to form the same surface ;
A conductive material layer filled in the through hole;
A plurality of conductive via portions disposed through the surface-side silicon dioxide layer so as to connect the wiring buried in any surface-side silicon dioxide layer and the desired conductive material layer;
A plurality of electric signal measuring pads which are connected to the wiring embedded in the uppermost surface side silicon dioxide layer and embedded in the same plane as the upper surface side silicon dioxide layer , and the uppermost layer surface A plurality of electrical signal measuring pads that are not connected to the wiring embedded in the side silicon dioxide layer and are embedded in the same plane as the surface side silicon dioxide layer ;
Passing through the surface side silicon dioxide layer so as to connect the electric signal measuring pad not connected to the wiring and the wiring embedded in any one of the surface side silicon dioxide layers lower than the uppermost layer A plurality of wiring via portions disposed; and
A plurality of electrode pads disposed on the back surface of the silicon substrate and connected to each conductive material layer;
The electric signal measuring jig is characterized in that the thickness of the silicon substrate is in the range of 100 to 600 μm and the inner diameter of the through hole is in the range of 10 to 100 μm.

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