JP6250309B2 - Manufacturing method of multilayer wiring board - Google Patents

Description

  The present invention relates to a method for manufacturing a multilayer wiring board, including a core board preparation step for preparing a core substrate, and a wiring laminated portion forming step for forming a wiring substrate laminated portion on both the core main surface and the core back surface. is there.

  In recent years, with the miniaturization of electrical equipment and electronic equipment, miniaturization and high density are demanded for multilayer wiring boards mounted on these equipments. As such a multilayer wiring substrate, for example, a substrate in which a buildup layer having a structure in which a resin insulating layer and a conductor layer are laminated is formed on both surfaces of a core substrate has been put into practical use. Conventionally, various techniques for improving the internal adhesion of the multilayer wiring board have been proposed (see, for example, Patent Documents 1 to 3). Specifically, Patent Document 1 discloses a technique for preventing delamination of a resin insulating layer by providing a dummy metallized layer (dummy electrode) between a low-temperature fired ceramic substrate (core substrate) and the resin insulating layer. Has been proposed. Patent Document 2 proposes a technique for improving adhesion to an insulating sheet (resin insulating layer) by forming dummy conductors (dummy electrodes) on both surfaces of a copper clad laminate (core substrate). ing. Further, Patent Document 3 proposes a technique for roughening the surface of the conductor layer by etching or the like to form fine irregularities and improving the adhesion with the resin insulating layer by an anchor effect obtained by the irregularities. .

Japanese Patent Laying-Open No. 2005-191243 (FIGS. 1-3, etc.) JP 2009-239114 A (FIG. 1 etc.) JP 2000-340948 A (paragraph [0008] etc.)

  Incidentally, in recent years, there has been a demand for further downsizing and higher density of the multilayer wiring board. For example, it is considered that the core board is made of a glass substrate. This is because the glass substrate has high flatness of the core main surface and the core back surface, and therefore has high dimensional accuracy and is advantageous for miniaturization of wiring.

  However, when the core substrate is a glass substrate, the following problems occur when the conventional techniques described in Patent Documents 1 to 3 are employed. That is, when the conventional technique described in Patent Documents 1 and 2 is adopted and a dummy electrode is formed between the core substrate and the resin insulation layer, the core substrate is made of glass that is easily broken, so that the glass portion in the vicinity of the dummy electrode There is a risk of cracking. And since the crack which generate | occur | produced in the glass part is easy to progress, it will cause damage to the core substrate itself, but it is difficult to inspect the crack in the core substrate. In this case, since there is a high possibility that a multilayer wiring board is manufactured using a defective core substrate, there is a problem in that the yield of the multilayer wiring board decreases. In general, cracks can be inspected by ultrasonic flaw detection, but there is a problem in that it is necessary to inspect underwater and the inspection takes time. In addition, when the conventional technique described in Patent Document 3 is adopted, the adhesion between the dummy electrode and the resin insulating layer is improved, but the adhesion of the resin to the smooth glass is small, so that the build-up layer is being formed. In addition, there is a high possibility that the resin insulating layer gradually peels from the core substrate. From the above, there is a problem that the predetermined reliability required for the multilayer wiring board cannot be imparted.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a method for manufacturing a multilayer wiring board capable of manufacturing a multilayer wiring board with excellent reliability by improving yield. There is.

As means (means 1) for solving the above-mentioned problems, a plurality of through-holes having a core main surface and a core back surface that are open at both the core main surface and the core back surface are formed. A core substrate preparation step of preparing a core substrate including an inorganic material having, and a wiring laminate portion having a structure in which a resin insulating layer and a conductor layer are laminated after the core substrate preparation step, on the core main surface and the core back surface In the manufacturing method of the multilayer wiring board including the wiring laminated portion forming step formed on both, the dummy electrode is disposed on the core main surface and the core back surface after the core substrate preparing step and before the wiring laminated portion forming step. in both above through the core substrate subjected to the dummy electrode formation step of forming so as to face each other, in the dummy electrode formation step, the conductor posts is formed in the through-hole, with respect to the core main surface When forming the main surface side surface electrode electrically connected to the conductor pillar and simultaneously forming the dummy electrode, and forming the back surface surface electrode electrically connected to the conductor pillar on the back surface of the core At the same time, the dummy electrode is formed, and in the wiring laminated portion forming step, at least one resin insulating layer is laminated on both the core main surface and the core back surface, The capacitance between the dummy electrode and the dummy electrode on the back side of the core is measured, and the main surface side opening for exposing the main surface side surface electrode is formed in the dummy electrode on the core main surface side, A back side opening that exposes the back side surface electrode is formed in the dummy electrode on the core back side, and a shape of the main surface side surface electrode in plan view is a shape of the main surface side surface electrode in plan view And the back side Plan view of the shape of the opening, it is a method for manufacturing a multilayer wiring board, characterized in that a shape and similar shape in plan view of the back side surface electrode.

  Therefore, according to the invention described in the means 1, by performing the dummy electrode forming step, the contact area between the dummy electrode formed on the core substrate and the resin insulating layer is increased, and the adhesion between the core substrate and the resin insulating layer is increased. Therefore, peeling (delamination) of the resin insulating layer hardly occurs. Further, in the wiring laminated portion forming step, by measuring the capacitance between the dummy electrode on the core main surface side and the dummy electrode on the core back surface side, a defect (specifically, based on the obtained measurement value) It is possible to detect whether or not the dummy electrode is peeled off or cracks are generated in the core substrate. Therefore, the problem that the multilayer wiring substrate is manufactured using the defective core substrate is prevented in advance, and the yield of the multilayer wiring substrate can be improved. From the above, a multilayer wiring board with excellent reliability can be manufactured.

  Hereinafter, a method for manufacturing a multilayer wiring board will be described.

  In the core substrate preparation step, a core substrate having a core main surface and a core back surface and including an insulating inorganic material is prepared by a conventionally known technique and prepared in advance. The material for forming the core substrate is not particularly limited as long as it is an insulating material, and can be appropriately selected in consideration of cost, workability, mechanical strength, and the like. Therefore, examples of the core substrate include a ceramic substrate and a glass substrate. As a material for forming the ceramic substrate, low-temperature fired glass ceramic, glass ceramic, or the like is preferably used. Further, borosilicate glass, low-temperature fired glass ceramic, glass ceramic or the like is preferably used as a material for forming the glass substrate. If the core substrate is a glass substrate made of glass having excellent insulating properties and smoothness, through-holes can be formed in the core substrate at a narrower pitch than when the core substrate is, for example, a resin substrate. The degree of freedom of the wiring provided in is increased. In addition, the contact area between the smooth glass (core substrate) and the resin (resin insulating layer) decreases as the dummy electrode is formed in the dummy electrode forming step described later, and therefore the resin insulating layer is less likely to be peeled off. .

  Here, the thickness of the core substrate is not particularly limited, but may be, for example, 10 μm or more and 400 μm or less. If the thickness of the core substrate is less than 10 μm, the core substrate becomes too thin, so that the strength of the core substrate may be reduced and damaged. On the other hand, when the thickness of the core substrate is larger than 400 μm, even if the capacitance is measured in the wiring laminated portion forming step, the measured capacitance is reduced, and the measured value when the dummy electrode is peeled off. Therefore, it becomes difficult to determine pass / fail based on the measured value.

  In the subsequent wiring laminated portion forming step, a wiring laminated portion having a structure in which a resin insulating layer and a conductor layer are laminated is formed on both the core main surface and the core back surface. The resin insulation layer can be appropriately selected in consideration of insulation, heat resistance, moisture resistance, and the like. Preferred examples of the polymer material for forming the resin insulation layer include thermosetting resins such as epoxy resin, phenol resin, urethane resin, silicone resin, polyimide resin, polycarbonate resin, acrylic resin, polyacetal resin, polypropylene resin, etc. And other thermoplastic resins. The conductor layer is mainly made of copper and is formed by a known method such as a subtractive method, a semi-additive method, or a full additive method.

  In addition, after the core substrate preparation step and before the wiring laminated portion formation step, a dummy electrode formation step is performed in which dummy electrodes are formed to face each other via the core substrate on both the core main surface and the core back surface. Here, the “dummy electrode” is formed of a conductor, but basically does not function as an electrode, and is not electrically and physically connected to other electrodes. The dummy electrode is mainly made of copper, and is formed by a known method such as a subtractive method, a semi-additive method, or a full additive method. Specifically, for example, techniques such as etching of copper foil, electroless copper plating, or electrolytic copper plating are applied. Note that a dummy electrode can be formed by etching after forming a thin film by a technique such as sputtering or CVD, or a dummy electrode can be formed by printing a conductive paste or the like.

  Here, the proportion of the dummy electrode in at least one of the core main surface and the core back surface is preferably 50% or more and 98% or less. If the proportion of the dummy electrode is less than 50%, the contact area between the core substrate and the resin insulating layer becomes large. Therefore, particularly when the core substrate is a smooth glass substrate, the resin insulating layer is peeled off. It becomes easy. Moreover, even if the capacitance is measured in the wiring layer forming step, the measured capacitance becomes small, and the measured value changes slightly when the dummy electrode is peeled off. It becomes difficult to judge pass / fail. On the other hand, when the proportion occupied by the dummy electrode is greater than 98%, the core substrate is provided with conductor columns penetrating the core main surface and the core back surface, and the core main surface and the core back surface are electrically connected to the conductor columns. When the electrode is formed, the gap between the dummy electrode and the surface electrode becomes small, which may cause a short circuit.

  Furthermore, in the dummy electrode forming step, the dummy electrode is preferably formed so as to cover at least one of the entire outer peripheral portion of the core main surface and the entire outer peripheral portion of the core back surface. In addition, peeling of the resin insulating layer is most likely to occur at the outer peripheral portion of the core substrate. Further, when a multilayer wiring board is manufactured, an impact is often applied to the side surface (core side surface) of the core substrate. Therefore, if the entire outer periphery of the core main surface and the entire outer periphery of the core back surface are covered with dummy electrodes, it is possible to prevent peeling of the resin insulation layer and damage to the core substrate during manufacturing. Can be improved.

  Further, in the wiring laminated portion forming step, the dummy electrode on the core main surface side and the dummy electrode on the core back surface side are formed in a state where at least one resin insulating layer is laminated on both the core main surface and the core back surface. Measure the capacitance between. A multilayer wiring board is manufactured through the above processes.

  In addition, the wiring laminated portion forming step is for measurement in which at least one resin insulating layer is laminated on both the core main surface and the core back surface, and the resin insulating layer is electrically connected to the dummy electrode. Including a measurement wiring formation process for forming a wiring, and after the measurement wiring formation process, the inspection jig was brought into contact with both the measurement wiring on the core main surface side and the measurement wiring on the core back surface side. In the state, the capacitance may be measured. In this case, since the capacitance is measured by bringing the inspection jig into contact with the measurement wiring formed separately from the dummy electrode, the defect is reliably detected based on the obtained measurement value. be able to.

  Further, after measuring the capacitance, the measurement wiring may be electrically connected to a power supply wiring or a ground wiring provided in the wiring laminated portion. In this way, the measurement wiring can be effectively used in the completed multilayer wiring board.

1 is a schematic cross-sectional view showing a multilayer wiring board in the present embodiment. The schematic plan view which shows the core board | substrate with which the dummy electrode was formed. Explanatory drawing which shows the manufacturing method of a multilayer wiring board. Explanatory drawing which shows the manufacturing method of a multilayer wiring board. Explanatory drawing which shows the manufacturing method of a multilayer wiring board. Explanatory drawing which shows the manufacturing method of a multilayer wiring board. Explanatory drawing which shows the manufacturing method of a multilayer wiring board. The schematic plan view which shows the core board | substrate with which the dummy electrode was formed in other embodiment. The schematic plan view which shows the core board | substrate with which the dummy electrode was formed in other embodiment. The schematic plan view which shows the core board | substrate with which the dummy electrode was formed in other embodiment.

  Hereinafter, an embodiment embodying the multilayer wiring board 10 of the present invention will be described in detail with reference to the drawings.

  As shown in FIG. 1, the multilayer wiring board 10 of the present embodiment is a glass interposer (glass relay board) for mounting an IC chip. The multilayer wiring substrate 10 includes a substantially rectangular plate-shaped core substrate 11, a main surface side buildup layer 31 (wiring laminated portion) formed on the core main surface 12 (upper surface in FIG. 1) of the core substrate 11, a core The back surface side buildup layer 32 (wiring lamination | stacking part) formed on the core back surface 13 (FIG. 1 lower surface) of the board | substrate 11 consists of.

  As shown in FIGS. 1 and 2, the core substrate 11 has one core main surface 12, one core back surface 13, and four core side surfaces 14, and has a substantially rectangular plate shape. The core substrate 11 of this embodiment is a glass substrate made of an insulating inorganic material (in this embodiment, borosilicate glass). The size of the core substrate 11 is set to 10 mm long × 10 mm wide. The thickness of the core substrate 11 is set to 10 μm or more and 400 μm or less (100 μm in this embodiment). In this embodiment, the thermal expansion coefficient of the core substrate 11 is less than 15 ppm / ° C., specifically about 4 to 5 ppm / ° C. In addition, the thermal expansion coefficient of the core board | substrate 11 says the average value of the measured value between 30 degreeC-400 degreeC.

  The core substrate 11 is formed with a plurality of through-holes 15 that are opened in both the core main surface 12 and the core back surface 13 in a lattice shape. Each through-hole 15 has a circular shape in plan view, and has both tapered shapes in which the inner diameter gradually increases toward the core main surface 12 side and the core back surface 13 side. In the through hole 15, a conductor column 16 made of copper is provided. In the present embodiment, for convenience of explanation, the conductor pillars 16 are illustrated in 3 rows × 3 rows, but actually there are more rows (specifically, 10 rows × 10 rows). Further, the distance (pitch) between the centers of the adjacent conductor columns 16 is set to 400 μm.

  As shown in FIG. 1 and FIG. 2, a plurality of main surface side surface electrodes 21 having a circular shape in plan view are arranged on the core main surface 12 of the core substrate 11 vertically and horizontally along the surface direction of the core main surface 12. On the core back surface 13 of the core substrate 11, a plurality of back surface electrodes 22 having a circular shape in plan view are arranged vertically and horizontally along the surface direction of the core back surface 13. Each surface electrode 21, 22 is electrically connected to the conductor column 16. The outer diameters of the surface electrodes 21 and 22 are set to be larger (150 μm in this embodiment) than the maximum diameter (100 μm in the present embodiment) of the conductor column 16. Moreover, the thickness of each surface electrode 21 and 22 in this embodiment is set to 10 micrometers.

  Further, a dummy electrode 51 made of copper having a thickness of 10 μm is formed on the core main surface 12 of the core substrate 11, and a dummy electrode made of copper having a thickness of 10 μm is also formed on the core back surface 13 of the core substrate 11. 52 is patterned. The dummy electrode 51 and the dummy electrode 52 are arranged to face each other with the core substrate 11 interposed therebetween. More specifically, the dummy electrode 51 covers the entire core main surface 12, and particularly covers the entire outer peripheral portion of the core main surface 12. Similarly, the dummy electrode 52 substantially entirely covers the core back surface 13, and particularly covers the entire outer peripheral portion of the core back surface 13. The ratio of the dummy electrode 51 in the core main surface 12 and the ratio of the dummy electrode 52 in the core back surface 13 are both 96.9%.

  As shown in FIGS. 1 and 2, the dummy electrode 51 has a plurality of main surface side openings 53 exposing the main surface side surface electrode 21, and the dummy electrode 52 has the back surface side surface electrode 22. A plurality of back side openings 54 to be exposed are formed. The openings 53 and 54 have a circular shape in a plan view, and the inner diameter is set to 200 μm. Therefore, the shape of the openings 53 and 54 in plan view is similar to the shape of the surface electrodes 21 and 22 in plan view. The main surface side surface electrode 21 is disposed in the main surface side opening 53 so that the outer surface faces the inner surface of the main surface side opening 53, and the rear surface side electrode 22 has an outer surface on the back surface side opening. It arrange | positions in the back surface side opening part 54 so that the inner surface of the part 54 may be faced. The size of the gap between the outer surface of the main surface side surface electrode 21 and the inner surface of the main surface side opening 53 (25 μm in this embodiment) is uniform. The size of the gap (25 μm in this embodiment) with the inner side surface of the back side opening 54 is uniform. That is, the dummy electrodes 51 and 52 are electrically independent from the surface electrodes 21 and 22.

  As shown in FIG. 1, the main surface side buildup layer 31 includes two resin insulating layers 33 and 35 made of a thermosetting resin (epoxy resin) having a thickness of 17.5 μm, and a conductor layer 41 made of copper. , 42 are laminated. In the present embodiment, the thermal expansion coefficient of the resin insulating layers 33 and 35 in the fully cured state is about 10 to 60 ppm / ° C., specifically 46 ppm / ° C. In addition, the thermal expansion coefficient in the completely cured state of the resin insulating layers 33 and 35 is an average value of measured values between 25 ° C. and 150 ° C. In the resin insulating layers 33 and 35, via conductors 43 formed by copper plating are provided. Further, the surface of the resin insulating layer 35 is almost entirely covered with a solder resist 37. An opening 46 for exposing the conductor layer 42 is formed at a predetermined position of the solder resist 37. A plurality of solder bumps 45 are provided on the surface of the conductor layer 42.

  As shown in FIG. 1, measurement wirings 61 that are electrically connected to the dummy electrode 51 on the core main surface 12 side are provided in a plurality of locations in the main surface side buildup layer 31. Each measurement wiring 61 includes a measurement via conductor 62 and a measurement conductor layer 63. The measurement via conductor 62 is formed by copper plating, is provided in the resin insulating layer 33, and is connected to the surface of the dummy electrode 51. The measurement conductor layer 63 is made of copper, is formed on the surface of the resin insulating layer 33, and is electrically connected to the end face of the measurement via conductor 62.

  Each solder bump 45 is electrically connected to a surface connection terminal of an IC chip (semiconductor integrated circuit element). The IC chip of this embodiment is a plate-like object having a rectangular shape in plan view of 12.0 mm long × 12.0 mm wide × 0.9 mm thick, and has a thermal expansion coefficient of about 3 to 4 ppm / ° C. (specifically (About 3.5 ppm / ° C.).

  As shown in FIG. 1, the back surface side buildup layer 32 has substantially the same structure as the main surface side buildup layer 31 described above. That is, the back-side buildup layer 32 has a structure in which two resin insulating layers 34 and 36 made of a thermosetting resin (epoxy resin) having a thickness of 17.5 μm and conductor layers 41 and 42 made of copper are laminated. have. In the present embodiment, the thermal expansion coefficient of the resin insulating layers 34 and 36 in a completely cured state is about 10 to 60 ppm / ° C., specifically 46 ppm / ° C. In addition, the thermal expansion coefficient in the completely cured state of the resin insulating layers 34 and 36 is an average value of measured values between 25 ° C. and 150 ° C. Further, via conductors 47 formed by copper plating are provided in the resin insulating layers 34 and 36, respectively. Further, the lower surface of the resin insulating layer 36 is almost entirely covered with a solder resist 38. An opening 48 that exposes the conductor layer 42 disposed on the lower surface of the resin insulating layer 36 is formed at a predetermined location of the solder resist 38. On the surface of the conductor layer 42, a plurality of solder bumps 49 are provided for electrical connection with a mother board (not shown).

  As shown in FIG. 1, measurement wirings 71 that are electrically connected to the dummy electrode 52 on the core back surface 13 side are provided in a plurality of locations in the back surface side buildup layer 32. Each measurement wiring 71 includes a measurement via conductor 72 and a measurement conductor layer 73. The measurement via conductor 72 is formed by copper plating, is provided in the resin insulating layer 34, and is connected to the surface of the dummy electrode 52. The measurement conductor layer 73 is made of copper, is formed on the surface of the resin insulating layer 34, and is electrically connected to the end face of the measurement via conductor 72.

  Next, the manufacturing method of the multilayer wiring board 10 of this embodiment is demonstrated.

  First, in the core substrate preparation step, the core substrate 11 is prepared by a conventionally known technique and prepared in advance (see FIG. 3). In the core substrate preparation step of this embodiment, a multi-piece core substrate is prepared in which a plurality of substrate formation regions to be the core substrate 11 are arranged vertically and horizontally along the plane direction.

  The core substrate 11 is manufactured as follows. First, a commercially available thin glass substrate (OA-10G manufactured by Nippon Electric Glass Co., Ltd.) is prepared. Next, a large number of through holes 15 are formed through the thin glass substrate by a known method such as laser irradiation, drilling, sandblasting, etc. (see FIG. 4). Further, titanium (Ti) is sputtered from the core main surface 12 side to form a titanium layer, and is formed on the titanium layer formed on the core main surface 12 and the inner surface of the through hole 15 on the core main surface 12 side. The titanium layer is a continuous layer without being divided. Further, sputtering of titanium is performed from the core back surface 13 side to form a titanium layer, and the titanium layer formed on the core back surface 13 and the titanium layer formed on the inner surface of the through hole 15 on the core back surface 13 side, It is a continuous layer without being divided. Further, copper (Cu) is sputtered from the core main surface 12 side and the core back surface 13 side to form a copper layer on the titanium layer.

  Further, a dummy electrode forming step is performed after the core substrate preparation step and before the wiring laminated portion forming step, which will be described later, to form the dummy electrode 51 on the core main surface 12 and the dummy electrode 52 on the core back surface 13 ( (See FIG. 5). Specifically, a dry film is laminated on each of the core main surface 12 and the core back surface 13 on which the titanium layer and the copper layer are formed to form a plating resist (not shown). Next, after patterning by photolithography, the surface of the copper layer formed on the inner surface of the through hole 15, the surface of the copper layer formed on the core main surface 12, and the copper formed on the core back surface 13 Electrolytic copper plating is performed on the surface of each layer. At this time, the conductor pillar 16 is formed in the through hole 15, the dummy electrode 51 is formed on the core main surface 12 simultaneously with the main surface side surface electrode 21, and the dummy electrode 52 is formed on the back surface side of the core back surface 13. It is formed simultaneously with the surface electrode 22 (see FIG. 5). Thereafter, the plating resist is peeled off, and the titanium layer and the copper layer protected by the plating resist are removed by etching. In addition, when forming a conductor pillar in the green sheet | seat of glass ceramic, after forming a copper layer, it fills in each through-hole 15 with the copper paste for conductor pillars using the paste press injection filling apparatus which is not shown in figure. Thereafter, the green sheet is dried to solidify the green sheet to some extent. Next, the green sheet is degreased and further fired at a predetermined temperature for a predetermined time. As a result, the glass ceramic and the copper in the paste are simultaneously sintered to form a core substrate on which a plurality of conductive pillars are formed.

  The dummy electrodes 51 and 52 may be formed by another method. More specifically, electrolytic copper plating is performed on the surface of the copper layer formed on the core main surface 12 and the surface of the copper layer formed on the core back surface 13 without forming a plating resist. At this point, a solid pattern covering the entire core main surface 12 is formed, and a solid pattern covering the entire core back surface 13 is formed. Thereafter, patterning is performed by a subtractive method. Specifically, a dry film is laminated on the core main surface 12 and the core back surface 13, and an etching resist having a predetermined pattern is formed by exposing and developing the dry film. In this state, patterning by etching is performed on the solid pattern on the core main surface 12 side and the core back surface 13 side. At this time, the dummy electrode 51 and the main surface side surface electrode 21 are formed on the core main surface 12, and the dummy electrode 52 and the back surface electrode 22 are formed on the core back surface 13 (see FIG. 5). Thereafter, the etching resist is peeled off.

  In the subsequent wiring laminated portion forming step, the main surface side buildup layer 31 is formed on the core main surface 12 and the back surface side buildup layer 32 is formed on the core back surface 13 based on a conventionally known technique (FIG. 6, see FIG. Specifically, first, a resin insulating layer 33 is formed by depositing (attaching) a thermosetting epoxy resin having a thickness of 17.5 μm on the core main surface 12. Also, a resin insulation layer 34 is formed by depositing (attaching) a thermosetting epoxy resin having a thickness of 17.5 μm on the core back surface 13. Instead of depositing a thermosetting epoxy resin, a photosensitive epoxy resin, an insulating resin, or a liquid crystal polymer (LCP) may be deposited.

  The wiring laminated portion forming process includes a measurement wiring forming process and an inspection process. In the measurement wiring formation step, the measurement wiring 61 is formed on the resin insulation layer 33 in a state where the resin insulation layer 33 is laminated on the core main surface 12, and the resin insulation layer of one layer is formed on the core back surface 13. With the layer 34 laminated, the measurement wiring 71 is formed on the resin insulating layer 34. More specifically, laser drilling is performed using a YAG laser or a carbon dioxide gas laser to form via holes at positions where the via conductors 43 and 47 and the measurement via conductors 62 and 72 are to be formed. Specifically, a via hole penetrating the resin insulating layer 33 is formed, and the surface of the main surface side surface electrode 21 and the surface of the dummy electrode 51 are exposed. In addition, a via hole penetrating the resin insulating layer 34 is formed to expose the surface of the back surface electrode 22 and the surface of the dummy electrode 52. Next, electrolytic copper plating is performed according to a conventionally known method to form via conductors 43 and 47 and measurement via conductors 62 and 72 inside the via holes, and the conductor layer 41 and the measurement on the resin insulating layers 33 and 34. Conductor layers 63 and 73 are formed. At this point, the measurement wiring 61 composed of the measurement via conductor 62 and the measurement conductor layer 63 and the measurement wiring 71 composed of the measurement via conductor 72 and the measurement conductor layer 73 are formed (see FIG. 6). .

  In the inspection process performed after the measurement wiring formation process, the probe 64 (inspection jig) is brought into contact with the measurement conductor layer 63 on the core main surface 12 side, and the measurement conductor layer 73 on the core back surface 13 side. A probe 74 (inspection jig) is brought into contact with (see FIG. 6). In this state, the capacitance between the dummy electrode 51 on the core main surface 12 side and the dummy electrode 52 on the core back surface 13 side is measured. And the quality is determined based on the measured value obtained by measuring the capacitance. Specifically, when the obtained measurement value is within the range of the measurement value (reference value) when the dummy electrodes 51 and 52 are not peeled off, it is determined that there is no defect in the core substrate 11. (Good). On the other hand, when the obtained measurement value is lower than the range of the reference value, it is determined that the core substrate 11 is defective (No).

  After the inspection process, a thermosetting epoxy resin having a thickness of 17.5 μm is deposited on the resin insulation layers 33 and 34 to form the resin insulation layers 35 and 36. Instead of depositing the thermosetting epoxy resin, a photosensitive epoxy resin, an insulating resin, or a liquid crystal polymer may be deposited. In this case, via holes are formed in the resin insulating layers 35 and 36 at positions where the via conductors 43 and 47 are to be formed by a laser processing machine or the like. Next, electrolytic copper plating is performed in accordance with a conventionally known technique to form via conductors 43 and 47 in the via holes of the resin insulating layers 35 and 36 and to form a conductor layer 42 on the resin insulating layers 35 and 36. At this point, the buildup layers 31 and 32 shown in FIG. 7 are completed.

  After the wiring laminated portion forming step, a solder resist 37, 38 is formed by applying and curing a photosensitive epoxy resin on the resin insulating layers 35, 36. Next, exposure and development are performed with a predetermined mask placed, and the openings 46 and 48 are patterned in the solder resists 37 and 38.

  Further, a solder paste is printed on the conductor layer 42 formed on the resin insulating layer 35. A solder paste is printed on the conductor layer 42 formed on the resin insulating layer 36. Next, the multi-chip substrate on which the solder paste is printed is placed in a reflow furnace and heated to a temperature 10 to 40 ° C. higher than the melting point of the solder. At this time, the solder paste is melted to form the IC chip mounting solder bumps 45 having a hemispherical shape, and the motherboard mounting solder bumps 49 having the same hemispherical shape are formed. .

  Further, the substrate forming regions are divided by cutting the multi-piece substrate along the outline of the substrate forming region using a conventionally known cutting device (laser processing machine, dicing device, etc.). A plurality of multilayer wiring boards 10 can be obtained simultaneously.

  Thereafter, an IC chip is placed on the surface of the main surface side buildup layer 31 constituting the multilayer wiring board 10. At this time, the surface connection terminals on the IC chip side and the solder bumps 45 are aligned. Then, each solder bump 45 is reflowed by heating to a temperature of about 220 to 240 ° C., whereby each solder bump 45 and the surface connection terminal are joined, and the multilayer wiring board 10 side and the IC chip side are electrically connected. Connecting. As a result, an IC chip is mounted on the multilayer wiring board 10.

  Therefore, according to the present embodiment, the following effects can be obtained.

  (1) According to the method for manufacturing the multilayer wiring board 10 of the present embodiment, the contact area between the dummy electrodes 51 and 52 formed on the core substrate 11 and the resin insulating layers 33 and 34 by performing the dummy electrode forming step. And the adhesion between the core substrate 11 and the resin insulation layers 33 and 34 is improved, and therefore the resin insulation layers 33 and 34 are less likely to be peeled off (delamination). Further, in the wiring laminated portion forming process (inspection process), the measured value obtained by measuring the capacitance between the dummy electrode 51 on the core main surface 12 side and the dummy electrode 52 on the core back surface 13 side is obtained. Based on this, it is possible to know whether or not a defect (specifically, peeling of the dummy electrodes 51 and 52 or occurrence of a crack in the core substrate 11) has occurred. Therefore, since the problem that the multilayer wiring board 10 is manufactured using the defective core substrate 11 is prevented in advance, the yield of the multilayer wiring board 10 can be improved. From the above, the multilayer wiring board 10 having excellent reliability can be manufactured.

  (2) In this embodiment, since the dummy electrode 51 is formed on the core main surface 12 and the dummy electrode 52 is formed on the core back surface 13, the rigidity of the core substrate 11 is increased. Improved handling. That is, when the multilayer wiring substrate 10 is manufactured, the core substrate 11 is less likely to be damaged when the core substrate 11 is transported from the previous process to the subsequent process.

  (3) In the present embodiment, the through holes 15 provided in the core substrate 11 have both tapered shapes in which the inner diameter gradually increases toward the substrate main surface 12 side and the core back surface 13 side. For this reason, the inner side surface of the through-hole 15 is not a surface perpendicular to the core main surface 12 and the core back surface 13 but is a surface inclined with respect to the core main surface 12 and the core back surface 13. As a result, when sputtering of titanium or copper, which is an anisotropic thin film forming method, is performed from the core main surface 12 side and the core back surface 13 side, titanium and copper are easily attached to the inner side surface of the through hole 15. Moreover, the conductive pillar 16 can be formed efficiently and reliably by filling the plating. Therefore, since the conduction by the conductor pillar 16 can be reliably ensured, the multilayer wiring board 10 with even higher reliability can be manufactured.

  (4) The IC chip of the present embodiment is disposed immediately above the core substrate 11. As a result, the conduction path for electrically connecting the IC chip and the core substrate 11 is the shortest. Therefore, it is possible to smoothly supply power to the IC chip. In addition, since noise entering between the IC chip and the core substrate 11 can be suppressed to a very low level, high reliability can be obtained without causing malfunction such as malfunction.

  In addition, the IC chip is supported by a glass substrate (core substrate 11) that is highly rigid, has a smaller thermal expansion coefficient than the resin insulating layers 33 to 36, and has a thermal expansion coefficient close to that of the IC chip. Therefore, since the core substrate 11 becomes difficult to deform, the IC chip mounted on the core substrate 11 can be supported more stably. Therefore, it is possible to prevent IC chip cracks and poor connections due to large thermal stress. Therefore, as an IC chip, a large IC chip of 10 mm square or more is considered to be brittle because stress (strain) due to a difference in thermal expansion is large and the influence of the thermal stress is large, and the heat generation is large and the thermal shock during use is severe. A low-k (low dielectric constant) IC chip can be used.

  In addition, you may change this embodiment as follows.

  In the embodiment described above, the measurement wiring electrically connected to the dummy electrodes 51 and 52 in a state where the resin insulating layers 33 and 34 are laminated on both the core main surface 12 and the core back surface 13 respectively. 61 and 71 were formed, and the capacitance was measured in a state where the probes 64 and 74 were brought into contact with both of the measurement wires 61 and 71, respectively. However, the measurement wirings 61 and 71 are formed in a state in which two or more resin insulation layers are laminated on the core main surface 12 and the core back surface 13, and the probes 64 are respectively connected to both the measurement wirings 61 and 71. , 74 may be in contact with each other, and the capacitance may be measured. In addition, before the resin insulating layer is laminated on the core main surface 12 and the core back surface 13, the probes 64 and 74 are brought into direct contact with the dummy electrodes 51 and 52, and the capacitance is measured in this state. You may do it.

  In the core substrate 11 of the above embodiment, the dummy electrodes 51 and 52 are formed to be a solid pattern (wide area pattern) having openings 53 and 54 for avoiding the surface electrodes 21 and 22. The shape of the dummy electrode may be changed as appropriate. For example, as shown in the core substrate 111 of FIG. 8, the dummy electrode 114 has a rectangular opening 113 in a plan view in which all the surface electrodes 112 are arranged, and has a rectangular frame shape in a plan view. There may be. The ratio of the dummy electrode 114 in the core main surface 115 (and the core back surface) is preferably 50% or more and 98% or less. For example, the ratio of the dummy electrode 114 in the core main surface 115 may be set to 64% by setting the width of the dummy electrode 114 to 2 mm. Further, by setting the width of the dummy electrode 114 to 1.5 mm, the ratio of the dummy electrode 114 in the core main surface 115 may be 51%.

  In the core substrate 11 of the above embodiment, the dummy electrode 51 is formed so as to cover the entire outer periphery of the core main surface 12, and the dummy electrode 52 is formed so as to cover the entire outer periphery of the core back surface 13. However, as shown in the core substrate 121 in FIG. 9, the dummy electrode 122 may be formed so as to cover only the central portion of the core main surface 123 without covering the outer peripheral portion of the core main surface 123. The ratio of the dummy electrode 122 in the core main surface 123 (and the core back surface) is preferably 50% or more and 98% or less. For example, the dummy electrode 122 may be formed in a rectangular shape in plan view of 8 mm in length × 8 mm in width so that the ratio of the dummy electrode 122 in the core main surface 123 may be 60.9%.

  In the core substrate 11 of the above embodiment, the shapes of the openings 53 and 54 of the dummy electrodes 51 and 52 (circular shape in plan view) and the shapes of the surface electrodes 21 and 22 (circular shape in plan view) are equal to each other. However, the shape of the opening of the dummy electrode and the shape of the surface electrode may be different from each other. For example, as shown in the core substrate 131 in FIG. 10, the opening 133 of the dummy electrode 132 may have a rectangular shape in plan view, and the surface electrode 134 may have a circular shape in plan view.

  In the above embodiment, after the capacitance is measured in the inspection process, the measurement wires 61 and 71 are connected to power supply wires (not shown) or ground wires (not shown) provided in the buildup layers 31 and 32, respectively. You may make it connect electrically. In this way, the measurement wirings 61 and 71 can be used effectively in the completed multilayer wiring board 10.

  In the above embodiment, the through holes 15 provided in the core substrate 11 have both tapered shapes in which the inner diameter gradually increases toward the core main surface 12 side and the core back surface 13 side. A single taper shape in which the inner diameter gradually increases toward the 12 side or the core back surface 13 side may be used. Note that the through hole does not have to be tapered.

  Next, the technical ideas grasped by the embodiment described above are listed below.

  (1) In the said means 1, the ratio for which the said dummy electrode occupies in at least one of the said core main surface and the said core back surface is 50% or more and 98% or less, The manufacturing method of the multilayer wiring board characterized by the above-mentioned.

  (2) In the above means 1, a titanium layer is formed by sputtering titanium after the core substrate preparation step and before the dummy electrode formation step, thereby forming a titanium layer on the core main surface and the core back surface. And a copper layer forming step of forming a copper layer on the titanium layer by performing copper sputtering, and in the dummy electrode forming step, the dummy electrode is formed on the surface of the copper layer. A method for manufacturing a multilayer wiring board.

  (3) In the above means 1, in the dummy electrode forming step, the dummy electrode is formed simultaneously with the formation of the main surface side surface electrode electrically connected to the conductor layer on the core main surface. A method for manufacturing a multilayer wiring board, comprising forming a back surface side surface electrode electrically connected to the conductor layer simultaneously with forming the dummy electrode on the back surface of the core.

DESCRIPTION OF SYMBOLS 10 ... Multilayer wiring board 11, 111, 121, 131 ... Core board | substrate 12, 115, 123 ... Core main surface 13 ... Core back surface 31 ... Main surface side buildup layer 32 as a wiring lamination part ... Back surface side as a wiring lamination part Build-up layers 33, 34, 35, 36 ... resin insulating layers 41,42 ... conductor layers 51,52,114,122,132 ... dummy electrodes 61,71 ... measurement wires 64,74 ... probes as inspection jigs

Claims (5)

A core substrate preparing step of preparing a core substrate including an inorganic material having an insulating property, wherein the core substrate includes a core main surface and a core back surface, and a plurality of through holes that are open on both the core main surface and the core back surface are formed; ,
A multilayer wiring board including a wiring laminated portion forming step of forming a wiring laminated portion having a structure in which a resin insulating layer and a conductor layer are laminated after the core substrate preparation step on both the core main surface and the core back surface In the manufacturing method of
A dummy electrode forming step of forming a dummy electrode so as to face each other through the core substrate on both the core main surface and the core back surface after the core substrate preparation step and before the wiring laminated portion forming step. Done
In the dummy electrode forming step, a conductor column is formed in the through hole, and a main surface side surface electrode electrically connected to the conductor column is formed simultaneously with the core main surface, and the dummy electrode is formed at the same time And, with respect to the core back surface, forming the back surface side surface electrode electrically connected to the conductor pillar and simultaneously forming the dummy electrode,
In the wiring laminated portion forming step, in the state where at least one resin insulating layer is laminated on both the core main surface and the core back surface, the core main surface side dummy electrode and the core back surface side measuring the capacitance between the dummy electrode,
A main surface side opening that exposes the main surface side surface electrode is formed in the dummy electrode on the core main surface side, and a back surface side opening that exposes the back surface side surface electrode to the dummy electrode on the core back surface side. Part is formed,
The shape in plan view of the main surface side opening is similar to the shape in plan view of the main surface side surface electrode, and the shape in plan view of the back surface side opening is in plan view of the back surface electrode. A method of manufacturing a multilayer wiring board, characterized in that it is similar in shape to the above . In the wiring laminated portion forming step, at least one resin insulating layer is laminated on both the core main surface and the core back surface, and the resin insulating layer is electrically connected to the dummy electrode. Including a measurement wiring forming step of forming a measurement wiring to be performed,
After the measurement wiring formation step, the capacitance is measured in a state where the inspection jig is in contact with both the measurement wiring on the core main surface side and the measurement wiring on the core back surface side. The method for manufacturing a multilayer wiring board according to claim 1.   3. The multilayer wiring board according to claim 2, wherein after the capacitance is measured, the measurement wiring is electrically connected to a power supply wiring or a ground wiring provided in the wiring laminated portion. Method.   4. The dummy electrode forming step according to claim 1, wherein the dummy electrode is formed so as to cover at least one of the entire outer peripheral portion of the core main surface and the entire outer peripheral portion of the core back surface. 2. A method for producing a multilayer wiring board according to item 1.   The method for manufacturing a multilayer wiring board according to claim 1, wherein the core substrate is a glass substrate.

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