JP6301595B2 - Wiring board and method for manufacturing multilayer wiring board - Google Patents

Description

  The present invention is a wiring board comprising a substrate body, a via conductor and a land, a substrate body preparation step for preparing the substrate body, a via conductor formation step for forming a via conductor, a land formation step for forming a land, The present invention relates to a method for manufacturing a multilayer wiring board including a wiring laminated portion forming step for forming a wiring laminated portion.

  In recent years, with the miniaturization of electrical equipment and electronic equipment, miniaturization and high density are demanded for multilayer wiring boards mounted on these equipments. As such a multilayer wiring substrate, for example, a substrate in which a buildup layer having a structure in which a resin insulating layer and a conductor layer are laminated is formed on both surfaces of a core substrate has been put into practical use. Conventionally, various techniques for detecting defects such as cracks have been proposed in order to improve reliability (see, for example, Patent Documents 1 and 2). Specifically, Patent Document 1 discloses a technique for detecting cracks and chips generated in a semiconductor integrated circuit element using inspection wiring (conductor pattern) provided on the outer periphery of the surface of the semiconductor integrated circuit element. Proposed. Patent Document 2 discloses a technique for detecting a crack generated in a process of dividing a multi-chip substrate into individual wiring boards using inspection wiring (wiring patterns) provided on the outer periphery of the surface of the wiring board. Has been proposed.

JP-A-6-244254 (FIG. 1 etc.) Japanese Patent Laying-Open No. 2005-347651 (FIG. 2 etc.)

  Incidentally, in recent years, there has been a demand for further downsizing and higher density of the multilayer wiring board. For example, it is considered that the core board is made of a glass substrate. This is because the glass substrate has high flatness on the main surface and the back surface of the substrate, and therefore has high dimensional accuracy and is advantageous for miniaturization of wiring.

  However, when the core substrate is a glass substrate, the following problems occur when the conventional techniques described in Patent Documents 1 and 2 are adopted. That is, when the core substrate is provided with through holes that open on the main surface and the back surface of the substrate, and via conductors are formed in the through holes, the core substrate is made of glass that is easily broken, so the through hole is the starting point in the glass portion. There is a risk of cracking. Therefore, even if the conventional technology described in Patent Documents 1 and 2 is employed and the inspection wiring is formed on the outer peripheral portion of the substrate main surface, the cracks generated in the central portion (through hole formation region) of the core substrate are not generated. Not enough to detect. In this case, since there is a high possibility that a multilayer wiring board is manufactured using a defective core substrate, the yield of the multilayer wiring board is reduced, and the predetermined reliability required for the multilayer wiring board cannot be provided. There is.

  The present invention has been made in view of the above problems, and a first object of the present invention is to provide a wiring board capable of improving reliability by reliably detecting defects. A second object is to provide a method for manufacturing a multilayer wiring board capable of manufacturing a multilayer wiring board having excellent reliability by improving the yield.

As means (means 1) for solving the above-mentioned problem, the substrate has a substrate main surface and a substrate back surface, and has a plurality of through holes opened at the substrate main surface and the substrate back surface, and has an insulating property. A substrate body including a material; a plurality of via conductors formed in the plurality of through holes; and a plurality of lands connected to the substrate main surface side end and the substrate back surface side end of the plurality of via conductors. An extended wiring extending along a substrate surface direction is formed on at least one of the substrate main surface and the back surface of the substrate, and at least a part of the extended wiring is adjacent to the wiring substrate. The extended wiring is disposed between a plurality of lands, and the thickness of the extended wiring is thinner than the thickness of the lands. The entire outer periphery of the substrate main surface and the entire outer periphery of the back surface of the substrate are interposed through the substrate body. Dami to face each other Electrodes are formed, the dummy electrode is electrically independent of the extension設配line and the land, and the dummy electrodes of the substrate main surface and the back surface side of the substrate of the dummy electrode are electrically independent of each other There is a wiring board characterized by this.

  Therefore, according to the invention described in the means 1, at least a part of the extended wiring is arranged between a plurality of adjacent lands. That is, the extended wiring is disposed in the vicinity of a location where a defect (specifically, generation of a crack starting from the through hole) is likely to occur in the substrate body. For this reason, if the extended wiring is a wiring for inspection, it is possible to reliably detect whether or not a failure has occurred based on the measurement result obtained by measuring the conduction state of the extended wiring. Therefore, the reliability of the wiring board can be improved.

  The wiring board includes a substrate body having a substrate main surface and a substrate back surface, and having a plurality of through-holes that open at the substrate main surface and the substrate back surface. The material for forming the substrate body is not particularly limited as long as it includes an inorganic material having an insulating property, and can be appropriately selected in consideration of cost, workability, mechanical strength, and the like. Therefore, examples of the substrate body include a ceramic substrate and a glass substrate. As a material for forming the ceramic substrate, low-temperature fired glass ceramic, glass ceramic, or the like is preferably used. Further, borosilicate glass, low-temperature fired glass ceramic, glass ceramic or the like is preferably used as a material for forming the glass substrate. If the substrate body is a glass substrate made of glass having excellent insulation and smoothness, through holes can be formed in the substrate body at a narrower pitch than when the substrate body is, for example, a resin substrate. The degree of freedom of wiring provided is increased.

  Here, the thickness of the substrate main body is not particularly limited, but may be, for example, 10 μm or more and 400 μm or less. If the thickness of the substrate main body is less than 10 μm, the substrate main body becomes too thin, so that the strength of the substrate main body may be reduced and damaged. On the other hand, when the thickness of the substrate main body is larger than 400 μm, the substrate main body, and consequently the wiring substrate, becomes thick.

  The plurality of via conductors constituting the wiring board are formed in the plurality of through holes. Such via conductors are, for example, gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), nickel (Ni), tin (Sn), lead (Pb), tungsten (W ) Or the like.

  The plurality of lands constituting the wiring board are connected to the substrate main surface side end and the substrate back surface side end of the plurality of via conductors. The land is mainly made of copper, and is formed by a known method such as a subtractive method, a semi-additive method, or a full additive method. Specifically, for example, techniques such as etching of copper foil, electroless copper plating, or electrolytic copper plating are applied. Note that a land can be formed by etching after forming a thin film by a technique such as sputtering or CVD, or a land can be formed by printing a conductive paste or the like.

  Furthermore, an extended wiring extending along the substrate surface direction is formed on at least one of the substrate main surface and the substrate back surface. The extended wiring is mainly made of copper and is formed by a known method such as sputtering or CVD. It is also possible to form an extended wiring by a technique such as etching of copper foil, electroless copper plating or electrolytic copper plating, or to form an extended wiring by printing a conductive paste or the like. The extended wiring is preferably formed mainly of the same conductive material as the land. In this way, it is not necessary to prepare a material different from the land when forming the extended wiring. Therefore, since the material necessary for manufacturing the wiring board is reduced, the cost of the wiring board can be reduced.

  Here, the width of the extended wiring is not particularly limited, but is preferably 10 μm or less, for example. Also, the thickness of the extended wiring is not particularly limited, but is preferably 1 μm or less, for example. If the width of the extended wiring is 10 μm or less and the thickness of the extended wiring is 1 μm or less, it becomes easy to be cut when a defect such as a crack occurs due to the deformation of the substrate body, so the conduction state of the extended wiring changes. This makes it easier to detect defects in the board body.

  The extended wiring is preferably formed on both the substrate main surface and the substrate back surface. In this way, even if a defect such as a crack occurs near the substrate main surface or near the back surface of the substrate body, the defect can be reliably detected. Moreover, the extended wiring may exist in a plurality of systems on at least one of the substrate main surface and the substrate back surface. In this way, even if there is an extended wiring that has already been damaged before the defect is inspected, it is possible to reliably detect the defect using another extended wiring.

  Furthermore, the extended wiring may have a plurality of wide inspection portions that can contact the inspection jig. In this case, since the inspection jig is brought into contact with the inspection section wider than the extension wiring, the conduction state of the extension wiring is measured, so that the defect is surely determined based on the obtained measurement value. Can be detected. Note that the position of the inspection unit is not particularly limited. For example, the inspection section may be provided at the end of the extended wiring, or may be provided at an intermediate portion of the extended wiring, but is particularly provided at the end of the extended wiring. Further, it is preferable that they are arranged on at least one of the outer peripheral portion of the substrate main surface and the outer peripheral portion of the substrate back surface. In this way, since the inspection part can be arranged avoiding the lands located on the main surface of the substrate or the back surface of the substrate, the inspection jig can be easily brought into contact with the inspection part.

Also, dummy electrodes are formed on the entire outer peripheral portion of the substrate main surface and the entire outer peripheral portion of the back surface of the substrate so as to face each other via the substrate body, and the dummy electrodes are electrically independent from the extended wiring and the land, the dummy electrode and the substrate rear surface side of the dummy electrodes on the main surface side is that not electrically independent of each other. In this case, when the wiring laminated portion having a structure in which the resin insulating layer and the conductor layer are laminated is formed on at least one of the main surface of the substrate and the back surface of the substrate, the dummy electrode formed on the substrate body and the resin are formed. Since the contact area with the insulating layer is increased and the adhesion between the substrate body and the resin insulating layer is improved, peeling (delamination) of the resin insulating layer is less likely to occur. In addition to detecting defects based on the measured values obtained by measuring the conductive state of the extended wiring, the capacitance between the dummy electrode on the substrate main surface side and the dummy electrode on the back surface side of the substrate is Also by measuring, it is possible to detect a defect (specifically, peeling of a dummy electrode or generation of a crack in the substrate body) based on the obtained measurement value. Therefore, the reliability of the wiring board can be further improved. Furthermore, peeling of the resin insulating layer is most likely to occur at the outer peripheral portion of the substrate body. Further, when manufacturing a wiring board, an impact is often applied to the side surface (substrate side surface) of the substrate body. Therefore, if the entire outer periphery of the substrate main surface and the entire outer periphery of the back surface of the substrate are covered with dummy electrodes as described above, it is possible to prevent peeling of the resin insulation layer and damage to the substrate body during manufacturing. The reliability of the substrate can be further improved.

  Here, the “dummy electrode” is formed of a conductor, but basically does not function as an electrode, and is not electrically and physically connected to other electrodes. The dummy electrode is mainly made of copper, and is formed by a known method such as a subtractive method, a semi-additive method, or a full additive method. Specifically, for example, techniques such as etching of copper foil, electroless copper plating, or electrolytic copper plating are applied. Note that a dummy electrode can be formed by etching after forming a thin film by a technique such as sputtering or CVD, or a dummy electrode can be formed by printing a conductive paste or the like.

As another means (means 2) for solving the above-mentioned problem, the substrate has a substrate main surface and a substrate back surface, and has a plurality of through holes opened in the substrate main surface and the substrate back surface, and has an insulating property. Substrate body preparation step of preparing a substrate body containing an inorganic material having, after the substrate body preparation step, via conductor formation step of forming a plurality of via conductors in the plurality of through holes, after the via conductor formation step, A land forming step for forming a plurality of lands connected to the substrate main surface side end portion and the substrate back surface side end portion in the plurality of via conductors, and after the land forming step, a resin insulating layer and a conductor layer are laminated. In a method for manufacturing a multilayer wiring board, comprising: a wiring laminated part forming step of forming a wiring laminated part having a structure on at least one of the substrate main surface and the substrate back surface. Before the part forming step, the extended wiring that extends along at least one of the substrate main surface and the back surface of the substrate along the substrate surface direction and at least part of which is located between the adjacent lands is formed. There is a manufacturing method of a multilayer wiring board characterized in that a forming process is performed, and an inspection process for inspecting a conductive state of the extended wiring is performed after the extended wiring forming process and before the wiring laminated portion forming process .

  Therefore, according to the invention described in the means 2, in the extended wiring forming step, the extended wiring is formed in the substrate main body by forming at least a part of the extended wiring between the adjacent lands. Specifically, it is arranged in the vicinity of a place where a crack is likely to occur). For this reason, based on the measurement result obtained by measuring the conductive state of the extended wiring, it is possible to reliably detect whether or not a failure has occurred. Therefore, the problem that the multilayer wiring board is manufactured using the defective substrate body is prevented in advance, so that the yield of the multilayer wiring board can be improved. From the above, a multilayer wiring board with excellent reliability can be manufactured.

  Hereinafter, a method for manufacturing a multilayer wiring board will be described.

  In the substrate main body preparation step, a substrate main body having a substrate main surface and a substrate back surface, having a plurality of through-holes opened on the substrate main surface and the substrate back surface, and including an insulating inorganic material by a conventionally known method Prepare and prepare in advance. In the subsequent via conductor forming step, a plurality of via conductors are formed in the plurality of through holes, and in the subsequent land forming step, a plurality of via conductors connected to the substrate main surface side end and the substrate back surface side end. Form a land.

  In the subsequent wiring laminated portion forming step, a wiring laminated portion having a structure in which a resin insulating layer and a conductor layer are laminated is formed on at least one of the substrate main surface and the substrate back surface. The resin insulation layer can be appropriately selected in consideration of insulation, heat resistance, moisture resistance, and the like. Preferred examples of the polymer material for forming the resin insulation layer include thermosetting resins such as epoxy resin, phenol resin, urethane resin, silicone resin, polyimide resin, polycarbonate resin, acrylic resin, polyacetal resin, polypropylene resin, etc. And other thermoplastic resins. The conductor layer is mainly made of copper and is formed by a known method such as a subtractive method, a semi-additive method, or a full additive method.

  Note that after the substrate body preparation step and before the wiring laminated portion formation step, the extension extends along at least one of the substrate main surface and the substrate back surface along the substrate surface direction, and at least a part thereof is positioned between a plurality of adjacent lands. An extended wiring forming process for forming the installed wiring is performed. A multilayer wiring board is manufactured through the above processes.

1 is a schematic cross-sectional view showing a multilayer wiring board in the present embodiment. The schematic plan view which shows the core board | substrate with which the extended wiring was formed. Explanatory drawing which shows the manufacturing method of a multilayer wiring board. Explanatory drawing which shows the manufacturing method of a multilayer wiring board. Explanatory drawing which shows the manufacturing method of a multilayer wiring board. Explanatory drawing which shows the manufacturing method of a multilayer wiring board. Explanatory drawing which shows the manufacturing method of a multilayer wiring board. Explanatory drawing which shows the manufacturing method of a multilayer wiring board. The schematic plan view which shows the core board | substrate with which the extended wiring was formed in other embodiment. The schematic plan view which shows the core board | substrate with which the extended wiring was formed in other embodiment. The schematic plan view which shows the core board | substrate with which the extended wiring was formed in other embodiment.

  Hereinafter, an embodiment embodying the multilayer wiring board 10 of the present invention will be described in detail with reference to the drawings.

  As shown in FIG. 1, the multilayer wiring board 10 of the present embodiment is a glass interposer (glass relay board) for mounting an IC chip. The multilayer wiring substrate 10 includes a substantially rectangular plate-shaped core substrate 11 (substrate body) and a main surface side build-up layer 31 (wiring laminated portion) formed on the substrate main surface 12 (upper surface in FIG. 1) of the core substrate 11. And a back-side buildup layer 32 (wiring laminate) formed on the substrate back surface 13 (the lower surface in FIG. 1) of the core substrate 11.

  As shown in FIGS. 1 and 2, the core substrate 11 has one substrate main surface 12, one substrate back surface 13, and four substrate side surfaces 14, and has a substantially rectangular plate shape. The core substrate 11 of this embodiment is a glass substrate made of an insulating inorganic material (in this embodiment, borosilicate glass). The size of the core substrate 11 is set to 10 mm long × 10 mm wide. The thickness of the core substrate 11 is set to 10 μm or more and 400 μm or less (100 μm in this embodiment). In this embodiment, the thermal expansion coefficient of the core substrate 11 is less than 15 ppm / ° C., specifically about 4 to 5 ppm / ° C. In addition, the thermal expansion coefficient of the core board | substrate 11 says the average value of the measured value between 30 degreeC-400 degreeC.

  The core substrate 11 is formed with a plurality of through-holes 15 that are open in both the substrate main surface 12 and the substrate back surface 13 in a lattice shape. Each through-hole 15 has a circular shape in plan view, and has a double taper shape in which the inner diameter gradually increases toward the substrate main surface 12 side and the substrate back surface 13 side. A via conductor 16 made of copper is provided in the through hole 15. In the present embodiment, for convenience of explanation, the via conductors 16 are illustrated in 3 columns × 3 columns, but actually there are more columns (specifically, 10 columns × 10 columns). The distance (pitch) between the centers of adjacent via conductors 16 is set to 400 μm.

As shown in FIGS. 1 and 2, on the substrate main surface 12 of the core substrate 11, a plurality of main surface side lands 21 having a circular shape in plan view are arranged vertically and horizontally along the surface direction of the substrate main surface 12. On the substrate back surface 13 of the core substrate 11, a plurality of back surface lands 22 having a circular shape in plan view are arranged vertically and horizontally along the surface direction of the substrate back surface 13. Each main surface side land 21 is electrically connected to an end portion of each via conductor 16 on the substrate main surface 12 side, and each back surface land 22 is electrically connected to an end portion of each via conductor 16 on the substrate back surface 13 side. Has been. The outer diameters of the lands 21 and 22 are set to be larger (150 μm in this embodiment) than the maximum diameter of the via conductor 16 (100 μm in this embodiment). In addition, the thickness of each land 21 and 22 in this embodiment is set to 10 μm.

A main surface side extended wiring 81 made of copper is patterned on the substrate main surface 12 of the core substrate 11, and a back surface side extension made of copper is also formed on the substrate back surface 13 of the core substrate 11. The wiring 82 is patterned. That is, the extended wirings 81 and 82 are formed on both the substrate main surface 12 and the substrate back surface 13. The extended wirings 81 and 82 have a linear shape with a width of 5 μm and a thickness of 1 μm, and extend along the substrate surface direction. More specifically, the main surface side extended wiring 81 exists only in one system on the substrate main surface 12, and a plurality of straight portions 86 extending in a straight line along the substrate surface direction and the straight portions 86 are orthogonal to each other. And a plurality of connecting portions 87 to be connected. Major surface extending設配line 81 is disposed a portion between the adjacent main-surface-side lands 21, the remaining portion is disposed between the dummy electrode 51 discussed later with the main surface-side lands 21. On the other hand, the back surface side extended wiring 82 exists in only one system on the back surface 13 of the substrate, and a straight line portion (not shown) that extends straight along the substrate surface direction and a connection that connects the straight line portions in an orthogonal state. Part (not shown). A part of the back side extended wiring 82 is arranged between the adjacent back side lands 22, and the remaining part is arranged between the back side land 22 and a dummy electrode 52 described later. The back surface side extended wiring 82 has the same planar shape as the main surface side extended wire 81.

  As shown in FIG. 2, the main surface side extended wiring 81 has main surface side inspection portions 83 and 84 that can contact a probe 85 (see FIG. 6) that is an inspection jig at two locations. Yes. The main surface side inspection portions 83 and 84 have a rectangular shape in plan view of 1 mm in length × 1 mm in width, and are wider than other portions in the main surface side extending wiring 81. The main surface side inspection portions 83 and 84 are provided at both ends of the main surface side extending wiring 81, respectively. Further, the main surface side inspection portions 83 and 84 are disposed in the vicinity of one substrate side surface 14 in the outer peripheral portion of the substrate main surface 12.

  Similarly, the back surface side extended wiring 82 has back surface side inspection parts (not shown) with which the probe 85 can come into contact at two locations. The back surface side inspection portion has a rectangular shape in plan view of 1 mm in length × 1 mm in width, and is wider than other portions in the back surface side extended wiring 82. The back side inspection portions are provided at both ends of the back side extended wiring 82, respectively. Further, the back surface side inspection portion is disposed in the vicinity of one substrate side surface 14 in the outer peripheral portion of the substrate back surface 13.

  As shown in FIGS. 1 and 2, a dummy electrode 51 made of copper having a thickness of 10 μm is patterned on the substrate main surface 12 of the core substrate 11, and on the substrate back surface 13 of the core substrate 11, similarly. A dummy electrode 52 made of copper having a thickness of 10 μm is patterned. The dummy electrode 51 and the dummy electrode 52 are arranged to face each other with the core substrate 11 interposed therebetween. More specifically, the dummy electrode 51 covers the entire outer peripheral portion of the substrate main surface 12, and the dummy electrode 52 covers the entire outer peripheral portion of the substrate back surface 13. The ratio of the dummy electrode 51 in the substrate main surface 12 and the ratio of the dummy electrode 52 in the substrate back surface 13 are both 51.0%.

  The dummy electrode 51 is formed with a main surface side opening 53 exposing the main surface side land 21 and the main surface side extended wiring 81, and the rear surface side land 22 and the back surface side extended wiring are formed on the dummy electrode 52. A back-side opening 54 that exposes 82 is formed. The openings 53 and 54 have a rectangular shape in plan view of 7 mm length × 7 mm width. The main surface side land 21 and the main surface side extended wiring 81 are arranged in the main surface side opening 53 so that the respective outer surfaces thereof face the inner surface of the main surface side opening 53, and the back surface side land 22. And the back side extended wiring 82 is disposed in the back side opening 54 so that the outer side faces the inner side of the back side opening 54. That is, the dummy electrodes 51 and 52 are electrically independent from the lands 21 and 22 and the extended wirings 81 and 82. The dummy electrode 51 on the substrate main surface 12 side and the dummy electrode 52 on the substrate back surface 13 side are electrically independent from each other.

  As shown in FIG. 1, the main surface side buildup layer 31 includes two resin insulating layers 33 and 35 made of a thermosetting resin (epoxy resin) having a thickness of 17.5 μm, and a conductor layer 41 made of copper. , 42 are laminated. In the present embodiment, the thermal expansion coefficient of the resin insulating layers 33 and 34 in a completely cured state is about 10 to 60 ppm / ° C., specifically 46 ppm / ° C. In addition, the thermal expansion coefficient in the completely cured state of the resin insulating layers 33 and 35 is an average value of measured values between 25 ° C. and 150 ° C. In the resin insulating layers 33 and 35, via conductors 43 formed by copper plating are provided. Further, the surface of the resin insulating layer 35 is almost entirely covered with a solder resist 37. An opening 46 for exposing the conductor layer 42 is formed at a predetermined position of the solder resist 37. A plurality of solder bumps 45 are provided on the surface of the conductor layer 42.

  As shown in FIG. 1, in the main surface side buildup layer 31, measurement wirings 61 that are electrically connected to the dummy electrodes 51 on the substrate main surface 12 side are provided at a plurality of locations. Each measurement wiring 61 includes a measurement via conductor 62 and a measurement conductor layer 63. The measurement via conductor 62 is formed by copper plating, is provided in the resin insulating layer 33, and is connected to the surface of the dummy electrode 51. The measurement conductor layer 63 is made of copper, is formed on the surface of the resin insulating layer 33, and is electrically connected to the end face of the measurement via conductor 62.

  Each solder bump 45 is electrically connected to a surface connection terminal of an IC chip (semiconductor integrated circuit element). The IC chip of this embodiment is a plate-like object having a rectangular shape in plan view of 6.0 mm in length, 6.0 mm in width, and 0.9 mm in thickness, and has a thermal expansion coefficient of about 3 to 4 ppm / ° C. (specifically (About 3.5 ppm / ° C.).

  As shown in FIG. 1, the back surface side buildup layer 32 has substantially the same structure as the main surface side buildup layer 31 described above. That is, the back-side buildup layer 32 has a structure in which two resin insulating layers 34 and 36 made of a thermosetting resin (epoxy resin) having a thickness of 17.5 μm and conductor layers 41 and 42 made of copper are laminated. have. In the present embodiment, the thermal expansion coefficient of the resin insulating layers 34 and 36 in a completely cured state is about 10 to 60 ppm / ° C., specifically 46 ppm / ° C. In addition, the thermal expansion coefficient in the completely cured state of the resin insulating layers 34 and 36 is an average value of measured values between 25 ° C. and 150 ° C. Further, via conductors 47 formed by copper plating are provided in the resin insulating layers 34 and 36, respectively. Further, the lower surface of the resin insulating layer 36 is almost entirely covered with a solder resist 38. An opening 48 that exposes the conductor layer 42 disposed on the lower surface of the resin insulating layer 36 is formed at a predetermined location of the solder resist 38. On the surface of the conductor layer 42, a plurality of solder bumps 49 are provided for electrical connection with a mother board (not shown).

  As shown in FIG. 1, measurement wiring 71 that is electrically connected to the dummy electrode 52 on the substrate back surface 13 side is provided in a plurality of locations in the back surface side buildup layer 32. Each measurement wiring 71 includes a measurement via conductor 72 and a measurement conductor layer 73. The measurement via conductor 72 is formed by copper plating, is provided in the resin insulating layer 34, and is connected to the surface of the dummy electrode 52. The measurement conductor layer 73 is made of copper, is formed on the surface of the resin insulating layer 34, and is electrically connected to the end face of the measurement via conductor 72.

  Next, the manufacturing method of the multilayer wiring board 10 of this embodiment is demonstrated.

  First, in the substrate body preparation step, the core substrate 11 is prepared by a conventionally known technique and prepared in advance (see FIG. 3). In the substrate body preparation step of the present embodiment, a multi-piece core substrate is prepared in which a plurality of substrate formation regions to be the core substrate 11 are arranged vertically and horizontally along the plane direction.

  The core substrate 11 is manufactured as follows. First, a commercially available thin glass substrate (OA-10G manufactured by Nippon Electric Glass Co., Ltd.) is prepared. The thin glass substrate of the present embodiment is a plate-like object having a rectangular shape in plan view of 100 mm length × 100 mm width × 100 μm thickness. Next, a large number of through holes 15 are formed through the thin glass substrate by a known method such as laser irradiation, drilling, sandblasting, etc. (see FIG. 4). Further, titanium (Ti) is sputtered from the substrate main surface 12 side to form a titanium layer, and is formed on the titanium layer formed on the substrate main surface 12 and the inner surface of the through hole 15 on the substrate main surface 12 side. The titanium layer is a continuous layer without being divided. Further, sputtering of titanium is performed from the substrate back surface 13 side to form a titanium layer, and the titanium layer formed on the substrate back surface 13 and the titanium layer formed on the inner surface of the through hole 15 on the substrate back surface 13 side, It is a continuous layer without being divided. Further, copper (Cu) is sputtered from the substrate main surface 12 side and the substrate back surface 13 side to form a copper layer on the titanium layer.

  In the via conductor formation process and land formation process after the substrate body preparation process, the via conductor 16 is formed in the through hole 15, and a plurality of main surface side lands 21 connected to the end of the via conductor 16 on the substrate main surface 12 side. And a plurality of backside lands 22 connected to the end of the via conductor 16 on the substrate backside 13 side. Specifically, a dry film is laminated on each of the substrate main surface 12 and the substrate back surface 13 on which the titanium layer and the copper layer are formed to form a plating resist (not shown). Next, after patterning by photolithography, the surface of the copper layer formed on the inner surface of the through hole 15, the surface of the copper layer formed on the substrate main surface 12, and the copper formed on the substrate back surface 13 Electrolytic copper plating is performed on the surface of each layer. At this time, the via conductor 16 is formed in the through hole 15, the main surface side land 21 is formed simultaneously with the dummy electrode 51 on the substrate main surface 12, and the back surface land 22 is formed on the substrate back surface 13 with the dummy electrode. 52 (see FIG. 5). Thereafter, the plating resist is peeled off, and the titanium layer and the copper layer protected by the plating resist are removed by etching. In addition, when forming a via conductor in the glass-ceramic green sheet, after forming a copper layer, it fills in each through-hole 15 with the copper paste for via conductors using the paste press injection filling apparatus which is not shown in figure. Thereafter, the green sheet is dried to solidify the green sheet to some extent. Next, the green sheet is degreased and further fired at a predetermined temperature for a predetermined time. As a result, the glass ceramic and the copper in the paste are simultaneously sintered to form a core substrate on which a plurality of via conductors are formed.

  The lands 21 and 22 may be formed by another method. More specifically, electrolytic copper plating is performed on the surface of the copper layer formed on the substrate main surface 12 and the surface of the copper layer formed on the substrate back surface 13 without forming a plating resist. At this point, a solid pattern covering the entire substrate main surface 12 is formed and a solid pattern covering the entire substrate back surface 13 is formed. Thereafter, patterning is performed by a subtractive method. Specifically, a dry film is laminated on the substrate main surface 12 and the substrate back surface 13, and an etching resist having a predetermined pattern is formed by exposing and developing the dry film. In this state, patterning by etching is performed on the solid pattern on the substrate main surface 12 side and the substrate back surface 13 side. At this time, the main surface side land 21 and the dummy electrode 51 are formed on the substrate main surface 12, and the back surface side land 22 and the dummy electrode 52 are formed on the substrate back surface 13 (see FIG. 5). Thereafter, the etching resist is peeled off.

  Further, an extended wiring forming step is performed after the substrate main body preparation step and before the wiring layer stacking step described later, and the main surface side extended wiring 81 is formed on the substrate main surface 12 by the lift-off method, and the back surface on the substrate back surface 13 is formed. Side extension wiring 82 is formed (see FIG. 6). Specifically, a photoresist material (not shown) is laminated on the substrate main surface 12 and the substrate back surface 13, respectively, and exposure and development are performed on the photoresist material, whereby the substrate main surface 12 and the substrate back surface 13 are formed. Openings to be exposed are formed at a plurality of locations. Next, by sputtering titanium from the substrate main surface 12 side, a titanium layer is formed on the surface exposed through the opening of the photoresist material on the substrate main surface 12 side. Further, sputtering of titanium is performed from the substrate back surface 13 side, and a titanium layer is formed on the surface exposed through the opening of the photoresist material on the substrate back surface 13 side. Further, copper is sputtered from the substrate main surface 12 side and the substrate back surface 13 side to form a copper layer on the titanium layer. At this time, the main surface side extended wiring 81 is formed on the substrate main surface 12, and the back surface side extended wiring 82 is formed on the substrate back surface 13 (see FIG. 6). Thereafter, the photoresist material is removed by immersing the core substrate 11 in a removing solution or spraying a peeling solution on the substrate main surface 12 and the substrate back surface 13 at a high pressure.

  Further, a first inspection step is performed after the extended wiring forming step and before the wiring laminated portion forming step to inspect the conductive state of the extended wires 81 and 82 (see FIG. 6). That is, the extended wirings 81 and 82 are inspection wirings. More specifically, in the first inspection step, the probe 85 is brought into contact with the main surface side inspection portions 83 and 84 at both ends of the main surface side extending wiring 81. And in this state, the electrical resistance value of the main surface side extension wiring 81 is measured, and the quality of the conduction state is determined based on the measured value obtained by measuring the electrical resistance value. Specifically, if the obtained measured value is within the range of the measured value (first reference value) when the main surface side extended wiring 81 is not deformed, the core substrate 11 has a problem. Not good (good). On the other hand, when the obtained measured value is higher than the range of the first reference value (that is, when the main surface side extending wiring 81 is deformed and extended), or when the electrical resistance value cannot be measured (that is, In the case where the main surface side extended wiring 81 is cut), it is determined that the core substrate 11 is defective (No).

  Further, in the first inspection process, the probes 85 are also brought into contact with both end portions of the back surface side extended wiring 82. And in this state, the electrical resistance value of the back surface side extended wiring 82 is measured, and the quality of the conduction state is determined based on the measured value obtained by measuring the electrical resistance value. Specifically, when the obtained measurement value is within the range of the measurement value (first reference value) when the back-side extended wiring 82 is not deformed, there is no defect in the core substrate 11. (Good). On the other hand, when the obtained measured value is higher than the range of the first reference value (that is, when the back surface side extended wiring 82 is deformed and extended), or when the electrical resistance value cannot be measured (that is, the back surface). When the side extension wiring 82 is cut), it is determined that the core substrate 11 has a problem (No).

  In the subsequent wiring laminated portion forming step, the main surface side buildup layer 31 is formed on the substrate main surface 12 and the back surface side buildup layer 32 is formed on the substrate back surface 13 based on a conventionally known technique (FIG. 7, see FIG. Specifically, first, a resin insulating layer 33 is formed by depositing (attaching) a thermosetting epoxy resin having a thickness of 17.5 μm on the substrate main surface 12. Also, a resin insulating layer 34 is formed by depositing (attaching) a thermosetting epoxy resin having a thickness of 17.5 μm on the back surface 13 of the substrate. Instead of depositing a thermosetting epoxy resin, a photosensitive epoxy resin, an insulating resin, or a liquid crystal polymer (LCP) may be deposited.

  The wiring laminated portion forming process includes a measurement wiring forming process and a second inspection process. In the measurement wiring formation step, the measurement wiring 61 is formed on the resin insulation layer 33 in a state where the single resin insulation layer 33 is laminated on the substrate main surface 12, and one layer of resin insulation is formed on the substrate back surface 13. With the layer 34 laminated, the measurement wiring 71 is formed on the resin insulating layer 34. More specifically, laser drilling is performed using a YAG laser or a carbon dioxide gas laser to form via holes at positions where the via conductors 43 and 47 and the measurement via conductors 62 and 72 are to be formed. Specifically, a via hole penetrating the resin insulating layer 33 is formed, and the surface of the main surface side land 21 and the surface of the dummy electrode 51 are exposed. Further, a via hole penetrating the resin insulating layer 34 is formed to expose the surface of the back surface side land 22 and the surface of the dummy electrode 52. Next, electrolytic copper plating is performed according to a conventionally known method to form via conductors 43 and 47 and measurement via conductors 62 and 72 inside the via holes, and the conductor layer 41 and the measurement on the resin insulating layers 33 and 34. Conductor layers 63 and 73 are formed. At this time, the measurement wiring 61 composed of the measurement via conductor 62 and the measurement conductor layer 63 and the measurement wiring 71 composed of the measurement via conductor 72 and the measurement conductor layer 73 are formed (see FIG. 7). .

  In the second inspection process performed after the measurement wiring formation process, the probe 64 is brought into contact with the measurement conductor layer 63 on the substrate main surface 12 side, and the probe is made on the measurement conductor layer 73 on the substrate back surface 13 side. 74 is brought into contact (see FIG. 7). In this state, the capacitance between the dummy electrode 51 on the substrate main surface 12 side and the dummy electrode 52 on the substrate back surface 13 side is measured. And the quality is determined based on the measured value obtained by measuring the capacitance. Specifically, when the obtained measurement value is within the range of the measurement value (second reference value) when the dummy electrodes 51 and 52 are not peeled off, there is no defect in the core substrate 11. Judge (good). On the other hand, when the obtained measured value is lower than the range of the second reference value, it is determined that the core substrate 11 is defective (No).

  After the second inspection step, a thermosetting epoxy resin having a thickness of 17.5 μm is deposited on the resin insulating layers 33 and 34 to form the resin insulating layers 35 and 36. Instead of depositing the thermosetting epoxy resin, a photosensitive epoxy resin, an insulating resin, or a liquid crystal polymer may be deposited. In this case, via holes are formed in the resin insulating layers 35 and 36 at positions where the via conductors 43 and 47 are to be formed by a laser processing machine or the like. Next, electrolytic copper plating is performed in accordance with a conventionally known technique to form via conductors 43 and 47 in the via holes of the resin insulating layers 35 and 36 and to form a conductor layer 42 on the resin insulating layers 35 and 36. At this point, the buildup layers 31 and 32 shown in FIG. 8 are completed.

  After the wiring laminated portion forming step, a solder resist 37, 38 is formed by applying and curing a photosensitive epoxy resin on the resin insulating layers 35, 36. Next, exposure and development are performed with a predetermined mask placed, and the openings 46 and 48 are patterned in the solder resists 37 and 38.

  Further, a solder paste is printed on the conductor layer 42 formed on the resin insulating layer 35. A solder paste is printed on the conductor layer 42 formed on the resin insulating layer 36. Next, the multi-chip substrate on which the solder paste is printed is placed in a reflow furnace and heated to a temperature 10 to 40 ° C. higher than the melting point of the solder. At this time, the solder paste is melted to form the IC chip mounting solder bumps 45 having a hemispherical shape, and the motherboard mounting solder bumps 49 having the same hemispherical shape are formed. .

  Further, the substrate forming regions are divided by cutting the multi-piece substrate along the outline of the substrate forming region using a conventionally known cutting device (laser processing machine, dicing device, etc.). A plurality of multilayer wiring boards 10 can be obtained simultaneously.

  Thereafter, an IC chip is placed on the surface of the main surface side buildup layer 31 constituting the multilayer wiring board 10. At this time, the surface connection terminals on the IC chip side and the solder bumps 45 are aligned. Then, each solder bump 45 is reflowed by heating to a temperature of about 220 to 240 ° C., whereby each solder bump 45 and the surface connection terminal are joined, and the multilayer wiring board 10 side and the IC chip side are electrically connected. Connecting. As a result, an IC chip is mounted on the multilayer wiring board 10.

  Next, the evaluation method and result of the core substrate 11 will be described.

  First, a measurement sample was prepared as follows. A core substrate obtained by performing each step (substrate body preparation step, via conductor formation step, land formation step, extended wiring formation step) under the same conditions as in this embodiment is prepared. did. Next, a crack was intentionally generated in the core substrate by bending the core substrate so that the main surface side of the substrate is convex. Moreover, the electrical resistance value of the main surface side extended wiring was measured with generation | occurrence | production of a crack. The electrical resistance value was measured on 10 measurement samples (core substrate).

  As a result, in some of the measurement samples, it was confirmed that the obtained measurement value increased, so that the main surface side extended wiring was deformed and extended. Moreover, since it became impossible to measure an electrical resistance value with the sample other than that, it was confirmed that the main surface side extension wiring was cut | disconnected. Therefore, it has been proved that the occurrence of defects such as cracks can be reliably detected if the extended wiring is formed on the main surface of the substrate or on the back surface of the substrate.

  Therefore, according to the present embodiment, the following effects can be obtained.

  (1) According to the multilayer wiring board 10 of the present embodiment, at least a part of the main surface side extended wiring 81 is disposed between the adjacent main surface side lands 21 and at least a part of the back surface side extended wiring 82 is provided. It arrange | positions between the back surface lands 22 adjacent. In other words, the extended wirings 81 and 82 are disposed in the vicinity of a location where a defect (specifically, generation of a crack starting from the through hole 15) is likely to occur in the core substrate 11. , 82 can be reliably detected based on the measured values obtained by measuring the electric resistance values. Therefore, since the problem that the multilayer wiring board 10 is manufactured using the defective core substrate 11 is prevented in advance, the yield of the multilayer wiring board 10 can be improved. From the above, the multilayer wiring board 10 having excellent reliability can be manufactured.

  (2) In the present embodiment, the extended wirings 81 and 82 (and the dummy electrodes 51 and 52) are formed on the core substrate 11, so that the extended wirings 81 and 82 (and the dummy electrodes 51 and 52) and the resin insulating layer are formed. Since the contact area with 33 and 34 is increased and the adhesion between the core substrate 11 and the resin insulating layers 33 and 34 is improved, peeling (delamination) of the resin insulating layers 33 and 34 hardly occurs. Therefore, since the problem that the multilayer wiring board 10 is manufactured using the defective core substrate 11 can be prevented more reliably, the yield of the multilayer wiring board 10 is further improved.

  (3) In this embodiment, the through-hole 15 provided in the core substrate 11 has a double taper shape in which the inner diameter gradually increases toward the substrate main surface 12 side and the substrate back surface 13 side. For this reason, the inner side surface of the through-hole 15 is not a surface perpendicular to the substrate main surface 12 and the substrate back surface 13 but is a surface inclined with respect to the substrate main surface 12 and the substrate back surface 13. As a result, when sputtering of titanium or copper, which is an anisotropic thin film forming method, is performed from the substrate main surface 12 side and the substrate back surface 13 side, titanium and copper are easily attached to the inner surface of the through hole 15. Moreover, the via conductor 16 can be formed efficiently and reliably by filling the plating. Therefore, since the conduction by the via conductor 16 can be surely ensured, the multilayer wiring board 10 having even higher reliability can be manufactured. In addition, since the through hole 15 has both tapered shapes, a titanium layer and a copper layer can be formed on the inner surface of the through hole 15, so that the vicinity of the through hole 15 of the core substrate 11 can be reinforced by the titanium layer and the copper layer. it can. As a result, the generation of cracks starting from the through hole 15 can be more reliably prevented. Even if a crack is generated, the yield of the multilayer wiring board 10 is further improved because the crack can be reliably detected by measuring the conduction state of the extended wirings 81 and 82.

  (4) The IC chip of the present embodiment is disposed immediately above the core substrate 11. As a result, the conduction path for electrically connecting the IC chip and the core substrate 11 is the shortest. Therefore, it is possible to smoothly supply power to the IC chip. In addition, since noise entering between the IC chip and the core substrate 11 can be suppressed to a very low level, high reliability can be obtained without causing malfunction such as malfunction.

  In addition, the IC chip is supported by a glass substrate (core substrate 11) that is highly rigid, has a smaller thermal expansion coefficient than the resin insulating layers 33 to 36, and has a thermal expansion coefficient close to that of the IC chip. Therefore, since the core substrate 11 becomes difficult to deform, the IC chip mounted on the core substrate 11 can be supported more stably. Therefore, it is possible to prevent IC chip cracks and poor connections due to large thermal stress. Therefore, as an IC chip, the stress (strain) due to the difference in thermal expansion coefficient becomes large, the influence of thermal stress is large, the calorific value is large and the thermal shock during use is severe, and it is said that it is brittle. A low-k (low dielectric constant) IC chip can be used.

  In addition, you may change this embodiment as follows.

  In the core substrate 11 of the above-described embodiment, the main surface side extended wiring 81 formed on the substrate main surface 12 is disposed between some adjacent main surface side lands 21 and is formed on the substrate back surface 13. The formed backside extended wiring 82 was disposed between some adjacent backside lands 22. However, the arrangement of the extended wiring may be changed. For example, as shown in the core substrate 111 (substrate body) in FIG. 9, the main surface side extended wiring 112 may be formed so as to pass between all adjacent main surface side lands 113. Further, as shown in the core substrate 121 (substrate body) in FIG. 10, the main surface side extended wiring 122 may be formed so as to surround all the main surface side lands 123. In addition, although the part (envelopment part 124) which surrounds the main surface side land 123 in the main surface side extension wiring 122 has comprised circular shape, other shapes, such as square shape, may be sufficient.

  In the core substrate 11 of the above embodiment, one main surface side extended wiring 81 exists on the substrate main surface 12, and one system rear surface side extended wiring 82 exists on the substrate back surface 13. However, the extended wirings 81 and 82 may exist in a plurality of systems on the substrate main surface 12 and the substrate back surface 13. For example, as shown in the core substrate 131 (substrate body) in FIG. 11, two main surface side extended wirings 132 may exist on the substrate main surface 133.

  In the core substrate 11 of the above embodiment, the main surface side inspection portions 83 and 84 are disposed in the vicinity of one substrate side surface 14 in the outer peripheral portion of the substrate main surface 12. However, you may make it arrange | position an inspection part in a different place. For example, as shown in FIG. 9, one main surface side inspection unit 114 is disposed in the vicinity of one substrate side surface 115, and the other main surface side inspection unit 116 is disposed on the substrate side surface 115 in the core substrate 111. You may arrange | position in the vicinity of the board | substrate side surface 117 located in the other side.

  In the first inspection process of the above embodiment, the electrical resistance values of the extended wirings 81 and 82 are measured, and the quality of the conduction state is determined based on the measurement values obtained by measuring the electrical resistance values. It was. However, the quality of the conductive state of the extended wires 81 and 82 may be determined by other methods. For example, it is determined whether or not the extended wires 81 and 82 are in an energized state. If the extended wires 81 and 82 are in an energized state, it is determined that the conductive state of the extended wires 81 and 82 is “good”. The conductive state of the extended wirings 81 and 82 may be determined as “No”.

  In the above-described embodiment, the measurement wiring electrically connected to the dummy electrodes 51 and 52 in a state where the resin insulating layers 33 and 34 are laminated on both the substrate main surface 12 and the substrate back surface 13 respectively. 61 and 71 were formed, and the capacitance was measured in a state where the probes 64 and 74 were brought into contact with both of the measurement wires 61 and 71, respectively. However, the measurement wirings 61 and 71 are formed in a state where two or more resin insulation layers are laminated on the substrate main surface 12 and the substrate back surface 13 respectively, and the probes 64 are respectively connected to both the measurement wirings 61 and 71. , 74 may be in contact with each other, and the capacitance may be measured. In addition, the probes 64 and 74 are brought into direct contact with the dummy electrodes 51 and 52 before the resin insulating layer is laminated on the substrate main surface 12 and the substrate back surface 13, and the capacitance is measured in this state. You may do it.

  In the above embodiment, the through hole 15 provided in the core substrate 11 has a double taper shape in which the inner diameter gradually increases toward the substrate main surface 12 side and the substrate back surface 13 side. A single taper shape in which the inner diameter gradually increases toward the 12 side or the substrate back surface 13 side may be used. Note that the through hole does not have to be tapered.

  Next, the technical ideas grasped by the embodiment described above are listed below.

  (1) The method for manufacturing a multilayer wiring board according to the above means 2, wherein an inspection step for inspecting the conductive state of the extended wiring is performed after the extended wiring forming step and before the wiring laminated portion forming step. .

  (2) In the technical idea (1), in the inspection step, the conduction state is inspected in a state where inspection jigs are in contact with both ends of the extended wiring. A method for manufacturing a multilayer wiring board.

  (3) In the technical idea (1) or (2), in the inspection step, the electrical resistance value of the extended wiring is measured, and the quality of the conductive state is determined based on the measured value. A method for manufacturing a multilayer wiring board.

DESCRIPTION OF SYMBOLS 10 ... Multilayer wiring board 11, 111, 121, 131 as a wiring board ... Core board | substrate 12,133 as a board | substrate main body ... Substrate main surface 13 ... Substrate back surface 15 ... Through-hole 16 ... Via conductor 21, 113, 123 ... As land Main surface side land 22 of the rear surface side land 31 as a land ... Main surface side buildup layer 32 as a wiring laminated portion ... Back surface side buildup layers 33, 34, 35, 36 as a wiring laminated portion ... Resin insulating layer 51 52 ... Dummy electrodes 41, 42 ... Conductor layers 81, 112, 122, 132 ... Main surface side extended wires 82 as extended wires ... Back side extended wires 83, 84, 114, 116 ... as extended wires. Main surface side inspection part 85 as an inspection part ... Probe as an inspection jig

Claims (8)

A substrate main body having a substrate main surface and a substrate back surface, having a plurality of through holes opened in the substrate main surface and the substrate back surface, and including an insulating inorganic material;
A plurality of via conductors formed in the plurality of through holes;
A wiring board comprising a plurality of lands connected to the substrate main surface side end portion and the substrate back surface side end portion of the plurality of via conductors,
An extended wiring extending along the substrate surface direction is formed on at least one of the substrate main surface and the substrate back surface,
At least a part of the extended wiring is disposed between the plurality of adjacent lands,
The thickness of the extended wiring is thinner than the thickness of the land,
Dummy electrodes are formed on the entire outer periphery of the substrate main surface and the entire outer periphery of the back surface of the substrate so as to face each other through the substrate body,
The dummy electrode is electrically independent from the extended wiring and the land;
The wiring board, wherein the dummy electrode on the substrate main surface side and the dummy electrode on the substrate back surface side are electrically independent from each other.   The wiring board according to claim 1, wherein the extended wiring is formed on both the substrate main surface and the substrate back surface.   The wiring board according to claim 1, wherein a plurality of systems of the extended wiring exist on at least one of the substrate main surface and the substrate back surface.   The wiring board according to claim 1, wherein the extended wiring is a wiring for inspection.   5. The wiring board according to claim 1, wherein the extended wiring includes a plurality of wide inspection portions with which an inspection jig can abut.   The wiring board according to claim 5, wherein the inspection section is provided at an end of the extended wiring.   The wiring board according to claim 5, wherein the inspection part is arranged on at least one of an outer peripheral part of the substrate main surface and an outer peripheral part of the back surface of the substrate.   The wiring substrate according to claim 1, wherein the substrate body is a glass substrate.

Images