JP2015037165A - Wiring board and manufacturing method of the same - Google Patents

Wiring board and manufacturing method of the same Download PDF

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JP2015037165A
JP2015037165A JP2013169121A JP2013169121A JP2015037165A JP 2015037165 A JP2015037165 A JP 2015037165A JP 2013169121 A JP2013169121 A JP 2013169121A JP 2013169121 A JP2013169121 A JP 2013169121A JP 2015037165 A JP2015037165 A JP 2015037165A
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conductor
wiring board
layer
conductor layer
flange portion
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JP6442136B2 (en
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宗之 岩田
Muneyuki Iwata
宗之 岩田
卓 宮本
Taku Miyamoto
卓 宮本
善明 長屋
Yoshiaki Nagaya
善明 長屋
豊 今西
Yutaka Imanishi
豊 今西
平野 聡
Satoshi Hirano
聡 平野
奈緒子 森
Naoko Mori
奈緒子 森
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Niterra Co Ltd
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NGK Spark Plug Co Ltd
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Abstract

PROBLEM TO BE SOLVED: To provide a wiring board and a manufacturing method of the same, which has less incidence of migration between conductor layers adjacent to each other on a surface of a substrate body composed of a single insulation layer even when a plurality of conductor layers are formed on the surface of the substrate body with high density are formed and through conductors which pierce the conductor layers and the insulation layer to connect the conductor layers and the insulation layer, and which can successfully connect the conductor layers and the through conductors.SOLUTION: A wiring board 1a comprises: a substrate body 2 which is composed of a single insulation layer r and has a pair of surfaces 3 and 4; conductor layers 10 formed on at least one surface 3 of the insulation layer r which composes the substrate body 2; and through conductors 6 which pierce the insulation layer r having the conductor layers 10 on the surface 3 and continuously pierce the conductor layers 10. The wiring board 1a further comprises a flange part 8 which is formed on a top face of each conductor layer 10 and prevails from an end 7 side of the through conductor 6 along a radial direction of the through conductor 6, in which conductivity of the flange part 8 at least on an outer edge 9 side is lower than conductivity of the through conductor 6.

Description

本発明は、例えば、単数または複数の絶縁層からなる基板本体の表面において複数の導体層を互いに接近して有し、且つ該導体層ごとに上記絶縁層を貫通する貫通導体の端部が貫通して接続されている配線基板およびその製造方法に関する。   The present invention, for example, has a plurality of conductor layers close to each other on the surface of a substrate body composed of one or a plurality of insulating layers, and the end portions of the through conductors that penetrate the insulating layers penetrate through the conductor layers. It is related with the wiring board connected in this way, and its manufacturing method.

例えば、ビア・オン・ビアやチップ・オン・ビアが可能で且つ高密度実装を可能とするため、樹脂フィルムの片面ごとに銅箔と接着剤層とを個別に設けた銅張り樹脂フィルムを用意し、上記銅箔を所定パターンのランド(導体層)に形成し且つ該ランドを含む上記樹脂フィルムを貫通する貫通孔内に対し、導電ペーストをスクリーン印刷により穴埋めすると共に、該導電ペーストの一部を上記ランドの上面における径方向の中間位置まで拡がるつば部として形成する多層配線基材の製造方法が開示されている(例えば、特許文献1参照)。   For example, in order to enable via-on-via and chip-on-via and high-density mounting, a copper-clad resin film with a copper foil and adhesive layer provided separately on each side of the resin film is prepared. Then, the copper foil is formed in lands (conductor layers) of a predetermined pattern, and the conductive paste is filled in the through holes penetrating the resin film including the lands by screen printing, and a part of the conductive paste Has been disclosed as a method of manufacturing a multilayer wiring substrate that forms a brim that extends to a radial intermediate position on the upper surface of the land (see, for example, Patent Document 1).

しかし、前記のような方法により製造された多層配線基材では、前記ランド上に位置するつば部の外縁側から、当該つば部を構成する導電ペーストに含まれる金属原子がイオン化して移動し易くなる。そのため、該イオン化した金属原子が、前記樹脂フィルムの表面上において、比較的高密度で形成された隣接する別のランドやその上面に位置する別のつば部に接近するように染み出して行く、所謂マイグレーションを生じる場合がある。その結果、前記樹脂フィルムの表面上で隣接するランド同士や前記つば部を含んで前記貫通孔に形成された導電ペースト同士が互いにショートする場合がある、という問題があった。
更に、上記ショートを防ぐため、前記つば部を設けることなく、前記貫通孔に穴埋めされる棒状の導電ペーストと前記ランドとを、両者の内・外周面の間においてのみ接続することも可能である。しかし、かかる接続構造にした場合、前記導電ペーストとランドとの接触面積が小さくなると共に、両者間における接着強度が不足して、電気的な接続不良を招く場合がある、という問題があった。
However, in the multilayer wiring substrate manufactured by the method as described above, the metal atoms contained in the conductive paste constituting the collar portion are easily ionized and moved from the outer edge side of the collar portion located on the land. Become. Therefore, on the surface of the resin film, the ionized metal atoms ooze out so as to approach another land formed at a relatively high density and another brim portion located on the upper surface thereof. So-called migration may occur. As a result, there is a problem that the conductive pastes formed in the through holes including the lands adjacent to each other on the surface of the resin film may short-circuit each other.
Furthermore, in order to prevent the short circuit, it is possible to connect the rod-shaped conductive paste filled in the through-hole and the land only between the inner and outer peripheral surfaces without providing the collar portion. . However, in the case of such a connection structure, there is a problem that the contact area between the conductive paste and the land becomes small and the adhesive strength between the two becomes insufficient, leading to poor electrical connection.

特開2002−353621号公報(第1〜17頁、図4〜6)JP 2002-353621 A (pages 1 to 17, FIGS. 4 to 6)

本発明は、背景技術で説明した問題点を解決し、任意数の絶縁層からなる基板本体の表面あるいは内部に複数の導体層を高密度で形成し、且つ該導体層と上記絶縁層とを連続して貫通する貫通導体を形成しても、上記表面などで隣接する導体層同士などの間におけるマイグレーションを生じにくく、且つ上記導体層と貫通導体とを確実に接続できる配線基板およびその製造方法を提供する、ことを課題とする。   The present invention solves the problems described in the background art, and forms a plurality of conductor layers at a high density on the surface or inside of a substrate body composed of an arbitrary number of insulating layers, and the conductor layers and the insulating layers are formed. Even if a continuous through-penetrating conductor is formed, migration between adjacent conductive layers on the surface or the like is unlikely to occur, and the wiring board and the through-conductor can be reliably connected, and a method for manufacturing the same It is an issue to provide.

課題を解決するための手段および発明の効果Means for Solving the Problems and Effects of the Invention

本発明は、前記課題を解決するため、前記基板本体を構成する絶縁層と該基板本体の表面などに形成した導体層とを連続して貫通する貫通導体の周囲側から前記導体層の上面に沿って拡がるフランジ部を設け、且つ該フランジ部の少なくとも外縁側を樹脂を含む組成とする、ことに着想して成されたものである。
即ち、本発明の配線基板(請求項1)は、単数の絶縁層からなるか、あるいは複数の絶縁層を積層してなり、一対の表面を有する基板本体と、該基板本体において、少なくとも1つの絶縁層における少なくとも一方の表面に形成された導体層と、該導体層を表面に有する上記絶縁層を貫通し、且つ該導体層をも連続して貫通する貫通導体と、を備えた配線基板であって、上記導体層の上面には、上記貫通導体の端部側から該貫通導体の径方向に沿って拡がるフランジ部が形成されており、該フランジ部の少なくとも外縁側における導電率は、上記貫通導体の導電率よりも低い、ことを特徴とする。
In order to solve the above-mentioned problem, the present invention provides an upper surface of the conductor layer from the peripheral side of the through conductor that continuously penetrates the insulating layer constituting the substrate body and the conductor layer formed on the surface of the substrate body. It is conceived that a flange portion that extends along the surface is provided, and at least the outer edge side of the flange portion has a resin-containing composition.
That is, the wiring board according to the present invention (Claim 1) is composed of a single insulating layer or a plurality of insulating layers, and has a substrate body having a pair of surfaces, and at least one of the substrate bodies. A wiring board comprising: a conductor layer formed on at least one surface of an insulating layer; and a penetrating conductor that penetrates the insulating layer having the conductor layer on the surface and continuously penetrates the conductor layer. Further, a flange portion is formed on the upper surface of the conductor layer so as to extend from the end portion side of the through conductor along the radial direction of the through conductor, and the conductivity on at least the outer edge side of the flange portion is as described above. It is characterized by being lower than the conductivity of the through conductor.

これによれば、前記フランジ部の少なくとも外縁側における導電率が、前記貫通導体の導電率よりも低いので、上記フランジ部が上面に形成された導体層と、該導体層に隣接して形成された別の導体層や該別の導体層の上面に位置するフランジ部との間において、前述した金属原子が移動して生じるマイグレーションをなくすか抑制し得る。その結果、前記基板本体の表面や内部の同じ層間に高密度で複数の導体層が形成されていても、これらの間における不用意なショートを確実に防ぐか抑制することが可能となる。
しかも、前記フランジ部が貫通導体と一体であることにより、該貫通導体が貫通している前記導体層と貫通導体との接触面積が比較的大きくなるので、該導体層と貫通導体との密着強度および電気的接続を容易に確保することも可能となる。
従って、例えば、基板本体の表面に電子部品を高密度で実装できる配線基板や、あるいは、Siウェハにおける同一面状に形成された多数の電子部品の検査を正確に行うための検査用配線基板に好適な配線基板を提供することが可能となる。
According to this, since the conductivity at least on the outer edge side of the flange portion is lower than the conductivity of the through conductor, the flange portion is formed adjacent to the conductor layer formed on the upper surface and the conductor layer. It is possible to eliminate or suppress the migration caused by the movement of the metal atoms described above between another conductor layer and the flange portion positioned on the upper surface of the other conductor layer. As a result, even if a plurality of conductor layers are formed at a high density between the surface of the substrate main body and the same internal layer, it is possible to reliably prevent or suppress an inadvertent short circuit between them.
In addition, since the flange portion is integral with the through conductor, the contact area between the through layer and the conductor layer through which the through conductor penetrates is relatively large, so that the adhesion strength between the conductor layer and the through conductor is increased. In addition, electrical connection can be easily ensured.
Therefore, for example, a wiring board that can mount electronic components on the surface of the substrate body at high density, or a wiring board for inspection for accurately inspecting a large number of electronic components formed on the same surface of a Si wafer. A suitable wiring board can be provided.

尚、前記基板本体を構成する絶縁層は、樹脂(例えば、ポリイミド)あるいはセラミック(例えば、アルミナ、ガラス−セラミック)からなる。
また、前記基板本体における一対の表面とは、相対的な名称であり、例えば、1つの絶縁層において互いに対向する表面および裏面を指称するものである。
更に、前記導体層は、例えば、Cuからなり、基板本体の表面上に追って実装する電子部品(例えば、ICチップ)の電極とロウ付けにより接合され、あるいは電子部品の電極と接触するプローブが接合される表面端子、または、当該基板本体を搭載するマザーボード(例えば、プリント基板)の電極と電気的に接続するための導体ピンがロウ付けされる裏面(表面)端子、あるいは上記マザーボードの電極とロウ付けされる裏面端子などが例示される。
また、前記フランジ部は、平面視において、前記貫通導体を中心部とするほぼ円形状、あるいは非円形状の任意な形状(変形多角形など)を呈する。
更に、前記フランジ部の厚みは、約数μm〜10μmである。
加えて、前記フランジ部の少なくとも外縁側の導電率と前記貫通導体の導電率とは、少なくとも前者が後者よりも10mS/cm低い。あるいは、少なくとも前者と後者との電気伝導率の差は、少なくとも10mS/cmである。
The insulating layer constituting the substrate body is made of resin (for example, polyimide) or ceramic (for example, alumina, glass-ceramic).
Further, the pair of front surfaces in the substrate body are relative names, for example, refer to the front and back surfaces facing each other in one insulating layer.
Further, the conductor layer is made of, for example, Cu, and is bonded to an electrode of an electronic component (for example, an IC chip) to be mounted on the surface of the substrate body by brazing or a probe that is in contact with the electrode of the electronic component is bonded. Or a back surface (front surface) terminal to which a conductor pin for electrically connecting to an electrode of a mother board (for example, a printed circuit board) on which the board body is mounted is brazed, The back terminal etc. which are attached are illustrated.
Moreover, the said flange part exhibits the substantially circular shape centering on the said through-conductor or non-circular arbitrary shapes (deformation polygon etc.) in planar view.
Furthermore, the thickness of the flange portion is about several μm to 10 μm.
In addition, the conductivity of at least the outer edge side of the flange portion and the conductivity of the through conductor are at least 10 mS / cm lower than the latter in the former. Alternatively, the difference in electrical conductivity between at least the former and the latter is at least 10 mS / cm.

また、本発明には、前記フランジ部の少なくとも外縁側は、樹脂を含んでいると共に、該フランジ部の外縁側を構成する上記樹脂の吸水率は、前記絶縁層の吸水率よりも小さい、配線基板(請求項2)も含まれる。
これによれば、前記導電率の低さに加えて、前記フランジ部の少なくとも外縁側に含まれている樹脂の吸水率が前記絶縁層の吸水率よりも小さいので、該フランジ部から水分を介したマイグレーションも防ぐか抑制することが可能となる。従って、隣接する導体層間におけるショートを一層確実に抑制し得る。
尚、前記フランジ部の外縁側を構成する前記樹脂の吸水率と前記絶縁層の吸水率とを比較すると、少なくとも前者が後者の約5〜50%である。これに合致する組み合わせとしては、前記絶縁層がポリイミドからなり、前記フランジ部の外縁側に含まれる樹脂がエポキシ系樹脂からなる組み合わせが挙げられる。
In the present invention, at least the outer edge side of the flange portion contains a resin, and the water absorption rate of the resin constituting the outer edge side of the flange portion is smaller than the water absorption rate of the insulating layer. A substrate (claim 2) is also included.
According to this, in addition to the low conductivity, the water absorption rate of the resin contained at least on the outer edge side of the flange portion is smaller than the water absorption rate of the insulating layer. It is possible to prevent or suppress migration. Therefore, a short circuit between adjacent conductor layers can be more reliably suppressed.
When the water absorption rate of the resin constituting the outer edge side of the flange portion is compared with the water absorption rate of the insulating layer, at least the former is about 5 to 50% of the latter. As a combination that matches this, there is a combination in which the insulating layer is made of polyimide and the resin included on the outer edge side of the flange portion is made of an epoxy resin.

更に、本発明には、前記フランジ部が上面に形成された前記導体層は、前記基板本体における少なくとも一方の表面に形成された表面導体層である、配線基板(請求項3)も含まれる。
これによれば、前記導体層が前記基板本体における一方あるいは双方の表面に形成された表面導体層または裏面導体層(表面導体層)であるため、例えば、基板本体の表面に電子部品を高密度で実装できる配線基板としたり、あるいは、搭載されるべきプリント基板などのマザーボードの表面に形成された多数の電極との間において、正確な電気的導通が取れる配線基板とすることが可能となる。
Furthermore, the present invention includes a wiring board (Claim 3) in which the conductor layer having the flange portion formed on the upper surface is a surface conductor layer formed on at least one surface of the substrate body.
According to this, since the conductor layer is a surface conductor layer or a back conductor layer (surface conductor layer) formed on one or both surfaces of the substrate body, for example, high density electronic components are formed on the surface of the substrate body. It is possible to provide a wiring board that can be mounted on the board, or a wiring board that can provide accurate electrical continuity with a large number of electrodes formed on the surface of a mother board such as a printed board to be mounted.

また、本発明には、前記貫通導体の端部は、前記フランジ部の上面よりも上方に突出している、配線基板(請求項4)も含まれる。
これによれば、前記貫通導体の端部と、前記基板本体の表面上に実装すべき電子部品の電極とを直に接触させるか、あるいは両者の間に挟まれたロウ材の薄い膜を介して、上記電子部品のロウ付けによる実装が行える。その結果、比較的少量のロウ材により、上記電子部品の電極と、貫通導体の端部との間における電気的導通を確実且つ容易に取ることが可能となる。
尚、前記貫通導体の端部は、前記導体層の上面よりも、少なくとも数10μm程度上方に突出している。
The present invention also includes a wiring board (Claim 4) in which the end portion of the through conductor protrudes upward from the upper surface of the flange portion.
According to this, the end of the through conductor and the electrode of the electronic component to be mounted on the surface of the substrate body are in direct contact with each other, or through a thin film of brazing material sandwiched between the two. Thus, the electronic component can be mounted by brazing. As a result, with a relatively small amount of brazing material, it is possible to reliably and easily establish electrical continuity between the electrode of the electronic component and the end portion of the through conductor.
The end portion of the through conductor protrudes upward by at least several tens of μm from the upper surface of the conductor layer.

加えて、本発明には、前記フランジ部は、前記導体層の上面における前記貫通導体の周囲側のみを被覆している、配線基板(請求項5)も含まれる。
これによれば、前記フランジ部は、前記導体層の上面における前記貫通導体の周囲側のみを被覆しており、且つ該導体層の上面における上記周囲側を含む周辺側を被覆していない。その結果、前記貫通導体の端部に加えて、導体層の上面における周辺側との間においても、実装すべき電子部品の電極との間で更にロウ付けすることで、一層確実な電気的導通を確保することが可能となる。
In addition, the present invention includes a wiring board (Claim 5) in which the flange portion covers only the peripheral side of the through conductor on the upper surface of the conductor layer.
According to this, the flange portion covers only the peripheral side of the through conductor on the upper surface of the conductor layer, and does not cover the peripheral side including the peripheral side on the upper surface of the conductor layer. As a result, in addition to the end portion of the through conductor, it is further brazed between the peripheral side of the upper surface of the conductor layer and the electrode of the electronic component to be mounted, thereby further ensuring electrical conduction. Can be secured.

一方、本発明による配線基板の製造方法(請求項6)は、単数の絶縁層からなるか、あるいは複数の絶縁層を積層してなり、一対の表面を有する基板本体と、該基板本体において、少なくとも1つの絶縁層における少なくとも一方の表面に形成された導体層と、該導体層を表面に有する上記絶縁層を貫通し、且つ該導体層をも連続して貫通する貫通導体と、を備えた配線基板の製造方法であって、上記絶縁層における少なくとも一方の表面に導体層を形成した導体付き絶縁層を準備する工程と、上記絶縁層および上記導体層を連続して貫通する貫通孔を形成する工程と、該貫通孔の開口部を囲む通し孔を有するマスクを上記導体層の上面に載置した状態で、上記貫通孔および通し孔に樹脂を含む導電性ペーストを充填する工程と、上記マスクを除去すると共に、上記貫通孔および通し孔に充填された導電性ペーストに含まれる樹脂を、上記貫通孔の周縁から上記導体層の上面に沿って該貫通孔の外周側に流れ出させることで、上記樹脂を含むフランジ部を形成する工程と、上記導電性ペーストおよびフランジ部を硬化処理する工程と、を含む、ことを特徴とする。   On the other hand, a method of manufacturing a wiring board according to the present invention (Claim 6) comprises a substrate body comprising a single insulating layer or a plurality of insulating layers, and having a pair of surfaces. A conductor layer formed on at least one surface of at least one insulating layer; and a through conductor penetrating the insulating layer having the conductor layer on the surface and continuously penetrating the conductor layer. A method for manufacturing a wiring board, comprising: preparing a conductive insulating layer in which a conductive layer is formed on at least one surface of the insulating layer; and forming a through hole that continuously penetrates the insulating layer and the conductive layer Filling a conductive paste containing a resin into the through hole and the through hole in a state where a mask having a through hole surrounding the opening of the through hole is placed on the upper surface of the conductor layer; mask And removing the resin contained in the conductive paste filled in the through hole and the through hole from the periphery of the through hole along the upper surface of the conductor layer to the outer peripheral side of the through hole. The method includes a step of forming a flange portion including a resin, and a step of curing the conductive paste and the flange portion.

これによれば、前記貫通孔の開口部を囲む通し孔を有するマスクを前記導体層の上面に載置した状態で、上記貫通孔および通し孔に導電性ペーストを充填した後、上記マスクを除去するとほぼ同時に、上記マスク厚みに相当する厚さの導電性ペーストの周囲から上記導体層の上面に沿って貫通孔の径方向に拡がるように、液状の樹脂が流れ出てフランジ部が形成される。そして、該フランジ部を導電性ペーストと共に硬化処理することによって、前記フランジを有する貫通導体、該貫通導体が貫通する導体層を含むと共に、前記マイグレーションに伴うショートが生じにくい前記配線基板を確実に製造することが可能となる。   According to this, with the mask having a through hole surrounding the opening of the through hole being placed on the upper surface of the conductor layer, the mask is removed after the through hole and the through hole are filled with the conductive paste. At substantially the same time, the liquid resin flows out from the periphery of the conductive paste having a thickness corresponding to the mask thickness so as to expand in the radial direction of the through hole along the upper surface of the conductor layer, thereby forming a flange portion. Then, by curing the flange portion together with the conductive paste, the wiring board including the through conductor having the flange and the conductor layer through which the through conductor penetrates is reliably manufactured. It becomes possible to do.

尚、前記貫通孔は、レーザ加工あるいはパンチングによって形成され、レーザ加工による場合の最大開口径は、例えば、約40〜50μmである。
また、前記導電性ペーストは、例えば、Ag粒子(約90wt%、平均粒径数μm(5μm未満))、エポキシ樹脂(約10wt%)、および溶剤などからなる。
更に、前記絶縁層と導体層とは、例えば、ポリイミド樹脂製のシートの片面に銅箔を予め貼り付けた導体付き絶縁層を用い、該Cu箔に対し、フォトリソグラフィ技術を施すことで、平面視で所要パターンを呈する前記導体層が成形される。
加えて、前記フランジ部は、主に液状のエポキシ樹脂と溶剤とからなり、前記マスクを除去した直後に、該マスクの通し孔に隣接していた位置から(表面)導体層の上面において貫通孔のほぼ径方向に沿って流れ出た樹脂系の組成物であり、硬化処理(約100〜200℃に加熱する所謂キュア処理)することにより、平面視でほぼ円形状あるいは非円形状(例えば、花弁形状、アメーバ状など)になって硬化する。
The through hole is formed by laser processing or punching, and the maximum opening diameter in the case of laser processing is, for example, about 40 to 50 μm.
The conductive paste is made of, for example, Ag particles (about 90 wt%, average particle size of several μm (less than 5 μm)), epoxy resin (about 10 wt%), and a solvent.
Furthermore, the insulating layer and the conductor layer are formed by, for example, using an insulating layer with a conductor in which a copper foil is bonded in advance on one side of a sheet made of polyimide resin, and applying a photolithography technique to the Cu foil. The said conductor layer which exhibits a required pattern visually is shape | molded.
In addition, the flange portion is mainly composed of a liquid epoxy resin and a solvent, and immediately after the mask is removed, a through hole is formed on the upper surface of the conductor layer from a position adjacent to the through hole of the mask. Is a resin-based composition that has flowed out substantially along the radial direction, and is substantially circular or non-circular (for example, petals) in a plan view by being cured (a so-called curing process that is heated to about 100 to 200 ° C.). Shape, amoeba, etc.) and cured.

また、本発明には、前記マスクに開設される通し孔の内径は、前記導体層の上面に開口する前記貫通孔の内径と同じか、該貫通孔の内径よりも大きい、配線基板の製造方法(請求項7)も含まれる。
これによれば、前記マスクに開設される通し孔の内径と前記導体層の上面に開口する前記貫通孔の内径と同じである場合、貫通導体には、その直径とほぼ同じ外径の端部を形成できる。一方、上記通し孔の内径が上貫通孔の内径よりも大きい場合、貫通導体には、その直径よりも太径の端部を形成できる。その結果、例えば、貫通導体の端部を主体に実装する電子部品の電極との導通を取ったり、あるいは、貫通導体の端部と導体層の上面における周辺側との双方によって、実装する電子部品の電極との導通を取ることを、容易に設設計することが可能となる。
Further, in the present invention, the inner diameter of the through hole opened in the mask is the same as or larger than the inner diameter of the through hole opened on the upper surface of the conductor layer. (Claim 7) is also included.
According to this, when the inner diameter of the through hole opened in the mask is the same as the inner diameter of the through hole opened on the upper surface of the conductor layer, the through conductor has an end portion having an outer diameter substantially the same as the diameter. Can be formed. On the other hand, when the inner diameter of the through hole is larger than the inner diameter of the upper through hole, an end portion having a diameter larger than the diameter can be formed on the through conductor. As a result, for example, an electrical component that is electrically connected to an electrode of an electronic component that mainly mounts the end portion of the through conductor, or is mounted by both the end portion of the through conductor and the peripheral side on the upper surface of the conductor layer. It is possible to easily design and establish the conduction with the electrodes.

更に、本発明には、前記フランジ部は、前記導体層の上面における前記貫通導体の周囲側のみを被覆している、配線基板の製造方法(請求項8)も含まれる。
これによれば、前記導体層の上面における周囲側を含む周辺側は、前記フランジ部に被覆されていないので、該導体層の周辺側をも含めて、実装すべき出新部品との導通を取ったり、あるいは厚み方向で隣接する絶縁層に形成された別の貫通導体との導通を取る場合にも、容易に対応することが可能となる。
Furthermore, the present invention includes a method for manufacturing a wiring board (Claim 8) in which the flange portion covers only the peripheral side of the through conductor on the upper surface of the conductor layer.
According to this, since the peripheral side including the peripheral side on the upper surface of the conductor layer is not covered with the flange portion, the conductive layer can be electrically connected to the new parts to be mounted including the peripheral side of the conductor layer. It is possible to easily cope with the case of taking electrical conductivity with another through conductor formed in an insulating layer adjacent in the thickness direction.

本発明による一形態の配線基板の要部を示す垂直断面図。The vertical sectional view showing the important section of the wiring board of one form by the present invention. 図1に示す配線基板の要部の平面図。The top view of the principal part of the wiring board shown in FIG. 上記配線基板の応用形態である配線基板の要部を示す垂直断面図。The vertical sectional view showing the important section of the wiring board which is an application form of the wiring board. 本発明による異なる形態の配線基板の要部を示す垂直断面図。The vertical sectional view which shows the principal part of the wiring board of a different form by this invention. 図4中の一点鎖線部分Xの部分拡大図。The elements on larger scale of the dashed-dotted line part X in FIG. (A),(B)は図1の配線基板を得るための製造工程を示す概略図。(A), (B) is the schematic which shows the manufacturing process for obtaining the wiring board of FIG. (A),(B)は図6に続く製造工程を示す概略図。(A), (B) is the schematic which shows the manufacturing process following FIG. (A),(B)は図7に続く製造工程を示す概略図。(A), (B) is the schematic which shows the manufacturing process following FIG. (A),(B)は図8に続く製造工程と得られた配線基板とを示す概略図。(A), (B) is the schematic which shows the manufacturing process following FIG. 8, and the obtained wiring board. (A),(B)は図3の配線基板を得るための製造工程を示す概略図。(A), (B) is the schematic which shows the manufacturing process for obtaining the wiring board of FIG. (A),(B)は別形態の配線基板を得るための製造工程を示す概略図。(A), (B) is the schematic which shows the manufacturing process for obtaining the wiring board of another form. (A),(B)は図11に続く製造工程を示す概略図。(A), (B) is the schematic which shows the manufacturing process following FIG. 図4で示した配線基板を得るための一製造工程を示す概略図。Schematic which shows one manufacturing process for obtaining the wiring board shown in FIG. 図13に続く製造工程と得られた配線基板の要部とを示す概略図。Schematic which shows the manufacturing process following FIG. 13, and the principal part of the obtained wiring board.

以下において、本発明を実施するための形態について説明する。
図1は、本発明による一形態の配線基板1aの要部を示す垂直断面図、図2は、図1の平面図である。
配線基板1aは、図1,図2に示すように、ポリイミドからなる単層の絶縁層rからなり、表面3および裏面(表面)4を有する基板本体2と、該基板本体2の表面3に比較的高密度で形成された複数の表面導体層(導体層)10と、上記基板本体2の表面3と裏面4との間を貫通し、且つ上記表面導体層10をも連続して貫通する貫通孔5に形成された貫通導体6とを備えている。前記貫通導体6の上端側には、表面導体層10の上面に沿って貫通導体6の径方向に拡がるフランジ部8が該貫通導体6と一体に接続されている。該フランジ部8の厚みは、約数μm〜10μmである。かかるフランジ部8の上面よりも上方(外側)には、約数10μm(例えば、20〜30μm)程度の高さで突出する貫通導体6の端部7が立設されている。
尚、前記貫通孔5は、パンチングによる打ち抜き加工により軸方向が直線状の円筒形を呈するが、例えば、前記基板本体2の表面3側からレーザを照射するレーザ加工により形成した場合には、表面3から裏面4に向かって徐々に直径が小さくなるテーパを有するほぼ円錐形状となり、前記貫通導体6も該形状と相似形になる。
また、前記基板本体2の裏面4には、各貫通導体6の下端部と個別に接続する裏面端子12が形成されている。
Hereinafter, modes for carrying out the present invention will be described.
FIG. 1 is a vertical sectional view showing an essential part of a wiring board 1a according to an embodiment of the present invention, and FIG. 2 is a plan view of FIG.
As shown in FIGS. 1 and 2, the wiring board 1 a is composed of a single-layer insulating layer r made of polyimide, a substrate body 2 having a front surface 3 and a back surface (front surface) 4, and a surface 3 of the substrate body 2. A plurality of surface conductor layers (conductor layers) 10 formed at a relatively high density, and between the front surface 3 and the back surface 4 of the substrate body 2, and also continuously penetrate the surface conductor layer 10. And a through conductor 6 formed in the through hole 5. A flange portion 8 extending in the radial direction of the through conductor 6 along the upper surface of the surface conductor layer 10 is integrally connected to the upper end side of the through conductor 6. The flange portion 8 has a thickness of about several μm to 10 μm. Above the upper surface of the flange portion 8 (outside), an end portion 7 of the penetrating conductor 6 protruding at a height of about several tens of μm (for example, 20 to 30 μm) is provided upright.
The through-hole 5 has a cylindrical shape with a linear axial direction by punching by punching. For example, when the through-hole 5 is formed by laser processing in which laser is irradiated from the surface 3 side of the substrate body 2, 3 has a substantially conical shape with a taper that gradually decreases in diameter from the back surface 4 toward the back surface 4, and the through conductor 6 also has a similar shape to the shape.
Further, a back surface terminal 12 is formed on the back surface 4 of the substrate body 2 so as to be individually connected to the lower end portion of each through conductor 6.

図1,図2に示すように、フランジ部8の外縁9は、表面導体層10の上面における貫通導体6の周囲側のみを被覆しており、換言すれば、表面導体層10の上面における周囲側を囲む周辺側は、上記フランジ部8には、被覆されていない。
前記貫通導体6は、主にAgからなり、表面導体層10および裏面端子12は、Cuからなる。一方、前記フランジ部8は、主にエポキシ系樹脂からなるが、前記貫通導体6の周囲に近付くに連れて、Ag粉末の含有量が傾斜状に増加する複合材の組成を有している。
そのため、少なくとも、前記フランジ部8の外縁9側の導電率は、貫通導体6の導電率よりも約10mS/cm(比で約30〜50%)程度低くなっている。また、前記フランジ部8を構成するエポキシ樹脂の吸水率は、前記絶縁層rを形成するポリイミドの吸水率よりも約10%程度小さい。
As shown in FIGS. 1 and 2, the outer edge 9 of the flange portion 8 covers only the peripheral side of the through conductor 6 on the upper surface of the surface conductor layer 10, in other words, the periphery on the upper surface of the surface conductor layer 10. The peripheral side surrounding the side is not covered with the flange portion 8.
The through conductor 6 is mainly made of Ag, and the front conductor layer 10 and the back terminal 12 are made of Cu. On the other hand, the flange portion 8 is mainly made of an epoxy resin, and has a composition of a composite material in which the content of Ag powder increases in an inclined manner as it approaches the periphery of the through conductor 6.
Therefore, at least the conductivity on the outer edge 9 side of the flange portion 8 is about 10 mS / cm lower than the conductivity of the through conductor 6 (roughly about 30 to 50%). Further, the water absorption rate of the epoxy resin constituting the flange portion 8 is about 10% smaller than the water absorption rate of the polyimide forming the insulating layer r.

尚、前記フランジ部8の外縁9側に含まれる樹脂の吸水率は、以下の方法(1),(2)によって測定した。
(1)フランジ部8の外縁9側に含まれる樹脂の組成を、EDS(エネルギー分散型X線分光法)分析、あるいはFT−IR(フーリエ変換赤外分光法)分析の何れかで特定する。
(2)上記(1)により特定された樹脂と同じ材料であって、吸水率を測定するのに十分なサイズを有するサンプルを準備し、IPC−TM−650 2.6.2の規格に準じた以下の(a)〜(c)の手順によって吸水率を測定する。
(a)乾燥時のサンプルの重量W1を測定する。
(b)水に浸した後の上記サンプルの重量W2を測定する。
(c)吸水率(%)を「(W1−W2)/W1×100」の式により算出する。
また、前記絶縁層rや後述する絶縁層r1の吸水率も上記方法によって測定した。
The water absorption rate of the resin contained on the outer edge 9 side of the flange portion 8 was measured by the following methods (1) and (2).
(1) The composition of the resin contained on the outer edge 9 side of the flange portion 8 is specified by either EDS (energy dispersive X-ray spectroscopy) analysis or FT-IR (Fourier transform infrared spectroscopy) analysis.
(2) Prepare a sample that is the same material as the resin specified in (1) and has a sufficient size for measuring the water absorption, and conforms to the standard of IPC-TM-650 2.6.2. Further, the water absorption is measured by the following procedures (a) to (c).
(a) The weight W1 of the sample at the time of drying is measured.
(b) The weight W2 of the sample after being immersed in water is measured.
(c) The water absorption rate (%) is calculated by the formula “(W1−W2) / W1 × 100”.
Moreover, the water absorption rate of the insulating layer r and an insulating layer r1 described later was also measured by the above method.

図1中の右上に示すように、表面導体層10の上面における周辺側、フランジ部8の上面、および貫通導体6の端部7の上に、例えば、Auロウからなるロウ材13を介して、ICチップなどの電子部品14を実装する場合、かかる電子部品14の底面に位置する電極(図示せず)と上記端部7とは、直に面接触するか、あるいは薄いAgロウの膜を挟んで接近する。一方、上記電極と表面導体層10の上面における周辺側とは、上記ロウ材13を介して接合される。端部7が上方に突出しているので、上記ロウ材13の使用量を低減することが可能となる。   As shown in the upper right in FIG. 1, on the peripheral side on the upper surface of the surface conductor layer 10, the upper surface of the flange portion 8, and the end portion 7 of the through conductor 6, for example, via a brazing material 13 made of Au brazing. When an electronic component 14 such as an IC chip is mounted, an electrode (not shown) located on the bottom surface of the electronic component 14 and the end portion 7 are in direct surface contact with each other, or a thin Ag wax film is formed. Get close together. On the other hand, the electrode and the peripheral side on the upper surface of the surface conductor layer 10 are joined via the brazing material 13. Since the end portion 7 protrudes upward, the amount of the brazing material 13 used can be reduced.

以上のような配線基板1aでは、前記フランジ部8の少なくとも外縁9側の導電率が、前記貫通導体6の導電率よりも低く、且つ上記フランジ部8に含まれるエポキシ樹脂の吸水率が、前記絶縁層rを構成するポリイミドの吸水率よりも小さい。そのため、上記フランジ部8が上面に形成された表面導体層10と、該表面導体層10に隣接して形成された別の表面導体層10や該別の表面導体層10の上面に位置する別のフランジ部8との間において、前述した金属原子が移動して生じるマイグレーションをなくすか抑制することができる。その結果、隣接する表面導体層10同士間や隣接する貫通導体6同士間における不用意なショートを防ぐことができる。
しかも、前記フランジ部8が貫通導体6と一体であり、該貫通導体6が貫通している前記表面導体層10との接触面積が比較的大きいので、該表面導体層10と貫通導体6との密着強度および電気的な接続を容易に確保することもできる。従って、基板本体2の表面3上に電子部品14を高密度で実装することができる。
In the wiring board 1a as described above, the conductivity of at least the outer edge 9 side of the flange portion 8 is lower than the conductivity of the through conductor 6, and the water absorption rate of the epoxy resin contained in the flange portion 8 is It is smaller than the water absorption rate of the polyimide constituting the insulating layer r. Therefore, the surface conductor layer 10 having the flange portion 8 formed on the upper surface, another surface conductor layer 10 formed adjacent to the surface conductor layer 10, and another surface conductor layer 10 positioned on the upper surface of the other surface conductor layer 10. The migration caused by the movement of the metal atoms described above can be eliminated or suppressed. As a result, an inadvertent short circuit between adjacent surface conductor layers 10 or between adjacent through conductors 6 can be prevented.
In addition, since the flange portion 8 is integral with the through conductor 6 and the contact area with the surface conductor layer 10 through which the through conductor 6 penetrates is relatively large, the surface conductor layer 10 and the through conductor 6 Adhesion strength and electrical connection can be easily ensured. Therefore, the electronic components 14 can be mounted on the surface 3 of the board body 2 with high density.

図3は、前記配線基板1aの応用形態である配線基板1bの要部を示す垂直断面図である。
配線基板1bは、図3に示すように、前記絶縁層rのみからなる基板本体2と、該基板本体2の表面3および裏面4に個別に形成した前記同様の表面導体層10および裏面導体層(表面導体層、導体層)11と、上記絶縁層r、表面導体層10、および裏面導体層11を連続して貫通する貫通孔5内に形成された貫通導体6とを備えている。表面導体層10の上面、および裏面導体層11の下面(上面)には、上記貫通導体6から径方向に沿って拡がるフランジ部8がほぼ上下対称に形成されている。尚、貫通導体6は、裏面4側にも端部7が突出している。
前記フランジ部8は、図3に示すように、その外縁9側の外領域8bと、貫通導体6の周囲側の内領域8aとからなる。このうち、外縁9側の外領域8bは、主にエポキシ樹脂からなるため、その導電率は、貫通導体6の導電率よりも低い。一方、上記内領域8aは、外領域8bよりも比較的Ag粉末を多く含んでいる。
FIG. 3 is a vertical sectional view showing a main part of a wiring board 1b which is an applied form of the wiring board 1a.
As shown in FIG. 3, the wiring board 1 b includes a substrate body 2 made of only the insulating layer r, and the same surface conductor layer 10 and back surface conductor layer that are individually formed on the front surface 3 and the back surface 4 of the substrate body 2. (Surface conductor layer, conductor layer) 11 and a through conductor 6 formed in a through hole 5 that continuously penetrates the insulating layer r, the surface conductor layer 10, and the back conductor layer 11. On the upper surface of the front surface conductor layer 10 and the lower surface (upper surface) of the back surface conductor layer 11, flange portions 8 extending in the radial direction from the through conductor 6 are formed substantially symmetrically. In addition, the end portion 7 of the through conductor 6 protrudes also on the back surface 4 side.
As shown in FIG. 3, the flange portion 8 includes an outer region 8 b on the outer edge 9 side and an inner region 8 a on the peripheral side of the through conductor 6. Among these, the outer region 8 b on the outer edge 9 side is mainly made of an epoxy resin, and therefore its conductivity is lower than the conductivity of the through conductor 6. On the other hand, the inner region 8a contains a relatively larger amount of Ag powder than the outer region 8b.

図3中の右下に示すように、前記基板本体2の裏面4に形成された裏面導体層11、フランジ部8、および貫通導体6の端部7の下側には、前記同様で且つ比較的少量のロウ材13を介して、下方に延びたピン本体18を含む導体ピン16の基フランジ17が接合される。
以上のような配線基板1bによれば、前記配線基板1aと同様な効果を奏すると共に、比較的少量のロウ材13を介して導体ピン16を接合でき、該配線基板1bを搭載すべきマザーボードとの電気的接続も容易且つ確実に取ることが可能となる。
尚、前記配線基板1a,1bにおける絶縁層rは、例えば、アルミナを主成分とするセラミックからなるものとしても良い。但し、前記フランジ部に含まれる樹脂の吸水率は、上記セラミックの吸水率よりも小さいことが望ましい。
As shown in the lower right in FIG. 3, the backside conductor layer 11 formed on the backside 4 of the substrate body 2, the flange portion 8, and the lower side of the end portion 7 of the through conductor 6 are similar to the above and compared. The base flange 17 of the conductor pin 16 including the pin body 18 extending downward is joined via a small amount of brazing material 13.
According to the wiring board 1b as described above, the same effect as that of the wiring board 1a can be obtained, and the conductor pins 16 can be joined via a relatively small amount of the brazing material 13, so that the wiring board 1b can be mounted on the motherboard. It is also possible to easily and surely take the electrical connection.
The insulating layer r in the wiring boards 1a and 1b may be made of a ceramic mainly composed of alumina, for example. However, it is desirable that the water absorption rate of the resin contained in the flange portion is smaller than the water absorption rate of the ceramic.

図4は、異なる形態の配線基板20の要部を示す垂直断面図、図5は、図4中の一点鎖線部分Xの部分拡大図である。
配線基板20は、図4に示すように、ポリイミドからなる前記同様の絶縁層r1,r2を積層した上層側の樹脂絶縁部2aと、例えば、アルミナを主成分とするセラミックの絶縁層c1〜c3を積層した下層側のセラミック絶縁部2bとを積層してなり、表面23および裏面(表面)24を有する基板本体22を備えている。
図4,図5に示すように、上層側の樹脂絶縁部2aは、表面23に複数の表面導体層10が比較的接近して形成され、該表面導体層10および絶縁層r1を貫通する貫通導体6の上端側には、上記導体層10の上面における貫通導体6の径方向に沿って拡がる前記同様のフランジ部8と、該フランジ部8の上面よりも上方に突出する前記同様の端部7とが形成されている。
FIG. 4 is a vertical cross-sectional view showing the main part of the wiring board 20 of a different form, and FIG. 5 is a partially enlarged view of a one-dot chain line part X in FIG.
As shown in FIG. 4, the wiring board 20 includes an upper resin insulating portion 2a in which the same insulating layers r1 and r2 made of polyimide are laminated, and ceramic insulating layers c1 to c3 mainly composed of alumina, for example. A substrate body 22 having a front surface 23 and a back surface (front surface) 24 is provided.
As shown in FIGS. 4 and 5, the resin insulating portion 2a on the upper layer side has a plurality of surface conductor layers 10 formed relatively close to the surface 23, and penetrates through the surface conductor layer 10 and the insulating layer r1. On the upper end side of the conductor 6, the same flange portion 8 extending along the radial direction of the through conductor 6 on the upper surface of the conductor layer 10, and the same end portion protruding upward from the upper surface of the flange portion 8. 7 are formed.

また、絶縁層r1,r2の層間には、複数の層間導体層(導体層)19が形成され、該導体層19および絶縁層r2を連続して貫通する複数の貫通導体6が、最上層の絶縁層r1を貫通する前記貫通導体6よりも、図4で左右方向に沿って互いの間隔を大きくなるようにして形成されている。図5に示すように、絶縁層r1,r2の層間に位置する複数の層間導体層19ごとの上面にも、貫通導体6の径方向に沿って拡がり且つ前記同様の領域8a,8bからなるフランジ部8が形成されている。該フランジ部8の外縁9は、上記層間導体層19の上面における貫通導体6の周縁と上記層間導体層19の外縁との中間に位置している。換言すれば、上記フランジ部8は、上記層間導体層19の上面における前記貫通導体6の周囲側のみを被覆している。
尚、絶縁層r2を貫通する貫通導体6の上端には、フランジ部8の上面から上方に突出する前記端部7がなく、絶縁層r1を貫通する貫通導体6の下端とほぼ直に接続している。上記端部7がないのは、後述する製造方法の積層および圧着工程で、上下の貫通導体6同士の当接により、圧縮されたことによる。また、図5中の符号wは、接着剤層を示す。
In addition, a plurality of interlayer conductor layers (conductor layers) 19 are formed between the insulating layers r1 and r2, and the plurality of through conductors 6 continuously passing through the conductor layer 19 and the insulating layer r2 are formed on the uppermost layer. It is formed so that the interval between the through conductors 6 penetrating the insulating layer r1 is larger along the horizontal direction in FIG. As shown in FIG. 5, the flange which extends along the radial direction of the through conductor 6 also on the upper surface of each of the plurality of interlayer conductor layers 19 located between the insulating layers r1 and r2 and includes the same regions 8a and 8b as described above. Part 8 is formed. The outer edge 9 of the flange portion 8 is located between the periphery of the through conductor 6 and the outer edge of the interlayer conductor layer 19 on the upper surface of the interlayer conductor layer 19. In other words, the flange portion 8 covers only the peripheral side of the through conductor 6 on the upper surface of the interlayer conductor layer 19.
Note that the upper end of the through conductor 6 that penetrates the insulating layer r2 does not have the end portion 7 protruding upward from the upper surface of the flange portion 8, and is connected almost directly to the lower end of the through conductor 6 that penetrates the insulating layer r1. ing. The absence of the end portion 7 is due to compression by contact between the upper and lower through conductors 6 in the laminating and crimping steps of the manufacturing method described later. Moreover, the code | symbol w in FIG. 5 shows an adhesive bond layer.

また、図4に示すように、下層側の前記セラミック絶縁部2bは、最上層の絶縁層c1の表面に形成され、且つ前記絶縁層r2を貫通する貫通導体6ごとの下端と接続する複数の配線層25と、最下層の絶縁層c3の裏面24に形成された複数の裏面端子27と、これらを個別に接続し且つこれらの間に位置する絶縁層c1〜c3を直線的に貫通する複数のビア導体26と、を備えている。尚、上記配線層25、裏面端子27、およびビア導体26は、WまたはMoからなる。
図4,図5に示すように、基板本体22の表面23に位置する複数の貫通導体6の端部7ごとの上方には、前記同様のロウ材13を介して、追って複数のプローブピン29の基フランジ28が個別に接合される。該プローブピン29は、図示しないSiウェハの表面に形成された多数の電子部品の電気的特性を検査するために用いられる。
即ち、前記配線基板20は、電子部品の検査用配線基板であり、基板本体22の表面23側に複数のプローブピン29を高密度で配設するためのものである。
Further, as shown in FIG. 4, the ceramic insulating portion 2b on the lower layer side is formed on the surface of the uppermost insulating layer c1 and is connected to the lower ends of the through conductors 6 penetrating the insulating layer r2. A wiring layer 25, a plurality of back surface terminals 27 formed on the back surface 24 of the lowermost insulating layer c3, and a plurality of the insulating layers c1 to c3 that are individually connected and linearly penetrate therebetween. Via conductor 26. The wiring layer 25, the back terminal 27, and the via conductor 26 are made of W or Mo.
As shown in FIGS. 4 and 5, a plurality of probe pins 29 are disposed above the end portions 7 of the plurality of through conductors 6 positioned on the surface 23 of the substrate body 22 via the brazing material 13 similar to the above. The base flanges 28 are individually joined. The probe pins 29 are used for inspecting the electrical characteristics of a large number of electronic components formed on the surface of a Si wafer (not shown).
That is, the wiring board 20 is a wiring board for inspection of electronic components, and is for arranging a plurality of probe pins 29 at a high density on the surface 23 side of the board body 22.

以上のような配線基板20では、基板本体22の表面23上および絶縁層r1,r2間付近に形成された各フランジ部8の少なくとも外縁9側の導電率が、前記貫通導体6の導電率よりも低く、且つ上記フランジ部8に含まれるエポキシ樹脂の吸水率が、前記絶縁層r1,r2を形成するポリイミドの吸水率よりも小さい。そのため、上記フランジ部8が上面に形成された表面導体層10あるいは層間導体層19と、該表面導体層10あるいは層間導体層19に隣接して形成された別の表面導体層10、あるいは層間導体層19や別の表面導体層10、あるいは別の層間導体層19の上面に位置する各フランジ部8との間において、前記同様にマイグレーションが生じにくくなる。その結果、前記表面3や絶縁層r1,r2間において隣接する上記導体層10,19同士間や、隣接する貫通導体6同士間における不用意なショートを確実に防ぐことができる。
更に、前記同様にして、前記導体層10,19と貫通導体6との密着強度および電気的な接続を容易に確保することもできる。従って、検査すべき多数の電子部品の電気的特性を正確に測定できる配線基板20となっている。
In the wiring board 20 as described above, the conductivity of at least the outer edge 9 side of each flange portion 8 formed on the surface 23 of the substrate body 22 and between the insulating layers r1 and r2 is greater than the conductivity of the through conductor 6. And the water absorption of the epoxy resin contained in the flange portion 8 is smaller than the water absorption of the polyimide forming the insulating layers r1 and r2. Therefore, the surface conductor layer 10 or the interlayer conductor layer 19 having the flange portion 8 formed on the upper surface, and another surface conductor layer 10 or the interlayer conductor formed adjacent to the surface conductor layer 10 or the interlayer conductor layer 19. Migration is less likely to occur between the layer 19, another surface conductor layer 10, or each flange portion 8 located on the upper surface of another interlayer conductor layer 19 as described above. As a result, an inadvertent short circuit between the conductor layers 10 and 19 adjacent between the surface 3 and the insulating layers r1 and r2 and between the adjacent through conductors 6 can be reliably prevented.
Further, in the same manner as described above, the adhesion strength and electrical connection between the conductor layers 10 and 19 and the through conductor 6 can be easily ensured. Accordingly, the wiring board 20 can accurately measure the electrical characteristics of a large number of electronic components to be inspected.

以下において、前記配線基板1aを得るための製造方法について説明する。
予め、図6(A)に示すように、ポリイミドからなる絶縁層rの表面3に銅箔からなる導体層10aを積層した導体付き絶縁層Z1を準備した。
次に、図6(A)中の矢印で示すように、導体付き絶縁層Z1の導体層10a側から、所定の位置ごとレーザLを照射した。尚、該レーザLには、UVレーザを用いた。その結果、図6(B)に示すように、導体層10aと絶縁層rの裏面4との間に、上端の開口径が約40μmであり、内面に僅かなテーパを有する貫通孔5が所定位置ごとに形成された。
次いで、図7(A)に示すように、上記貫通孔5の開口部を囲み且つ該開口部と同じ内径の通し孔32を有し、且つ厚みが数10μmのスクリーンマスク(マスク)30を、上記貫通孔5と通し孔32とが同心となるように、前記導体付き絶縁層Z1の導体層10a上に載置した。かかる状態で、図7(B)に示すように、上記通し孔32と貫通孔5とに対し、Ag粉末とエポキシ樹脂とを含む導電性ペースト34を充填した。該導電性ペースト34は、貫通孔5内を埋めた貫通部36と、通し孔32内の上端部37とからなる。
Below, the manufacturing method for obtaining the said wiring board 1a is demonstrated.
As shown in FIG. 6A, an insulating layer Z1 with a conductor in which a conductor layer 10a made of copper foil was laminated on the surface 3 of an insulating layer r made of polyimide was prepared in advance.
Next, as indicated by an arrow in FIG. 6A, the laser L was irradiated from the conductor layer 10a side of the insulating layer with conductor Z1 at a predetermined position. For the laser L, a UV laser was used. As a result, as shown in FIG. 6B, a through hole 5 having an opening diameter of about 40 μm at the upper end and a slight taper on the inner surface is provided between the conductor layer 10a and the back surface 4 of the insulating layer r. Formed for each position.
Next, as shown in FIG. 7A, a screen mask (mask) 30 that surrounds the opening of the through hole 5 and has a through hole 32 having the same inner diameter as the opening and has a thickness of several tens of μm, The through hole 5 and the through hole 32 were placed on the conductor layer 10a of the insulating layer with conductor Z1 such that the through hole 5 and the through hole 32 were concentric. In this state, as shown in FIG. 7B, the through hole 32 and the through hole 5 were filled with a conductive paste 34 containing Ag powder and an epoxy resin. The conductive paste 34 includes a through portion 36 that fills the through hole 5 and an upper end portion 37 in the through hole 32.

尚、前記導電性ペースト34は、例えば、Ag粒子(約90wt%、平均粒径数μm(5μm未満))、エポキシ樹脂(約10wt%)、および若干の溶剤などからなる。
引き続いて、図8(A)に示すように、前記マスク30を前記導体層10aの上から除去した。かかる除去とほぼ同時に、図8(B)中の矢印で示すように、前記導電性ペースト34に含まれていた液状のエポキシ樹脂が、導体層10aの上面を前記貫通孔5の径方向に沿って、該貫通孔5の周縁からその外周側に向かって流れ出た。その結果、上記樹脂を主成分とし、且つ平面視がほぼ円形状を呈するフランジ部38が前記導電性ペースト34の上端側と一体に形成された。
また、前記絶縁層rの裏面4における貫通導体6の下端面が露出する位置ごとにも、スクリーンマスクを介して、前記同様の導電性ベーストを所定パターンで形成して、未硬化状態である複数の裏面端子12(図示せず)を形成した。
The conductive paste 34 is made of, for example, Ag particles (about 90 wt%, average particle size of several μm (less than 5 μm)), epoxy resin (about 10 wt%), and some solvent.
Subsequently, as shown in FIG. 8A, the mask 30 was removed from above the conductor layer 10a. At substantially the same time as the removal, as shown by the arrow in FIG. 8B, the liquid epoxy resin contained in the conductive paste 34 passes the upper surface of the conductor layer 10a along the radial direction of the through hole 5. Then, it flowed from the peripheral edge of the through hole 5 toward the outer peripheral side. As a result, a flange portion 38 containing the resin as a main component and having a substantially circular shape in plan view was formed integrally with the upper end side of the conductive paste 34.
In addition, a conductive pattern similar to the above is formed in a predetermined pattern via a screen mask at each position where the lower end surface of the through conductor 6 is exposed on the back surface 4 of the insulating layer r, and a plurality of uncured states are formed. Back terminal 12 (not shown) was formed.

更に、フランジ部38を含む前記導電性ペースト34および裏面端子12を、約100〜200℃に加熱する所謂キュア処理(硬化処理)を行うことによって、上記ペースト12中の樹脂バインダを硬化させた。
その結果、図9(A)に示すように、前記貫通部36は、主にAgからなる貫通導体6となり、その上端である端部7が下記のフランジ部8の上面よりも上方に突出しており、該端部7の周囲には、導体層10aの上面における貫通導体6の径方向に沿って拡がって硬化したエポキシ樹脂を主成分とする厚みが約数μm〜10μmのフランジ部8が形成された。
尚、上記フランジ部8のうち、貫通導体6の周囲側である内領域(8a)には、Ag粉末が若干残留していた。また、前記絶縁層rの裏面4には、図示しない複数の裏面端子12が硬化されていても良い。
そして、前記導体層10aを形成する銅箔に対し、その上面への感光性樹脂の被覆、該樹脂に対する紫外線のパターン照射、および現像(腐蝕)液の接触、および上記樹脂の剥離などからなるフォトリソグラフィ技術を用いたパターニングを施した。
Furthermore, the resin binder in the paste 12 was cured by performing a so-called curing process (curing process) in which the conductive paste 34 including the flange portion 38 and the back surface terminal 12 were heated to about 100 to 200 ° C.
As a result, as shown in FIG. 9A, the penetrating portion 36 becomes a penetrating conductor 6 mainly made of Ag, and an end portion 7 which is the upper end of the penetrating portion projects upward from the upper surface of the flange portion 8 described below. A flange 8 having a thickness of about several μm to 10 μm, which is mainly composed of an epoxy resin that spreads and hardens along the radial direction of the through conductor 6 on the upper surface of the conductor layer 10a, is formed around the end 7. It was done.
In the flange portion 8, a slight amount of Ag powder remained in the inner region (8 a) on the peripheral side of the through conductor 6. A plurality of back terminals 12 (not shown) may be cured on the back surface 4 of the insulating layer r.
The copper foil forming the conductor layer 10a is coated with a photosensitive resin on its upper surface, irradiated with an ultraviolet pattern on the resin, contacted with a developing (corrosion) solution, and peeling of the resin. Patterning using a lithography technique was performed.

その結果、図9(B)に示すように、前記導体層10aは、平面視で円形状を呈し且つその中心部を貫通導体6が貫通すると共に、上面における貫通導体6の周囲側に前記フランジ8が位置する表面導体層10となった。
最後に、外部に露出する前記貫通導体6の端部7、表面導体層10、および裏面端子12の表面に対し、電解メッキを施して、Niメッキ膜およびAuメッキ膜を順次被覆した。これによって、前記図1,図2で示した前記配線基板1aを得ることができた。
尚、前記貫通孔5は、パンチングによる打ち抜き加工、エッチング加工、あるいは炭酸ガスレーザやエキシマレーザなどの照射によって形成しても良い。
また、前記導体付き絶縁層Z1は、前記絶縁層rの表・裏面3,4の双方に銅箔からなる導体層10a,10bを予め形成した導体付き絶縁層Z2としても良い。
As a result, as shown in FIG. 9B, the conductor layer 10a has a circular shape in a plan view, and the through conductor 6 penetrates through the center of the conductor layer 10a, and the flange is formed around the through conductor 6 on the upper surface. The surface conductor layer 10 in which 8 is located was obtained.
Finally, the end portion 7 of the through conductor 6 exposed to the outside, the surface conductor layer 10 and the surface of the back terminal 12 were subjected to electrolytic plating to sequentially coat the Ni plating film and the Au plating film. As a result, the wiring board 1a shown in FIGS. 1 and 2 was obtained.
The through hole 5 may be formed by punching by punching, etching, or irradiation with a carbon dioxide laser or excimer laser.
The insulating layer with conductor Z1 may be an insulating layer with conductor Z2 in which conductor layers 10a and 10b made of copper foil are formed in advance on both the front and back surfaces 3 and 4 of the insulating layer r.

以上のような配線基板1aの製造方法によれば、前記貫通孔5の開口部を囲む通し孔32を有する前記マスク30を前記導体層10aの上面に載置して、上記貫通孔5と通し孔32とに導電性ペースト34を充填した後、上記マスク30を除去するとほぼ同時に、上記マスク30の厚みに相当する厚さの導電性ペースト34の周囲から上記導体層10aの上面に沿って上記貫通孔5の径方向に拡がるように、液状の樹脂が流れ出てフランジ部38が形成された。更に、該フランジ部38を導電性ペースト34と共に硬化処理することにより、前記フランジ8を有する貫通導体6、該貫通導体6が貫通する表面導体層10を含むと共に、前記マイグレーションに伴うショートが生じにくい配線基板1aを確実に製造することができた。   According to the method for manufacturing the wiring board 1a as described above, the mask 30 having the through hole 32 surrounding the opening of the through hole 5 is placed on the upper surface of the conductor layer 10a and is passed through the through hole 5. After filling the hole 32 with the conductive paste 34, the mask 30 is removed, and at the same time, from the periphery of the conductive paste 34 having a thickness corresponding to the thickness of the mask 30 along the upper surface of the conductor layer 10 a. The liquid resin flowed out so that the flange portion 38 was formed so as to expand in the radial direction of the through hole 5. Further, the flange portion 38 is cured together with the conductive paste 34 to include the through conductor 6 having the flange 8 and the surface conductor layer 10 through which the through conductor 6 penetrates, and a short circuit due to the migration hardly occurs. The wiring board 1a could be reliably manufactured.

図10は、前記配線基板1bの製造方法を説明する概略図である。
図10(A)に示すように、予め、前記絶縁層rの表・裏面3,4の双方に銅箔からなる導体層10a,10bを予め形成した導体付き絶縁層Z2を準備する工程と、該絶縁層Z2を打ち抜き加工して前記貫通孔5を形成する工程と、該貫通孔5の中間位置まで図示しない塞ぎ棒を導体層10b側の開口部から挿入し且つ導体層10aの開口部側に前記マスク30を配置した状態で、前記導電性ペースト34を充填する工程と、該ペースト34を硬化処理することにより貫通導体6aを形成する工程とを順次行った。そして、前記絶縁層Z2を上下逆にすることで、図10(A)に示す状態とした。
次に、図10(B)に示すように、前記貫通孔5の導体層10b側の開口部からも、前記導電性ペースト34を充填する工程と、該導電性ペースト34などを硬化処理することにより通導体36を形成する工程とを順次行った。更に、前記同様のメッキ工程を行った。その結果、前記図3で示した前記配線基板1bを得ることができた。
以上のような配線基板1bの製造方法によっても、前記配線基板1aの製造方法と同様な効果を奏することができた。
FIG. 10 is a schematic view illustrating a method for manufacturing the wiring board 1b.
As shown in FIG. 10 (A), a step of preparing an insulating layer Z2 with a conductor in which conductor layers 10a and 10b made of copper foil are previously formed on both the front and back surfaces 3 and 4 of the insulating layer r; A step of punching the insulating layer Z2 to form the through-hole 5, and a closing rod (not shown) is inserted from the opening on the conductor layer 10b side to the middle position of the through-hole 5 and the opening side of the conductor layer 10a In the state where the mask 30 is disposed, the step of filling the conductive paste 34 and the step of forming the through conductor 6a by curing the paste 34 were sequentially performed. Then, the insulating layer Z2 was turned upside down to obtain the state shown in FIG.
Next, as shown in FIG. 10B, the step of filling the conductive paste 34 from the opening on the conductor layer 10b side of the through hole 5 and the curing treatment of the conductive paste 34 and the like. Then, the process of forming the conductor 36 was sequentially performed. Further, the same plating process as described above was performed. As a result, the wiring board 1b shown in FIG. 3 was obtained.
Also by the method for manufacturing the wiring substrate 1b as described above, the same effects as those of the method for manufacturing the wiring substrate 1a could be achieved.

図11,図12は、前記とは若干異なる形態の配線基板の製造方法に関する。
予め、図11(A)に示すように、前記同様に準備した導体付き絶縁層Z1の導体層10a側からレーザ加工による貫通孔5を形成した後、該貫通孔5の開口部を囲み且つ貫通孔5の導体層10a側の内径よりも大きな内径の通し孔33を有するスクリーンマスク31を、通し孔33と貫通孔5とが同心状となるようにして、導体層10aの上面に載置した。
かかる状態で、図11(B)に示すように、上記貫通孔5および通し孔33内に、前記同様の導電性ペースト34aを充填した。
次いで、図12(A)に示すように、上記マスク31を除去した。その結果、充填された導電性ペースト34aにおける貫通部36の上端には、平面視で貫通孔5の前記内径よりも大径である端部37aが形成された。
11 and 12 relate to a method of manufacturing a wiring board having a slightly different form.
As shown in FIG. 11A, a through hole 5 is formed by laser processing from the conductor layer 10a side of the insulating layer with conductor Z1 prepared in the same manner as described above, and then the opening of the through hole 5 is surrounded and penetrated. A screen mask 31 having a through hole 33 having an inner diameter larger than the inner diameter of the hole 5 on the conductor layer 10a side was placed on the upper surface of the conductor layer 10a so that the through hole 33 and the through hole 5 were concentric. .
In this state, as shown in FIG. 11B, the same conductive paste 34a as described above was filled in the through hole 5 and the through hole 33.
Next, as shown in FIG. 12A, the mask 31 was removed. As a result, an end portion 37a having a diameter larger than the inner diameter of the through hole 5 in plan view was formed at the upper end of the through portion 36 in the filled conductive paste 34a.

更に、上記マスク31を除去した直後において、図12(A)中の矢印で示ように、前記導電性ペースト34aの周囲から導体層10aの上面における貫通孔5の径方向に沿って拡がり、液状のエポキシ樹脂からなり、且つ平面視がほぼ円形状を呈するフランジ部38が上記ペースト34aの上端側と一体に形成された。
そして、図12(B)に示すように、導電性ペースト34aおよびフランジ部38を硬化処理して、それぞれ前記同様の貫通導体6およびフランジ部8とした後、前記同様にして導体層10aを所定パターンの表面導体層10に形成した。
前記マスク31を用いた配線基板の製造方法によれば、図12(B)に示すように、前記端部7に比べて大径の端部7aを有する貫通導体6と、前記同様のフランジ部8とを含むと共に、前期同様の効果を奏する配線基板が得られた。
更に、上記方法により得られた配線基板では、大径の端部7aの上方に前記導体ピン16またはプローブピン29を容易且つ強固に接合することも可能となる。
Further, immediately after the removal of the mask 31, as shown by the arrow in FIG. 12A, it spreads from the periphery of the conductive paste 34a along the radial direction of the through hole 5 on the upper surface of the conductor layer 10a, and is liquid. A flange portion 38 made of an epoxy resin and having a substantially circular shape in plan view was formed integrally with the upper end side of the paste 34a.
Then, as shown in FIG. 12B, the conductive paste 34a and the flange portion 38 are cured to form the same through conductor 6 and flange portion 8, respectively, and then the conductor layer 10a is formed in the same manner as described above. It formed in the surface conductor layer 10 of the pattern.
According to the method of manufacturing a wiring board using the mask 31, as shown in FIG. 12B, the through conductor 6 having an end 7a having a larger diameter than the end 7 and the same flange as described above. 8 and a wiring board having the same effect as the previous period was obtained.
Furthermore, in the wiring board obtained by the above method, the conductor pin 16 or the probe pin 29 can be easily and firmly joined above the large-diameter end portion 7a.

図13,図14は、前記配線基板20の製造方法を示す部分概略図である。
予め、絶縁層r1,r2の表面3ごとに導体層10aを形成した2枚の導体付き絶縁層Z1を準備する工程と、該絶縁層Z1ごとの導体層10a側からレーザ加工による貫通孔5を形成する工程と、該貫通孔5内および前記マスク30の通し孔32内ごとに前記同様の導電性ペースト34を充填する工程、上記マスク30を除去し且つ前記同様のフランジ部8を形成する工程と、該フランジ部8および上記ペースト34を硬化処理する工程と、導体層10aごとに対してフォトリソグラフィ技術を施して、複数の表面導体層10または層間導体層19を形成する工程を順次行った。尚、上記絶縁層r1,r2の裏面4側には、予め、それぞれ接着剤層wが形成してあった。
その結果、図13に示すように、絶縁層r1,r2と、これらの表面3ごとに形成された複数の前記導体層10,19とを有し、かかる導体層10,19および絶縁層r1または絶縁層r2を連続して貫通する貫通導体6と、上記導体層10,19ごとの上面における貫通導体6の周囲側のみを被覆するフランジ部8とを有する2つの単位基板k1,k2が得られた。
13 and 14 are partial schematic views showing a method for manufacturing the wiring board 20.
A step of preparing two insulating layers with conductor Z1 in which a conductor layer 10a is formed for each surface 3 of the insulating layers r1 and r2 in advance, and through holes 5 by laser processing from the conductor layer 10a side of each insulating layer Z1. A step of forming, a step of filling the same conductive paste 34 in each of the through holes 5 and the through holes 32 of the mask 30, and a step of removing the mask 30 and forming the same flange portion 8 Then, the step of hardening the flange portion 8 and the paste 34 and the step of forming a plurality of the surface conductor layers 10 or the interlayer conductor layers 19 by applying a photolithography technique to each conductor layer 10a were sequentially performed. . An adhesive layer w was previously formed on the back surface 4 side of the insulating layers r1 and r2.
As a result, as shown in FIG. 13, it has insulation layers r1 and r2 and a plurality of the conductor layers 10 and 19 formed for each surface 3, and the conductor layers 10 and 19 and the insulation layer r1 or Two unit substrates k1 and k2 having a through conductor 6 that continuously penetrates the insulating layer r2 and a flange portion 8 that covers only the peripheral side of the through conductor 6 on the upper surface of each of the conductor layers 10 and 19 are obtained. It was.

別途に、アルミナ粉末を含む3枚のグリーンシートを用意し、該グリーンシートごとの所定位置に打ち抜き加工またはレーザ加工を行って複数のビアホールを形成し、該ビアホールにW粉末を含む導電性ペーストを充填し、未焼成である複数のビア導体26を形成した(何れも図示せず)。上記グリーンシートのうち、追って最上層となるグリーンシートの表面において、該グリーンシートを貫通するビア導体26の上端面が露出する位置ごとに対し、上記同様の導電性ペーストをスクリーン印刷して、未焼成である複数の配線層25を形成した。一方、追って最下層となるグリーンシートの裏面において、該グリーンシートを貫通するビア導体26の下端面が露出する位置ごとに対し、上記同様の導電性ペーストをスクリーン印刷して、未焼成である複数の裏面端子27を形成した。
次いで、上記3枚のグリーンシートを所定順に積層し且つ圧着した後、該グリーンシートの積層体を焼成することによって、各グリーンシートが焼成されたセラミックの絶縁層c1〜c3と、これらと同時に焼成された配線層25、直線状または僅かなテーパを有する円錐形状のビア導体26、裏面端子27とを有するセラミック絶縁部2bを形成した。
Separately, three green sheets containing alumina powder are prepared, a plurality of via holes are formed by punching or laser processing at predetermined positions for each green sheet, and a conductive paste containing W powder is formed in the via holes. A plurality of via conductors 26 that were filled and unfired were formed (none shown). Of the green sheets, the same conductive paste as described above is screen-printed on the surface of the green sheet that will be the uppermost layer, and the upper end surface of the via conductor 26 penetrating the green sheet is exposed. A plurality of wiring layers 25 for firing were formed. On the other hand, on the back surface of the green sheet that will be the lowermost layer later, the same conductive paste as described above is screen-printed for each position where the lower end surface of the via conductor 26 that penetrates the green sheet is exposed, and a plurality of unfired Back terminal 27 was formed.
Next, after laminating and pressing the three green sheets in a predetermined order, the green sheet laminate is fired to fire the ceramic insulating layers c1 to c3 in which each green sheet is fired, and simultaneously fire these. The ceramic insulating portion 2b having the wiring layer 25, the linear via conductor 26 having a slight taper, and the back terminal 27 was formed.

更に、図13中の白抜きの矢印で示すように、前記単位基板k1,k2をそれらの厚み方向に沿って接着剤wを介して積層し、これらを前記セラミック絶縁部2bにおいて最上層に位置するセラミック層c1の表面上に圧着して接着した。
その結果、図14に示すように、前記単位基板k1,k2の絶縁層r1,r2からなる前記樹脂絶縁層2aとセラミック絶縁部2bとから構成された基板本体22と、絶縁層r1,r2を貫通する上下2本の貫通導体6と、セラミックの絶縁層c1〜c3を厚み方向に沿って貫通する直線状のビア導体26などとを備えた配線基板20が得られた。尚、前記絶縁層r2側の貫通導体6の端部7は、前記圧着時において、厚み方向に沿って圧縮されていた。
上記配線基板20では、その基板本体22の表面23において隣接する表面導体層10同士間や、貫通導体6同士間におけるマイグレーションは、上記導体層10ごとの上面における貫通導体6の周囲側のみを被覆するフランジ部8により、なくすか抑制されていた。更に、絶縁層r1,r2間において隣接する層間導体層19同士間や、これらを貫通する貫通導体6同士間でのマイグレーションも、上記導体層19ごとの上面における貫通導体6の周囲側のみを被覆するフランジ部8により、なくすか抑制されていた。
Further, as indicated by the white arrows in FIG. 13, the unit substrates k1 and k2 are stacked via the adhesive w along their thickness direction, and these are positioned as the uppermost layer in the ceramic insulating portion 2b. The surface of the ceramic layer c1 to be bonded was pressed and adhered.
As a result, as shown in FIG. 14, the substrate body 22 composed of the resin insulating layer 2a composed of the insulating layers r1 and r2 of the unit substrates k1 and k2 and the ceramic insulating portion 2b, and the insulating layers r1 and r2 are formed. A wiring board 20 including two upper and lower through conductors 6 penetrating therethrough and linear via conductors 26 penetrating the ceramic insulating layers c1 to c3 along the thickness direction was obtained. The end portion 7 of the through conductor 6 on the insulating layer r2 side was compressed along the thickness direction during the crimping.
In the wiring substrate 20, migration between adjacent surface conductor layers 10 on the surface 23 of the substrate body 22 or between the through conductors 6 covers only the peripheral side of the through conductor 6 on the upper surface of each conductor layer 10. The flange portion 8 to be removed was slightly suppressed. Furthermore, migration between the adjacent interlayer conductor layers 19 between the insulating layers r1 and r2 and between the through conductors 6 penetrating them covers only the peripheral side of the through conductor 6 on the upper surface of each conductor layer 19. The flange portion 8 to be removed was slightly suppressed.

以上のような配線基板20の製造方法によれば、基板本体22の表面23や絶縁層r1,r2間において、比較的高い密度で形成された前記導体層10,19同士間などのショートをほぼ皆無にでき、且つ該導体層10,19とこれらを貫通する貫通導体6とを高い密着強度をもって接続することができた。
従って、基板本体22の表面23の上方に突出する貫通導体6ごとの端部7の上に前記プローブピン29を接合して立設することで、Siウェハに形成された多数の電子部品ごとの電気的特性を正確に測定できる検査用配線基板20を、確実に提供できることが可能となった。
尚、上記貫通導体6ごとの端部7の上に前記導体ピン16を立設しても良い。
According to the manufacturing method of the wiring board 20 as described above, a short circuit between the conductor layers 10 and 19 formed at a relatively high density between the surface 23 of the substrate body 22 and the insulating layers r1 and r2 is almost eliminated. In addition, the conductor layers 10 and 19 and the through conductor 6 penetrating them could be connected with high adhesion strength.
Therefore, the probe pins 29 are joined and erected on the end portions 7 for the respective through conductors 6 protruding above the surface 23 of the substrate body 22, so that each of the numerous electronic components formed on the Si wafer is provided. It has become possible to reliably provide the inspection wiring board 20 capable of accurately measuring the electrical characteristics.
The conductor pin 16 may be erected on the end 7 of each through conductor 6.

本発明は、以上において説明した各形態に限定されるものではない。
例えば、前記絶縁層rは、ポリイミド以外の樹脂、あるいは各種のセラミックからなるものであっても良い。
また、前記導電性ペースト34は、金属成分として、Ag粒子を含むものに限らず、Cu粒子を含むものや、Ag粒子とCu粒子の双方を含むなど他の導電性ペーストを用いても良い。
更に、前記基板本体は、3層以上の前記絶縁層rを積層した形態や、1層,2層,あるいは4層以上のセラミックの絶縁層cを積層した形態としても良い。
また、前記表面導体層10や層間導体層19を所定のパターンに形成する工程は、前記絶縁層Z1,Z2を準備した工程の直後、あるいは貫通孔5を形成する工程の直後において行っても良い。
更に、前記マスクには、薄い金属板のメタルマスク、樹脂フィルム、あるいはセラミックグリーンシートなどを用いても良い。
加えて、前記配線基板1a,1b,20などの製造方法は、多数個取りの形態によって行うことも可能である。
The present invention is not limited to the embodiments described above.
For example, the insulating layer r may be made of a resin other than polyimide or various ceramics.
Further, the conductive paste 34 is not limited to a metal component containing Ag particles, and other conductive pastes such as those containing Cu particles or containing both Ag particles and Cu particles may be used.
Further, the substrate main body may have a form in which three or more insulating layers r are laminated, or a form in which one, two, or four or more ceramic insulating layers c are laminated.
The step of forming the surface conductor layer 10 and the interlayer conductor layer 19 in a predetermined pattern may be performed immediately after the step of preparing the insulating layers Z1 and Z2 or immediately after the step of forming the through hole 5. .
Further, a thin metal plate metal mask, a resin film, a ceramic green sheet or the like may be used as the mask.
In addition, the method of manufacturing the wiring boards 1a, 1b, 20 and the like can be performed in a multi-cavity form.

本発明によれば、所要数の絶縁層からなる基板本体の表面あるいは内部に複数の導体層を高密度で形成し、且つ該導体層と上記絶縁層とを連続して貫通する貫通導体を形成しても、上記表面や絶縁層同士の層間で隣接する導体層同士などの間におけるマイグレーションを生じにくく、且つ上記導体層と貫通導体とを確実に接続できる配線基板、およびその製造方法を提供することができる。   According to the present invention, a plurality of conductor layers are formed at a high density on the surface or inside of a substrate body made up of a required number of insulating layers, and through conductors that continuously penetrate the conductor layers and the insulating layers are formed. Even so, there is provided a wiring board that is less likely to cause migration between adjacent conductor layers between the surfaces and between the insulating layers, and that can reliably connect the conductor layer and the through conductor, and a method for manufacturing the same. be able to.

1a,1b,20…配線基板
2,22……………基板本体
3,23……………表面
4,24……………裏面(表面)
5……………………貫通孔
6……………………貫通導体
7,7a……………貫通導体の端部
8……………………フランジ部
9……………………フランジ部の外縁
10,11…………表面/裏面導体層(導体層)
10a,10b……導体層
19…………………層間導体層(導体層)
30,31…………スクリーンマスク(マスク)
32,33…………通し孔
34,34a………導電性ペースト
r,r1,r2……絶縁層
c1〜c3…………絶縁層
Z1,Z2…………導体付き絶縁層
1a, 1b, 20 ... wiring board 2,22 ......... board body 3,23 ......... front side 4,24 ......... back side (front side)
5 …………………… Through hole 6 …………………… Penetration conductor 7, 7a …………… End of penetration conductor 8 …………………… Flange portion 9 ……… …………… Outer edge of flange 10, 11, ………… Front / back conductor layer (conductor layer)
10a, 10b …… Conductor layer 19 ……………… Interlayer conductor layer (conductor layer)
30, 31 ………… Screen mask (mask)
32, 33 ………… Through hole 34, 34a ……… Conductive paste r, r1, r2 …… Insulating layer c1 to c3 ………… Insulating layer Z1, Z2 ………… Insulating layer with conductor

Claims (8)

単数の絶縁層からなるか、あるいは複数の絶縁層を積層してなり、一対の表面を有する基板本体と、
上記基板本体において、少なくとも1つの絶縁層における少なくとも一方の表面に形成された導体層と、
上記導体層を表面に有する上記絶縁層を貫通し、且つ該導体層をも連続して貫通する貫通導体と、を備えた配線基板であって、
上記導体層の上面には、上記貫通導体の端部側から該貫通導体の径方向に沿って拡がるフランジ部が形成されており、
上記フランジ部の少なくとも外縁側における導電率は、上記貫通導体の導電率よりも低い、
ことを特徴とする配線基板。
A substrate body made of a single insulating layer or laminated with a plurality of insulating layers and having a pair of surfaces;
In the substrate body, a conductor layer formed on at least one surface of at least one insulating layer;
A wiring board comprising a through conductor penetrating through the insulating layer having the conductor layer on the surface and penetrating through the conductor layer continuously,
On the upper surface of the conductor layer, a flange portion that extends from the end side of the through conductor along the radial direction of the through conductor is formed,
The conductivity on at least the outer edge side of the flange portion is lower than the conductivity of the through conductor,
A wiring board characterized by that.
前記フランジ部の少なくとも外縁側は、樹脂を含んでいると共に、該フランジ部の外縁側を構成する上記樹脂の吸水率は、前記絶縁層の吸水率よりも小さい、
ことを特徴とする請求項1に記載の配線基板。
At least the outer edge side of the flange portion contains resin, and the water absorption rate of the resin constituting the outer edge side of the flange portion is smaller than the water absorption rate of the insulating layer.
The wiring board according to claim 1.
前記フランジ部が上面に形成された前記導体層は、前記基板本体における少なくとも一方の表面に形成された表面導体層である、
ことを特徴とする請求項1または2に記載の配線基板。
The conductor layer having the flange portion formed on the upper surface is a surface conductor layer formed on at least one surface of the substrate body.
The wiring board according to claim 1 or 2, wherein
前記貫通導体の端部は、前記フランジ部の上面よりも上方に突出している、
ことを特徴とする請求項1乃至3の何れか一項に記載の配線基板。
The end portion of the through conductor protrudes upward from the upper surface of the flange portion,
The wiring board according to any one of claims 1 to 3, wherein
前記フランジ部は、前記導体層の上面における前記貫通導体の周囲側のみを被覆している、
ことを特徴とする請求項1乃至4の何れか一項に記載の配線基板。
The flange portion covers only the peripheral side of the through conductor on the upper surface of the conductor layer.
The wiring board according to any one of claims 1 to 4, wherein the wiring board is provided.
単数の絶縁層からなるか、あるいは複数の絶縁層を積層してなり、一対の表面を有する基板本体と、
上記基板本体において、少なくとも1つの絶縁層における少なくとも一方の表面に形成された導体層と、
上記導体層を表面に有する上記絶縁層を貫通し、且つ該導体層をも連続して貫通する貫通導体と、を備えた配線基板の製造方法であって、
上記絶縁層における少なくとも一方の表面に導体層を形成した導体付き絶縁層を準備する工程と、
上記絶縁層および上記導体層を連続して貫通する貫通孔を形成する工程と、
上記貫通孔の開口部を囲む通し孔を有するマスクを上記導体層の上面に載置した状態で、上記貫通孔および通し孔に樹脂を含む導電性ペーストを充填する工程と、
上記マスクを除去すると共に、上記貫通孔および通し孔に充填された導電性ペーストに含まれる樹脂を、上記貫通孔の周縁から上記導体層の上面に沿って該貫通孔の外周側に流れ出させることで、上記樹脂を含むフランジ部を形成する工程と、
上記導電性ペーストおよびフランジ部を硬化処理する工程と、を含む、
ことを特徴とする配線基板の製造方法。
A substrate body made of a single insulating layer or laminated with a plurality of insulating layers and having a pair of surfaces;
In the substrate body, a conductor layer formed on at least one surface of at least one insulating layer;
A method of manufacturing a wiring board comprising: a through conductor penetrating through the insulating layer having the conductor layer on a surface thereof and continuously penetrating through the conductor layer;
Preparing an insulating layer with a conductor in which a conductive layer is formed on at least one surface of the insulating layer;
Forming a through-hole that continuously penetrates the insulating layer and the conductor layer;
Filling the through hole and the through hole with a conductive paste containing a resin with a mask having a through hole surrounding the opening of the through hole placed on the upper surface of the conductor layer;
The mask is removed, and the resin contained in the conductive paste filled in the through hole and the through hole is caused to flow from the periphery of the through hole to the outer peripheral side of the through hole along the upper surface of the conductor layer. And forming a flange portion containing the resin,
Curing the conductive paste and the flange portion,
A method for manufacturing a wiring board.
前記マスクに開設される通し孔の内径は、前記導体層の上面に開口する前記貫通孔の内径と同じか、該貫通孔の内径よりも大きい、
ことを特徴とする請求項6に記載の配線基板の製造方法。
The inner diameter of the through hole established in the mask is the same as or larger than the inner diameter of the through hole that opens on the upper surface of the conductor layer,
The method for manufacturing a wiring board according to claim 6.
前記フランジ部は、前記導体層の上面における前記貫通導体の周囲側のみを被覆している、
ことを特徴とする請求項6または7に記載の配線基板の製造方法。
The flange portion covers only the peripheral side of the through conductor on the upper surface of the conductor layer.
The method for manufacturing a wiring board according to claim 6 or 7, wherein:
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11397052B2 (en) 2019-09-12 2022-07-26 Ngk Insulators, Ltd. Heat exchanger

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JP2007142147A (en) * 2005-11-18 2007-06-07 Matsushita Electric Ind Co Ltd Conductive paste composition, printed wiring board using same, and manufacturing method thereof
JP2007281336A (en) * 2006-04-11 2007-10-25 Fujikura Ltd Method of manufacturing double sided printed wiring board and multilayer printed wiring board
JP2008198733A (en) * 2007-02-09 2008-08-28 Fujikura Ltd Multilayer interconnection board and manufacturing method thereof
JP2009049444A (en) * 2008-12-05 2009-03-05 Panasonic Corp Method of manufacturing multilayer circuit board
JP2013102201A (en) * 2013-01-21 2013-05-23 Ngk Spark Plug Co Ltd Wiring board manufacturing method

Patent Citations (5)

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Publication number Priority date Publication date Assignee Title
JP2007142147A (en) * 2005-11-18 2007-06-07 Matsushita Electric Ind Co Ltd Conductive paste composition, printed wiring board using same, and manufacturing method thereof
JP2007281336A (en) * 2006-04-11 2007-10-25 Fujikura Ltd Method of manufacturing double sided printed wiring board and multilayer printed wiring board
JP2008198733A (en) * 2007-02-09 2008-08-28 Fujikura Ltd Multilayer interconnection board and manufacturing method thereof
JP2009049444A (en) * 2008-12-05 2009-03-05 Panasonic Corp Method of manufacturing multilayer circuit board
JP2013102201A (en) * 2013-01-21 2013-05-23 Ngk Spark Plug Co Ltd Wiring board manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11397052B2 (en) 2019-09-12 2022-07-26 Ngk Insulators, Ltd. Heat exchanger

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