JP6301812B2 - Wiring board and manufacturing method thereof - Google Patents

Description

  The present invention relates to a wiring substrate including a plate-shaped glass substrate and a laminated portion provided on both surfaces of the glass substrate and having a structure in which a plurality of resin insulating layers are laminated, and a method for manufacturing the same.

  In recent years, with the miniaturization of electrical equipment and electronic equipment, miniaturization and high density are also required for wiring boards mounted on these equipment. As such a wiring board, for example, a substrate in which laminated parts having a structure in which resin insulating layers are laminated is formed on both surfaces of a core base material has been put into practical use. In general, a wiring board is a multi-cavity wiring board in which a plurality of board forming areas to be wiring boards are arranged along a plane direction, along the outline of the board forming area using a dicing blade. It can be obtained by cutting.

  By the way, in recent years, further miniaturization and higher density of the wiring substrate have been demanded, and for example, it has been proposed to use a core substrate as a glass substrate (see, for example, Patent Documents 1 to 4). This is because the glass substrate has high dimensional accuracy because the flatness of the substrate main surface and the substrate back surface is high, which is advantageous for miniaturization of wiring.

JP 2012-142084 A (paragraph [0015] etc.) JP2013-075808 (paragraph [0019] etc.) JP 2007-51017 A (paragraphs [0018] to [0022] etc.) JP 2001-139348 A (paragraph [0019], FIG. 1 etc.)

  However, as shown in FIG. 10, when the core base material is the glass base material 101, the following problems occur. That is, since the wiring board is obtained by cutting a multi-piece wiring board using a dicing blade as described above, the end surface 102 of the glass base material 101 tends to be rough, and large concave portions 103 and convex portions tend to be generated. It is in. In this case, due to the difference in thermal expansion between the glass substrate 101 and the resin insulating layer 104 (lamination portion), the thermal stress concentrates on the recess 103 of the end surface 102 of the glass substrate 101. There is a high possibility that a crack 105 starting from 103 is generated. As a result, the yield of the wiring board is lowered, and there is a problem that the predetermined reliability required for the wiring board cannot be provided.

  In Patent Documents 1 to 4, it is proposed to remove the recess by flattening the end surface of the glass substrate by etching or the like. However, since the resin insulating layer usually contains an inorganic filler (silica filler), there is a problem that the inorganic filler is removed when etching is performed.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a wiring board capable of improving reliability by preventing the occurrence of cracks in a glass substrate. is there. Another object is to provide a method for manufacturing a wiring board capable of manufacturing a wiring board having excellent reliability.

  As means (means 1) for solving the above-mentioned problems, a plate-shaped glass substrate having a substrate main surface and a substrate back surface, and both the substrate main surface and the substrate back surface are provided. And a laminated part having a structure in which a plurality of resin insulation layers are laminated, wherein an end face of the glass substrate and an end face of the resin insulation layer are exposed on a side surface of the wiring board. The wiring substrate is characterized in that the end surface of the glass substrate has a surface roughness Ra smaller than the end surface of the resin insulating layer and a surface roughness Rz of 1.10 μm or less.

  Therefore, according to the invention described in the means 1, the surface roughness Ra of the end surface of the glass substrate is smaller than the surface roughness Ra of the end surface of the resin insulating layer, and the surface roughness Rz of the end surface of the glass substrate is 1. Since the thickness is 10 μm or less, the concave portion generated in the end surface of the glass substrate is reduced. As a result, the thermal stress due to the difference in thermal expansion between the glass substrate and the resin insulation layer (laminated portion) is less likely to concentrate on the recesses formed on the end surface of the glass substrate, so that cracks originating from the recesses are generated. Can be prevented. As a result, since the yield of the wiring board can be improved, the reliability of the wiring board is improved.

  Here, “surface roughness Ra” described in this specification is an arithmetic average roughness Ra defined in JIS B0601: 2001, and “surface roughness Rz” is also JIS B0601: This is the maximum height Rz defined in 2001. In addition, the measuring method of surface roughness Ra and Rz shall comply with JIS B0651: 2001. For example, the surface roughness Ra, Rz of the end face of the glass substrate is measured as follows. First, the end surface of the glass substrate (specifically, the center in the thickness direction of the glass substrate when the range from the center in the thickness direction of the glass substrate to the main surface of the substrate or the back surface of the substrate is 100%) 5 measurement areas (10 μm long × 10 μm wide) in the range of 80% to 80%. Next, after measuring the surface roughness of each measurement region using a laser microscope, the average value of the obtained measurement values is calculated. The calculated average values are the surface roughness Ra and Rz.

  The surface roughness Rz of the end face of the glass substrate is 1.10 μm or less, more preferably 0.70 μm or less. If the surface roughness Rz is larger than 1.10 μm, the maximum depth of the concave portion generated on the end surface of the glass base material is increased. Therefore, the difference in thermal expansion between the glass base material and the resin insulating layer (lamination portion) is increased. As a result, thermal stress tends to concentrate on the recess, and cracks starting from the recess tend to occur on the glass substrate.

  The laminated portion constituting the wiring board has a structure in which a plurality of resin insulating layers are laminated. The resin insulation layer can be appropriately selected in consideration of insulation, heat resistance, moisture resistance, and the like. Specific examples of the material for forming the resin insulation layer include thermosetting resins such as epoxy resins, phenol resins, urethane resins, silicone resins, and polyimide resins, cycloolefin resins, polycarbonate resins, acrylic resins, polyacetal resins, and polypropylene resins. A thermoplastic resin etc. are mentioned. In addition, composite materials of these resins and organic fibers such as glass fibers (glass woven fabrics and glass nonwoven fabrics) and polyamide fibers, or three-dimensional network fluorine-based resin base materials such as continuous porous PTFE, epoxy resins, etc. A resin-resin composite material impregnated with a thermosetting resin may be used.

  The laminated portion preferably has a structure in which a metal wiring layer is disposed between a plurality of resin insulating layers. In this way, since an electric circuit can be formed in the laminated portion, the function of the wiring board can be enhanced. Here, the metal wiring layer can be formed using various conductive metals such as copper, silver, gold, platinum, nickel, titanium, aluminum, and chromium, but in particular, it is mainly composed of copper. Is good. As a method for forming the metal wiring layer, a known method such as a subtractive method, a semi-additive method, or a full additive method is employed. Specifically, for example, techniques such as etching of copper foil, electroless copper plating, or electrolytic copper plating are applied. It is also possible to form a metal wiring layer by etching after forming a thin film by a technique such as sputtering or CVD, or to form a metal wiring layer by printing a conductive paste or the like.

  The glass base material which comprises the said wiring board has a base material main surface and the base material back surface located in the other side. The material for forming the glass substrate can be appropriately selected in consideration of cost, workability, insulation, mechanical strength, and the like. As the glass substrate forming material, borosilicate glass, low-temperature fired glass ceramic, glass ceramic and the like are preferably used.

  In addition, it is good for the glass base material to have a penetration conductor which makes a base material main surface side and a base material back surface side conduct | electrically_connect while penetrating a glass base material in the thickness direction. If it does in this way, the lamination | stacking part by the side of a base material main surface and the lamination | stacking part by the side of a base material back can be reliably electrically connected via a penetration conductor. Here, the through conductor is made of a conductive metal such as gold, silver, copper, platinum, palladium, nickel, tin, lead, or tungsten, and particularly preferably made of copper having high conductivity and low cost. .

  Moreover, although the thickness of a glass base material is not specifically limited, For example, it is good that it is 0.5 mm or less. If the thickness of the glass base material is larger than 0.5 mm, the glass base material and thus the wiring board will be thick.

  As another means (means 2) for solving the above-mentioned problem, a glass substrate preparation step of preparing a plate-like glass substrate having a substrate main surface and a substrate back surface, and after the glass substrate preparation step A method of manufacturing a wiring board including a laminated part forming step of forming a laminated part having a structure in which a plurality of resin insulating layers are laminated on both the base material main surface and the base material back surface, After the laminated portion forming step, an exposure step for exposing the end surface of the glass base and the end surface of the resin insulating layer, which are side surfaces of the wiring board, and irradiating the end surface of the glass base with laser. The irradiation step of making the surface roughness Ra of the end surface of the glass substrate smaller than the end surface of the resin insulating layer and setting the surface roughness Rz of the end surface of the glass substrate to 1.10 μm or less is performed. Wiring board characterized by There is a production method.

  Therefore, according to the invention described in means 2, in the irradiation step, if the end surface of the glass substrate is irradiated with a laser, the surface roughness Ra of the end surface of the glass substrate is equal to the surface roughness of the end surface of the resin insulating layer. While being smaller than Ra, since the surface roughness Rz of the end surface of the glass substrate is 1.10 μm or less, the concave portion generated on the end surface of the glass substrate can be reduced. As a result, the thermal stress due to the difference in thermal expansion between the glass substrate and the resin insulation layer (laminated portion) is less likely to concentrate on the recesses formed on the end surface of the glass substrate, so that cracks originating from the recesses are generated. Can be prevented. As a result, since the yield of the wiring board can be improved, the reliability of the wiring board is improved.

  In the glass substrate preparation step, a glass substrate for multi-cavity where a plurality of substrate forming regions to be glass substrates are arranged along the plane direction is prepared. A multi-cavity wiring board having a laminated portion is formed on both the main surface of the glass base material and the back surface of the base material. In the exposure process, the multi-cavity wiring board is formed in the base material formation region. You may make it obtain the wiring board which the end surface of the glass base material and the end surface of the resin insulation layer exposed by cutting along an outline. If it does in this way, a plurality of wiring boards can be manufactured efficiently.

  Here, as a method of cutting the multi-cavity wiring board along the outline of the base material formation region, a method of mechanically cutting the multi-cavity wiring substrate using a dicing blade, or a base material formation region And a method of dividing the multi-piece wiring board along the break groove after forming the break groove along the outer shape line.

1 is a schematic cross-sectional view showing a wiring board in the present embodiment. The principal part sectional drawing which shows the resin base material of the glass base material, the main surface side buildup layer, and the resin insulating layer of a back surface side buildup layer. The schematic sectional drawing which shows a glass base material preparatory process. The schematic sectional drawing which shows the process of forming the 1st resin insulation layer. The schematic sectional drawing which shows the process of forming a through-hole in a glass base material. The schematic sectional drawing which shows the process of forming a through-hole conductor and a metal wiring layer. The schematic sectional drawing which shows the process of forming the 2nd resin insulation layer. The schematic sectional drawing which shows the process of forming a via hole in the 2nd resin insulation layer. The schematic sectional drawing which shows the process of forming the 3rd resin insulation layer. The schematic sectional drawing which shows the problem of a prior art.

  Hereinafter, an embodiment of the wiring board 10 of the present invention will be described in detail with reference to the drawings.

  As shown in FIG. 1, the wiring board 10 of this embodiment is a wiring board for mounting an IC chip. The wiring board 10 includes a substantially rectangular plate-shaped glass base material 11, a main surface side buildup layer 30 (lamination part) provided on the base material main surface 12 (upper surface in FIG. 1) of the glass base material 11, The back surface side buildup layer 40 (lamination | stacking part) provided on the base material back surface 13 (FIG. 1 lower surface) of the glass base material 11 consists of.

  The glass substrate 11 has a substrate main surface 12 and a substrate back surface 13 and has a substantially rectangular plate shape. The glass substrate 11 of the present embodiment is a substrate made of an inorganic material having an insulating property (in this embodiment, borosilicate glass). In addition, the magnitude | size of the glass base material 11 is set to 20 mm long x 20 mm wide. Moreover, the thickness of the glass base material 11 is set to 0.5 mm or less (in this embodiment, 0.1 mm (= 100 μm)). In the present embodiment, the thermal expansion coefficient of the glass substrate 11 is less than 15 ppm / ° C., specifically 3.8 ppm / ° C. In addition, the thermal expansion coefficient of the glass base material 11 says the average value of the measured value between 30 degreeC-400 degreeC.

  As shown in FIG. 1, the glass substrate 11 has a plurality of through-holes 15 that are opened in both the substrate main surface 12 and the substrate back surface 13 in a lattice shape. A through hole conductor 16 (through conductor) made of copper is formed in the through hole 15. These through-hole conductors 16 penetrate the glass substrate 11 in the thickness direction, and are electrically connected to the substrate main surface 12 side and the substrate back surface 13 side. The inside of the through-hole conductor 16 is filled with a closing body 17 such as an epoxy resin.

  The main surface side buildup layer 30 is composed of one resin insulating layer 31 made of a primer resin (thermosetting epoxy resin) having a thickness of 3 μm and two layers of resin made of a thermosetting epoxy resin having a thickness of 23 μm. The insulating layers 32 and 33 and the metal wiring layers 34, 35 and 36 made of copper having a thickness of 8 μm are stacked. In other words, the main surface side build-up layer 30 includes the metal wiring layer 34 disposed between the resin insulating layer 31 and the resin insulating layer 32, and the metal wiring between the resin insulating layer 32 and the resin insulating layer 33. It has a structure in which the layer 35 is disposed. In the present embodiment, the thermal expansion coefficient of the resin insulating layers 31 to 33 in a completely cured state is about 10 to 100 ppm / ° C., specifically 23 ppm / ° C. That is, the thermal expansion coefficient (3.8 ppm / ° C.) of the glass substrate 11 described above is smaller than the thermal expansion coefficient of the resin insulating layers 31 to 33. In addition, the thermal expansion coefficient in the completely cured state of the resin insulating layers 31 to 33 is an average value of measured values between 25 ° C. and 150 ° C. In addition, an inorganic filler (silica filler) is added to the insulating resin material (thermosetting epoxy resin) constituting the resin insulating layers 31 to 33. In the present embodiment, the content of the inorganic filler in the resin insulating layers 32 and 33 is 63% by weight. On the other hand, the content of the inorganic filler in the resin insulating layer 31 is smaller than the content of the inorganic filler in the resin insulating layers 32 and 33, and is 45% by weight in this embodiment. The average particle size of the inorganic filler is 0.25 μm.

  As shown in FIG. 1, a part of the metal wiring layer 34 on the surface of the first resin insulating layer 31 is electrically connected to the upper end of the through-hole conductor 16. Further, via conductors 37 formed by copper plating are provided in the resin insulating layers 32 and 33, respectively. The surface of the resin insulation layer 33 is almost entirely covered with a solder resist layer 38 (resin insulation layer) made of epoxy resin and having a thickness of about 30 μm. An opening 39 for exposing the metal wiring layer 36 is formed at a predetermined portion of the solder resist layer 38. That is, the main surface side build-up layer 30 has a structure in which the metal wiring layer 36 is disposed between the resin insulating layer 33 and the solder resist layer 38. A plurality of solder bumps 51 are disposed on the surface of the metal wiring layer 36. Each solder bump 51 is electrically connected to the surface connection terminal of the IC chip.

  As shown in FIG. 1, the back side buildup layer 40 has substantially the same structure as the main surface side buildup layer 30 described above. That is, the back-side buildup layer 40 is composed of one resin insulation layer 41 made of a primer resin (thermosetting epoxy resin) having a thickness of 3 μm and two layers of resin insulation made of a thermosetting epoxy resin having a thickness of 23 μm. The layers 42 and 43 and the metal wiring layers 44, 45 and 46 made of copper having a thickness of 8 μm are stacked. In other words, the back-side buildup layer 40 includes a metal wiring layer 44 disposed between the resin insulating layer 41 and the resin insulating layer 42, and a metal wiring layer disposed between the resin insulating layer 42 and the resin insulating layer 43. 45 is arranged. In the present embodiment, the thermal expansion coefficient of the resin insulating layers 41 to 43 in a completely cured state is about 10 to 100 ppm / ° C., specifically 23 ppm / ° C. That is, the thermal expansion coefficient (3.8 ppm / ° C.) of the glass substrate 11 described above is the thermal expansion coefficient of the resin insulating layers 41 to 43 and the thermal expansion coefficient (23 ppm / ° C. of the resin insulating layers 31 to 33 described above. ) Is smaller than. In addition, the thermal expansion coefficient in the completely cured state of the resin insulating layers 41 to 43 is an average value of measured values between 25 ° C. and 150 ° C. In addition, an inorganic filler (silica filler) is added to the insulating resin material (thermosetting epoxy resin) constituting the resin insulating layers 41 to 43. In the present embodiment, the content of the inorganic filler in the resin insulating layers 42 and 43 is 63% by weight. On the other hand, the content of the inorganic filler in the resin insulation layer 41 is smaller than the content of the inorganic filler in the resin insulation layers 42 and 43, and is 45% by weight in this embodiment. The average particle size of the inorganic filler is 0.5 μm.

  As shown in FIG. 1, a part of the metal wiring layer 44 on the lower surface of the first resin insulating layer 41 is electrically connected to the lower end of the through-hole conductor 16. Furthermore, via conductors 47 formed by copper plating are provided in the resin insulating layers 42 and 43, respectively. The lower surface of the resin insulation layer 43 is almost entirely covered with a solder resist layer 48 (resin insulation layer) made of epoxy resin and having a thickness of about 30 μm. An opening 49 for exposing the metal wiring layer 46 is formed at a predetermined position of the solder resist layer 48. That is, the back-side buildup layer 40 has a structure in which the metal wiring layer 46 is disposed between the resin insulating layer 43 and the solder resist layer 48. On the surface of the metal wiring layer 46, a plurality of solder bumps 52 are provided for electrical connection with a mother board (not shown). The wiring board 10 shown in FIG. 1 is mounted on the mother board by each solder bump 52.

  As shown in FIGS. 1 and 2, the entire end surface 21 of the glass substrate 11 is exposed on the side surface 20 of the wiring substrate 10. Further, on the side surface 20, the entire end surface 22 of the resin insulating layer 31, the entire end surface 23 of the resin insulating layer 32, the entire end surface 24 of the resin insulating layer 33, the entire end surface 25 of the resin insulating layer 41, and the end surface 26 of the resin insulating layer 42 are provided. The entire end face 27 of the resin insulating layer 43, the entire end face 28 of the solder resist layer 38, and the entire end face 29 of the solder resist layer 48 are exposed.

  As shown in FIG. 2, the concavo-convex portions 61 are formed in substantially the entire end surfaces 22 to 27 of the resin insulating layers 31 to 33 and 41 to 43 and substantially all of the end surfaces 28 and 29 of the solder resist layers 38 and 48. Is formed. By forming the uneven portion 61, the surface roughness Ra (arithmetic average roughness Ra) of the end faces 22 to 29 becomes 0.10 μm or more (0.12 μm in this embodiment). The region A1 on the glass base material 11 side in the end surfaces 22 and 25 of the resin insulating layers 31 and 41 is a pull-down concave portion that is pulled down to the center side of the wiring substrate 10 from the end surface 21 of the glass base material 11. Since the resin insulation layers 31 and 41 have a higher laser absorptivity than the glass base material 11, when the laser is irradiated toward the end surface 21 of the glass base material 11 in order to adjust the surface roughness Ra and Rz, a region is obtained. A1 is pulled down from the end face 21. Further, portions of the resin insulating layers 31 and 41 that are in contact with the glass substrate 11 are easily melted by receiving heat from the glass substrate 11 during laser irradiation. For this reason, the lowered recess is deepest at the boundary between the resin insulating layers 31 and 41 and the glass substrate 11.

  On the other hand, the concavo-convex portion 62 is also formed in substantially the entire end surface 21 of the glass substrate 11. By forming the uneven portion 62, the surface roughness Ra of the end face 21 is 0.01 μm, and the surface roughness Rz (maximum height Rz) of the end face 21 is 0.70 μm or less (in this embodiment, 0.24 μm). . That is, the surface roughness Ra of the end surface 21 is the surface roughness Ra (0.12 μm) of the end surfaces 22 to 27 of the resin insulating layers 31 to 33 and 41 to 43 and the end surfaces 28 and 29 of the solder resist layers 38 and 48. Is smaller than the surface roughness Ra (0.12 μm).

  Next, the manufacturing method of the wiring board 10 of this embodiment is demonstrated.

  First, in the glass substrate preparation step, a glass substrate 11 having a substrate main surface 12 and a substrate back surface 13 is prepared in advance (see FIG. 3). Specifically, an alkali-free thin glass substrate is prepared. The alkali-free thin glass substrate has a rectangular plate shape of 150 mm long × 150 mm wide × 0.1 mm thick (= 100 μm). The non-alkali thin glass substrate is a glass substrate for multi-piece production in which a plurality of base material forming regions to be the glass base material 11 are arranged vertically and horizontally along the plane direction.

  And after a glass base material preparatory process, a washing process is carried out and base material main surface 12 and base material back surface 13 of glass base material 11 (glass base material for many pieces) are washed. Next, a coupling process is performed on the entire substrate main surface 12 and the entire substrate back surface 13 using a conventionally known silane coupling agent (for example, manufactured by Shin-Etsu Chemical Co., Ltd.).

  In the subsequent laminated portion forming step, the main surface side buildup layer 30 is formed on the base material main surface 12 and the back surface side buildup layer 40 is formed on the base material back surface 13 based on a conventionally known method. Specifically, first, a main surface side resin sheet to be the uncured resin insulating layer 31 is laminated on the base material main surface 12 subjected to the coupling treatment. Moreover, the back surface side resin sheet used as the resin insulating layer 41 of an unhardened state is laminated on the base material back surface 13 to which the coupling process was similarly performed. The main surface side resin sheet and the back surface side resin sheet are made of a primer resin (thermosetting epoxy resin in the present embodiment) and have a rectangular plate shape of 150 mm long × 150 mm wide × 3 μm thick. Thereafter, when heat treatment (temporary curing) is performed for a predetermined time, the main surface side resin sheet is cured to become the first resin insulating layer 31, and the back surface side resin sheet is cured to be the first resin insulating layer. 41 (see FIG. 4).

  Next, laser drilling is performed using a carbon dioxide gas laser, and a large number of through-holes 15 penetrating through the glass substrate 11 and the resin insulating layers 31 and 41 are formed (see FIG. 5). Further, a desmear process for removing smear remaining in the through hole 15 is performed.

  Next, by performing electroless copper plating and electrolytic copper plating using a semi-additive method, the through-hole conductor 16 is formed in the through-hole 15, and the metal wiring is respectively formed on the surfaces of the resin insulating layers 31 and 41. Layers 34 and 44 are formed (see FIG. 6). Note that the through-hole conductor 16 and the metal wiring layers 34 and 44 may be formed using another method, for example, a subtractive method or a full additive method.

  And after performing the surface roughening process which roughens the surface of the metal wiring layers 34 and 44, the closure body 17 is filled and formed in the through-hole conductor 16 (refer FIG. 7). Next, a thermosetting epoxy resin having a thickness of 23 μm is applied (attached) on the resin insulating layers 31 and 41 to form second resin insulating layers 32 and 42 (see FIG. 7). Instead of depositing a thermosetting epoxy resin, an insulating resin such as a liquid crystal polymer or a photosensitive epoxy resin may be deposited. Further, laser drilling is performed using a YAG laser or a carbon dioxide laser to form via holes 73 and 74 at positions where via conductors 37 and 47 are to be formed (see FIG. 8). Specifically, a via hole 73 penetrating the resin insulating layer 32 is formed to expose the surface of the metal wiring layer 34, and a via hole 74 penetrating the resin insulating layer 42 is formed to form a surface of the metal wiring layer 44. To expose.

  Further, a desmear process for removing smear remaining in the via holes 73 and 74 is performed. Next, the inner surface of the via holes 73 and 74, the surface of the resin insulating layer 32 (upper surface in FIG. 8), and the surface of the resin insulating layer 42 (lower surface in FIG. 8) are not used by using a semi-additive method. By performing electrolytic copper plating and electrolytic copper plating, via conductors 37 and 47 are formed in the via holes 73 and 74, respectively, and metal wiring layers 35 and 45 are formed on the surfaces of the resin insulating layers 32 and 42, respectively. (See FIG. 9).

  Next, a thermosetting epoxy resin having a thickness of 23 μm is applied (attached) onto the resin insulation layers 32 and 42 to form third resin insulation layers 33 and 43 (see FIG. 9). Instead of depositing a thermosetting epoxy resin, an insulating resin such as a liquid crystal polymer or a photosensitive epoxy resin may be deposited. Further, laser drilling is performed using a YAG laser or a carbon dioxide laser to form via holes (not shown) at positions where via conductors 37 and 47 are to be formed. Specifically, a via hole penetrating the resin insulating layer 33 is formed to expose the surface of the metal wiring layer 35, and a via hole penetrating the resin insulating layer 43 is formed to expose the surface of the metal wiring layer 45. Let

  Further, a desmear process for removing smear remaining in the via hole is performed. Next, electroless copper is used for the inner surface of the via hole, the surface of the resin insulating layer 33 (upper surface in FIG. 9), and the surface of the resin insulating layer 43 (lower surface in FIG. 9) using a semi-additive method. By performing plating and electrolytic copper plating, via conductors 37 and 47 are formed in the via holes formed in the resin insulation layers 33 and 43, respectively, and metal wiring layers are formed on the surfaces of the resin insulation layers 33 and 43, respectively. 36 and 46 are formed (see FIG. 9).

  Next, a solder resist layer 38 is formed by applying and curing a photosensitive epoxy resin on the surface of the resin insulating layer 33. Further, a solder resist layer 48 is formed by applying and curing a photosensitive epoxy resin on the surface of the resin insulating layer 43. Next, exposure and development are performed in a state in which a predetermined mask is arranged to form an opening 39 in the solder resist layer 38 and an opening 49 in the solder resist layer 48. In addition, the thing of this state is the wiring board for multi-cavity in which the buildup layers 30 and 40 were provided in both on the base-material main surface 12 and base-material back surface 13 of a multi-cavity glass base material, respectively. Can be grasped.

  Further, a solder paste is printed on the metal wiring layer 36 formed on the surface of the resin insulating layer 33. A solder paste is printed on the metal wiring layer 46 formed on the surface of the resin insulating layer 43. Next, the multi-piece wiring board on which the solder paste is printed is placed in a reflow furnace and heated to a temperature 10 to 40 ° C. higher than the melting point of the solder. At this point, the solder paste is melted to form IC chip mounting solder bumps 51 that are hemispherically raised, and also the motherboard mounting solder bumps 52 that are also hemispherically raised are formed. .

  In the exposure step after the laminated portion forming step, the multi-cavity wiring board is cut along the outline of the base material formation region using a conventionally known cutting device (a dicing device in the present embodiment). In the present embodiment, a multi-piece wiring board is mechanically cut using a dicing blade equivalent to # 1000 under conditions of a processing speed of 1 mm / s and a rotation speed of 30000 rpm. As a result, the substrate forming regions are divided, and the end surface 21 of the glass substrate 11, the end surfaces 22 to 27 of the resin insulating layers 31 to 33 and 41 to 43, and the end surfaces 28 and 29 of the solder resist layers 38 and 48 are formed. A plurality of exposed wiring boards 10 are obtained simultaneously (see FIG. 1). At this time, the surface roughness Rz of the end surface 21 of the glass substrate 11 is 1.25 μm.

  In the subsequent irradiation process, with the laser irradiation device (not shown) directed to the end surface 21 of the glass substrate 11, a laser (carbonic acid in the present embodiment) is applied to the end surface 21 so as not to contact the end surfaces 22 to 29 as much as possible. (Gas laser) is irradiated to melt the end of the glass substrate 11 so that the end face 21 is leveled. At this time, the laser irradiation apparatus irradiates the laser while moving in parallel with the surface direction of the end face 21. Specifically, the laser irradiation device irradiates the laser while reciprocating in the thickness direction of the glass substrate 11. Note that the end face 21 may be leveled by shortening the shot interval of the pulse wave or increasing the scanning speed (moving speed) of the continuous wave. Here, the incident angle of the laser formed by the incident direction in which the laser is incident and the normal line of the end face 21 is set to 0 ° to 45 ° (0 ° in the present embodiment).

  As a result, the surface roughness Ra of the end surface 21 is the surface roughness Ra (0.12 μm) of the end surfaces 22 to 27 of the resin insulating layers 31 to 33 and 41 to 43 and the end surfaces 28 of the solder resist layers 38 and 48. , 29 is a value (0.01 μm) smaller than the surface roughness Ra (0.12 μm). At the same time, the surface roughness Rz of the end face 21 changes from 1.25 μm to 0.70 μm or less (in this embodiment, 0.24 μm). Further, part of the laser irradiated on the end surface 21 is also irradiated on the end surfaces 22 and 25 of the resin insulating layers 31 and 41. At this time, the resin insulating layers 31 and 41 having a relatively high laser absorption rate are more soluble than the glass substrate 11 having a relatively low laser absorption rate. As a result, the region A1 on the glass substrate 11 side of the end surfaces 22 and 25 of the resin insulating layers 31 and 41 is in a state of being pulled down from the end surface 21 of the glass substrate 11 (see FIG. 2).

  Thereafter, an IC chip is placed on the wiring board 10. At this time, the surface connection terminals on the IC chip side and the solder bumps 51 are aligned. Then, each solder bump 51 is reflowed by heating to a temperature of about 220 to 240 ° C., thereby joining each solder bump 51 and the surface connection terminal to electrically connect the wiring substrate 10 side and the IC chip side. To do. As a result, an IC chip is mounted on the wiring board 10.

  Next, a method for evaluating a wiring board and the result will be described.

  First, a measurement sample was prepared as follows. The same wiring board as the wiring board 10 of this embodiment was prepared, and this was used as Sample 1. Also, five types of wiring boards obtained by changing the surface roughness Ra, Rz of the end surface of the glass base material and the surface roughness Ra of the end surface of the resin insulating layer were prepared, did. In sample 6, the surface roughness Ra of the end surface of the glass substrate was made larger than the surface roughness Ra of the end surface of the resin insulating layer. In Samples 3 to 6, the surface roughness Rz of the glass substrate was made larger than 0.70 μm, and in Samples 5 and 6, the surface roughness Rz of the glass substrate was made larger than 1.10 μm. In addition, 22 measurement samples were prepared for each.

Next, a thermal shock test in which a thermal cycle of −65 ° C. to 150 ° C. was applied a plurality of times to each measurement sample (samples 1 to 6) was performed. And when the frequency | count of a thermal cycle reached | attained 100 times, 300 times, 500 times, 700 times, and 1000 times, it was observed whether the crack generate | occur | produced in the glass substrate of each measurement sample. And the yield (ratio of the thing which generation | occurrence | production of a crack is not confirmed) of each measurement sample was computed. The results are shown in Table 1.

  As a result, it was confirmed that the yields of Samples 5 and 6 were not 100% in all the thermal shock tests with different thermal cycle application times. In particular, in sample 6, when the thermal cycle reached 1000 times, it was confirmed that the yield was 0% (that is, cracks occurred in all measurement samples). Moreover, in samples 3-6, the crack of the glass base material was confirmed by the thermal cycle of 500 times, 700 times, and 1000 times.

  On the other hand, in samples 1 to 4, it was confirmed that the yield was 100% when the applied heat cycle was 100 times and 300 times. In particular, in samples 1 and 2, it was confirmed that the yield was 100% in all the thermal shock tests in which the number of thermal cycles was different.

  From the above, the surface roughness Ra of the end surface of the glass substrate is made smaller than the surface roughness Ra of the end surface of the resin insulating layer, and the surface roughness Rz of the end surface of the glass substrate is 1.10 μm or less. This proves that the glass substrate is less likely to crack and the wiring substrate yield is increased. Further, it was proved that if the surface roughness Rz of the end surface of the glass base material is 0.70 μm or less, cracks are less likely to occur and the yield of the wiring board is further increased.

  Therefore, according to the present embodiment, the following effects can be obtained.

  (1) According to the wiring substrate 10 of the present embodiment, the surface roughness Ra of the end surface 21 of the glass base 11 is the surface roughness Ra of the end surfaces 22 to 27 of the resin insulating layers 31 to 33 and 41 to 43, and Since the surface roughness Ra of the end faces 28 and 29 of the solder resist layers 38 and 48 is smaller than that of the solder resist layers 38 and 48 and the surface roughness Rz of the end face 21 is 0.24 μm, concave portions (specifically, irregularities) The concave portion in the portion 62 is reduced. As a result, the thermal stress due to the difference in thermal expansion between the glass substrate 11 and the resin insulating layers 31 and 41 is less likely to concentrate on the recesses generated in the end surface 21, and therefore the crack 105 starting from the recesses (see FIG. 10). Can be prevented. As a result, since the yield of the wiring board 10 can be improved, the reliability of the wiring board 10 is improved.

  (2) The prior art described in Japanese Patent Application Laid-Open No. 2014-22465 discloses a technique for protecting the end face of a glass substrate with a resin. However, since a resin that covers the end face of the glass base material is required, there is a problem that the manufacturing cost of the wiring board increases. On the other hand, in this embodiment, since it is not necessary to prepare a resin that covers the end surface of the glass base material, the material necessary for manufacturing the wiring substrate 10 is reduced, and the cost of the wiring substrate 10 can be reduced. Become.

  (3) In this embodiment, the thermal expansion coefficient (3.8 ppm / ° C.) of the glass substrate 11 is smaller than the thermal expansion coefficient (23 ppm / ° C.) of the resin insulating layers 31 to 33 and 41 to 43. . In this case, the thermal stress resulting from the difference in thermal expansion between the glass substrate 11 and the resin insulating layers 31 and 41 is concentrated on the glass substrate 11 that is harder than the resin insulating layers 31 to 33 and 41 to 43. As a result, a decrease in adhesion at the interface between the glass substrate 11 and the resin insulating layers 31 and 41 due to the deformation of the glass substrate 11 is prevented, so that the resin insulating layers 31 and 41 from the glass substrate 11 are prevented. Peeling (delamination) is less likely to occur. In addition, when the thermal expansion coefficient of the glass base material 11 becomes larger than the thermal expansion coefficient of the resin insulating layers 31 to 33 and 41 to 43, thermal stress is applied to the resin insulating layers 31 to 33 and 41 to 43 softer than the glass base material 11. Therefore, the resin insulating layers 31 to 33 and 41 to 43 are likely to be deformed, and there is a possibility that the adhesiveness at the interface between the glass substrate 11 and the resin insulating layers 31 and 41 may be reduced.

  (4) The IC chip of this embodiment is disposed directly above the glass substrate 11 and the buildup layers 30 and 40. As a result, the conduction path for electrically connecting the IC chip to the glass substrate 11 and the buildup layers 30 and 40 is the shortest. Therefore, it is possible to smoothly supply power to the IC chip. In addition, since noise entering between the IC chip and the glass base material 11 and the buildup layers 30 and 40 can be suppressed to a very low level, high reliability can be obtained without causing malfunction such as malfunction. .

  Further, the IC chip is highly rigid, has a smaller thermal expansion coefficient than the resin insulating layers 31 to 33 and 41 to 43, and is supported by the glass substrate 11 having a thermal expansion coefficient close to that of the IC chip. Therefore, since the glass base material 11 becomes difficult to deform | transform, the IC chip mounted in the wiring board 10 provided with the glass base material 11 can be supported more stably. Therefore, it is possible to prevent IC chip cracks and poor connections due to large thermal stress. Therefore, as an IC chip, a large IC chip of 10 mm square or more is considered to be brittle because stress (strain) due to a difference in thermal expansion is large and the influence of the thermal stress is large, and the heat generation is large and the thermal shock during use is severe. A low-k (low dielectric constant) IC chip can be used.

  In addition, you may change this embodiment as follows.

  In the wiring substrate 10 of the above embodiment, the surface roughness Ra of the end surface 21 of the glass base material 11 is smaller than the surface roughness Ra of the end surfaces 22 to 27 of the resin insulating layers 31 to 33 and 41 to 43. The surface roughness Rz was 0.70 μm or less (specifically 0.24 μm). However, it may be a wiring board (see Examples 3 and 4 in Table 1) in which the surface roughness Rz of the end surface of the glass base material is larger than 0.70 μm and not larger than 1.10 μm.

  In the above-described embodiment, the through-hole conductor 16 is used as a through conductor that conducts the substrate main surface 12 side and the substrate back surface 13 side of the glass substrate 11. However, a conductor different from the through-hole conductor 16 may be used as the through conductor. For example, a conductor formed so that the inside of the through hole 15 is completely filled with plating or conductive paste may be used as the through conductor.

  Next, the technical ideas grasped by the embodiment described above are listed below.

  (1) In the above means 1, the end face of the glass substrate has a surface roughness Rz set to 0.70 μm or less.

  (2) In the above means 1, the end face of the resin insulating layer has a surface roughness Ra set to 0.10 μm or more.

  (3) The wiring board according to the above means 1, wherein the resin insulating layer contains an inorganic filler.

  (4) In the above means 2, in the irradiation step, the end surface of the glass base material is irradiated with a laser to melt the end portion of the glass base material and level the end surface. Manufacturing method.

  (5) In the said means 2, the said irradiation process WHEREIN: Surface roughness Rz of the end surface of the said glass base material shall be 0.70 micrometer or less, The manufacturing method of the wiring board characterized by the above-mentioned.

DESCRIPTION OF SYMBOLS 10 ... Wiring board 11 ... Glass base material 12 ... Base material main surface 13 ... Base material back surface 16 ... Through-hole conductor 20 as a penetration conductor ... Side surface 21 of a wiring board ... End surface 22,23,24,25 of a glass base material 26, 27, 28, 29 ... end face 30 of resin insulating layer ... main surface side buildup layers 31, 32, 33, 41, 42, 43 ... laminated resin layer 34, 35, 36, 44, 45, ... 46... Metal wiring layers 38 and 48... Solder resist layer 40 as a resin insulation layer... Back side buildup layer as a laminated portion

Claims (6)

A plate-like glass substrate having a substrate main surface and a substrate back surface;
A wiring board provided on both the base material main surface and the back surface of the base material, and including a laminated portion having a structure in which a plurality of resin insulating layers are laminated,
On the side surface of the wiring board, the end surface of the glass base and the end surface of the resin insulating layer are exposed,
An end face of the glass base material has a surface roughness Ra smaller than an end face of the resin insulating layer, and a surface roughness Rz of 1.10 μm or less.   The wiring board according to claim 1, wherein the laminated portion has a structure in which a metal wiring layer is disposed between the plurality of resin insulating layers.   The said glass base material has a penetration conductor which makes the said base material main surface side and the said base material back surface side conduct | electrically_connect while penetrating the said glass base material in the thickness direction. Wiring board.   The wiring substrate according to claim 1, wherein the glass substrate has a thickness of 0.5 mm or less. A glass substrate preparation step of preparing a plate-like glass substrate having a substrate main surface and a substrate back surface;
A wiring board including a laminated part forming step of forming a laminated part having a structure in which a plurality of resin insulating layers are laminated after the glass base material preparing process on both the base material main surface and the base material back surface. A manufacturing method of
After the laminated part forming step,
An exposure step of exposing the end surface of the glass base and the end surface of the resin insulating layer, which are the side surfaces of the wiring board;
By irradiating the end surface of the glass substrate with laser, the surface roughness Ra of the end surface of the glass substrate is made smaller than the end surface of the resin insulating layer, and the surface roughness of the end surface of the glass substrate is reduced. A method of manufacturing a wiring board, comprising performing an irradiation step of reducing the thickness Rz to 1.10 μm or less. In the glass substrate preparation step, preparing a glass substrate for multi-cavity in which a plurality of substrate forming regions to be the glass substrate are arranged along the plane direction,
In the laminated part forming step, a multi-cavity wiring board provided with the laminated part on both the base material main surface and the back surface of the base material of the multi-cavity glass base material is formed,
In the exposing step, the wiring substrate in which the end surface of the glass substrate and the end surface of the resin insulating layer are exposed by cutting the multi-cavity wiring substrate along the outline of the base material forming region The method of manufacturing a wiring board according to claim 5, wherein the wiring board is obtained.

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