JP6950795B2 - Glass circuit board - Google Patents

Description

The present invention relates to a multi-layer circuit board using a glass as a substrate, particularly a semiconductor package substrate, an interposer, and a substrate for an optical element, and relates to circuit miniaturization, dimensional stability improvement, and reliability improvement.

In order to meet the recent demand for miniaturization and high functionality of electronic devices, a laminated multi-chip package in which a plurality of semiconductor chips are laminated in a semiconductor device has been developed. The laminated multi-chip package is suitable for miniaturization and high integration because it stacks a plurality of semiconductor chips into one package, and has been commercialized mainly for memory products such as DRAM. However, in the conventional laminated multi-chip package, since each chip to be laminated and the package substrate are connected by wire bonding, the number of terminals that can be pulled out from each chip is small, and if the number of chips to be laminated increases, space for a wire loop can be secured and the package can be secured. There is a problem that it becomes difficult to secure the wire bonding pad of the substrate and it becomes difficult to stack a large number of chips.

On the other hand, recently, a chip laminating technique using a through silicon via (TSV; Silicon Via) as shown in FIG. 1A has been developed. The TSV is a through electrode provided on a silicon substrate, and can be electrically connected between the stacked chips and between the chip and the package substrate by using the TSV. FIG. 1A is an example of a laminated multi-chip package (also called a 3D package) in which a logic chip and a memory chip are three-dimensionally laminated by TSV. In this example, the case where four memory chips 101 are stacked is shown. The memory chips 101 and the logic chip 105 and the package substrate 104 are conducted with each other via the TSV 102, and are connected by bumps 103. The bump 103 is made of a metal such as solder or copper. Such chip stacking technology using TSV eliminates the need for wires that have been used in the past, making it possible to easily increase the number of chips to be stacked, and further reduces the connection distance between chips and between chips and package substrates. It is shortened and is advantageous for high-speed signal transmission. Further, while the conventional wire for wire bonding has a diameter of 20 to 30 μm, the TSV can be formed with a diameter of 10 μm or less, so that more terminals can be pulled out, and large-capacity communication can be performed. There are many merits such as being possible.

However, the production of a semiconductor chip with a TSV requires many steps, which causes a problem that the production takes time and cost. Further, in the case of the 3D package shown in FIG. 1A in which a TSV is formed on a logic chip, since the memory chip and the logic chip are connected by TSVs having the same pitch, a unified standard for TSV bump pitch between logic chip and memory chip manufacturers. It is necessary to provide. In this case, there are design restrictions on the logic chip, which causes a problem of high design cost. Further, in the case of a 3D package, it is necessary to join the chips manufactured by the logic chip and the memory chip maker at the assembly maker, and further mount the chips on the semiconductor package substrate. If a defect is found after assembling the semiconductor package, there are many problems such as quality assurance and manufacturing responsibility that it is not possible to clarify whether it is a defect at the assembly manufacturer or a manufacturing defect at one of the chip manufacturers, which hinders its widespread use. It has become.

From the above, it is considered that the multi-chip package shown in FIG. 1B, in which the three-dimensional chip of the DRAM memory, which is relatively easy to stack TSVs, and the logic chip are mounted horizontally on the semiconductor package substrate, is the most realistic. (So-called 2.5D package). In the 3D package, the signal wiring between the memory and the logic is connected by a minute TSV, but in the case of the 2.5D package, it is necessary to connect the signal lines between multiple semiconductor chips in a plane on the semiconductor package substrate. It becomes. Therefore, since the number of wirings is inevitably required to be extremely large on the semiconductor package substrate side, the demand for fineness and multi-layering is becoming more stringent, and in this application, fine wirings of L / S = 5/5 μm or less are formed. Technology and interlayer connection with a via diameter of 30 μm or less are required. Therefore, in the 2.5D package, as shown in FIG. 1B, the three-dimensional stacked memory and the logic chip are mounted on a silicon interposer 106 manufactured by a semiconductor process capable of finely connecting the logic chip, and the semiconductor chip is further mounted. A method of mounting the silicon interposer 106 on the semiconductor package substrate 104 has been proposed (see Patent Documents 1 to 4).

However, since the silicon interposer is manufactured by the wafer process, there is a problem that the manufacturing cost is higher than that of the semiconductor package substrate manufactured in a panel size larger than that of the wafer. Further, the silicon interposer has a problem that the process cost of TSV formation is high. Further, since silicon is a semiconductor, in order to form a wiring circuit, it is necessary to form an oxide film on the silicon surface to insulate and then form the circuit wiring. Therefore, there is a problem that the transmission characteristics of the wiring circuit formed on the silicon interposer are worse than those of the circuit formed on the glass substrate or the glass epoxy substrate which is an insulator.

Therefore, glass interposers are attracting attention as interposers having materials other than silicon in the core layer, and research and development are becoming active. The advantages of using glass for the core layer are that it is not limited in various thicknesses and sizes, is inexpensive, and has excellent smoothness and flatness, so that fine wiring can be formed with L / S = 5/5 μm or less. Advantageous in properties, linear thermal expansion coefficient (CTE) is around 3ppm like silicon, excellent mounting stability, dimensional stability and high elasticity, excellent chemical stability, high insulation Transmission characteristics can be improved. Furthermore, due to its optical transparency, it is also attracting attention as an optical element application such as an image sensor. Further, a technique for forming a through hole in a glass substrate has been developed, and it has become possible to perform a fine through hole processing having a diameter of 50 μm or more and 100 μm or less even if the glass thickness is 300 μm by electric discharge machining or laser processing.

Here, a method for manufacturing a circuit board using a main glass as a substrate will be briefly described by taking a glass interposer as an example. In this example, a method of manufacturing by a built-up method equivalent to a semiconductor package substrate is shown. First, a glass substrate to be used as a substrate is prepared. Through holes are formed on the glass substrate by using a known method such as electric discharge machining or laser machining. Subsequently, a thin metal layer of 1 μm or less is formed on the glass surface and the inner surface of the through hole by a known method such as electroless plating or a sputtering method, a vapor deposition method, or a CVD method to perform a conductivity treatment.

Multiple routes can be considered in the subsequent steps. In the first method, so-called through-hole filling is conceivable in which the entire thin metal layer is energized and electrolytic plating is performed to fill the double-sided surface layer and the through-hole with metal. This method has the advantage that vias can be formed directly above the through holes, which saves space. However, when the entire through holes having a diameter of 50 μm to 100 μm are filled with electrolytic plating, the metal thickness on both surfaces is at least 25 μm to 50 μm. And thicken. In this case, after forming a photorest pattern on the surface metal by photolithography, wiring is formed by a subtractive method that removes unnecessary metal layer parts by etching, but this method requires an interposer for a thick metal layer. It becomes impossible to form a fine circuit. Further, although it depends on the shape of the through hole such as the aspect ratio of the glass thickness and the hole diameter, it is difficult to completely fill the inside of the through hole with the electrolytic plating layer, and especially when the aspect ratio is 2 or more, the inside of the through hole is filled. There was a problem that the reliability was lowered because voids and seams were included.

In the second method, the entire thin metal layer is similarly energized and electrolytically plated to plate both sides of the surface layer and the inside of the through holes. However, after the plating is completed before the through holes are filled, the surface metal is used. This is a method of forming a circuit by patterning a photorest on the top and removing unnecessary metal layers by etching. As a result of examination by the present inventor, even in this method, the miniaturization limit is reached at about L / S = 20/20 μm, and it is impossible to form a fine circuit required for interposer applications. Similarly, it was extremely difficult to form fine wiring with L / S = 5/5 μm or less even in the wiring formation by the hole-filling printing, polishing, lid plating, and subtractive method, which are known manufacturing methods for printed wiring boards.

In the third method, a resist layer is formed on a thin metal layer, and after patterning so as to remove the resist on the through hole portion and the wiring portion, the wiring and the through hole are simultaneously formed and thickened by electrolytic plating. This is a method of forming by a semi-additive method in which a thin metal layer is removed by etching after the resist is peeled off. According to this method, it is possible to form fine wiring of L / S = 5/5 μm or less required for an interposer. Furthermore, by heating and pressurizing the built-up resin on both sides of the surface layer circuit with a vacuum laminator in a later process, the surface layer insulating layer can be formed and the built-up resin filling protection in the hollow through hole can be performed at the same time. Therefore, it is an efficient method.

However, when the above-mentioned third method is performed, depending on the resin used, even if the filling is performed by the vacuum laminating method, the build-up resin cannot be filled to the inside of the through hole, and as a result, air voids are included. Semiconductor device assembly process For example, due to the thermal history of mass reflow, the contained voids burst, causing a problem that the reliability of the circuit board cannot be ensured.

Further, in the case of a resin having poor fluidity, the resin thickness around the through hole becomes thin, and there is a problem that a dent is generated immediately above the through hole. Even if the resin has good fluidity and can be laminated flat, the resin thickness on the through-hole portion is thicker than that on the flat glass portion without through-hole, so that the resin is cured and shrunk. If it is large, there is a problem that a dent is generated just above the through hole. From the above, the resin directly above the through hole has a dent of about 5 μm, which causes a chronic problem that a fine circuit cannot be formed because flatness cannot be ensured.

Furthermore, when the coefficient of linear thermal expansion of the resin formed directly above the glass circuit is large, stress due to the difference in the coefficient of linear thermal expansion between the glass substrate and the insulating resin layer is accumulated due to the addition of the thermal history in the subsequent process. In addition, in the dicing step of individualizing the glass core substrate, there has been a problem that a back crack phenomenon that breaks so as to peel off in the plane direction within the glass thickness is likely to occur.

Japanese Unexamined Patent Publication No. 2001-102479 Japanese Unexamined Patent Publication No. 2002-373962 Japanese Unexamined Patent Publication No. 2002-261204 Japanese Unexamined Patent Publication No. 2000-332168

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to enable the formation of fine circuits by ensuring the flatness of the insulating resin layer while ensuring long-term reliability, and further. An object of the present invention is to provide a wiring board using a glass as a substrate, which facilitates the formation of a fine multilayer circuit, and a method for manufacturing the same.

One aspect of the present invention is a glass having a through hole formed through both sides of a glass substrate, a through hole made of at least a cylindrical hollow metal layer covering the inner wall of the through hole, and a metal circuit formed on both sides of the glass substrate. A part of the metal circuit formed on both sides of the circuit board is connected to the through hole, the front and back sides are electrically conductive, and at least the hollow part of the through hole and both sides of the glass circuit board are made of the same first insulating resin. The thickness of the first insulating resin layer that is filled and coated and laminated on both sides of the glass circuit substrate is in the range of 5 μm or more and 30 μm or less from the upper surface of the metal circuit, and the first insulating resin is a thermosetting resin or an inorganic filler. The average particle size of the inorganic filler is 0.4 μm or more, the maximum particle size is 5 μm or less, the filling amount of the inorganic filler is 60 wt% or more, the average linear thermal expansion coefficient from 25 ° C. to the glass transition temperature or less is 25 ppm or less. A via hole and a metal circuit are formed on one insulating resin, one or more layers of a second insulating resin are laminated on the first insulating resin, and a via hole and a metal circuit are formed on each layer of the second insulating resin. (Ii) The thickness of the insulating resin layer is in the range of 5 μm or more and 30 μm or less from the upper surface of the metal circuit underneath, and the second insulating resin contains a thermosetting resin and an inorganic filler, and the average filler diameter of the inorganic filler is It is a glass circuit substrate characterized by having a maximum filler diameter of 0.2 μm or less, a maximum filler diameter of 2 μm or less, and an inorganic filler filling amount of 65 wt% or less.

According to the present invention, a first insulating resin having good filling property inside the through hole is laminated on both sides of the glass core substrate on the through hole and the glass core substrate in which metal circuits are formed on both sides of the glass. Since voids generated in the holes can be effectively suppressed, a glass core substrate having long-term connection reliability can be provided. Further, according to the present invention, since the first insulating resin has a large amount of the inorganic filler filled, it is possible to suppress the amount of curing shrinkage of the insulating resin filled inside the through hole, which is caused by the curing shrinkage directly above the through hole. The flatness of the resin surface can be ensured by suppressing the dents. Therefore, it is possible to provide a glass circuit board in which fine circuits can be easily formed and a method for manufacturing the same. Further, by using a second insulating resin on the first insulating resin, which is easier to process fine wiring and small diameter vias, it is possible to provide a glass circuit board having a fine multilayer wiring layer.

Schematic diagram of a conventional laminated multi-multi-chip package (3D package) Schematic diagram of a conventional laminated multi-multi-chip package (2.5D package via an interposer) Schematic diagram showing a manufacturing process of a glass circuit board according to an embodiment of the present invention. Schematic diagram showing a manufacturing process of a glass circuit board according to an embodiment of the present invention. Schematic diagram showing a manufacturing process of a glass circuit board according to an embodiment of the present invention. Schematic diagram showing a manufacturing process of a glass circuit board according to an embodiment of the present invention. Schematic diagram showing a manufacturing process of a glass circuit board according to an embodiment of the present invention. Schematic diagram showing a manufacturing process of a glass circuit board according to an embodiment of the present invention. Schematic diagram showing a manufacturing process of a glass circuit board according to an embodiment of the present invention. Schematic diagram showing a manufacturing process of a glass circuit board according to an embodiment of the present invention. Schematic diagram showing a manufacturing process of a glass circuit board according to an embodiment of the present invention. Schematic diagram showing a manufacturing process of a glass circuit board according to an embodiment of the present invention. Schematic diagram showing a manufacturing process of a glass circuit board according to an embodiment of the present invention. Schematic diagram showing a manufacturing process of a glass circuit board according to an embodiment of the present invention. Schematic diagram showing a manufacturing process of a glass circuit board according to an embodiment of the present invention.

Hereinafter, one embodiment of the present invention will be described in detail with reference to FIGS. 2A to 2M which are cross-sectional views. The present embodiment is an example of the embodiment of the present invention, and the following description does not limit the glass core substrate of the present invention.

First, the glass core 201 in which the through hole 202 shown in FIG. 2A is formed is prepared. The glass core 201 can be formed by providing a through hole 202 in a glass material by a known method. The glass material is not limited to the present invention, but _{contains SiO 2} as a main component. As the glass material, low expansion glass having a linear expansion coefficient of 3 to 4 ppm / ° C., soda glass having a linear expansion coefficient of 8 to 9 ppm / ° C., or the like can be used. The coefficient of linear expansion of the glass material can be adjusted in the range of 3 to 9 ppm / ° C. by changing the production method or adding a metal component such as Na. The coefficient of linear expansion (CTE) can be measured by thermomechanical analysis (TMA) according to JIS R3102: 1995 for glass or JIS K7197: 2012 for plastics. The glass substrate preferably has a thickness in the range of 50 μm to 1000 μm. More preferably, it is 100 μm or more and 500 μm or less. If it is 50 μm or less, it becomes difficult to handle during the manufacturing process. When it is 1000 μm or more, it becomes difficult to machine a fine through hole having a diameter of 100 μm or less and a pitch of 200 μm or less.

Known methods for through-hole machining include laser machining, electric discharge machining, sandblast machining when a photosensitive resist material is used, dry etching, and chemical etching with hydrofluoric acid and the like. Further, it is possible to prepare a glass core by using photosensitive glass. It is preferable because laser machining and electric discharge machining are simple and the throughput is good. The laser that can be used can be selected from a CO ₂ laser, a UV laser, a picosecond laser, a femtosecond laser, and the like.

Subsequently, as shown in FIG. 2B, the conductive layer 203 is formed on the inner wall and the surface of the through hole of the glass core substrate 201. The conductive layer 203 may be formed after the adhesion layer (not shown) is introduced on the glass core substrate 201. The adhesion layer is introduced to improve the adhesion between the glass surface and the conductive layer 203, and is not limited to the present invention, but examples thereof include tin oxide, indium oxide, zinc oxide, and nickel-. It can be selected from one or more selected from the group consisting of phosphorus (Ni-P), chromium, chromium oxide, aluminum nitride, copper nitride, aluminum oxide, tantalum, titanium and copper. More preferably, it is preferably selected from titanium and chromium. The thickness of the adhesion layer is not limited to the present invention, but it is preferably 0.01 μm or more and 1 μm or less. The adhesion layer can be formed by using any technique known in the art such as a sputtering method, an electroless plating method, a CVD method, and a vapor deposition method.

It is desirable that the conductive layer 203 is a material having high electrical connection stability. Materials that can be used are, for example, metals selected from the group consisting of copper, silver, gold, nickel, platinum, palladium, ruthenium and tin, and tin-silver, tin-silver-copper, tin-copper, tin- Includes alloys selected from the group consisting of bismuth and tin-lead. It is preferably copper or nickel. The thickness of the conductive layer is not limited to the present invention, but it is preferably 0.01 μm or more and 1 μm or less. The method for forming the conductive layer can be selected from, for example, a sputtering method, an electroless plating method, a CVD method, a vapor deposition method, and the like.

Subsequently, the resist pattern 204 is formed on the glass core substrate on which the conductive layer 203 is formed as shown in FIG. 2C. The resist can be selected from a liquid positive resist, a liquid negative resist, and a dry film resist. The liquid resist coating method can be selected from slit coating, curtain coating, die coating, spray coating, electrostatic coating, inkjet coating, gravure coating, screen printing, gravure offset printing, spin coating, and doctor coating. If it is a dry film resist, a resist layer can be formed by a roll laminator. After forming resist layers on both surfaces of the conductive layer, a desired pattern is formed on the glass core substrate by a photolithography method. The resist pattern is aligned and patterned so that the portion where the later electrolytic plating layer is formed is exposed. The thickness of the resist layer depends on the thickness of the electrolytic plating in the subsequent process, but is preferably 3 μm or more and 25 μm or less. If it is thinner than 3 μm, the electrolytic plating cannot be increased to 3 μm or more, which may reduce the connection reliability of the circuit. If it is thicker than 25 μm, it becomes difficult to form fine wiring with L / S = 5/5 μm or less.

Subsequently, as shown in FIG. 2D, the electrolytic plating circuit layer 205 is formed by electrolytic plating using the conductive layer. The metal layer of the through-hole inner wall 206 and the circuit portion can be thickened by electrolytic plating. The metal that can be electroplated can be selected from copper, nickel, tin, gold, silver, solder and the like. Desirably, copper and nickel are preferable because they are simple and inexpensive. The thickness of the electrolytic plating is preferably 1 μm or more and 20 μm or less. If the electroplating layer is 1 μm or less, the connection reliability of the circuit may not be maintained. If it is thicker than 20 μm, it is difficult to form a resist pattern having a thickness of 20 μm or more, so that a fine circuit cannot be formed.

Subsequently, after peeling off the photoresist 204 that is no longer needed after the electrolytic plating shown in FIG. 2D, the conductive layer 203 is separated as a circuit by etching and removing it, whereby the circuit layer 205 is formed on both sides as shown in FIG. 2E. The finished glass core substrate is obtained.

As shown in FIG. 2F, the first insulating resin layer 207 is formed on both sides of the glass core substrate, and the through-hole portion is also filled. The thickness of the first insulating resin layer is adjusted so that the thickness (T1) from the upper surface of the circuit layer 205 formed on both surfaces of the glass core substrate is 5 μm or more and 30 μm or less. If it is less than 5 μm, it becomes difficult to secure the insulating property between the layers. If it is larger than 30 μm, it becomes difficult to form a minute via hole of 30 μm or less. The method for forming the insulating resin is not limited in the present invention, but a method of forming the first insulating resin layer formed on the support film by thermocompression bonding with a vacuum laminator is preferable because it is general, simple, and has good productivity. The first insulating resin layer can be formed by thermosetting after laminating. The support film may be peeled off before or after thermosetting as appropriate.

The first insulating resin in the present invention is composed of a thermosetting resin and an inorganic filler. Thermocurable resins include epoxy resins, phenolic resins, urea resins, melamine resins, unsaturated polyester resins, polyimide resins, cyanate resins, polyimide resins, benzocyclobutene resins, polybenzoxazole resins, cycloolefin resins and modifications thereof. Things can be mentioned. These resins may be used alone or in combination. Epoxy resin and cyanate resin are more preferable because they are generally used.

The inorganic filler of the first insulating resin in the present invention includes oxides such as glass, silica and alumina, hydroxides such as calcium hydroxide, carbonates such as calcium carbonate, sulfates such as barium sulfate, talc, and the like. Examples thereof include silicates such as mica and wallastonite, but spherical silica is preferable. The reason for this is that it is easy to control the particle size because it is easy to obtain spherical objects with the same particle size, and surface treatment such as silane coupling treatment is possible.

The first insulating resin preferably has an average particle size of the inorganic filler of 0.4 μm or more, a maximum filler diameter of 5 μm or less, and an inorganic filler filling amount of 60 wt% or more. The average particle size of the inorganic filler is a value measured by a laser diffraction particle size distribution measuring device (Microtrack MT 3300EX manufactured by Nikkiso Co., Ltd.). As a result of repeated studies by the present inventor, it has been found that the resin filling / embedding property in the through hole, curing shrinkage, and small diameter via workability of 30 μm or less largely depend on the inorganic filler diameter and distribution, and the filling amount of the inorganic filler. The present invention has been reached. The average particle size of the inorganic filler affects the resin filling property, the small diameter via workability, and the filler filling amount. It was found that when the thickness is less than 0.4 μm, the viscosity does not decrease sufficiently during vacuum thermal laminating, so that fluidity cannot be ensured and the probability of air voids occurring inside the through holes increases. Further, the maximum particle size according to the present invention is 5 μm or less. When the maximum particle size is larger than 5 μm, the shape is bad when processing a fine via hole of 30 μm or less, and it becomes difficult to process the fine via hole with a predetermined size. Therefore, the maximum filler diameter needs to be 5 μm or less. When the filler filling amount is increased, it is not feasible because it is difficult to perform fine filling with an inorganic filler having a single particle size. Therefore, a particle size distribution having an average particle size of 0.4 μm or more and a maximum particle size of 5 μm or less is preferable.

Further, it was found that the amount of curing shrinkage of the resin can be effectively controlled by the amount of the inorganic filler filled, which led to the invention. The amount of the inorganic filler filled in the first insulating resin according to the present invention is 60 wt% or more. If it is less than 60 Wt%, the influence of curing shrinkage is large, and a portion of the through hole directly above 208 where the dent due to curing shrinkage exceeds 5 μm is generated. Fine wiring with L / S = 5/5 μm or less cannot be manufactured with good yield on the surface of the insulating resin. Further, when the filler filling amount is less than 60 wt%, the linear thermal expansion coefficient (CTE) of the first insulating resin layer cannot be sufficiently reduced. The first insulating resin according to the present invention is adjusted so that the coefficient of linear thermal expansion (CTE) from 25 ° C. to the glass transition temperature or lower is 25 ppm or less. By adjusting the coefficient of linear thermal expansion to 25 ppm or less, it is possible to suppress a back crack defect that breaks so as to peel off in the plane direction within the glass thickness when the circuit is individualized. The coefficient of linear thermal expansion can be measured by thermomechanical analysis (TMA) according to JIS K7197: 2012 for plastics.

Subsequently, as shown in FIG. 2G, the via hole 209 is formed by a known method. The diameter of the via hole formed here is preferably 50 μm or less. More preferably, it is 30 μm or less because high-density wiring can be formed. It is desirable that the via hole is formed by a laser processing machine. The laser processing machine can be selected from CO2 laser, UV laser, picosecond laser, femtosecond laser and the like. More preferably, a UV laser is preferable because it is advantageous for small diameter machining of via holes. After forming a via hole by a known laser processing, it is desirable to remove the smear after the laser processing by performing a known desmear treatment.

Subsequently, as shown in FIG. 2H, the first insulating resin and the conductive layer 203 inside the via hole are formed. The conductive layer can be formed by a method selected from electroless plating, sputtering, CVD method, and vapor deposition method. For example, electroless plating can be selected from electroless copper plating and electroless nickel plating. Electroless copper plating is preferable. If it is a sputtering, CVD or vapor deposition method, it can be selected from copper, silver, gold, titanium, nickel, platinum, palladium, chromium and the like. These may be used in combination or individually. More preferably, copper, nickel, titanium, or chromium is preferable because it has good adhesion to the resin. The total thickness of the conductive layer is preferably 2 μm or less. More preferably, it is 1 μm or less because it is advantageous for forming fine wiring.

The step of FIG. 2I is a step of forming the resist pattern 204 on the conductive layer 203 as in the previous step of FIG. 2C. The resist can be selected from a liquid positive resist, a liquid negative resist, and a dry film resist in the same manner as above. Regarding the method for forming the resist layer, the same method as the method described above can be used. After forming resist layers on both surfaces of the conductive layer, a pattern is formed by a photolithography method. It is desirable that the thickness of the resist layer is 3 μm or more and 25 μm or less as before. If it is thinner than 3 μm, the electrolytic plating cannot be increased to 3 μm or more, which may reduce the connection reliability of the circuit. If it is thicker than 25 μm, it becomes difficult to form fine wiring with L / S = 5/5 μm or less.

Subsequently, in the cross-sectional view shown in FIG. 2J, the resist pattern 204 is formed on the conductive layer 203 of FIG. It is a schematic diagram of the removed substrate. In the first insulating resin of the present invention, a dent of 5 μm or more is not generated even in the case of 208 directly above the through hole, so that even a fine wiring having L / S = 5/5 μm or less can be manufactured with good yield. It will be possible.

According to the present invention, as shown in FIG. 2K, the second insulating resin layer 210 is formed on the circuit layer 205 formed on the first insulating resin layer 207. The thickness of the second insulating resin layer is adjusted so that the thickness (T2) from the upper surface of the circuit layer 205 is 5 μm or more and 30 μm or less. When it is 5 μm or less, it becomes difficult to secure the insulating property between the layers. When it is 30 μm or more, it becomes difficult to form a minute via hole of 30 μm or less. The method for forming the insulating resin is not limited in the present invention, but a method of forming the first insulating resin layer formed on the support film by thermocompression bonding with a vacuum laminator is preferable because it is general, simple, and has good productivity. The first insulating resin layer can be formed by thermosetting after laminating. The support film may be peeled off before or after thermosetting as appropriate.

The second insulating resin in the present invention is composed of a thermosetting resin and an inorganic filler. Thermocurable resins include epoxy resins, phenolic resins, urea resins, melamine resins, unsaturated polyester resins, polyimide resins, cyanate resins, polyimide resins, benzocyclobutene resins, polybenzoxazole resins, cycloolefin resins and modifications thereof. Things can be mentioned. These resins may be used alone or in combination. Epoxy resin and cyanate resin are more preferable because they are generally used.

The inorganic filler of the second insulating resin in the present invention includes oxides such as glass, silica and alumina, hydroxides such as calcium hydroxide, carbonates such as calcium carbonate, sulfates such as barium sulfate, talc, and the like. Examples thereof include silicates such as mica and wallastonite, but spherical silica is preferable. The reason for this is that it is easy to control the particle size because it is easy to obtain spherical objects with the same particle size, and surface treatment such as silane coupling treatment is possible.

The second insulating resin preferably has an average filler diameter of 0.2 μm or less, a maximum filler diameter of 2 μm or less, and an inorganic filler filling amount of 65 wt% or less. As a result of repeated research by the present inventor, the filling property inside the through hole is important in the first insulating resin layer, but it is not necessary in the second insulating resin layer. A study was made for the purpose of enabling the formation of higher-density wiring. As a result, in the formation of fine wiring formability of L / S = 5/5 μm or less, more preferably L / S = 3/3 μm or less, and the formation of small diameter via holes with a via diameter of 30 μm or less, more preferably 20 μm or less, the average filler diameter. The present invention has been made by finding that the fine circuit formability is good when the diameter is 0.2 μm or less and the maximum filler diameter is 2 μm or less. If the average filler diameter is larger than 0.2 μm, the via processing shape of 20 μm or less will be deteriorated. Further, when it is larger than 0.2 μm, the unevenness of the resin surface after smearing is large, and the formation of fine wiring with L / S = 3/3 μm or less results in a result that the yield cannot be improved and the production cannot be performed. If the maximum filler diameter is larger than 2 μm, the resin filling property in the space portion between the fine wirings deteriorates, which causes swelling. The average particle size of the inorganic filler according to the present invention is a value measured by a laser diffraction particle size distribution measuring device.

Further, when the filler filling amount is larger than 65 wt%, the filler is exposed on the resin surface in the desmear treatment after the laser via processing, and the adhesion with the conductive layer in the subsequent process is deteriorated, so that the wiring is peeled off. Therefore, it was found that the fine line forming property deteriorated. Therefore, the filler filling amount is preferably 65 wt% or less. From the above, it is preferable that the average filler diameter is 0.2 μm or less, the maximum filler diameter is 2 μm or less, and the inorganic filler filling amount is 65 wt% or less as the second insulating resin.

In the steps after the formation of the second insulating resin layer 210 shown in FIG. 2K, the wiring layer 205 can be formed on the second insulating resin layer 210 by repeating the same steps as in FIGS. 2G to 2J described above (FIG. 2K). 2L). The circuit layer thickness on the second insulating resin layer 210 and the second insulating resin layer may be the same as that on the first insulating resin layer 207 and the first insulating resin layer, but more preferably thinner. good. The via hole diameter may be the same as that of the first insulating resin layer, but more preferably a smaller diameter. FIG. 2M shows a schematic diagram in which a multilayer circuit board using glass as a substrate is produced by repeating the formation of the second insulating resin layer 210 and the formation of the wiring layer twice more.

(Creation of glass core substrate)
As an example and a comparative example of the present invention, a glass circuit board having a 4-2-4 structure was manufactured by the steps shown in FIGS. 2A to 2M. A through hole having a hole diameter of 100 μm was formed on a glass substrate having a thickness of 0.3 mm by a CO ₂ laser, which is a known technique, and annealed at 500 ° C. to remove processing strain (FIG. 2A). Subsequently, as shown in FIG. 2B, the titanium layer 0.05 μm and the copper layer 0.5 μm were sputtered to form the conductive layer 203. Subsequently, after forming both sides of a dry film resist having a thickness of 10 μm, patterning is performed on both sides using a photomask on which a minimum line width L / S = 5/5 μm is drawn, and then patterning is performed by developing with 1% sodium carbonate. A glass substrate was obtained (Fig. 2C). Further, electrolytic plating was performed to a thickness of 7 μm (Fig. 2D), and after stripping the resist, the copper layer of the conductive layer was removed with an etching solution consisting of sulfuric acid-hydrogen peroxide, and the titanium layer was removed with a potassium hydroxide-hydrogen peroxide mixed etchant. , A substrate (FIG. 2E) in which a circuit was formed on glass was obtained.

(First insulation resin layer formation and circuit formation)
Subsequently, as the first insulating resin having a thickness of 12 μm, the first insulating resin layer 207 was formed by vacuum laminating the resins having the contents of Examples 1 and 2 and Comparative Examples 1 to 3 shown in Table 1 (FIG. 2F). .. The thickness of the first insulating resin on the circuit layer 205 was 10 μm. Subsequently, a via hole having a via diameter of 25 μm was formed with a UV-YAG laser, and desmear treatment was performed with an alkaline thermopermanganate solution (FIG. 2G). After the desmear treatment, the conductive layer 203 was formed on both sides by a sputtering method with a titanium layer of 0.04 μm and a copper layer of 0.3 μm (FIG. 2H). Further, a dry film resist having a thickness of 7 μm was formed on both sides and patterned to obtain a substrate having a resist pattern having a minimum line width L / S = 3/3 μm formed on both sides (FIG. 2I). Electroplating was performed to a thickness of 5 μm, resist peeling, and the titanium and copper layers were removed by etching to obtain a glass substrate having a circuit formed on the first insulating resin (FIG. 2J).

(Multilayer circuit formation by repeating the formation of the second insulating resin layer and the circuit formation)
Subsequently, as the second insulating resin having a thickness of 10 μm, the second insulating resin layer 210 was formed by vacuum laminating the second resins of Examples 1 and 2 and Comparative Examples 1 to 3 shown in Table 1. The thickness of the second insulating resin on the circuit layer 205 was 7 μm. Subsequent steps are carried out in the same manner as in FIGS. 2G to 2J. Subsequently, a via hole having a via diameter of 15 μm was formed with a UV-YAG laser, and desmear treatment was performed with an alkaline thermal permanganate solution. After the desmear treatment, a conductive layer was formed on both sides by a sputtering method with a titanium layer of 0.04 μm and a copper layer of 0.2 μm. Further, a liquid positive resist was formed at 5 μm on both sides and patterned to obtain a substrate having a resist pattern formed on both sides. Electroplating was performed to a thickness of 4 μm, resist peeling, titanium, and copper layers were removed by etching to obtain a glass multilayer circuit board in which a circuit with a minimum line width L / S = 2/2 μm was formed on the second insulating resin (. FIG. 2L). Further, by repeating the formation of the second insulating resin layer and the formation of the circuit in the same manner, a multilayer circuit board using a glass having a 4-2-4 structure as a substrate was obtained (FIG. 2M).

Table 1 shows the configurations of the first insulating resin layer and the second insulating resin layer of the glass core substrate according to the examples and comparative examples of the present invention.

The following tests were carried out on the examples and comparative examples of the present invention.
(Test item 1) Reflow heat resistance test results As pretreatment, after dehumidifying and baking at 125 ° C. for 24 hours, holding at 30 ° C., 60% RH, and 192H, 260 ° C. peak reflow was performed three times. Further reflow was performed 20 times. Through-hole voids can be detected by this test.
(Test item 2) AOI inspection result after wiring formation on the first insulating layer Poor resolution and poor wiring formation in the L / S = 5/5 μm portion due to the dent directly above the through hole on the first insulating resin. And defects caused by poorly formed small diameter vias.
(Test item 3) Occurrence of spine cracking after dicing process (Test item 4) AOI inspection result after wiring formation on the second insulating resin Wiring formability and small diameter via workability on the second insulating resin were confirmed.

The test results are shown in Table 2 below. Good results are indicated by ○, and poor results are indicated by ×.

In Examples 1 and 2, the implantability was good without the generation of voids in the through holes. Furthermore, as a result of adjusting the average particle size, the maximum particle size, and the filling amount of the filler within the range of the first insulating resin layer according to the present invention, small diameter via workability, wiring formability, and dents directly above the through hole could be manufactured without any problem. .. Further, even on the second insulating resin, as a result of the control within the range according to the present invention, it was possible to manufacture fine wiring peeling and small diameter via workability without any problem. Further, even in the dicing individualization step, dicing could be performed without any problem without breaking in the glass layer.

Comparative Example 1 is a comparative example in which the average particle size and the maximum particle size are large. Although the results were good in the reflow resistance test, the average particle size of the filler was large, and in the AOI test in Test Item 2, a large number of small-diameter via formation defects and circuit peeling were confirmed. Further, on the second insulating resin layer, the average particle size and the maximum particle size were large, and via processing defects and wiring peeling occurred frequently. Further, probably because the linear thermal expansion coefficient of the first insulating resin layer is large, back cracks occur during dicing and the product cannot be manufactured.

In Comparative Example 2, the average particle size and the maximum particle size of the first insulating resin are within the adjustment range according to the present invention, but the filling amount is as small as 50%. In this result, although there was no problem in the reflow resistance test, poor wiring formation due to the dent directly above the through hole on the first insulating resin layer was confirmed. This result suggests that the effect of curing shrinkage appears because the filler filling amount is small. Further, since the filler filling amount is small, poor back cracking occurs after dicing. In the upper layer of the second insulating resin, the filler diameter was large, and many small-diameter via processing defects and fine wire formation defects were observed, making it difficult to manufacture.

In Comparative Example 3, the average filler diameter and the filling amount are at a level smaller than the range of the present invention. In this case, voids can be confirmed in the reflow resistance test, which suggests that the molten clay is high due to the small average filler diameter. Furthermore, poor wiring formation due to the dent directly above the through hole was confirmed. It is considered that this is because the filling amount of the filler is less than the specified amount. Furthermore, back cracks were confirmed in the process after dicing. In the second insulating resin layer, a lot of circuit peeling was observed, and it was difficult to manufacture with good yield.

As described above, according to the present invention, a first insulating resin having good filling property inside the through hole is laminated on both sides of the glass core substrate on the through hole and the glass core substrate in which metal circuits are formed on both sides of the glass. By doing so, voids generated in the through holes can be effectively suppressed, so that a glass core substrate having long-term connection reliability can be provided. Further, according to the present invention, since the first insulating resin has a large amount of the inorganic filler filled, it is possible to suppress the amount of curing shrinkage of the insulating resin filled inside the through hole, which is caused by the curing shrinkage directly above the through hole. The flatness of the resin surface can be ensured by suppressing the dents. Therefore, it is possible to provide a glass circuit board in which fine circuits can be easily formed and a method for manufacturing the same. Further, by using a second insulating resin on the first insulating resin, which is easier to process fine wiring and small diameter vias, it is possible to provide a glass circuit board having a fine multilayer wiring layer.

The present invention is useful for glass core semiconductor package substrates, interposers, substrates for optical elements, etc., which have high reliability and high-density multilayer wiring.

101 Memory Chip 102 TSV; Through Silicon Via
103 Bump 104 Package Substrate 105 Logic Chip 106 Silicon Interposer 201 Glass Core Substrate 202 Through Hole 203 Conductive Layer 204 Resist Layer (Pattern)
205 Circuit layer 206 Conducted hollow through hole 207 First insulating resin layer 208 First insulating resin layer surface directly above the through hole 209 Via hole 210 Second insulating resin layer

Claims (5)

A glass circuit board having a through hole formed through both sides of the glass substrate, a through hole made of at least a cylindrical hollow metal layer covering the inner wall of the through hole, and a metal circuit formed on both sides of the glass substrate. ,
A part of the metal circuit formed on both sides is connected to the through hole, and the front and back sides are electrically conductive.
At least the hollow portion of the through hole and both sides of the glass circuit board are filled and coated with the same first insulating resin, and the thickness of the first insulating resin laminated on both sides of the glass circuit board is from the upper surface of the metal circuit. In the range of 5 μm or more and 30 μm or less,
The first insulating resin contains a thermosetting resin and an inorganic filler, and the average particle size of the inorganic filler is 0.4 μm or more, the maximum particle size is 5 μm or less, the filling amount of the inorganic filler is 60 wt% or more, and the glass transition temperature is from 25 ° C. The average linear thermal expansion coefficient up to the following is 25 ppm or less,
A via hole and a metal circuit are formed on the first insulating resin, and a via hole and a metal circuit are formed.
One or more layers of the second insulating resin are laminated on the first insulating resin, via holes and metal circuits are formed on each layer of the second insulating resin, and the thickness of the second insulating resin is the lower layer thereof. Within a range of 5 μm or more and 30 μm or less from the upper surface of the metal circuit of the above.
The second insulating resin contains a thermosetting resin and an inorganic filler, and is characterized in that the average filler diameter of the inorganic filler is 0.2 μm or less, the maximum filler diameter is 2 μm or less, and the filling amount of the inorganic filler is 65 wt% or less. Glass circuit board. The glass circuit board according to claim 1, wherein the thickness of the glass substrate is 50 μm or more and 1000 μm or less. The glass circuit board according to claim 1, wherein the linear expansion coefficient of the glass material is 3 ppm / ° C. or higher and 9 ppm / ° C. or lower. The glass circuit substrate according to claim 1, wherein at least one of the first insulating resin and the second insulating resin is made of an epoxy resin, a cyanate resin, or a combination thereof. The glass circuit board according to claim 1, wherein the inorganic filler contained in at least one of the first insulating resin and the second insulating resin is spherical silica.

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