JP6747063B2 - Glass circuit board - Google Patents

Description

The present invention relates to miniaturization of a circuit, improvement of dimensional stability, and improvement of reliability of a glass-based multilayer circuit board, particularly a semiconductor package board, an interposer, and an optical element board.

In order to meet the recent demand for miniaturization and high functionality of electronic devices, a laminated multi-chip package in which a plurality of semiconductor chips are laminated in a semiconductor device has been developed. The stacked multi-chip package is suitable for miniaturization and high integration because a plurality of semiconductor chips are stacked to form a single package, and has been commercialized mainly for memory products such as DRAM. However, in the conventional stacked multi-chip package, since each chip to be stacked and the package substrate are connected by wire bonding, the number of terminals that can be pulled out from each chip is small, and when the number of chips to be stacked is increased, a space for a wire loop and a package are secured. There is a problem that it is difficult to secure a wire bonding pad on the substrate, and it is difficult to stack a large number of chips.

On the other hand, recently, a chip stacking technique using a through silicon via (TSV; Through Silicon Via) as shown in FIG. 1A has been developed. TSV is a through electrode provided on a silicon substrate, and it is possible to electrically connect between the stacked chips and between the chip and the package substrate by using the TSV. FIG. 1A shows an example of a stacked multi-chip package (also called a 3D package) in which a logic chip and a memory chip are three-dimensionally stacked by TSV. In this example, a case where four memory chips 101 are stacked is shown. The memory chips 101 and the logic chip 105 and the package substrate 104 are electrically connected via the TSVs 102, and are connected by the bumps 103. The bumps 103 are formed of solder or a metal such as copper. With the chip stacking technology using such TSVs, it is possible to easily increase the number of chips to be stacked because the wires that have been used conventionally are not necessary, and further, the connection distances between chips and between the chips and the package substrate can be improved. It is also shortened, which is advantageous for high-speed signal transmission. Further, while the conventional wire for wire bonding has a diameter of 20 to 30 μm, the TSV can be formed with a diameter of 10 μm or less, so that more terminals can be drawn out and a large capacity communication can be achieved. There are many merits such as being possible.

However, many steps are required to manufacture the semiconductor chip with TSV, which causes a problem that manufacturing takes time and cost. Further, in the case of the 3D package shown in FIG. 1A in which the TSV is formed on the logic chip, since the memory chip and the logic chip are connected with the TSV having the same pitch, a unified standard of the TSV bump pitch between the manufacturers of the logic chip and the memory chip. Need to be provided. In this case, there is a problem in that the design cost of the logic chip is limited and the design cost is increased. Further, in the case of the 3D package, it is necessary to assemble the chips manufactured by the logic chip manufacturer and the memory chip manufacturer by the assembly manufacturer and then mount the chips on the semiconductor package substrate. When defects are discovered after assembling even semiconductor packages, there are many problems such as quality assurance and manufacturing responsibility that it is not possible to clarify whether it is a defect at the assembly manufacturer or a manufacturing defect of any chip manufacturer, which is an obstacle to popularization It has become.

From the above, it is considered that the multi-chip package shown in FIG. 1B, in which the three-dimensional chip of the DRAM memory in which TSV stacking is relatively easy and the logic chip are horizontally mounted on the semiconductor package substrate, is most realistic. (So-called 2.5D package). In the 3D package, the signal wiring between the memory and the logic is connected by a minute TSV, but in the 2.5D package, the signal line connection between the plurality of semiconductor chips needs to be planarly connected on the semiconductor package substrate. Becomes Therefore, the number of wirings is inevitably large on the semiconductor package substrate side, and the demand for finer/multi-layered is becoming more severe. In this application, fine wiring with L/S=5/5μm or less is formed. Technology and interlayer connection with a via diameter of 30 μm or less are required. Therefore, in the 2.5D package, as shown in FIG. 1B, the three-dimensional laminated memory and the logic chip are mounted on a silicon interposer 106 manufactured by a semiconductor process, which enables fine connection, and a semiconductor chip is further mounted. A method of mounting the silicon interposer 106 on the semiconductor package substrate 104 has been proposed (see Patent Documents 1 to 4).

However, since the silicon interposer is manufactured by a wafer process, there is a problem that the manufacturing cost is higher than that of a semiconductor package substrate manufactured in a panel size larger than that of the wafer. Further, the silicon interposer has a problem that the process cost for forming the TSV is high. Further, since silicon is a semiconductor, in order to form a wiring circuit, it is necessary to form an oxide film on the silicon surface to insulate it and then form circuit wiring. Therefore, there is a problem that the transmission characteristics of the wiring circuit formed on the silicon interposer are worse than those of the circuit formed on the glass substrate or the glass epoxy substrate which is an insulator.

Therefore, the glass interposer is attracting attention as an interposer having a material other than silicon as the core layer, and research and development have been activated. The advantage of using glass for the core layer is that various thicknesses and sizes are not limited, and it is inexpensive, and smoothness and flatness are excellent. Therefore, fine wiring with L/S=5/5 μm or less is formed. That the linear thermal expansion coefficient (CTE) is around 3 ppm, which is similar to that of silicon, it has excellent mounting stability, dimensional stability, and high elasticity, excellent chemical stability, and high insulation. The transmission characteristics can be improved. Furthermore, due to its optical transparency, it is also gaining attention as a use for optical elements such as image pickup elements. Further, a technique for forming a through hole in a glass substrate has been developed, and it has become possible to perform a fine through hole having a diameter of 50 μm or more and 100 μm or less even if the glass thickness is 300 μm by electric discharge machining or laser machining.

Here, a glass interposer is taken as an example to briefly explain a method of manufacturing a circuit board using glass as a main body. In this example, a method of manufacturing the semiconductor package substrate by a built-up method, which is equivalent to that of the semiconductor package substrate, is shown. First, a glass substrate to be a base is prepared. Through holes are formed in a glass substrate by using a known method such as electric discharge machining or laser machining. Then, a thin metal layer having a thickness of 1 μm or less is formed on the glass surface and the inner surface of the through hole by a known method such as electroless plating or a sputtering method, a vapor deposition method, a CVD method or the like on the glass, and a conductive treatment is performed.

Multiple paths are possible in subsequent steps. In the first method, so-called through-hole filling is conceivable in which electric current is applied to the entire thin metal layer for electrolytic plating to fill the metal in the double-sided surface layer and the through-hole. This method has an advantage that a via can be formed right above the through hole and space can be saved. However, when the inside of the through hole having a diameter of 50 μm to 100 μm is entirely filled with electrolytic plating, both surface metal thicknesses are at least 25 μm to 50 μm. And get thicker. In this case, after forming a photo rest pattern on the surface metal by photolithography, wiring is formed by a subtractive method in which an unnecessary metal layer portion is removed by etching.In this method, a thick metal layer is required by an interposer. It becomes impossible to form a fine circuit. Further, it is difficult to completely fill the inside of the through hole with the electrolytic plating layer, depending on the shape of the through hole such as the glass thickness and the aspect ratio of the hole diameter. Especially, when the aspect ratio is 2 or more, the inside of the through hole is There was a problem that the voids and seams were included and the reliability decreased.

In the second method, the thin metal layer is similarly energized to carry out electrolytic plating to plate both surfaces of the surface layer and the inside of the through hole, but after the plating is completed before the through hole is filled, the surface metal is In this method, a circuit is formed by patterning a photorest on the top and removing an unnecessary metal layer by etching. As a result of examination by the present inventors, even in this method, it was impossible to form a fine circuit required for an interposer application because the miniaturization limit was reached at L/S=20/20 μm. Similarly, it is very difficult to form fine wiring with L/S=5/5 μm or less even in wiring formation by hole filling printing, polishing, lid plating, and subtractive methods, which are known manufacturing methods for printed wiring boards.

The third method is to form a resist layer on a thin metal layer, perform patterning so as to remove the resist on the through hole portion and the wiring portion, and then simultaneously form and increase the wiring and the through hole by electrolytic plating. In this method, a thin metal layer is removed by etching after the resist is removed by a semi-additive method. According to this method, it is possible to form fine wiring of L/S=5/5 μm or less required for the interposer. In a later process, the build-up resin can be formed on both surfaces of the surface layer circuit by heating and pressurizing it with a vacuum laminator, and the surface layer insulating layer can be formed and the build-up resin filling protection inside the hollow through-hole can be performed at the same time. Therefore, it is an efficient method.

However, when the above-mentioned third method is carried out, even if the filling is performed by the vacuum laminating method depending on the resin used, the build-up resin cannot be filled up to the inside of the through hole and the air void is included. A semiconductor device assembling process, for example, a thermal history such as mass reflow, causes the enclosed voids to burst, causing a problem that the reliability of the circuit board cannot be ensured.

Further, in the case of a resin having poor fluidity, the thickness of the resin around the through hole becomes thin, which causes a problem that a recess is formed directly above the through hole. Even if the resin has good fluidity and can be laminated flat, the resin thickness on the through-hole part is thicker than on the flat glass part without the through-hole, so that the curing shrinkage of the resin does not occur. In the case of a large size, there was a problem that a recess was formed immediately above the through hole. As described above, the resin immediately above the through hole has a recess of about 5 μm, and since the flatness cannot be secured, a chronic problem that a fine circuit cannot be formed occurs.

Furthermore, when the linear thermal expansion coefficient of the resin formed directly above the glass circuit is large, the stress due to the difference in the linear thermal expansion coefficient between the glass substrate and the insulating resin layer accumulates due to the thermal history in the subsequent process. In addition, in the dicing step of dividing the glass core substrate into pieces, there is a problem that a back crack phenomenon in which the glass core substrate breaks so as to peel off in the plane direction within the glass thickness is likely to occur.

JP 2001-102479 A JP, 2002-373962, A JP, 2002-261204, A JP, 2000-332168, A

The present invention has been made in order to solve the above-mentioned problems, and an object thereof is to make it possible to form a fine circuit by ensuring the flatness of an insulating resin layer while ensuring long-term reliability. It is an object of the present invention to provide a glass-based wiring board on which a fine multilayer circuit can be easily formed and a method for manufacturing the same.

One aspect of the present invention is a glass having a through hole formed through both surfaces of a glass substrate, a through hole formed of a cylindrical hollow metal layer covering at least the inner wall of the through hole, and a metal circuit formed on both surfaces of the glass substrate. In the circuit board, a part of the metal circuit formed on both sides is connected to the through hole, the front and back sides are electrically conducted, and at least the hollow part of the through hole and both surfaces of the glass circuit board are made of the same first insulating resin. Filled and coated, the first insulating resin contains a thermosetting resin and an inorganic filler, the inorganic filler has an average particle size of 0.4 μm or more, a maximum particle size of 5 μm or less, an inorganic filler filling amount of 60 wt% or more, and glass from 25° C. the average linear thermal expansion coefficient of up to below the transition temperature of Ri der less 25 ppm, via holes and metal circuit on the first insulating resin is formed, a layer of one or more second insulating resin on the first insulating resin is laminated, the A via hole and a metal circuit are formed on each layer of the second insulating resin, and the second insulating resin contains a thermosetting resin and an inorganic filler, and the average filler diameter of the inorganic filler is 0.2 μm or less and the maximum filler diameter is 2 μm. hereinafter, the inorganic filler loading is Ru der less 65 wt%.

Further, a metal layer, a glass substrate duplex, the first insulating resin, and a metal circuit formed on each layer of the second insulating resin is at least copper, nickel, titanium, may include either chromium.

According to the present invention, a glass core substrate having through-holes and metal circuits formed on both sides of the glass is laminated with a first insulating resin having good filling properties into the through holes on both sides of the glass core substrate. Since voids generated in the holes can be effectively suppressed, it is possible to provide a glass core substrate having long-term connection reliability. Furthermore, according to the present invention, since the first insulating resin has a large amount of the inorganic filler filled therein, it is possible to suppress the amount of curing shrinkage of the insulating resin filled inside the through hole, which results from the curing shrinkage just above the through hole. The flatness of the resin surface can be ensured by suppressing the depression. Therefore, it is possible to provide a glass circuit board on which a fine circuit can be easily formed and a manufacturing method thereof. Further, a glass circuit board having a fine multi-layer wiring layer can be provided by using a second insulating resin on which the fine wiring and small-diameter vias can be easily processed on the first insulating resin.

Schematic diagram of conventional stacked multi-multi chip package (3D package) Schematic diagram of conventional stacked multi-multi chip package (2.5D package via interposer) The schematic diagram which shows the manufacturing process of the glass circuit board in one Embodiment of this invention. The schematic diagram which shows the manufacturing process of the glass circuit board in one Embodiment of this invention. The schematic diagram which shows the manufacturing process of the glass circuit board in one Embodiment of this invention. The schematic diagram which shows the manufacturing process of the glass circuit board in one Embodiment of this invention. The schematic diagram which shows the manufacturing process of the glass circuit board in one Embodiment of this invention. The schematic diagram which shows the manufacturing process of the glass circuit board in one Embodiment of this invention. The schematic diagram which shows the manufacturing process of the glass circuit board in one Embodiment of this invention. The schematic diagram which shows the manufacturing process of the glass circuit board in one Embodiment of this invention. The schematic diagram which shows the manufacturing process of the glass circuit board in one Embodiment of this invention. The schematic diagram which shows the manufacturing process of the glass circuit board in one Embodiment of this invention. The schematic diagram which shows the manufacturing process of the glass circuit board in one Embodiment of this invention. The schematic diagram which shows the manufacturing process of the glass circuit board in one Embodiment of this invention. The schematic diagram which shows the manufacturing process of the glass circuit board in one Embodiment of this invention.

An embodiment of the present invention will be described below in detail with reference to the sectional views 2A to 2M. This embodiment is an example of the embodiment of the present invention, and the glass core substrate of the present invention is not limited by the following description.

First, a glass core 201 having a through hole 202 shown in FIG. 2A is prepared. The glass core 201 can be formed by providing a through hole 202 in a glass material by a known method. The glass material is not limited to the present invention, but has SiO ₂ as a main component. As the glass material, low expansion glass having a linear expansion coefficient of 3 to 4 ppm/°C, soda glass having a linear expansion coefficient of 8 to 9 ppm/°C, or the like can be used. The linear expansion coefficient of the glass material can be adjusted within the range of 3 to 9 ppm/° C. by changing the manufacturing method or adding a metal component such as Na. The coefficient of linear expansion (CTE) can be measured by thermomechanical analysis (TMA) according to JIS R3102:1995 for glass or JIS K7197:2012 for plastics. The glass substrate preferably has a thickness in the range of 50 μm to 1000 μm. More preferably, it is 100 μm or more and 500 μm or less. If it is 50 μm or less, handling becomes difficult during the manufacturing process. If it is 1000 μm or more, it becomes difficult to process fine through holes having a diameter of 100 μm or less and a pitch of 200 μm or less.

Known methods for the through-hole processing include laser processing, electric discharge processing, sandblasting when a photosensitive resist material is used, dry etching, and chemical etching processing using hydrofluoric acid or the like. Further, the glass core can be prepared by using a photosensitive glass. Laser processing and electric discharge processing are preferable because they are simple and have high throughput. A laser that can be used can be selected from a CO ₂ laser, a UV laser, a picosecond laser, a femtosecond laser, and the like.

Subsequently, as shown in FIG. 2B, the conductive layer 203 is formed on the inner wall and the surface of the through hole of the glass core substrate 201. The conductive layer 203 may be formed after introducing an adhesion layer (not shown) on the glass core substrate 201. The adhesive layer is introduced to improve the adhesiveness between the glass surface and the conductive layer 203, and is not intended to limit the present invention, but as an example, tin oxide, indium oxide, zinc oxide, nickel- It can be selected from one or more selected from the group consisting of phosphorus (Ni-P), chromium, chromium oxide, aluminum nitride, copper nitride, aluminum oxide, tantalum, titanium and copper. More preferably, it is desired to be selected from titanium and chromium. The thickness of the adhesion layer is not limited to the present invention, but is preferably 0.01 μm or more and 1 μm or less. The adhesion layer can be formed by using any technique known in the art, such as a sputtering method, an electroless plating method, a CVD method, and a vapor deposition method.

The conductive layer 203 is preferably made of a material having high electrical connection stability. Materials that can be used are, for example, metals selected from the group consisting of copper, silver, gold, nickel, platinum, palladium, ruthenium and tin, and tin-silver, tin-silver-copper, tin-copper, tin-. Includes an alloy selected from the group consisting of bismuth and tin-lead. Copper or nickel is preferable. The thickness of the conductive layer is not limited to the present invention, but is preferably 0.01 μm or more and 1 μm or less. The method of forming the conductive layer can be selected from, for example, a sputtering method, an electroless plating method, a CVD method, a vapor deposition method and the like.

Subsequently, as shown in FIG. 2C, a resist pattern 204 is formed on the glass core substrate on which the conductive layer 203 is formed. The resist can be selected from liquid positive resist, liquid negative resist, and dry film resist. The liquid resist coating method can be selected from slit coating, curtain coating, die coating, spray coating, electrostatic coating, inkjet coating, gravure coating, screen printing, gravure offset printing, spin coating, and doctor coating. If it is a dry film resist, the resist layer can be formed by a roll laminator. After forming a resist layer on both surfaces of the conductive layer, a desired pattern is formed on the glass core substrate by photolithography. The resist pattern is aligned and patterned so that a portion where a later electrolytic plating layer is formed is exposed. The thickness of the resist layer depends on the thickness of electrolytic plating in the subsequent step, but is preferably 3 μm or more and 25 μm or less. If the thickness is less than 3 μm, electrolytic plating cannot be increased to 3 μm or more, and the connection reliability of the circuit may decrease. When the thickness is more than 25 μm, it becomes difficult to form fine wiring with L/S=5/5 μm or less.

Subsequently, as shown in FIG. 2D, an electrolytic plated circuit layer 205 is formed by electrolytic plating using the conductive layer. The electrolytic plating can increase the thickness of the inner wall 206 of the through hole and the metal layer of the circuit portion. The metal that can be electroplated can be selected from copper, nickel, tin, gold, silver, solder and the like. Desirably, copper and nickel are preferable because they are simple and inexpensive. The thickness of electrolytic plating is preferably 1 μm or more and 20 μm or less. If the electrolytic plating layer is 1 μm or less, the connection reliability of the circuit may not be maintained. If the thickness is thicker than 20 μm, it is difficult to form a resist pattern having a thickness of 20 μm or more, so that a fine circuit cannot be formed.

Subsequently, after removing the photoresist 204 that is no longer needed after the electrolytic plating described in FIG. 2D, the conductive layer 203 is removed by etching to separate it into a circuit, thereby forming the circuit layers 205 on both surfaces as illustrated in FIG. 2E. The obtained glass core substrate is obtained.

As shown in FIG. 2F, the first insulating resin layer 207 is formed on both surfaces of the glass core substrate, and the through holes are also filled. The thickness of the first insulating resin layer is adjusted to be 5 μm or more and 30 μm or less from the upper surface of the circuit layer 205 formed on both surfaces of the glass core substrate. When the thickness is less than 5 μm, it becomes difficult to secure insulation between layers. If it is larger than 30 μm, it becomes difficult to form a minute via hole of 30 μm or less. The method of forming the insulating resin is not limited in the present invention, but a method of forming the first insulating resin layer formed on the support film by thermocompression bonding with a vacuum laminator is preferable because it is general and simple and has good productivity. The first insulating resin layer can be formed by thermosetting after laminating. The peeling of the support film may be carried out before or after thermosetting and may be carried out appropriately.

The first insulating resin in the present invention is composed of a thermosetting resin and an inorganic filler. Examples of the thermosetting resin include epoxy resin, phenol resin, urea resin, melamine resin, unsaturated polyester resin, polyimide resin, cyanate resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, cycloolefin resin and modifications thereof. Things can be mentioned. These resins may be used alone or in combination. Epoxy resin and cyanate resin are more preferable because they are common.

The inorganic filler of the first insulating resin in the present invention, glass, silica, oxides such as alumina, hydroxides such as calcium hydroxide, carbonates such as calcium carbonate, sulfates such as barium sulfate, talc, Examples thereof include silicates such as mica and wollastonite, and spherical silica is preferable. The reason is that spherical particles having a uniform particle size are easily obtained, so that the particle size can be easily controlled and surface treatment such as silane coupling treatment is possible.

The first insulating resin preferably has an average particle diameter of the inorganic filler of 0.4 μm or more, a maximum filler diameter of 5 μm or less, and an inorganic filler filling amount of 60 wt% or more. The average particle size of the inorganic filler is a value measured by a laser diffraction particle size distribution measuring device (Microtrac MT 3300EX manufactured by Nikkiso Co., Ltd.). As a result of repeated studies by the present inventor, it was found that the resin filling/embedding property in the through hole, the curing shrinkage, and the workability of small-diameter vias of 30 μm or less largely depend on the inorganic filler diameter and distribution and the inorganic filler filling amount. The present invention was reached. The average particle size of the inorganic filler affects the resin filling property, the small diameter via processing property, and the filler filling amount. It was found that when the thickness is less than 0.4 μm, the fluidity cannot be ensured because the viscosity does not fall sufficiently during vacuum heat lamination, and the probability of air voids occurring inside the through hole increases. Further, the maximum particle size according to the present invention is 5 μm or less. If the maximum particle size is larger than 5 μm, the shape is not good when processing a fine via hole of 30 μm or less, and it becomes difficult to process with a predetermined size, so the maximum filler diameter needs to be 5 μm or less. In the case of increasing the filler filling amount, it is difficult to achieve fine packing with an inorganic filler having a single particle size, which is impossible. Therefore, a particle size distribution having an average particle size of 0.4 μm or more and a maximum particle size of 5 μm or less is suitable.

Further, it was found that the curing shrinkage amount of the resin can be effectively controlled by the inorganic filler filling amount, and the present invention was accomplished. The inorganic filler filling amount of the first insulating resin according to the present invention is 60 wt% or more. When it is less than 60 Wt %, the curing shrinkage has a large effect, and the portion 208 immediately above the through hole has a recess exceeding 5 μm due to the curing shrinkage. It becomes impossible to manufacture fine wiring with L/S=5/5 μm or less on the surface of the insulating resin with a high yield. Further, when the filler filling amount is less than 60 wt %, the linear thermal expansion coefficient (CTE) of the first insulating resin layer cannot be sufficiently reduced. The first insulating resin according to the present invention is adjusted so that the coefficient of linear thermal expansion (CTE) from 25° C. to the glass transition temperature is 25 ppm or less. By adjusting the coefficient of linear thermal expansion to 25 ppm or less, it is possible to suppress a back crack defect that breaks so as to peel in the in-plane direction of the glass thickness when the circuit is singulated. The linear thermal expansion coefficient can be measured by thermomechanical analysis (TMA) according to JIS K7197:2012 for plastics.

Subsequently, as shown in FIG. 2G, a via hole 209 is formed by a known method. The diameter of the via hole formed here is preferably 50 μm or less. More preferably, the thickness is 30 μm or less because high-density wiring can be formed. It is desirable that the via hole be formed by a laser processing machine. The laser processing machine can be selected from CO ₂ laser, UV laser, picosecond laser, femtosecond laser and the like. A UV laser is more preferable because it is advantageous for processing a small diameter via hole. After forming a via hole by a known laser processing, it is desirable to remove smear after the laser processing by performing a known desmear treatment.

Subsequently, as shown in FIG. 2H, the first insulating resin and the conductive layer 203 inside the via hole are formed. The conductive layer can be formed by a method selected from electroless plating, sputtering, CVD method and vapor deposition method. For example, electroless plating can be selected from electroless copper plating and electroless nickel plating. Electroless copper plating is preferable. The sputtering, CVD or vapor deposition method can be selected from copper, silver, gold, titanium, nickel, platinum, palladium, chromium and the like. These may be used in combination or may be used alone. More preferably, copper, nickel, titanium, and chromium are desirable because they have good adhesion to the resin. The total thickness of the conductive layer is preferably 2 μm or less. More preferably, it is 1 μm or less because it is advantageous for forming fine wiring.

The step of FIG. 2I is a step of forming the resist pattern 204 on the conductive layer 203, similarly to the step of FIG. 2C. The resist can be selected from a liquid positive resist, a liquid negative resist and a dry film resist as described above. Regarding the method of forming the resist layer, the same method as that described above can be used. After forming a resist layer on both surfaces of the conductive layer, a pattern is formed by photolithography. The thickness of the resist layer is preferably 3 μm or more and 25 μm or less, as in the above. If the thickness is less than 3 μm, electrolytic plating cannot be increased to 3 μm or more, and the connection reliability of the circuit may decrease. If the thickness is more than 25 μm, it becomes difficult to form fine wiring with L/S=5/5 μm or less.

Subsequently, in the cross-sectional view illustrated in FIG. 2J, similarly to the above description, after forming the resist pattern 204 on the conductive layer 203 in FIG. 2I, electrolytic plating is performed, the resist layer is peeled and removed, and then the conductive layer 203 is etched. It is a schematic diagram of the removed substrate. Since the first insulating resin of the present invention does not cause a recess of 5 μm or more even in the portion directly above the through hole 208, even fine wiring of L/S=5/5 μm or less can be manufactured with a good yield. It will be possible.

According to the present invention, as shown in FIG. 2K, the second insulating resin layer 210 is formed on the circuit layer 205 formed on the first insulating resin layer 207. The thickness of the second insulating resin layer is adjusted to be 5 μm or more and 30 μm or less from the upper surface of the circuit layer 205. When the thickness is 5 μm or less, it becomes difficult to secure insulation between layers. When it is 30 μm or more, it becomes difficult to form a minute via hole of 30 μm or less. The method of forming the insulating resin is not limited in the present invention, but a method of forming the first insulating resin layer formed on the support film by thermocompression bonding with a vacuum laminator is preferable because it is general and simple and has good productivity. The first insulating resin layer can be formed by thermosetting after laminating. The peeling of the support film may be carried out before or after thermosetting and may be carried out appropriately.

The second insulating resin in the present invention is composed of a thermosetting resin and an inorganic filler. Examples of the thermosetting resin include epoxy resin, phenol resin, urea resin, melamine resin, unsaturated polyester resin, polyimide resin, cyanate resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, cycloolefin resin and modifications thereof. Things can be mentioned. These resins may be used alone or in combination. Epoxy resin and cyanate resin are more preferable because they are common.

The inorganic filler of the second insulating resin in the present invention, glass, silica, oxides such as alumina, hydroxides such as calcium hydroxide, carbonates such as calcium carbonate, sulfates such as barium sulfate, talc, Examples thereof include silicates such as mica and wollastonite, and spherical silica is preferable. The reason is that spherical particles having a uniform particle size are easily obtained, so that the particle size can be easily controlled and surface treatment such as silane coupling treatment is possible.

The second insulating resin preferably has an average filler diameter of 0.2 μm or less, a maximum filler diameter of 2 μm or less, and an inorganic filler filling amount of 65 wt% or less. As a result of repeated studies by the present inventor, the filling property inside the through hole is important in the first insulating resin layer, but not necessary in the second insulating resin layer, and it is specialized in fine via forming property and fine wiring forming property. A study was conducted for the purpose of enabling higher density wiring formation. As a result, L/S=5/5 μm or less, more preferably L/S=3/3 μm or less fine wiring formability, and a via diameter of 30 μm or less, more preferably 20 μm or less. Of 0.2 μm or less and a maximum filler diameter of 2 μm or less, the present invention was found to have good formability of fine circuits. When the average filler diameter is larger than 0.2 μm, the via processed shape of 20 μm or less is deteriorated. Further, if it is larger than 0.2 μm, the unevenness of the resin surface after smear is large, and the result is that the fine wiring with L/S=3/3 μm or less cannot be manufactured with a high yield. When the maximum filler diameter is larger than 2 μm, the resin filling property into the space between the fine wirings deteriorates, which causes swelling. The average particle size of the inorganic filler according to the present invention is a value measured by a laser diffraction particle size distribution measuring device.

Further, when the filler filling amount is larger than 65 wt %, the filler is exposed on the resin surface in the desmear treatment after the laser via processing, and the adhesiveness with the conductive layer in the subsequent step is deteriorated, causing peeling of the wiring. It was found that the fine line formability deteriorates. Therefore, the filler filling amount is preferably 65 wt% or less. From the above, it is suitable for the second insulating resin that the average filler diameter is 0.2 μm or less, the maximum filler diameter is 2 μm or less, and the inorganic filler filling amount is 65 wt% or less.

In the steps after the formation of the second insulating resin layer 210 shown in FIG. 2K, the wiring layer 205 can be formed on the second insulating resin layer 210 by repeating the same steps as those of FIGS. 2L). The thickness of the circuit layer on the second insulating resin layer 210 and the second insulating resin layer may be the same as that of the circuit layers on the first insulating resin layer 207 and the first insulating resin layer, but more preferably it may be thin. good. The diameter of the via hole may be the same as that of the first insulating resin layer, but more preferably it may be smaller. FIG. 2M shows a schematic view in which the formation of the second insulating resin layer 210 and the formation of the wiring layer are repeated twice more to form a multilayer circuit board having glass as a base.

(Creation of glass core substrate)
As an example and a comparative example of the present invention, a glass circuit board having a 4-2-4 structure was manufactured by the steps shown in FIGS. A through-hole having a hole diameter of 100 μm was formed on a glass substrate having a thickness of 0.3 mm by a known technique of CO ₂ laser, and annealing was performed at 500° C. to remove processing strain (FIG. 2A). Subsequently, as shown in FIG. 2B, the titanium layer 0.05 μm and the copper layer 0.5 μm were sputtered to form the conductive layer 203. Subsequently, after forming a dry film resist having a thickness of 10 μm on both sides, patterning is performed on both sides using a photomask on which a minimum line width L/S=5/5 μm is drawn, followed by development treatment with 1% sodium carbonate to perform patterning. A glass substrate was obtained (Fig. 2C). Further, electroplating is performed to a thickness of 7 μm (FIG. 2D), and after removing the resist, the copper layer of the conductive layer and the titanium layer are removed with a potassium hydroxide-hydrogen peroxide mixed etchant with an etching solution containing sulfuric acid-hydrogen peroxide. A substrate having a circuit formed on glass (FIG. 2E) was obtained.

(First insulating resin layer formation and circuit formation)
Subsequently, as the first insulating resin having a thickness of 12 μm, the first insulating resin layer 207 was formed by vacuum laminating the resins having the contents of Examples 1 and 2 and Comparative Examples 1 to 3 shown in Table 1 (FIG. 2F). .. The thickness of the first insulating resin on the circuit layer 205 was 10 μm. Then, a via hole having a via diameter of 25 μm was formed with a UV-YAG laser, and desmear treatment was performed with an alkaline hot permanganate solution (FIG. 2G). After the desmear treatment, a conductive layer 203 was formed on both sides of the titanium layer 0.04 μm and the copper layer 0.3 μm by the sputtering method (FIG. 2H). Further, a 7 μm thick dry film resist was formed on both sides and patterned to obtain a substrate having a resist pattern with a minimum line width L/S=3/3 μm formed on both sides (FIG. 2I). Electrolytic plating was performed to a thickness of 5 μm to remove the resist, and the titanium and copper layers were removed by etching to obtain a glass substrate having a circuit formed on the first insulating resin (FIG. 2J).

(Multilayer circuit formation by repeating second insulating resin layer formation and circuit formation)
Then, the second insulating resin layer 210 was formed by vacuum laminating the second resins of Examples 1 and 2 and Comparative Examples 1 to 3 shown in Table 1 as the second insulating resin having a thickness of 10 μm. The thickness of the second insulating resin on the circuit layer 205 was 7 μm. Subsequent steps are performed similarly to FIGS. Subsequently, a via hole having a via diameter of 15 μm was formed with a UV-YAG laser, and desmear treatment was performed with an alkaline hot permanganate solution. After the desmear treatment, a conductive layer was formed on both surfaces by sputtering with a titanium layer of 0.04 μm and a copper layer of 0.2 μm. Further, a liquid positive resist having a thickness of 5 μm was formed on both surfaces and patterned to obtain a substrate having resist patterns formed on both surfaces. A glass multilayer circuit board having a circuit with a minimum line width L/S=2/2 μm formed on the second insulating resin was obtained by performing electrolytic plating with a thickness of 4 μm and removing the resist and etching away the titanium and copper layers ( FIG. 2L). Further, by repeating the formation of the second insulating resin layer and the formation of the circuit by the same method, a multi-layer circuit board having a 4-2-4 structure glass as a base body was obtained (FIG. 2M).

Table 1 shows the configurations of the first insulating resin layer and the second insulating resin layer of the glass core substrates according to Examples and Comparative Examples of the present invention.

The following tests were conducted on the examples and comparative examples of the present invention.
(Test item 1) Results of reflow heat resistance test As a pretreatment, after dehumidifying bake at 125°C for 24 hours, holding at 30°C, 60% RH, and 192H, 260°C peak reflow was performed three times. Further, reflow was performed 20 times. Through-hole voids can be detected by this test.
(Test item 2) AOI inspection result after formation of wiring on the first insulating layer Defects in the L/S=5/5 μm portion and wiring formation failure due to the depression right above the through hole on the first insulating resin. And a defect occurs due to a defective formation of a small diameter via.
(Test item 3) Occurrence of back crack after dicing process (Test item 4) AOI inspection result after wiring formation on second insulating resin Wiring formability on the second insulating resin and small-diameter via workability were confirmed.

The test results are shown in Table 2 below. Good results are indicated by ◯, and other results are indicated by x.

In Examples 1 and 2, the embeddability was good without the generation of voids in the through holes. Furthermore, as a result of adjusting the average particle size, the maximum particle size, and the filling amount of the filler within the range of the first insulating resin layer according to the present invention, the small-diameter via processability, the wiring formability, and the depression directly above the through hole can be produced without any problem. .. Further, even on the second insulating resin, as a result of control within the range according to the present invention, peeling of fine wiring and small-diameter via workability could be produced without problems. Further, even in the dicing individualization process, dicing could be performed without causing any cracks in the glass layer.

Comparative Example 1 is a comparative example in which the average particle size and the maximum particle size are large. Although the results were good in the reflow resistance test, the average particle size of the filler was large, and in the AOI test in test item 2, many small-diameter via formation defects and circuit peeling were confirmed. Further, on the second insulating resin layer, the average particle diameter and the maximum particle diameter were large, and via processing defects and wiring peeling occurred frequently. Furthermore, probably because the linear thermal expansion coefficient of the first insulating resin layer was large, back cracking occurred during dicing, and manufacturing was not possible.

In Comparative Example 2, the average particle size and the maximum particle size of the first insulating resin are within the adjustment range according to the present invention, but the filling amount is as small as 50%. In this result, although there was no problem in the reflow resistance test, it was confirmed that the wiring formation failure was caused by the depression just above the through hole on the first insulating resin layer. It is suggested that this result is due to the effect of curing shrinkage due to the small filler loading. Furthermore, since the filler filling amount is small, back cracking defects after dicing occur. In the upper layer of the second insulating resin, the filler diameter was large, and many small diameter via processing defects and fine line formation defects were observed, making it difficult to manufacture.

In Comparative Example 3, the average filler diameter and the filling amount are smaller than the range of the present invention. In this case, voids can be confirmed in the reflow resistance test, which suggests that the molten clay becomes high because the average filler diameter is small. Further, it was confirmed that the wiring formation failure was caused by the depression right above the through hole. It is considered that this is because the filling amount of the filler is less than the specified amount. In addition, back cracks were confirmed in the process after dicing. In the second insulating resin layer, a large amount of circuit peeling was observed, and it was difficult to manufacture with good yield.

As described above, according to the present invention, the first insulating resin, which has a good filling property into the through hole, is laminated on both surfaces of the glass core substrate, on the glass core substrate having the through-holes and the metal circuits formed on both surfaces of the glass. By doing so, voids generated in the through holes can be effectively suppressed, and thus a glass core substrate having long-term connection reliability can be provided. Furthermore, according to the present invention, since the first insulating resin has a large amount of the inorganic filler filled therein, it is possible to suppress the amount of curing shrinkage of the insulating resin filled inside the through hole, which results from the curing shrinkage just above the through hole. The flatness of the resin surface can be ensured by suppressing the depression. Therefore, it is possible to provide a glass circuit board on which a fine circuit can be easily formed and a manufacturing method thereof. Further, a glass circuit board having a fine multi-layer wiring layer can be provided by using a second insulating resin on which the fine wiring and small-diameter vias can be easily processed on the first insulating resin.

INDUSTRIAL APPLICABILITY The present invention is useful for a glass core semiconductor package substrate, an interposer, a substrate for an optical element, etc., which has high reliability and high-density multilayer wiring.

101 memory chip 102 TSV; Through Silicon Via
103 bumps 104 package substrate 105 logic chip 106 silicon interposer 201 glass core substrate 202 through hole 203 conductive layer 204 resist layer (pattern)
205 Circuit Layer 206 Hollow Conductive Through Hole 207 First Insulating Resin Layer 208 First Insulating Resin Layer Surface 209 Immediately Above the Through Hole 209 Via Hole 210 Second Insulating Resin Layer

Claims (2)

A glass circuit board having a through hole penetrating both sides of the glass substrate, a through hole formed of a cylindrical hollow metal layer covering at least the inner wall of the through hole, and a metal circuit formed on both sides of the glass substrate. ,
Part of the metal circuit formed on both sides is connected to the through hole, the front and back are electrically conducted,
At least the through-hole hollow portion and both surfaces of the glass circuit board are filled and covered with the same first insulating resin,
The first insulating resin contains a thermosetting resin, an inorganic filler,
The inorganic filler having an average particle diameter of 0.4μm or more, a maximum particle size of 5μm or less, the inorganic filler filling amount 60 wt% or more, Ri average linear thermal expansion coefficient of Der below 25ppm to below the glass transition temperature from 25 ° C.,
A via hole and a metal circuit are formed on the first insulating resin,
One or more layers of the second insulating resin are laminated on the first insulating resin, and a via hole and a metal circuit are formed on each layer of the second insulating resin,
Said second insulating resin, a thermosetting resin, comprising an inorganic filler, the following average filler size 0.2μm of the inorganic filler, the maximum filler size of 2μm or less, the inorganic filler loading is less der Rukoto 65 wt% wherein, the glass circuit board. And the metal layer, the glass substrate duplex, the first insulating resin, and, said metal circuit formed on each layer of the second insulating resin, that contains at least copper, nickel, titanium, or chromium The glass circuit board according to claim 1, which is characterized.

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