JP6840935B2 - Wiring circuit board manufacturing method - Google Patents
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- JP6840935B2 JP6840935B2 JP2016094542A JP2016094542A JP6840935B2 JP 6840935 B2 JP6840935 B2 JP 6840935B2 JP 2016094542 A JP2016094542 A JP 2016094542A JP 2016094542 A JP2016094542 A JP 2016094542A JP 6840935 B2 JP6840935 B2 JP 6840935B2
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- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
本発明は、インターポーザとして使用可能な貫通電極付き配線回路基板及びその製造方法に関する。 The present invention relates to a wiring circuit board with a through electrode that can be used as an interposer and a method for manufacturing the same.
ウェハプロセスで製造される各種のメモリー、ＣＭＯＳ（相補型金属酸化膜半導体）、ＣＰＵ（中央演算処理装置）等の半導体素子は、電気的接続用の端子を有する。その接続用端子のピッチと、半導体素子と電気的な接続がなされるべきプリント基板側の接続部のピッチとは、通常、そのスケールが数倍から数十倍程度異なる。そのため、半導体素子とプリント基板を電気的に接続する場合、インターポーザと称されるピッチ変換のための仲介用基板（半導体素子実装用基板）が使用される。このインターポーザの一方の面に、半導体素子を実装し、他方の面もしくは基板の周辺でプリント基板との接続が行われる。 Semiconductor elements such as various memories manufactured by the wafer process, CMOS (complementary metal oxide semiconductor), and CPU (central processing unit) have terminals for electrical connection. The pitch of the connection terminal and the pitch of the connection portion on the printed circuit board side where the semiconductor element should be electrically connected are usually different in scale from several times to several tens of times. Therefore, when the semiconductor element and the printed circuit board are electrically connected, an interposer, which is called an interposer, is used as an intermediary board (semiconductor element mounting board) for pitch conversion. A semiconductor element is mounted on one surface of the interposer, and the other surface or the periphery of the substrate is connected to the printed circuit board.
半導体素子をプリント板に実装するためのインターポーザとしては、これまで有機基板や有機ビルドアップ基板が用いられてきた。ところが、昨今のスマートフォンに代表されるような急速な電子機器の高性能化により、半導体素子を縦に積層したり、メモリーやロジックといった異なる半導体素子を同一基板上に並べて実装したりする３次元実装技術や２．５次元実装技術の開発が必要不可欠となりつつある。これらの開発により、電子機器類のさらなる高速化・大容量化・低消費電力化などの実現が可能と考えられているが、半導体素子の高密度化に伴いインターポーザにもより微細な配線を作りこむことが求められている。 Organic substrates and organic build-up substrates have been used as interposers for mounting semiconductor elements on printed circuit boards. However, due to the rapid improvement in the performance of electronic devices such as smartphones these days, three-dimensional mounting is such that semiconductor elements are vertically stacked or different semiconductor elements such as memory and logic are mounted side by side on the same substrate. Development of technology and 2.5D mounting technology is becoming indispensable. It is thought that these developments will make it possible to further increase the speed, capacity, and power consumption of electronic devices, but as the density of semiconductor elements increases, finer wiring will be created for the interposer. It is required to squeeze.
ところが、従来の有機材料を用いた基板では、樹脂の吸湿や温度による伸縮が大きくスケールを合わせた微細配線の形成が難しいという問題を有していた。 However, the conventional substrate using an organic material has a problem that it is difficult to form fine wiring in which the scale is matched due to the large expansion and contraction of the resin due to moisture absorption and temperature.
そこで、近年基材にシリコンやガラスを用いるインターポーザの開発に大きな注目が集まっている。これらの材料からなる基板は、有機基板を用いた際に問題となっていた吸湿や伸縮の影響をほとんど受けないため、微細配線の形成に有利である。また、高い加工性を有するため、内部に微細な貫通孔をあけてその孔を導電性物質で充填して作るＴＳＶ（Ｔｈｒｏｕｇｈ−Ｓｉｌｉｃｏｎ Ｖｉａ）やＴＧＶ（Ｔｈｒｏｕｇｈ−Ｇｌａｓｓ Ｖｉａ）と呼ばれる貫通電極が形成できる。この貫通電極は、配線長を短縮し基板の表裏面の配線同士を最短距離で接続可能とするため、信号伝送速度の高速化など優れた電気特性を実現させる。さらには、内部に配線を形成する構造のため電子デバイスの小型化や高密度化にも有効な実装方法であることや、貫通電極の採用により多ピン並列接続が可能となり、ＬＳＩ自体を高速化させる必要がなくなるため低消費電力化が実現できるなど、多数の利点を有する。 Therefore, in recent years, great attention has been paid to the development of interposers that use silicon or glass as the base material. Substrates made of these materials are hardly affected by moisture absorption and expansion and contraction, which have been problems when using organic substrates, and are therefore advantageous for forming fine wiring. In addition, since it has high workability, through electrodes called TSV (Through-Silicon Via) and TGV (Through-Glass Via) are formed by making fine through holes inside and filling the holes with a conductive substance. it can. Since this through electrode shortens the wiring length and enables the wiring on the front and back surfaces of the substrate to be connected to each other in the shortest distance, excellent electrical characteristics such as high signal transmission speed are realized. Furthermore, since the structure forms wiring inside, it is an effective mounting method for miniaturization and high density of electronic devices, and the adoption of through electrodes enables multi-pin parallel connection, which speeds up the LSI itself. It has many advantages such as low power consumption because it is not necessary to make it.
シリコンインターポーザとガラスインターポーザとを比較すると、シリコンインターポーザは、ガラスインターポーザよりも微細化が可能であり、また配線やＴＳＶ形成プロセスが確立されている一方で、丸いシリコンウエハでしか扱えないためウエハ周辺部が使用できないことや大型サイズで一括して生産できないためコストが高くなるという大きな欠点を有する。その点、ガラスインターポーザでは、大型パネルでの大量処理が可能であり、またロール・ツー・ロール方式での生産方法も考えられるため大幅なコストダウンが可能となる。また、放電やレーザなどで貫通孔を形成するＴＧＶとは異なり、ＴＳＶはガスエッチングにより孔を掘っていくため、加工時間が長くなることやウエハを薄く削る工程を含むことなどもコストを上げる要因となっている。 Comparing the silicon interposer and the glass interposer, the silicon interposer can be made finer than the glass interposer, and while the wiring and TSV formation process are established, it can be handled only with a round silicon wafer, so the peripheral part of the wafer. However, it has a big drawback that the cost is high because it cannot be used and it cannot be collectively produced in a large size. In that respect, the glass interposer can process a large amount of large panels, and a roll-to-roll method can be considered, which enables a significant cost reduction. Also, unlike the TGV, which forms through holes by electric discharge or laser, the TSV digs holes by gas etching, which increases the cost due to the long processing time and the inclusion of a process of thinly cutting the wafer. It has become.
さらに、電気特性の面ではガラスインターポーザは基板自体がシリコンインターポーザと違って絶縁体のため、高速回路においても寄生素子発生の懸念がなく、より電気特性に優れる。そもそも基板にガラスを用いると絶縁膜を形成させる工程自体が必要ないため、絶縁信頼が高く工程の短縮も可能となる。 Further, in terms of electrical characteristics, since the substrate itself of the glass interposer is an insulator unlike the silicon interposer, there is no concern about the generation of parasitic elements even in a high-speed circuit, and the glass interposer is more excellent in electrical characteristics. In the first place, if glass is used for the substrate, the step itself of forming the insulating film is not required, so that the insulation reliability is high and the step can be shortened.
以上のように、低コストにインターポーザを作ることができるガラスであるが、大きな欠点は、微細な配線を形成させるプロセスが確立していないこと、またガラスに対して配線材料の主流となりつつある銅が密着しないため、基板上に配線を形成させるには表面への特殊な処理を必要とすることにある。さらに、ＴＧＶの形成は、スルーホールフィリングやビアフィリングの工程を必要とするため、ボイドが発生し信頼性に大きな問題を抱えている。 As described above, glass can be used to make interposers at low cost, but the major drawbacks are that the process for forming fine wiring has not been established, and copper is becoming the mainstream wiring material for glass. Because the wires do not adhere to each other, a special treatment on the surface is required to form the wiring on the substrate. Further, since the formation of the TGV requires the steps of through-hole filling and via filling, voids are generated and there is a big problem in reliability.
例えばガラスインターポーザを用いて高密度実装を可能にする方法は、特許文献１等において提案されている。しかしながら、特許文献１の技術にあっては、従来の有機樹脂と比べて微細な銅配線を形成したガラスインターポーザを使用しているものの、配線の形成方法に関する詳細な記述が無いために、信頼性に欠ける。 For example, a method for enabling high-density mounting using a glass interposer has been proposed in Patent Document 1 and the like. However, in the technique of Patent Document 1, although a glass interposer in which fine copper wiring is formed as compared with the conventional organic resin is used, there is no detailed description about the wiring forming method, so that the reliability is high. Lacking.
また、無電解めっきを用いて無粗化でガラス上に金属膜を形成させる方法は、特許文献２等に提案されているが、配線に使用できるようめっき膜を厚くしていくと密着力が十分でないため簡単に剥離するおそれを有する。 Further, a method of forming a metal film on glass without roughening by using electroless plating has been proposed in Patent Document 2 and the like, but if the plating film is thickened so that it can be used for wiring, the adhesion becomes stronger. Since it is not sufficient, it may be easily peeled off.
図２２は、従来の配線回路基板２００の一例の断面図である。図２２に示すように、ガラス基材２０１に数ミクロン厚の配線を形成する際、電解めっき等で導電性の金属材料を厚付けするが、ガラス基材２０１と導電性の金属材料２０３との界面に密着性を有する無機密着層２０４を形成する必要がある。しかし、依然としてガラス基材２０１と導電性の金属材料２０３との密着性が不十分であることや、配線形成後に不要な部分の無機密着層を剥離することが難しいなどの課題がある。また、貫通孔２１３の開口部のエッジ形状が鋭角に仕上がるため、貫通電極２１４と配線層２０５を形成した際、貫通孔２１３の開口部のエッジに応力が集中し信頼性が低下するなどの課題がある。 FIG. 22 is a cross-sectional view of an example of the conventional wiring circuit board 200. As shown in FIG. 22, when forming a wiring having a thickness of several microns on the glass base material 201, the conductive metal material is thickened by electroplating or the like, but the glass base material 201 and the conductive metal material 203 are combined. It is necessary to form the inorganic adhesive layer 204 having adhesiveness at the interface. However, there are still problems such as insufficient adhesion between the glass base material 201 and the conductive metal material 203, and difficulty in peeling off the inorganic adhesive layer in an unnecessary portion after forming the wiring. Further, since the edge shape of the opening of the through hole 213 is finished at an acute angle, when the through electrode 214 and the wiring layer 205 are formed, stress is concentrated on the edge of the opening of the through hole 213 and the reliability is lowered. There is.
本発明は、上記課題を解決するためになされたものであり、ガラス基材の両面の凹部と第一層目の配線層との密着力を大幅に向上させ、貫通電極の応力集中を緩和でき、接続信頼性を向上させことができる、信頼性の高いガラスインターポーザとして使用可能な配線回路基板及びその製造方法を提供することにある。 The present invention has been made to solve the above problems, and can significantly improve the adhesion between the recesses on both sides of the glass substrate and the wiring layer of the first layer, and can alleviate the stress concentration of the through electrode. An object of the present invention is to provide a wiring circuit board that can be used as a highly reliable glass interposer and a method for manufacturing the same, which can improve the connection reliability.
また、本発明の別の態様は、ガラス基材の内部に貫通電極を有する多層構造の貫通電極付き配線回路基板の製造方法であって、ガラス基材にレーザ加工により貫通孔を形成する貫通孔形成工程と、ガラス基材の両面の貫通孔の開口部を含む領域に凹部をエッチングにより形成するエッチング工程と、ガラス基材の両面と貫通孔の内壁とを導電性の金属材料で被覆する被覆工程と、導電性の金属材料をガラス基材の最表面を終点として研磨除去する研磨工程とを有し、貫通孔の開口部の周縁部が曲面形状であって、かつ、周縁部の内径が貫通孔の外方に向かって徐々に広がっていることを特徴とする配線回路基板の製造方法である。 Another aspect of the present invention is a method for manufacturing a wiring circuit substrate with a through electrode having a multi-layer structure having a through electrode inside a glass base material, in which a through hole is formed in the glass base material by laser processing. The forming step, the etching step of forming a recess by etching in the region including the openings of the through holes on both sides of the glass base material, and the coating of both sides of the glass base material and the inner wall of the through holes with a conductive metal material. It has a step and a polishing step of polishing and removing a conductive metal material from the outermost surface of a glass base material as an end point, and the peripheral edge of the opening of the through hole has a curved shape and the inner diameter of the peripheral edge is large. This is a method for manufacturing a wiring circuit board, which is characterized in that it gradually expands toward the outside of the through hole.
また、エッチング工程は、所定濃度のフッ酸溶液を用いたウェットエッチングにより行われ、貫通孔の開口部の周縁部のガラスを除去して周縁部を曲面形状に形成してもよい。 Further, the etching step may be performed by wet etching using a hydrofluoric acid solution having a predetermined concentration, and the glass at the peripheral edge of the opening of the through hole may be removed to form the peripheral edge into a curved surface shape.
また、エッチング工程は、反応性ガスを用いたドライエッチングにより行われ、凹部のエッチング深さに対し、貫通孔の中央部よりも貫通孔の上端及び下端の開口部のエッチングが進行し貫通孔の中心軸を含む断面がＸ形状となり、貫通孔の開口部の周縁部の溶融ガラスを除去して周縁部を曲面形状に形成してもよい。 Further, the etching step is performed by dry etching using a reactive gas, and the etching of the upper end and lower end openings of the through hole proceeds more than the central portion of the through hole with respect to the etching depth of the recess, and the through hole The cross section including the central axis may be X-shaped, and the molten glass at the peripheral edge of the opening of the through hole may be removed to form the peripheral edge in a curved shape.
また、エッチング工程において、凹部の表面粗さＲａを１００ｎｍ以下にしてもよい。 Further, in the etching step, the surface roughness Ra of the recess may be set to 100 nm or less.
また、被覆工程において、ガラス基材両面及び貫通孔の内壁に無機密着層を形成した後に、ガラス基材の両面及び貫通孔の内壁を導電性の金属材料で被覆してもよい。 Further, in the coating step, after forming an inorganic adhesive layer on both sides of the glass base material and the inner wall of the through hole, both sides of the glass base material and the inner wall of the through hole may be coated with a conductive metal material.
また、無機密着層は、酸化錫、酸化インジウム、酸化亜鉛、ニッケル、ニッケルリン、クロム、酸化クロム、チッ化アルミ、チッ化銅、酸化アルミ、タンタル、チタン、銅のうち、単体の材料の単層の膜、または、これらのうちの２種類以上の材料を複合させた２層以上の積層の膜であってもよい。 The inorganic adhesion layer is a simple substance of tin oxide, indium oxide, zinc oxide, nickel, nickel phosphorus, chromium, chromium oxide, aluminum titrated, copper titrated, aluminum oxide, tantalum, titanium, and copper. It may be a film of layers, or a laminated film of two or more layers in which two or more kinds of materials thereof are composited.
また、導電性の金属材料が、銅、銀、金、ニッケル、白金、パラジウム、ルテニウム、錫、錫銀、錫銀銅、錫銅、錫ビスマス、錫鉛のうちいずれかの単体金属、または、これらのうちの二つ以上の化合物、のいずれかであってもよい。 Further, the conductive metal material is any single metal of copper, silver, gold, nickel, platinum, palladium, ruthenium, tin, tin silver, tin silver copper, tin copper, tin bismuth, tin lead, or It may be any one of two or more of these compounds.
また、研磨工程において、ガラス基材の最表面を終点として化学機械研磨によりガラス基材の最表面上の無機密着層及び導電性の金属材料を除去し、凹部に導電性の金属材料からなる第一層目の配線層と、貫通孔に第一層目の配線層に接続される貫通電極とを有するコア基材を形成してもよい。 Further, in the polishing step, the inorganic adhesive layer and the conductive metal material on the outermost surface of the glass base material are removed by chemical mechanical polishing starting from the outermost surface of the glass base material, and the concave portion is made of the conductive metal material. A core base material having a first layer wiring layer and a through electrode connected to the first layer wiring layer in the through hole may be formed.
また、ガラス基材の少なくとも一方の面に絶縁性樹脂層を積層し、第一層目の配線層と導通をとるための導通ビアを形成し、絶縁性樹脂層の上に第二層目の配線層とを形成する工程を更に有してもよい。 Further, an insulating resin layer is laminated on at least one surface of the glass base material to form a conductive via for conducting conduction with the wiring layer of the first layer, and a second layer is formed on the insulating resin layer. It may further have a step of forming a wiring layer.
また、絶縁性樹脂層が、エポキシ／フェノール系樹脂、アクリル系樹脂、ポリイミド樹脂、シクロオレフィン、ポリベンゾオキサゾール樹脂、液晶ポリマー樹脂のうちいずれか一つの材料、または、これらの材料のうちの少なくとも一つと酸化ケイ素とを組み合わせた複合材料を用いてもよい。 Further, the insulating resin layer is a material of any one of epoxy / phenol-based resin, acrylic-based resin, polyimide resin, cycloolefin, polybenzoxazole resin, and liquid crystal polymer resin, or at least one of these materials. A composite material in which a mixture of polyimide and silicon oxide may be used may be used.
本発明の貫通電極付き配線回路基板及びその製造方法によれば、ガラス基材の両面の凹部と第一層目の配線層との密着力を大幅に向上させ、貫通電極の応力集中を緩和でき、接続信頼性を向上させることができる、信頼性の高いガラスインターポーザとして使用可能な配線回路基板を簡便に作製することができる。 According to the wiring circuit board with a through electrode and the manufacturing method thereof of the present invention, the adhesion between the recesses on both sides of the glass substrate and the wiring layer of the first layer can be significantly improved, and the stress concentration of the through electrode can be relaxed. , A wiring circuit board that can be used as a highly reliable glass interposer that can improve connection reliability can be easily manufactured.
以下、本発明の実施形態について、図面を参照しつつ説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
［コア基板１０の構成］
図１は、本実施形態に係る配線回路基板を構成するコア基板の断面図である。図１に示すように、本実施形態に係る配線回路基板を構成するコア基板１０は、ガラス基材１と、貫通電極１４と、貫通電極１４に接続される第一層目の配線層５とを有する。貫通電極１４は、貫通孔１３に埋め込まれた導電性の金属材料３よりなる。第一層目の配線層５は、ガラス基材１の表面に形成された凹部６に埋め込まれた導電性の金属材料３よりなる。貫通電極１４と、第一層目の配線層５には、無機密着層４が設けられている。貫通電極１４の隙間には、穴埋め樹脂１２が充填されている。
[Structure of core substrate 10]
FIG. 1 is a cross-sectional view of a core substrate constituting the wiring circuit board according to the present embodiment. As shown in FIG. 1, the core substrate 10 constituting the wiring circuit board according to the present embodiment includes a glass base material 1, a through electrode 14, and a first layer wiring layer 5 connected to the through electrode 14. Has. The through electrode 14 is made of a conductive metal material 3 embedded in the through hole 13. The wiring layer 5 of the first layer is made of a conductive metal material 3 embedded in a recess 6 formed on the surface of the glass base material 1. An inorganic adhesion layer 4 is provided on the through electrode 14 and the wiring layer 5 of the first layer. The gaps between the through electrodes 14 are filled with the fill-in-the-blank resin 12.
図２〜図６は、本実施形態に係る配線回路基板を構成するコア基板の製造工程を示す図である。以下、図１を用いて、図２〜図６を併せて参照しながらコア基板の製造工程を説明する。 2 to 6 are diagrams showing a manufacturing process of a core substrate constituting the wiring circuit board according to the present embodiment. Hereinafter, the manufacturing process of the core substrate will be described with reference to FIGS. 2 to 6 with reference to FIG.
まず、図２に示すように、ガラス基材１に貫通孔１３を形成する。ガラス基材１は、低膨張ガラス（熱膨張率：３〜４ｐｐｍ／℃）、ソーダガラス（熱膨張率：８〜９ｐｐｍ／℃）などが使用可能であり、製造方法や、Ｎａ等の金属成分の添加により、熱膨張率を３〜９ｐｐｍ／℃の範囲に制御が可能である。貫通孔１３形成前のガラス基材１のＲａ（算術平均粗さ）は１０ｎｍ以下である。 First, as shown in FIG. 2, a through hole 13 is formed in the glass base material 1. As the glass base material 1, low expansion glass (coefficient of thermal expansion: 3 to 4 ppm / ° C.), soda glass (coefficient of thermal expansion: 8 to 9 ppm / ° C.) and the like can be used, and the production method and metal components such as Na can be used. The coefficient of thermal expansion can be controlled in the range of 3 to 9 ppm / ° C. by the addition of. Ra (arithmetic mean roughness) of the glass base material 1 before forming the through hole 13 is 10 nm or less.
なお、ガラス基材１の熱膨張率は、ＪＩＳ：Ｒ３１０２やＪＩＳ：Ｋ７１９７に従い、ＴＭＡ（熱機械分析）にて測定した値である。また、ガラス基材のＲａ（算術平均粗さ）は触針式の膜厚計にて測定した値である。 The coefficient of thermal expansion of the glass substrate 1 is a value measured by TMA (thermomechanical analysis) according to JIS: R3102 and JIS: K7197. The Ra (arithmetic mean roughness) of the glass substrate is a value measured by a stylus type film thickness meter.
ガラス基材１に貫通孔１３を形成する方法としては、ＣＯ２レーザやＵＶレーザの他に、ピコ秒レーザやフェムト秒レーザ、エキシマレーザや放電加工、感光性ガラスやブラスト加工等を使用可能であるが、加工速度や加工穴の形状が良好なＣＯ２レーザが最も望ましい。 As a method for forming the through hole 13 in the glass base material 1, in addition to the CO 2 laser and the UV laser, a picosecond laser, a femtosecond laser, an excimer laser, a discharge process, a photosensitive glass, a blast process, and the like can be used. However, a CO 2 laser with good machining speed and hole shape is most desirable.
次に、図３に示すように、ガラス基材１の両面にマスキング材を用いて成膜し、凹部６に相当する領域に開口が設けられたレジストパタンを形成する。マスキング材としては、例えば、感光性のレジスト２や、Ｃｒスパッタ膜１１のような耐腐食性を有する金属箔膜が使用可能である。レジストパタンの形成方法の一例として、ガラス基材１の両面に、スパッタリング法によりＣｒスパッタ膜１１を成膜し、このＣｒスパッタ膜１１上に感光性レジスト層２を積層した後に、フォトマスクを用いた露光処理、現像処理及び洗浄を行うことで、凹部６に相当する領域に開口が設けられたレジストパタンを形成することが挙げられる。尚、開口が設けられたレジストパタンの形成方法はこれに限定されない。 Next, as shown in FIG. 3, a film is formed on both surfaces of the glass base material 1 using a masking material to form a resist pattern having an opening in a region corresponding to the recess 6. As the masking material, for example, a photosensitive resist 2 or a metal foil film having corrosion resistance such as a Cr sputtered film 11 can be used. As an example of a method for forming a resist pattern, a Cr sputtered film 11 is formed on both surfaces of a glass substrate 1 by a sputtering method, a photosensitive resist layer 2 is laminated on the Cr sputtered film 11, and then a photomask is used. It is possible to form a resist pattern in which an opening is provided in a region corresponding to the recess 6 by performing the exposure treatment, the development treatment, and the cleaning. The method of forming the resist pattern provided with the opening is not limited to this.
次に、図４に示すように、第一層目の配線層５に相当する凹部６を形成する。凹部６は、レジストパタンに設けられた開口から露出したガラス基材１をエッチングすることで形成することができる。凹部６は、ガラス基材１の両面の貫通孔１３の開口部を含む領域にそれぞれ形成される。ガラスエッチングは、所定濃度のフッ酸水溶液によるＷｅｔエッチングや、フッ素系のガスを使用したＤｒｙエッチングが使用可能である。フッ酸水溶液は、フッ化水素を主成分とし、硝酸や、エッチング速度や液安定性を制御する添加剤を添加した混合溶液を使用すればよく、その比率や温度はエッチング量やエッチング時間により規定すればよい。凹部６の形成後、マスキング材を剥離液にて剥離除去することで、凹部６と貫通孔１３とを有するガラス基材１が得られる。 Next, as shown in FIG. 4, a recess 6 corresponding to the wiring layer 5 of the first layer is formed. The recess 6 can be formed by etching the glass base material 1 exposed from the opening provided in the resist pattern. The recesses 6 are formed in the regions including the openings of the through holes 13 on both sides of the glass base material 1, respectively. As the glass etching, Wet etching with a hydrofluoric acid aqueous solution having a predetermined concentration and Dry etching using a fluorine-based gas can be used. As the hydrofluoric acid aqueous solution, a mixed solution containing hydrogen fluoride as a main component and nitric acid and additives for controlling the etching rate and liquid stability may be used, and the ratio and temperature are specified by the etching amount and etching time. do it. After the recess 6 is formed, the masking material is peeled off and removed with a stripping solution to obtain a glass base material 1 having the recess 6 and the through hole 13.
ガラス基材１のエッチングにより、貫通孔１３の内壁と開口部周縁とがエッチングされる。貫通孔１３の開口部は熱歪が残ったり、部分融解したりして変質しエッチングが入り易い状態になっており、エッチングの進行が速い事により貫通孔１３の開口部の周縁部を曲面形状に加工することが可能である。つまり、図４に示すように、貫通孔の開口部の周縁部を、曲面形状であって、かつ、周縁部の内径が貫通孔の外方に向かって徐々に広がっている形状となるように加工することが可能である。 By etching the glass base material 1, the inner wall of the through hole 13 and the peripheral edge of the opening are etched. The opening of the through hole 13 is in a state where thermal strain remains or is partially melted and deteriorated so that etching can easily enter. Due to the rapid progress of etching, the peripheral edge of the opening of the through hole 13 has a curved surface shape. It can be processed into. That is, as shown in FIG. 4, the peripheral edge of the opening of the through hole has a curved surface shape, and the inner diameter of the peripheral edge gradually expands toward the outside of the through hole. It can be processed.
Ｗｅｔエッチングは等方的にエッチングが進む為、貫通孔１３の内壁を均等にエッチングすることができ、貫通孔１３内の熱歪領域を溶解除去することができる。一方、Ｄｒｙエッチングは貫通孔１３の開口部が中央部より反応性が速い為、貫通孔１３の中心軸を含む断面がＸ形状のエッチング形状となり、導電性の金属材料３の充填が容易になるなどのメリットがある。 Since Wet etching proceeds isotropically, the inner wall of the through hole 13 can be uniformly etched, and the heat strain region in the through hole 13 can be dissolved and removed. On the other hand, in Dry etching, since the opening of the through hole 13 is faster than the central portion, the cross section including the central axis of the through hole 13 has an X-shaped etching shape, which facilitates filling of the conductive metal material 3. There are merits such as.
ガラス基材１のエッチング面は、ＷｅｔエッチングやＤｒｙエッチングにより荒さを調整することが可能である。ガラス基材１のエッチング面を荒らす事で、無機密着層４や導電性の金属材料３の密着性を向上することが可能である。ガラス基材１の凹部６のＲａ（算術表面粗さ）は、第一層目の配線層５に電流を通す際の高周波域にて電流の表皮効果により抵抗値上昇に繋がる。凹部６のＲａが１００ｎｍを超えるとガラス基材１と配線層５との密着性は向上するが配線設計や使用条件により抵抗値の上昇が許容できなくなる為、凹部６のＲａは１００ｎｍ以下が望ましい。 The roughness of the etched surface of the glass substrate 1 can be adjusted by Wet etching or Dry etching. By roughening the etching surface of the glass base material 1, it is possible to improve the adhesion of the inorganic adhesion layer 4 and the conductive metal material 3. Ra (arithmetic surface roughness) of the recess 6 of the glass base material 1 leads to an increase in resistance value due to the skin effect of the current in the high frequency region when the current is passed through the wiring layer 5 of the first layer. If the Ra of the recess 6 exceeds 100 nm, the adhesion between the glass base material 1 and the wiring layer 5 is improved, but the increase in resistance value cannot be tolerated depending on the wiring design and usage conditions. Therefore, the Ra of the recess 6 is preferably 100 nm or less. ..
次に、図５に示すように、凹部６を形成したガラス基材１の両面及び貫通孔１３の内壁に導電性の金属材料３を被覆し、貫通孔１３内に残った空隙に穴埋め樹脂１２を充填する。導電性の金属材料３の被覆は、ガラス基材１の両面及び貫通孔１３の内壁に、ガラス基材１との密着性を確保する為の無機密着層４を形成した後、導電性の金属材料３で凹部６を含むガラス基材１の両面及び貫通孔１３の内壁を被覆する。このとき、凹部６における無機密着層４と導電性の金属材料３とを併せた膜厚は凹部６の深さより厚い膜厚で形成する。また、導電性の金属材料３は、無機密着層４が形成された貫通孔１３の内部を完全に充填できる膜厚で形成しても良い。 Next, as shown in FIG. 5, the conductive metal material 3 is coated on both sides of the glass base material 1 on which the recess 6 is formed and the inner wall of the through hole 13, and the voids remaining in the through hole 13 are filled with the filling resin 12. To fill. The conductive metal material 3 is coated with the conductive metal after forming the inorganic adhesive layer 4 for ensuring the adhesion with the glass substrate 1 on both sides of the glass substrate 1 and the inner wall of the through hole 13. The material 3 covers both sides of the glass base material 1 including the recess 6 and the inner wall of the through hole 13. At this time, the film thickness of the inorganic adhesive layer 4 and the conductive metal material 3 in the recess 6 is formed to be thicker than the depth of the recess 6. Further, the conductive metal material 3 may be formed with a film thickness that can completely fill the inside of the through hole 13 in which the inorganic adhesion layer 4 is formed.
無機密着層４は、酸化錫、酸化インジウム、酸化亜鉛、ニッケル、ニッケルリン、クロム、酸化クロム、チッ化アルミ、チッ化銅、酸化アルミ、タンタル、チタン、銅のうち、単体の材料の単層の膜、または、クロム／銅、チタン／銅のように２種類以上の材料を複合させた２層以上の積層の膜が使用可能である。スパッタ成膜や無電解めっきや水溶液への浸漬形成や導電性ペーストの印刷などの方法で形成すれば良い。 The inorganic adhesive layer 4 is a single layer of a single material among tin oxide, indium oxide, zinc oxide, nickel, nickel phosphorus, chromium, chromium oxide, aluminum titrated, copper titrated, aluminum oxide, tantalum, titanium, and copper. Or a laminated film having two or more layers in which two or more kinds of materials are composited, such as chromium / copper and titanium / copper, can be used. It may be formed by a method such as sputter film formation, electroless plating, immersion formation in an aqueous solution, or printing of a conductive paste.
導電性の金属材料３は、銅、銀、金、ニッケル、白金、パラジウム、ルテニウム、錫、錫銀、錫銀銅、錫銅、錫ビスマス、錫鉛のうちいずれかの単体金属、または、これらのうちの二つ以上の化合物が使用可能である。電解めっきや導電性ペーストの印刷などの方法で形成すれば良い。 The conductive metal material 3 is any single metal of copper, silver, gold, nickel, platinum, palladium, ruthenium, tin, tin silver, tin silver copper, tin copper, tin bismuth, tin lead, or these. Two or more of these compounds can be used. It may be formed by a method such as electrolytic plating or printing of a conductive paste.
電解めっきにて形成する場合、貫通孔１３の内部はコンフォーマルめっきやフィルドめっきにより形成することが可能である。コンフォーマルめっき後に貫通孔１３内に残った空隙は、シリカと有機樹脂とからなる穴埋め樹脂１２や導電性金属材料とプライマーとからなる導電性ペーストにて充填すれば良い。なお、穴埋め樹脂や導電性ペーストを充填する方法として、スクリーン印刷法やディペンサーなどが可能である。 When formed by electrolytic plating, the inside of the through hole 13 can be formed by conformal plating or filled plating. The voids remaining in the through holes 13 after the conformal plating may be filled with the fill-in-the-blank resin 12 made of silica and an organic resin or the conductive paste made of a conductive metal material and a primer. As a method of filling the fill-in-the-blank resin or the conductive paste, a screen printing method, a depenser, or the like is possible.
次に、図６に示すように、化学機械研磨（ＣＭＰ）にて、ガラス基材１の最表面１５が露出するまで研磨処理することで、第一層目の配線層５を得ることができる。ＣＭＰのスラリーは無機密着層４と導電性の金属材料３とを研磨除去できるものを選べば良い。金属材料３が電解Ｃｕめっきの場合、過酸化水素、酸化セリウム、酸化ケイ素からなるスラリーを使用することで、ガラス基材１の最表面１５より高い無機密着層４及び導電性の金属材料３を除去することができる。 Next, as shown in FIG. 6, the first layer wiring layer 5 can be obtained by polishing until the outermost surface 15 of the glass substrate 1 is exposed by chemical mechanical polishing (CMP). .. The CMP slurry may be selected so that the inorganic adhesive layer 4 and the conductive metal material 3 can be polished and removed. When the metal material 3 is electrolytic Cu plating, by using a slurry composed of hydrogen peroxide, cerium oxide, and silicon oxide, the inorganic adhesion layer 4 higher than the outermost surface 15 of the glass substrate 1 and the conductive metal material 3 can be obtained. Can be removed.
ガラス基材１の最表面１５の上に残った無機密着層４や金属材料３はＣＭＰで完全に除去するのが望ましいが、残渣として無機密着層４や金属材料３が残った場合はＷｅｔエッチングにて溶解除去することも可能である。 It is desirable to completely remove the inorganic adhesive layer 4 and the metal material 3 remaining on the outermost surface 15 of the glass substrate 1 by CMP, but if the inorganic adhesive layer 4 and the metal material 3 remain as a residue, wet etching is performed. It is also possible to dissolve and remove with.
以上により、貫通孔１３の内壁に導電性の金属材料３が形成された貫通電極１４と、凹部６を導電性の金属材料３で充填した第一層目の配線層５とを形成することで、コア基板１０を得ることができる。 As described above, the through electrode 14 in which the conductive metal material 3 is formed on the inner wall of the through hole 13 and the first layer wiring layer 5 in which the recess 6 is filled with the conductive metal material 3 are formed. , The core substrate 10 can be obtained.
本実施形態に係るコア基板１０によれば、第一層目の配線層５をガラス基板１の凹部６に形成し、ガラス基板１の凹部６の内壁を微細に荒らして凹凸を形成することで、ガラス基板１と第一層目の配線層５との密着力を大幅に向上させることができ、且つ、配線層５の表面以外の全ての面がガラス基材１と密着していることで、前処理無しでも高い密着性を有し、ハンドリング時の信頼性が向上される。また、貫通孔１３の開口部の周縁部が曲面形状になり応力集中を緩和することができるため、高い接続信頼性と優れた電気特性を実現することができる。 According to the core substrate 10 according to the present embodiment, the wiring layer 5 of the first layer is formed in the recess 6 of the glass substrate 1, and the inner wall of the recess 6 of the glass substrate 1 is finely roughened to form irregularities. The adhesion between the glass substrate 1 and the first layer wiring layer 5 can be significantly improved, and all surfaces other than the surface of the wiring layer 5 are in close contact with the glass substrate 1. It has high adhesion even without pretreatment, and reliability during handling is improved. Further, since the peripheral edge of the opening of the through hole 13 has a curved surface shape and stress concentration can be relaxed, high connection reliability and excellent electrical characteristics can be realized.
［配線回路基板１００の構成］
図７は、本実施形体の配線回路基板の断面図である。図７に示すように、本実施形態に係る配線回路基板（ガラスインターポーザ）１００は、上述したコア基板１０と、絶縁性樹脂層７と、第二層目の配線層８と、導通ビア９と、絶縁性樹脂層１６と、導通パッド１８を備えている。第二層目以降の配線層及び絶縁性樹脂層は必要により設定すればよく、特に規定するものではない。
[Structure of Wiring Circuit Board 100]
FIG. 7 is a cross-sectional view of the wiring circuit board of the present embodiment. As shown in FIG. 7, the wiring circuit board (glass interposer) 100 according to the present embodiment includes the above-mentioned core substrate 10, the insulating resin layer 7, the second wiring layer 8, and the conductive via 9. The insulating resin layer 16 and the conduction pad 18 are provided. The wiring layer and the insulating resin layer after the second layer may be set as necessary, and are not particularly specified.
図８は、本実施形態に係る配線回路基板の製造工程を示す図である。以下、図７及び図８を併せて参照しながら説明する。 FIG. 8 is a diagram showing a manufacturing process of the wiring circuit board according to the present embodiment. Hereinafter, description will be made with reference to FIGS. 7 and 8.
まず、図８に示すように、絶縁性樹脂層７をコア基板１０の両面に形成する。絶縁性樹脂層７の材料としては、エポキシ／フェノール系樹脂、ポリイミド樹脂、シクロオレフィン、ポリベンゾオキサゾール（ＰＢＯ）樹脂、液晶ポリマー樹脂のうちいずれか一つの材料、またはこれらの材料のうちの少なくとも一つと酸化ケイ素などの無機フィラーなどとを組み合わせた複合材料を用いることが可能である。また、絶縁性樹脂層７の材料としては、例えば、ドライフィルムや液状レジストが使用可能である。 First, as shown in FIG. 8, the insulating resin layer 7 is formed on both sides of the core substrate 10. The material of the insulating resin layer 7 is any one of epoxy / phenol-based resin, polyimide resin, cycloolefin, polybenzoxazole (PBO) resin, liquid crystal polymer resin, or at least one of these materials. It is possible to use a composite material in which a resin is combined with an inorganic filler such as silicon oxide. Further, as the material of the insulating resin layer 7, for example, a dry film or a liquid resist can be used.
次に、絶縁性樹脂７に導通ビア孔を形成した後に、この導通ビア孔に導通ビア９を形成する。導通ビア９は、第一層目の配線層５と第二層目の配線層８とを、電気的に接続させている。 Next, after forming a conductive via hole in the insulating resin 7, a conductive via 9 is formed in the conductive via hole. The conductive via 9 electrically connects the wiring layer 5 of the first layer and the wiring layer 8 of the second layer.
導通ビア９は、絶縁性樹脂層７に形成した導通ビア孔の内部に、コンフォーマルめっきやフィルドめっき、導電性ペーストの充填等、導電性物質を充填する加工を行って形成する。絶縁性樹脂層７に導通ビア孔を形成する方法は、例えば、絶縁性樹脂層７の材料により選択すれば良く、絶縁性樹脂層７の材料が熱硬化性樹脂であれば、ＣＯ２レーザやＵＶレーザ等を用いた加工により形成可能であり、レーザ加工の後は、レーザ加工で発生したスミアを除去する為にデスミア処理を行えば良い。また、絶縁性樹脂層７の材料が感光性レジストの場合は、フォトリソ法にて形成すれば良い。 The conductive via 9 is formed by performing a process of filling a conductive substance such as conformal plating, filled plating, and filling of a conductive paste inside the conductive via hole formed in the insulating resin layer 7. The method of forming conductive via holes in the insulating resin layer 7 may be selected, for example, depending on the material of the insulating resin layer 7. If the material of the insulating resin layer 7 is a thermosetting resin, a CO 2 laser or the like may be used. It can be formed by processing with a UV laser or the like, and after the laser processing, a desmear treatment may be performed to remove the smear generated by the laser processing. When the material of the insulating resin layer 7 is a photosensitive resist, it may be formed by a photolithography method.
次に、導通ビア９及び絶縁性樹脂７上に第二の配線層８を形成する。第二層目の配線層８の形成方法は特に規定しないが、無機密着層４として無電解めっき、または、スパッタ膜を使用し、電解めっきにて厚付けし、セミアディティブ法やサブトラクティブ法によりパタン形成する方法を用いればよい。 Next, the second wiring layer 8 is formed on the conductive via 9 and the insulating resin 7. The method for forming the wiring layer 8 of the second layer is not particularly specified, but electroless plating or a sputtering film is used as the inorganic adhesion layer 4, and the wiring layer 8 is thickened by electrolytic plating, and is thickened by the semi-additive method or the subtractive method. A pattern forming method may be used.
以上により、本実施形態に係る多層構造の貫通電極付き回路基板１００を得ることができる。本実施形態の配線回路基板１００によれば、コア基板１０の貫通電極１４の小径化や狭ピッチ化およびガラス基材１表面の配線の微細化が可能となる。また、ガラス基材１の両面に形成した第二層目の配線層８との間で、貫通電極１４の集積度が高く、かつ高い導通信頼性を実現することが可能となる。 As described above, the circuit board 100 with a through electrode having a multi-layer structure according to the present embodiment can be obtained. According to the wiring circuit board 100 of the present embodiment, it is possible to reduce the diameter and pitch of the through electrodes 14 of the core substrate 10 and to make the wiring on the surface of the glass substrate 1 finer. Further, it is possible to realize a high degree of integration of the through electrodes 14 and high conduction reliability with the second layer wiring layer 8 formed on both surfaces of the glass base material 1.
本発明の実施例について、配線回路基板の製造方法を説明する。 A method of manufacturing a wiring circuit board will be described with respect to an embodiment of the present invention.
［実施例１］
以下、実施例１について、図１及び図７を参照しつつ、図２〜図６、図８を用いて説明する。
[Example 1]
Hereinafter, Example 1 will be described with reference to FIGS. 1 and 7, with reference to FIGS. 2 to 6 and 8.
ガラス基材１は、厚さ０．３ｍｍ、大きさ３００×３００ｍｍの低膨張ガラス（Ｒａ：１０ｎｍ、ＣＴＥ：３．８ｐｐｍ／℃）を使用した。ガラス基材１への貫通孔１３の形成には、ＣＯ２レーザを使用し、レーザパルス巾１００μｓ以下、ピーク出力４ｋＷ以上にて行った。貫通孔１３の内径は、Ｔｏｐ６０μｍΦ、Ｂｏｔｔｏｍ４０μｍΦにて形成した（図２）。 As the glass base material 1, low-expansion glass (Ra: 10 nm, CTE: 3.8 ppm / ° C.) having a thickness of 0.3 mm and a size of 300 × 300 mm was used. A CO 2 laser was used to form the through hole 13 in the glass substrate 1, and the laser pulse width was 100 μs or less and the peak output was 4 kW or more. The inner diameter of the through hole 13 was formed to be Top 60 μmΦ and Bottom 40 μmΦ (FIG. 2).
貫通孔１３を形成したガラス基材１の両面にマスキング材としてＣｒ膜１１をスパッタ成膜し、このＣｒ膜１１上に感光性ネガレジストフィルム２をラミネートした。次に、凹部６に相当する部分が開口したレジストパタンを形成し、開口部のＣｒ膜１１を硝酸セルムアンモニウムからなるエッチング液で溶解除去した（図３）。 A Cr film 11 was sputter-deposited on both sides of the glass substrate 1 having the through holes 13 formed as a masking material, and the photosensitive negative resist film 2 was laminated on the Cr film 11. Next, a resist pattern in which the portion corresponding to the recess 6 was opened was formed, and the Cr film 11 in the opening was dissolved and removed with an etching solution made of selumammonium nitrate (FIG. 3).
次に、Ｃｒ膜１１の開口部を２５℃に温度制御した３％フッ酸に添加剤を添加した水溶液にてエッチングし深さ５μｍの凹部６を形成した。ガラス基材のエッチング後、マスキング材のＣｒ膜１１及び感光性ネガレジスト２を剥離除去した（図４）。フッ酸水溶液によるエッチングにより、貫通孔１３の内径はＴｏｐ７０μｍΦ、Ｂｏｔｔｏｍ５０μｍΦになった。貫通孔１３の開口部の周縁部が溶解され、貫通孔１３の開口部の周縁部を曲面形状にすることができた（図４）。また、凹部６の算術表面粗さＲａは７０ｎｍとなり、エッチング前のガラス基材１表面に比べ粗化面が得られた。尚、凹部６のＲａ（算術平均粗さ）は、触針式膜厚計にて測定した。 Next, the opening of the Cr film 11 was etched with an aqueous solution prepared by adding an additive to 3% hydrofluoric acid whose temperature was controlled to 25 ° C. to form a recess 6 having a depth of 5 μm. After etching the glass substrate, the Cr film 11 of the masking material and the photosensitive negative resist 2 were peeled off and removed (FIG. 4). By etching with an aqueous hydrofluoric acid solution, the inner diameter of the through hole 13 became Top 70 μmΦ and Bottom 50 μmΦ. The peripheral edge of the opening of the through hole 13 was melted, and the peripheral edge of the opening of the through hole 13 could be formed into a curved surface shape (FIG. 4). Further, the arithmetic surface roughness Ra of the recess 6 was 70 nm, and a roughened surface was obtained as compared with the surface of the glass substrate 1 before etching. The Ra (arithmetic mean roughness) of the recess 6 was measured with a stylus type film thickness meter.
次に、凹部６を形成したガラス基材１の両面にスパッタ成膜にて０．０５μｍ厚のＴｉ膜と、０．３μｍ厚のＣｕ膜とを連続成膜し、貫通孔１３内のスパッタ膜が付かない部分の補完のため、無電解Ｎｉめっきを０．２μｍの厚みで形成して、無機密着層４を形成した。次に、凹部６を含むガラス基材１の両面に、導電性の金属材料３を電解銅めっきにて８μｍの膜厚で形成した。次に、貫通孔１３内をコンフォーマル銅めっきにて８μｍの厚さで形成した。次に、貫通孔１３内のコンフォーマル銅めっきの隙間に対して、シリカフィラーとエポキシ系樹脂からなる永久穴埋め樹脂１２をスクリーン印刷にて充填した（図５）。 Next, a 0.05 μm-thick Ti film and a 0.3 μm-thick Cu film were continuously formed on both sides of the glass substrate 1 on which the recess 6 was formed by sputtering, and the sputtered film in the through hole 13 was formed. Electroless Ni plating was formed to a thickness of 0.2 μm to form the inorganic adhesive layer 4 in order to supplement the portion where the residue was not attached. Next, a conductive metal material 3 was formed on both sides of the glass base material 1 including the recess 6 by electrolytic copper plating to a film thickness of 8 μm. Next, the inside of the through hole 13 was formed by conformal copper plating to a thickness of 8 μm. Next, the gap of the conformal copper plating in the through hole 13 was filled with a permanent hole filling resin 12 composed of a silica filler and an epoxy resin by screen printing (FIG. 5).
次に、ガラス基材１の両面の永久穴埋め樹脂１２と導電性の金属材料３と無機密着層４とをガラス基材１の最表面１５を終点として、酸化セリウムとシリカと過酸化水素の混合液からなる研磨剤を使用して化学機械研磨して、第一層目の配線層５と貫通電極１４とを作製した。これにより、コア基板１０を得た（図６）。 Next, the permanent filling resin 12 on both sides of the glass base material 1, the conductive metal material 3, and the inorganic adhesive layer 4 are mixed with cerium oxide, silica, and hydrogen peroxide, with the outermost surface 15 of the glass base material 1 as the end point. The first layer wiring layer 5 and the through electrode 14 were produced by chemical mechanical polishing using a liquid abrasive. As a result, the core substrate 10 was obtained (FIG. 6).
次に、絶縁性樹脂層７をコア基板１０の両面に積層した。絶縁性樹脂７の材料には、エポキシ系樹脂からなる層間絶縁用フィルム（ＡＢＦ）を使用した。次に、絶縁性樹脂層７に孔を形成し、導電ビア９を形成した。導通ビア９は、フィルドめっきにて形成した。絶縁性樹脂７への導通ビア９の形成には、ＵＶ−ＹＡＧレーザを使用し、内径は２０μｍΦにて形成した（図８）。 Next, the insulating resin layer 7 was laminated on both sides of the core substrate 10. As the material of the insulating resin 7, an interlayer insulating film (ABF) made of an epoxy resin was used. Next, a hole was formed in the insulating resin layer 7 to form a conductive via 9. The conductive via 9 was formed by filled plating. A UV-YAG laser was used to form the conductive via 9 on the insulating resin 7, and the inner diameter was 20 μmΦ (FIG. 8).
次に、配線層８を形成し、最表面の絶縁性樹脂層１６には感光性のソルダーレジストを形成し、導通パッド１８に無電解Ｎｉ／Ｐｔ／Ａｕめっきにて表面処理を施しし、多層構造の貫通電極付き配線回路基板１００を得た（図７）。 Next, the wiring layer 8 is formed, a photosensitive solder resist is formed on the outermost insulating resin layer 16, and the conduction pad 18 is surface-treated by electroless Ni / Pt / Au plating to form a multilayer. A wiring circuit board 100 with a through electrode having a structure was obtained (FIG. 7).
なお、実施例１では、絶縁性樹脂層７の上の配線層８の層数を１層とし、最表面の絶縁性樹脂層をソルダーレジスト１６とし、導通パッド１８表面の表面処理を無電解Ｎｉ／Ｐｔ／Ａｕめっきとしたが、これらの構成は、特に限定するものではない。また、貫通電極１４をコンフォーマル銅めっきにより形成したが、フィルド銅めっきとすることで永久穴埋め樹脂１２の印刷工程を省略する構成も可能である。 In Example 1, the number of layers of the wiring layer 8 above the insulating resin layer 7 is set to 1, the outermost insulating resin layer is set to solder resist 16, and the surface treatment of the surface of the conduction pad 18 is electroless Ni. Although / Pt / Au plating is used, these configurations are not particularly limited. Further, although the through electrode 14 is formed by conformal copper plating, it is possible to omit the printing step of the permanent hole filling resin 12 by using filled copper plating.
［実施例２］
以下、実施例２について、図１及び図７を参照しつつ、図９から図１４を用いて説明する。
[Example 2]
Hereinafter, Example 2 will be described with reference to FIGS. 1 and 7, with reference to FIGS. 9 to 14.
ガラス基材１は、厚さ０．３ｍｍ、大きさ３００×３００ｍｍの低膨張ガラス（Ｒａ：１０ｎｍ、ＣＴＥ：３．８ｐｐｍ／℃）を使用した。ガラス基材１への貫通孔１３の形成には、ＵＶレーザによるガラス改質と、ガラス改質部を所定濃度のフッ酸にてエッチングする工法を使用した。ガラス改質部を２５℃に温度制御した３％フッ酸水溶液にてエッチングし貫通孔１３を形成した。貫通孔１３の内径は、Ｔｏｐ４０μｍΦ、Ｂｏｔｔｏｍ３０μｍΦにて形成した（図９）。 As the glass base material 1, low-expansion glass (Ra: 10 nm, CTE: 3.8 ppm / ° C.) having a thickness of 0.3 mm and a size of 300 × 300 mm was used. For the formation of the through hole 13 in the glass base material 1, a method of modifying the glass with a UV laser and etching the glass reformed portion with a predetermined concentration of hydrofluoric acid was used. The glass modification part was etched with a 3% hydrofluoric acid aqueous solution whose temperature was controlled to 25 ° C. to form through holes 13. The inner diameter of the through hole 13 was formed to be Top 40 μmΦ and Bottom 30 μmΦ (FIG. 9).
貫通孔１３を形成したガラス基材１の両面にマスキング材としてＣｒ膜１１をスパッタ成膜し、このＣｒ膜１１上に感光性ネガレジストフィルム２をラミネートした。次に、凹部６に相当する部分が開口したレジストパタンを形成し、開口部のＣｒ膜１１を硝酸セルムアンモニウムからなるエッチング液で溶解除去した（図１０）。 A Cr film 11 was sputter-deposited on both sides of the glass substrate 1 having the through holes 13 formed as a masking material, and the photosensitive negative resist film 2 was laminated on the Cr film 11. Next, a resist pattern in which the portion corresponding to the recess 6 was opened was formed, and the Cr film 11 in the opening was dissolved and removed with an etching solution made of selumammonium nitrate (FIG. 10).
次に、Ｃｒ膜１０の開口部を２５℃に温度制御した３％フッ酸に添加剤を添加した水溶液にてエッチングし深さ２μｍの凹部６を形成した。ガラス基材のエッチング後、マスキング材のＣｒ膜１１及び感光性ネガレジスト２を剥離除去した。フッ酸水溶液によるエッチングにより、貫通孔１３の内径はＴｏｐ４４μｍΦ、Ｂｏｔｔｏｍ３４μｍΦになった。貫通孔１３の開口部の周縁部が溶解され、貫通孔１３の開口部の周縁部を曲面形状にすることができた（図１１）。また、凹部６の算術表面粗さＲａは７０ｎｍとなり、エッチング前のガラス基材１表面に比べ粗化面が得られた（図１１）。尚、凹部６のＲａ（算術平均粗さ）は、触針式膜厚計にて測定した。 Next, the opening of the Cr film 10 was etched with an aqueous solution prepared by adding an additive to 3% hydrofluoric acid whose temperature was controlled to 25 ° C. to form a recess 6 having a depth of 2 μm. After etching the glass substrate, the Cr film 11 of the masking material and the photosensitive negative resist 2 were peeled off and removed. By etching with an aqueous hydrofluoric acid solution, the inner diameter of the through hole 13 became Top 44 μmΦ and Bottom 34 μmΦ. The peripheral edge of the opening of the through hole 13 was melted, and the peripheral edge of the opening of the through hole 13 could be formed into a curved surface shape (FIG. 11). Further, the arithmetic surface roughness Ra of the recess 6 was 70 nm, and a roughened surface was obtained as compared with the surface of the glass substrate 1 before etching (FIG. 11). The Ra (arithmetic mean roughness) of the recess 6 was measured with a stylus type film thickness meter.
次に、凹部６を形成したガラス基材１の両面にスパッタ成膜にて０．０５μｍ厚のＴｉ膜と、０．３μｍ厚のＣｕ膜とを連続成膜し、貫通孔１３内のスパッタ膜が付かない部分の補完の為無電解Ｎｉめっきを０．２μｍの厚みで形成して、無機密着層４を形成した。次に、凹部６を含むガラス基材１の両面に、導電性の金属材料３を電解銅めっきにて１０μｍの膜厚で形成した。次に、貫通孔１３内をコンフォーマル銅めっきにて１０μｍの厚さで形成した（図１２）。 Next, a 0.05 μm-thick Ti film and a 0.3 μm-thick Cu film were continuously formed on both sides of the glass substrate 1 on which the recess 6 was formed by sputtering, and the sputtered film in the through hole 13 was formed. Electroless Ni plating was formed to a thickness of 0.2 μm in order to complement the portion not to be covered with, and the inorganic adhesive layer 4 was formed. Next, a conductive metal material 3 was formed on both sides of the glass base material 1 including the recess 6 by electrolytic copper plating to a film thickness of 10 μm. Next, the inside of the through hole 13 was formed by conformal copper plating to a thickness of 10 μm (FIG. 12).
次に、ガラス基材１の両面の導電性の金属材料３と無機密着層４とをガラス基材１の最表面１５を終点として、酸化セリウムとシリカと過酸化水素の混合液からなる研磨剤を使用して化学機械研磨して、第一層目の配線層５と貫通電極１４とを作製した（図１３）。 Next, an abrasive composed of a mixed solution of cerium oxide, silica, and hydrogen peroxide, with the conductive metal material 3 on both sides of the glass base material 1 and the inorganic adhesive layer 4 as end points on the outermost surface 15 of the glass base material 1. The first layer of the wiring layer 5 and the through electrode 14 was manufactured by chemical mechanical polishing using the above (FIG. 13).
次に、絶縁性樹脂層７をガラス基材１の両面に積層し、貫通電極１４内のコンフォーマル銅めっきの隙間を絶縁性樹脂７にて樹脂充填した。絶縁性樹脂７の材料には、エポキシ系樹脂からなるＡＢＦを使用した。次に、絶縁性樹脂層７に孔を形成し、導電ビア９を形成した。導通ビア９は、フィルドめっきにて形成した。絶縁性樹脂７への導通ビア９の形成には、ＵＶ−ＹＡＧレーザを使用し、内径は２０μｍΦにて形成した（図１４）。 Next, the insulating resin layer 7 was laminated on both sides of the glass base material 1, and the gap of the conformal copper plating in the through electrode 14 was resin-filled with the insulating resin 7. As the material of the insulating resin 7, ABF made of an epoxy resin was used. Next, a hole was formed in the insulating resin layer 7 to form a conductive via 9. The conductive via 9 was formed by filled plating. A UV-YAG laser was used to form the conductive via 9 on the insulating resin 7, and the inner diameter was 20 μmΦ (FIG. 14).
次に、配線層８を形成し、最表面の絶縁性樹脂層１６には感光性のソルダーレジストを形成し、導通パッド１８に無電解Ｎｉ／Ｐｔ／Ａｕめっきにて表面処理を施し、多層構造の貫通電極付き配線回路基板１００を得た（図７）。 Next, the wiring layer 8 is formed, a photosensitive solder resist is formed on the outermost insulating resin layer 16, and the conduction pad 18 is surface-treated by electroless Ni / Pt / Au plating to form a multilayer structure. A wiring circuit board 100 with a through electrode was obtained (FIG. 7).
なお、実施例２でも、絶縁性樹脂層７の上の配線層８の層数を１層とし、最表面の絶縁性樹脂層をソルダーレジストとし、導通パッド１８表面の表面処理を無電解Ｎｉ／Ｐｔ／Ａｕめっきとしたが、これらの構成は、特に限定するものではない。また、貫通電極１４をコンフォーマル銅めっきにより形成したが、フィルド銅めっきとすることで充填し、化学機械研磨（ＣＭＰ）にてガラス基材１の最表面１５上の導電性の金属材料３及び無機密着層４とともに除去する構成も可能である。 Also in Example 2, the number of layers of the wiring layer 8 above the insulating resin layer 7 is set to 1, the outermost insulating resin layer is used as a solder resist, and the surface treatment of the surface of the conductive pad 18 is electroless Ni /. Although Pt / Au plating is used, these configurations are not particularly limited. Further, although the through electrode 14 was formed by conformal copper plating, it was filled with filled copper plating, and the conductive metal material 3 and the conductive metal material 3 on the outermost surface 15 of the glass substrate 1 were subjected to chemical mechanical polishing (CMP). It is also possible to remove it together with the inorganic adhesive layer 4.
［比較例］
以下、比較例について、図１５〜図２１を用いて説明する。
[Comparison example]
Hereinafter, a comparative example will be described with reference to FIGS. 15 to 21.
ガラス基材１は、厚さ０．３ｍｍ、大きさ３００ｍｍ×３００ｍｍの低膨張ガラス（Ｒａ：１０ｎｍ、ＣＴＥ：３．８ｐｐｍ／℃）を使用した。ガラス基材１への貫通孔１３の形成には、ＣＯ２レーザを使用した。貫通孔１３の内径は、Ｔｏｐ６０μｍΦ、Ｂｏｔｔｏｍ４０μｍΦにて形成した（図１５）。 As the glass base material 1, low-expansion glass (Ra: 10 nm, CTE: 3.8 ppm / ° C.) having a thickness of 0.3 mm and a size of 300 mm × 300 mm was used. A CO 2 laser was used to form the through hole 13 in the glass substrate 1. The inner diameter of the through hole 13 was formed to be Top 60 μmΦ and Bottom 40 μmΦ (FIG. 15).
次に、このガラス基材１の両面にスパッタ成膜にて０．０５μｍ厚のＴｉ膜と、０．３μｍ厚のＣｕ膜とを連続成膜し、貫通孔１３内のスパッタ膜が付かない部分の補完のため無電解Ｎｉめっきを０．２μｍの厚みで形成して、無機密着層４を形成した（図１６）。 Next, a 0.05 μm-thick Ti film and a 0.3 μm-thick Cu film are continuously formed on both sides of the glass substrate 1 by sputtering, and a portion in the through hole 13 where the sputtering film is not attached. Electroless Ni plating was formed to a thickness of 0.2 μm to complement the above, and the inorganic adhesion layer 4 was formed (FIG. 16).
次に、第一層目の配線層５は、ネガ形ドライフィルムにて配線層５の形状に開口したパタンを形成し、セミアディティブ法にてガラス基材１のパタン開口部に電解銅めっきにて６μｍの膜厚で形成した。次に、貫通孔１３内に貫通電極１４をコンフォーマル銅めっきにて形成した。次に、ネガレジストパタンをアルカリ系の剥離液にて剥離し、露出した無機密着層４のＮｉめっき層をＷｅｔエッチングし、次にスパッタＣｕ層をＷｅｔエッチングし、次にスパッタＴｉ層をＷｅｔエッチングし、第一層目の配線層５を形成した（図１７）。 Next, the wiring layer 5 of the first layer forms a pattern opened in the shape of the wiring layer 5 with a negative dry film, and electrolytic copper plating is applied to the pattern opening of the glass base material 1 by a semi-additive method. It was formed with a film thickness of 6 μm. Next, the through electrode 14 was formed in the through hole 13 by conformal copper plating. Next, the negative resist pattern is peeled off with an alkaline stripping solution, the Ni-plated layer of the exposed inorganic adhesion layer 4 is Wet-etched, then the sputtered Cu layer is Wet-etched, and then the sputtered Ti layer is Wet-etched. Then, the first layer of the wiring layer 5 was formed (FIG. 17).
絶縁性樹脂層７をガラス基材１の両面に積層し、貫通孔１３内のコンフォーマル銅めっきの隙間を絶縁性樹脂７にて充填した。絶縁性樹脂７の材料には、エポキシ系樹脂からなるＡＢＦを使用した。次に、ガラス基材１の両面の絶縁性樹脂層７に孔を形成し、導電ビア９を形成した。導通ビア９は、フィルドめっきにて形成した。絶縁性樹脂７への導通ビア９の形成は、ＵＶ−ＹＡＧレーザを使用し、内径は２０μｍΦにて形成した（図１８）。 The insulating resin layer 7 was laminated on both sides of the glass base material 1, and the gaps of the conformal copper plating in the through holes 13 were filled with the insulating resin 7. As the material of the insulating resin 7, ABF made of an epoxy resin was used. Next, holes were formed in the insulating resin layers 7 on both sides of the glass base material 1, and conductive vias 9 were formed. The conductive via 9 was formed by filled plating. The conductive via 9 was formed on the insulating resin 7 by using a UV-YAG laser and having an inner diameter of 20 μmΦ (FIG. 18).
次に、導通ビア９と絶縁性樹脂層７表面にシード層として無電解Ｃｕめっきを形成し、第二層目の配線層８の形状に開口したネガレジストパタン１１を形成し、電解Ｃｕめっきにて配線層８を厚盛り形成した（図１９）。 Next, electroless Cu plating is formed as a seed layer on the surfaces of the conductive via 9 and the insulating resin layer 7, and a negative resist pattern 11 opened in the shape of the wiring layer 8 of the second layer is formed for electrolytic Cu plating. The wiring layer 8 was thickly formed (FIG. 19).
ネガレジストパタン１１をアルカリ系の剥離液にて剥離し、露出したシード層のＣｕ層をＷｅｔエッチングし、第二層目の配線層８を形成した（図２０）。 The negative resist pattern 11 was peeled off with an alkaline stripping solution, and the Cu layer of the exposed seed layer was wet-etched to form the wiring layer 8 of the second layer (FIG. 20).
最表面の絶縁性樹脂層１６には感光性のソルダーレジストを形成し、導通パッド１８に無電解Ｎｉ／Ｐｔ／Ａｕめっきにて表面処理を施し、多層構造の貫通電極付き配線回路基板１００を形成した（図２１）。 A photosensitive solder resist is formed on the outermost insulating resin layer 16, and the conduction pad 18 is surface-treated by electroless Ni / Pt / Au plating to form a wiring circuit board 100 with a through electrode having a multi-layer structure. (Fig. 21).
［実施例１、２及び比較例の評価方法］
信頼性試験は、冷熱衝撃試験（ＴＳＴ） ＪＥＤＥＣ、ＪＥＳＤ２２−Ａ１０６Ｂ、Ｃ：１２５℃⇔−５５℃ ４００サイクル にて、断線の有無で評価した。
また、配線密着性は、ピール試験機を用いて、ＪＩＳ Ｈ８６３０に準拠し、ガラス基材上のめっき皮膜に１０ｍｍ幅の切れ込みを入れ、９０°剥離して測定した。
表１に発明例１，２及び比較例のデータをまとめた。
[Evaluation method of Examples 1 and 2 and Comparative Example]
The reliability test was evaluated by the thermal shock test (TST) JEDEC, JESD22-A106B, C: 125 ° C.⇔-55 ° C. for 400 cycles with or without disconnection.
The wiring adhesion was measured by making a 10 mm wide notch in the plating film on the glass substrate and peeling it by 90 ° using a peel tester in accordance with JIS H8630.
Table 1 summarizes the data of Invention Examples 1 and 2 and Comparative Examples.
［実施例１、実施例２の評価］
実施例１、実施例２は、フッ酸溶液のエッチングにより凹部６を形成することにより、貫通孔１３の開口部の周縁部が曲面形状になり、配線層５に対し応力集中を低減する効果が得られた。また、フッ酸溶液のエッチングにより、貫通孔１３の熱歪領域の除去によりマイクロクラックの発生の解消や、凹部６の算術表面粗さＲａを１００ｎｍ以下まで粗化することができた。これにより、貫通電極１４の応力集中の抑制やマイクロクラックの発生の抑制、及び、ガラス基材１と第一層目の配線層５との密着性の向上が可能となった。
[Evaluation of Example 1 and Example 2]
In Examples 1 and 2, by forming the recess 6 by etching the hydrofluoric acid solution, the peripheral edge of the opening of the through hole 13 has a curved surface shape, which has the effect of reducing stress concentration on the wiring layer 5. Obtained. Further, by etching the hydrofluoric acid solution, the generation of microcracks could be eliminated by removing the heat strain region of the through hole 13, and the arithmetic surface roughness Ra of the recess 6 could be roughened to 100 nm or less. This makes it possible to suppress the stress concentration of the through electrode 14, suppress the occurrence of microcracks, and improve the adhesion between the glass base material 1 and the wiring layer 5 of the first layer.
また、無機密着層４にエッチング性の難しい材料を選択した場合であっても、ガラス基材１の最表面１５が露出するまで化学機械研磨（ＣＭＰ）することで、容易に第一層目の配線層５を形成することが可能なことを確認した。また、実施例２の如く、貫通電極１４内の配線厚を厚く形成し、ガラス基材の第一層目の配線層５の線幅を細くし、かつ、配線層５の厚みを薄く形成した場合であっても、接続信頼性の高い微細配線回路基板を形成することが可能なことを確認した。 Further, even when a material having a difficult etching property is selected for the inorganic adhesive layer 4, the first layer can be easily obtained by chemical mechanical polishing (CMP) until the outermost surface 15 of the glass substrate 1 is exposed. It was confirmed that the wiring layer 5 can be formed. Further, as in the second embodiment, the wiring thickness in the through electrode 14 is formed to be thick, the line width of the wiring layer 5 of the first layer of the glass substrate is thinned, and the thickness of the wiring layer 5 is thinned. Even in this case, it was confirmed that it is possible to form a fine wiring circuit board with high connection reliability.
これらの結果、実施例１及び２に係る配線回路基板１００は、配線層の線幅を細くし、かつ、配線層の厚みを薄く形成した場合であっても、高温−低温の温度変化を伴う信頼性試験において剥離破断を回避し、高い接続信頼性を得ることができることを確認した。 As a result, the wiring circuit board 100 according to Examples 1 and 2 is accompanied by a temperature change between high temperature and low temperature even when the line width of the wiring layer is thin and the thickness of the wiring layer is thin. In the reliability test, it was confirmed that peeling breakage could be avoided and high connection reliability could be obtained.
［比較例の評価］
比較例によれば、ガラス基材１の表面に、第一層目の配線層５と、絶縁性樹脂７と、配線層８とを積層形成して配線回路基板１００を作製することは可能であるが、無機密着層４のＷｅｔエッチングを３種の薬液で３回行う必要があるため、エッチング性の低い金属材料などがエッチング不良に繋がるリスクが高くなることが分かった。
[Evaluation of comparative example]
According to the comparative example, it is possible to fabricate the wiring circuit board 100 by laminating the first layer wiring layer 5, the insulating resin 7, and the wiring layer 8 on the surface of the glass base material 1. However, since it is necessary to perform Wet etching of the inorganic adhesive layer 4 three times with three kinds of chemicals, it has been found that a metal material having low etching property has a high risk of leading to poor etching.
また、ガラス基材１の表面の平滑な面に第一層目の配線層５を形成する為密着性が実施例１、２に比べやや低下することを確認した。また、ＴＳＴ後の断線の原因は、貫通電極１４の開口部の周縁部起点の配線層の破断、シード層剥離不足によるショートよるものであった。これにより、貫通孔１３の開口部の周縁部が鋭角に仕上がる為応力集中による配線層５の断線のリスクが実施例１，２に比べ高いことを確認した。 Further, it was confirmed that the adhesion was slightly lowered as compared with Examples 1 and 2 because the wiring layer 5 of the first layer was formed on the smooth surface of the surface of the glass base material 1. Further, the cause of the disconnection after TST was a short circuit due to a breakage of the wiring layer starting from the peripheral edge of the opening of the through electrode 14 and insufficient peeling of the seed layer. As a result, it was confirmed that the risk of disconnection of the wiring layer 5 due to stress concentration is higher than that of Examples 1 and 2 because the peripheral edge of the opening of the through hole 13 is finished at an acute angle.
［実施例と比較例との対比］
以上説明したように、本発明によれば、充分な信頼性を有する配線回路基板１００を提供することが可能であることを確認した。
[Comparison between Examples and Comparative Examples]
As described above, it has been confirmed that according to the present invention, it is possible to provide the wiring circuit board 100 having sufficient reliability.
本発明に係る配線回路基板及びその製造方法によれば、特に、パッケージ基板と半導体素子との間に介在する配線回路基板や、半導体素子を接続するための配線回路基板を備える半導体装置の製造に利用可能である。 According to the wiring circuit board and the manufacturing method thereof according to the present invention, in particular, for manufacturing a wiring circuit board interposed between a package board and a semiconductor element, and a semiconductor device including a wiring circuit board for connecting a semiconductor element. It is available.
１ … ガラス
２ … レジスト
３ … 導電性の金属材料
４ … 無機密着層
５ … 第一層目の配線層
６ … 凹部
７ … 絶縁性樹脂
８ … 第二層目の配線層
９ … 導通ビア
１０ … コア基板
１１ … レジスト
１２ … 穴埋め樹脂
１３ … 貫通孔
１４ … 貫通電極
１５ … ガラス基材の最表面
１６ … ソルダーレジスト
１８ … 導通パッド
１００ …配線回路基板
1 ... Glass 2 ... Resist 3 ... Conductive metal material 4 ... Inorganic adhesion layer 5 ... First layer wiring layer 6 ... Recessed 7 ... Insulating resin 8 ... Second layer wiring layer 9 ... Conductive via 10 ... Core substrate 11 ... Resist 12 ... Filling resin 13 ... Through hole 14 ... Through electrode 15 ... Outermost surface of glass substrate 16 ... Solder resist 18 ... Conductive pad 100 ... Wiring circuit board
Claims (10)
前記ガラス基材にレーザ加工により貫通孔を形成する貫通孔形成工程と、
前記ガラス基材の両面の前記貫通孔の開口部を含む領域に凹部をエッチングにより形成するエッチング工程と、
前記ガラス基材の両面と前記貫通孔の内壁とを導電性の金属材料で被覆する被覆工程と、
前記導電性の金属材料を前記ガラス基材の最表面を終点として研磨除去する研磨工程とを有し、
前記貫通孔の開口部の周縁部が曲面形状であって、かつ、前記周縁部の内径が前記貫通孔の外方に向かって徐々に広がっていることを特徴とする配線回路基板の製造方法。 A method for manufacturing a wiring circuit board with a through electrode having a multi-layer structure having a through electrode inside a glass substrate.
A through-hole forming step of forming a through-hole in the glass substrate by laser processing,
An etching step of forming a recess by etching in a region including an opening of the through hole on both sides of the glass substrate.
A coating step of coating both sides of the glass substrate and the inner wall of the through hole with a conductive metal material,
It has a polishing step of polishing and removing the conductive metal material with the outermost surface of the glass base material as an end point.
A method for manufacturing a wiring circuit board, characterized in that the peripheral edge of the opening of the through hole has a curved surface shape, and the inner diameter of the peripheral edge gradually expands toward the outside of the through hole.
前記貫通孔の開口部の前記周縁部のガラスを除去して前記周縁部を曲面形状に形成することを特徴とする請求項１に記載した配線回路基板の製造方法。 The etching step is performed by wet etching using a hydrofluoric acid solution having a predetermined concentration.
The method for manufacturing a wiring circuit board according to claim 1, wherein the peripheral portion of the opening of the through hole is removed of glass to form the peripheral portion in a curved shape.
前記凹部のエッチング深さに対し、前記貫通孔の中央部よりも前記貫通孔の上端及び下端の開口部のエッチングが進行し前記貫通孔の中心軸を含む断面がＸ形状となり、前記貫通孔の開口部の前記周縁部の溶融ガラスを除去して前記周縁部を曲面形状に形成することを特徴とする請求項１に記載した配線回路基板の製造方法。 The etching step is performed by dry etching using a reactive gas.
With respect to the etching depth of the recess, etching of the upper and lower ends of the through hole proceeds from the central portion of the through hole, and the cross section including the central axis of the through hole becomes X-shaped. The method for manufacturing a wiring circuit board according to claim 1, wherein the molten glass at the peripheral portion of the opening is removed to form the peripheral portion into a curved surface shape.
ロム、酸化クロム、チッ化アルミ、チッ化銅、酸化アルミ、タンタル、チタン、銅のうち、単体の材料の単層の膜、または、これらのうちの２種類以上の材料を複合させた２層以上の積層の膜であることを特徴とする請求項５に記載した配線回路基板の製造方法。 The inorganic adhesion layer is a single layer of a single material among tin oxide, indium oxide, zinc oxide, nickel, nickel phosphorus, chromium, chromium oxide, aluminum titrated, copper titrated, aluminum oxide, tantalum, titanium, and copper. The method for manufacturing a wiring circuit board according to claim 5, wherein the film is a film of two or more layers in which two or more kinds of materials thereof are composited.
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| US11152294B2 (en) * | 2018-04-09 | 2021-10-19 | Corning Incorporated | Hermetic metallized via with improved reliability |
| KR102475010B1 (en) * | 2018-05-29 | 2022-12-07 | 3디 글래스 솔루션즈 인코포레이티드 | Low insertion loss rf transmission line |
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| CN113474311B (en) | 2019-02-21 | 2023-12-29 | 康宁股份有限公司 | Glass or glass ceramic article with copper-metallized through-holes and process for making same |
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