JP2020053512A - Wiring circuit board, semiconductor device, and manufacturing method of wiring circuit board - Google Patents

Abstract

To provide a wiring circuit board using a glass substrate having a through hole, which prevents separation of a wiring pattern due to a difference in thermal expansion coefficient and has sufficient reliability.SOLUTION: When a wiring circuit board 100 using a glass substrate 1 having a through hole 13 is manufactured by forming an inorganic adhesion layer 4 as an adhesion-enhancing layer with the glass substrate, and forming a wiring pattern 5 made of a conductive material thereon, the sum of a value obtained by multiplying stress generated in the inorganic adhesion layer by the film thickness and a value obtained by multiplying the stress generated in the wiring pattern by the film thickness is 2250 (N/m) or less.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a printed circuit board and a semiconductor device, and more particularly to a printed circuit board interposed between a package substrate and an IC chip.

The IC chip cannot be directly connected to a printed wiring board such as a motherboard. This is because the pitch of the electrode terminals of the IC chip is several tens μm to several hundred μm, whereas the pitch of the electrode terminals that can be formed on the printed wiring board is several hundred μm or more.
A package substrate is used as an article for matching the pitch between an IC chip having a different electrode pitch and a printed wiring board.

Ceramic or resin is used as the material of the package substrate. Here, the resistance value of the ceramic package substrate is high because a metal wiring manufactured by firing is used. Further, the dielectric constant of ceramic is high, and it is difficult to mount a high-performance IC that operates at a high frequency. On the other hand, the resin package substrate can use copper wiring by plating, so that the wiring resistance can be reduced. Further, the dielectric constant of the resin is low, and it is relatively easy to mount a high-performance IC operating at a high frequency.
Here, as a technique for interposing a printed circuit board between a package substrate and an IC chip, for example, Patent Literature 1 and Patent Literature 2 can be cited.

  In recent years, as a high-end printed circuit board, a printed circuit board using silicon or glass as a material of the board has been actively researched and attracted attention.

  In a printed circuit board using silicon or glass as a substrate, a technique called TSV (Through-Silicon Via) or TGV (Through-Glass Via) in which a through hole is formed inside and a hole is filled with a conductive material is used. This is a major feature. The through-electrode formed by this technique has a short wiring length by connecting the front and back surfaces at the shortest distance, and is expected to have excellent electrical characteristics that can cope with an increase in signal transmission speed. In addition, since the coefficient of linear expansion is equal to or close to that of an IC chip, a change in the dimensions of the substrate during heating is small, and higher-density mounting and higher-density wiring may be realized. Further, by employing through electrodes, multi-pin parallel connection becomes possible, and it is expected that low power consumption can be realized because excellent electrical characteristics can be obtained without the need to speed up the LSI itself.

  In particular, in recent years, great attention has been paid to a printed circuit board using a glass substrate. One of the great interests in a printed circuit board using a glass substrate is realization of cost reduction. It is considered that a printed circuit board using a silicon substrate can be manufactured only in a wafer size, whereas a printed circuit board using a glass substrate is considered to be capable of mass processing on a large panel. There is a possibility that the problem of cost, which has been regarded as a major problem in a printed circuit board intended for use, can be solved.

  However, when manufacturing a printed circuit board using a glass substrate, there are some problems to be overcome. One of them is that a glass substrate has a large difference in thermal expansion coefficient and Young's modulus from a conductive material such as copper. In addition, since the adhesion strength of a conductive material such as copper to a glass substrate is not sufficient, a wiring pattern made of a conductive material is required in a manufacturing process of a printed circuit board, a high-temperature process during mounting, and a temperature cycle of a reliability test. Is separated from the surface of the glass substrate.

JP 2001-102479 A JP-A-2002-373962

  In order to solve the above-mentioned problems, the present invention provides a wiring circuit board using a glass substrate having a through hole, which prevents peeling of a wiring pattern due to a difference in thermal expansion coefficient and has sufficient reliability. It is an object to provide a circuit board.

As means for solving the above problems, the invention according to claim 1 of the present invention includes a wiring pattern made of a conductive material on the front and back surfaces of a glass substrate having a through hole, and the wiring pattern is provided in the through hole. In a printed circuit board using a core substrate that is conducted by a through electrode pattern made of a conductive material,
The wiring pattern and the through electrode pattern are provided on the surface of the glass substrate and in the through hole via an inorganic adhesive layer made of a conductive material,
The sum of a value obtained by multiplying the stress generated in the inorganic adhesion layer by the film thickness and a value obtained by multiplying the stress generated in the wiring pattern by the film thickness is 2250 (N / m) or less. Is a printed circuit board.

  In the invention described in claim 2, the diameter of the through hole is larger than twice the upper limit of the thickness of the through electrode pattern, and the form of the through electrode pattern is along the longitudinal direction of the through hole. The printed circuit board according to claim 1, wherein the center line portion has a hollow cylindrical shape.

  Further, in the invention according to claim 3, the diameter of the through hole is not more than twice the upper limit of the thickness of the through electrode pattern, and the form of the through electrode pattern is such that the through hole has the conductive property. The printed circuit board according to claim 1, wherein the printed circuit board has a column shape filled with a material.

  The invention according to claim 4 is characterized in that the inorganic adhesion layer is formed of tin oxide, indium oxide, zinc oxide, nickel, nickel phosphorus, chromium, chromium oxide, aluminum nitride, aluminum oxide, tantalum, titanium, and copper. The wiring according to any one of claims 1 to 3, wherein the wiring comprises a single-layer body or a laminate of two or more layers made of any one material selected from the group consisting of two or more materials. It is a circuit board.

  The invention according to claim 5 is characterized in that the conductive material is copper, silver, gold, nickel, platinum, palladium, ruthenium, tin, tin silver, tin silver copper, tin copper, tin bismuth, or tin lead. A single layer or a laminate of two or more layers of any one material or a compound thereof, or any two or more materials or a compound thereof, or any one or more of The printed circuit board according to any one of claims 1 to 4, wherein the printed circuit board is any one of a mixture of a powder of a material and a resin material.

  The invention according to claim 6 is characterized in that any one of epoxy / phenol, polyimide, cycloolefin, and PBO or a composite material thereof is used as the insulating resin layer. 2. The printed circuit board according to item 1.

According to a seventh aspect of the present invention, a semiconductor element is connected via a conductive pad portion provided on one surface of the printed circuit board according to the first aspect. Semiconductor device.

The invention according to claim 8 is a method for manufacturing a wired circuit board according to any one of claims 1 to 6,
Forming a through hole in the glass substrate,
Forming the inorganic adhesive layer on the front and back surfaces of the glass substrate and the inner wall of the through-hole,
Forming the first wiring pattern made of the conductive material and the through electrode pattern on the inorganic adhesion layer;
A step of manufacturing a core substrate by removing the inorganic adhesive layer exposed at a portion other than the first wiring pattern and the through electrode pattern;
A step A of forming the insulating resin layer on the front and back surfaces of the core substrate;
Forming a via hole serving as the conductive via at a desired portion of the insulating resin layer on the first wiring pattern;
A step C of forming the wiring pattern and the conductive via on the insulating resin layer in which the via hole is formed;
And a step of repeating steps A to C as many times as necessary.

  The printed circuit board of the present invention is provided with an inorganic adhesion layer having a value of (stress × film thickness) of 2250 N / m between a glass substrate and a wiring pattern penetrating electrode or pattern formed by electrolytic copper plating. Therefore, the difference in the coefficient of thermal expansion is reduced. As a result, it is possible to prevent the wiring pattern and the through electrode pattern from peeling off from the glass substrate, and at the same time, it is possible to improve the connection reliability in a heat cycle test or the like.

FIG. 3 is a cross-sectional view illustrating an example of a cross-sectional structure of the printed circuit board according to the present invention. FIG. 3 is a cross-sectional view illustrating an example of a semiconductor device manufactured using the printed circuit board of the present invention. FIG. 4 is an explanatory diagram illustrating a method for manufacturing the printed circuit board of the present invention shown in the first embodiment. FIG. 9 is an explanatory view illustrating a method for manufacturing the wired circuit board of the present invention shown in Embodiment 2. FIG. 9 is an explanatory diagram illustrating a method for manufacturing the printed circuit board shown in the comparative example.

<Wiring circuit board>
The printed circuit board of the present invention includes a wiring pattern made of a conductive material on the front and back surfaces of a glass substrate having a through-hole, and the wiring pattern is electrically connected by a through-electrode pattern made of a conductive material provided in the through-hole. This is a printed circuit board using a core substrate made of:

  In the wired circuit board of the present invention, the wiring pattern and the through electrode pattern are provided on the surface of the glass substrate and in the through hole via an inorganic adhesive layer made of a conductive material. The sum of the value obtained by multiplying the stress generated in the inorganic adhesion layer by the film thickness and the value obtained by multiplying the stress generated in the wiring pattern by the film thickness is 2250 (N / m) or less. It is a feature.

Further, in the wired circuit board of the present invention, a first wiring pattern made of a conductive material is provided on the front and back surfaces of a glass substrate having a through hole, and the first wiring pattern is made of a conductive material provided in the through hole. At least one surface of the core substrate which is electrically connected by the through electrode pattern is provided with at least one set of an insulating resin layer and a wiring pattern made of a conductive material alternately.
The wiring pattern is electrically connected to the wiring pattern via a conductive via provided in the insulating resin layer, and a conductive pad serving as an opening for connecting to an external circuit is provided on the uppermost insulating resin layer. The printed circuit board may be provided with a solder resist layer in which a portion is formed.

  The inorganic adhesion layer is made of any one material selected from tin oxide, indium oxide, zinc oxide, nickel, nickel phosphorus, chromium, chromium oxide, aluminum nitride, aluminum oxide, tantalum, titanium, and copper. It is preferably a single layer or a laminate of two or more layers made of two or more materials.

  The conductive material is any one material selected from copper, silver, gold, nickel, platinum, palladium, ruthenium, tin, tin silver, tin silver copper, tin copper, tin bismuth, and tin lead. Or a compound thereof, or a single-layer body or a laminate of two or more layers of any two or more materials or a compound thereof, or a powder and a resin material of any one or more materials. Or a mixture thereof.

  The insulating resin layer is preferably made of any one of epoxy / phenol, polyimide, cycloolefin, and PBO, or a composite material thereof.

  In the printed circuit board of the present invention, when the diameter of the through hole is larger than twice the upper limit of the thickness of the through electrode pattern, the form of the through electrode pattern is centered along the longitudinal direction of the through hole. The line portion has a hollow cylindrical shape. When the thickness is not more than twice the upper limit film thickness, it is preferable that the shape of the through electrode pattern is a column shape in which the through holes are filled with the conductive material.

  Here, the upper limit film thickness means that the inorganic adhesion layer formed on the surface of the glass substrate and the inner wall surface of the through hole, and the first wiring pattern and the through electrode pattern formed thereon are peeled off from the glass substrate. Refers to the maximum film thickness that cannot be obtained.

The printed circuit board of the present invention having the above-described configuration has sufficient reliability by preventing peeling between the wiring pattern and the glass substrate due to thermal expansion and contraction in the manufacturing process or the reliability test. .
Hereinafter, the printed circuit board of the present invention will be described in detail.

The coefficient of thermal expansion of the glass substrate is 3 to 4 ppm / ° C for low expansion glass and 8 to 9 ppm / ° C for soda glass, and can be controlled at 3 to 9 ppm / ° C by the manufacturing method and addition of metal components such as Na. is there. The Young's modulus of the glass substrate varies depending on the component, but is about 77 GPa.
Copper, which is often used as a conductive material, has a coefficient of thermal expansion of about 16 ppm / ° C. and a Young's modulus of about 110 GPa.

  By forming an inorganic adhesive layer with a lower stress than the conductive material on the through hole formed on the glass substrate and on both front and back surfaces, the difference in stress between the conductive material and the substrate causes the compressive stress of the conductive material itself to the glass substrate. Can be prevented, and the adhesion between the glass substrate and the conductive material can be improved.

  The conductive material has a compressive stress with respect to the glass substrate, the stress of the inorganic adhesive layer is preferably a compressive stress smaller than the stress of the conductive material, and the stress of the inorganic adhesive layer is the absolute value of the compressive stress of the conductive material. An equivalent tensile stress may be used.

Further, it is desirable that the sum of (stress × film thickness) of each layer of the wiring pattern composed of the laminated film of the conductive layer and the inorganic adhesive layer exerts a force of 2250 N / m or less on the thin film per unit width of pulling the glass substrate. If the value is higher than this, a phenomenon occurs in which the wiring pattern peels off from the glass substrate due to the heat history in the process.

  When the conductive material is copper plating, a stress acts in the direction of pulling the glass substrate, and the total thickness of the wiring pattern is 25 μm, and the value of (stress × film thickness) is equivalent to 2250 N / m. When the thickness of the copper plating increases, the wiring pattern is separated from the glass substrate into the region where the wiring pattern is peeled off, and the core substrate made of glass is damaged by the heat history of the manufacturing process.

  In the printed circuit board of the present invention, if the stress of the inorganic adhesion layer used is a tensile stress, the directions in which the forces of the respective layers act are the same, so that the thickness of the copper plating needs to be less than 25 μm.

  If the inorganic adhesive layer has a compressive stress, the force acts in a direction to cancel the force. Therefore, the thickness of the copper plating can be set to be larger than 25 μm within a range where the sum of (stress × film thickness) does not exceed 2250 N / m.

The force applied to the thin film can be calculated from the stress and the film thickness, and the stress can be calculated from the coefficient of thermal expansion and the Young's modulus.
The coefficient of thermal expansion was measured by TMA according to JIS R3102 and JIS K7197.
The stress applied to the thin film formed on the silicon wafer was determined by the Stoney equation using the radius of curvature R relating to the warpage of the substrate determined by measurement using laser light.
The Young's modulus was determined from the stress and strain.
(Stoney equation)
σ (stress) = Es × t _S ² / (6 × (1−Vs) × R × t _F ) (1)
σ: stress Es: Young's modulus of the substrate Vs: Poisson's ratio of the substrate ts: thickness of the substrate t _F : thickness of the thin film R: radius of curvature When measuring the stress, a 525 μm-thick silicon wafer was used as the substrate.
Force on thin film = σ x conductive layer thickness (N / m) ... (2)
Can be calculated as

  Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

The sectional configuration of the printed circuit board of the present invention will be described below with reference to FIG.
The printed circuit board 100 according to the present embodiment has a structure shown in FIG. As shown in FIG. 1, the printed circuit board 100 includes a wiring pattern 5 made of a conductive material and a penetrating electrode via an inorganic adhesive layer 4 on both front and back surfaces of a glass substrate 1 containing SiO ₂ as a main component and in a through hole 13. A pattern 3 (or 3-1) is formed (see FIGS. 3A to 3C).

The structure of the printed circuit board 100 includes an inorganic adhesive layer 4 on the glass substrate 1 including the inner wall surface of the through hole, and a conductive layer 14 including the wiring pattern 5 and the through electrode pattern 3 on the inorganic adhesive layer 4. And an insulating resin layer 7 on the conductive layer 14. Further, a second-layer wiring pattern 8 is provided on the insulating resin layer 7, and the conductive layer 14 and the wiring pattern 8 are electrically connected via the conductive via 9. Is a wiring circuit board with through electrodes having a multilayer structure in which the required number of layers is repeatedly laminated in that order.
Note that the required number of layers and the form of the metal layer of the through electrode pattern shown in FIG. 1 are shown as an example, and are not particularly limited to this configuration.

Next, a sectional configuration of the semiconductor device of the present invention will be described below with reference to FIG.
The semiconductor element 11 is mounted on one surface of the printed circuit board 100 (FIG. 1) of the present invention, and is mounted on a printed board on the other surface of the printed circuit board 100. Solder balls are used for each connection.
For bonding on the side on which the semiconductor element 11 is mounted on the printed circuit board 100, flip-chip mounting (micro-bump bonding) using micro-bumps, which are smaller solder balls, is usually used. After that, an underfill is filled between the semiconductor element 11 and the printed circuit board 100. In addition, flip-chip mounting (bump bonding) using solder balls larger than micro-bumps is performed for bonding between the printed circuit board 100 and a printed wiring board such as a motherboard.
The shape and connection method of the semiconductor element 11 shown in FIG. 2 are shown as one example, and the present invention is not limited to this.

<Structure of printed circuit board>
The configuration of the printed circuit board 100 according to the present invention is such that an inorganic adhesion layer 4 is laminated on both the front and back surfaces of the glass substrate 1 and the inner wall of the through hole 13 on the glass substrate 1 (see FIG. 3A) in which the through hole 13 is formed. The insulating resin layer 7 covers both surfaces of the core substrate 10-1 in which the wiring pattern 5 made of a conductive material and the through electrode pattern 3 are laminated on the inorganic adhesion layer 4 (see FIGS. 3D and 3E). ), A second-layer wiring pattern 8 is formed on the insulating resin layer 7, and a second-layer wiring pattern 8 on the surface of the core substrate 10-1 and the second-layer wiring pattern 8 on the insulating resin layer 7 are formed. (See FIG. 3E) in which a conductive via 9 is formed in order to electrically connect.

(Through hole)
The method of forming the through hole 13 (see FIG. 3A) is not particularly limited, but it can be formed by a CO ₂ laser, a UV laser, a short pulse laser, electric discharge machining, or the like, and eliminates thermal distortion of the through hole 13 itself. For this purpose, it is possible to remove the heat-strained portion by a method of baking the glass substrate 1 at a high temperature or by etching with hydrofluoric acid.

The diameter of the through-hole 13 may be determined according to the specifications of the product to be used. However, the structure of the through-hole electrode pattern 3 has an upper limit in the thickness of the conductive material that can be formed on the glass substrate 1. A tubular or filled structure should be selected for the purpose of keeping the material within the upper limit film thickness.
In the case of a cylindrical structure, it may be filled with the insulating resin layer 7 that covers the core substrate 10-1 (see FIG. 3D) (see FIG. 3E).
The stress between the conductive layer 14 and the inorganic adhesion layer 4 is also generated in the through electrode pattern 3, and when the through electrode pattern 3 is formed to have an allowable thickness or more, the through electrode pattern 3 becomes the inner wall surface of the through hole 13 of the glass substrate 1 (see FIG. 3). The phenomenon of peeling off from the surface occurs.

(Inorganic adhesion layer)
As the inorganic adhesion layer 4, tin oxide, indium oxide, zinc oxide, nickel (15 ppm) having high adhesion between the glass substrate 1 and the conductive material forming the conductive layer 14 and having a higher coefficient of thermal expansion than the glass substrate 1 is used. / ° C), electroless nickel-phosphorus plating, chromium (8 ppm / ° C), chromium oxide, aluminum nitride, aluminum oxide, tantalum (6 ppm / ° C), titanium (9 ppm / ° C), copper (16 ppm / ° C), etc. Can be used.

  It is desirable that the upper limit of the coefficient of thermal expansion of the inorganic adhesive layer 4 be lower than the conductive material forming the conductive layer 14.

By using the inorganic adhesion layer 4, the stress applied between the conductive material forming the conductive layer 14 and the interlayer caused by the difference in the coefficient of thermal expansion between the glass substrate 1 can be reduced, and peeling of the conductive material can be avoided. it can.

  It is possible to use a single layer of the material of the inorganic adhesion layer 4 exemplified above or a single layer of two or more kinds of composite materials such as an ITO film (9 ppm / ° C.). It is also possible to use a laminated film of two or more layers such as chromium / copper and titanium / copper.

  The thickness of the inorganic adhesion layer 4 is not particularly limited, but if it is 0.1 μm or more and 1 μm or less, an effect of alleviating the difference between the adhesion to the glass substrate 1 and the coefficient of thermal expansion can be obtained.

  Although the method for forming the inorganic adhesion layer 4 is not particularly limited, it can be formed by a sputtering film forming method, an electroless plating method, or the like.

(Conductive layer)
The conductive material forming the conductive layer 14 is one material selected from copper, silver, gold, nickel, platinum, palladium, ruthenium, tin, tin silver, tin silver copper, tin copper, tin bismuth, and tin lead Or a layered product obtained by laminating any two or more single materials, or a compound containing any metal or alloy thereof. A material having high adhesion to the inorganic adhesion layer 4 and high electrical connection stability may be selected. Alternatively, a conductive paste that is a mixture of a metal powder containing one or more of these metals and a resin material can also be used.

  The method for forming the conductive layer 14 is not particularly limited, but an electroless plating method or an electrolytic plating method is possible.

  When the through electrode pattern 3 formed by the plating method is formed in a cylindrical structure, it may be formed by conformal plating, and in the case of a filled structure, it may be formed by filled plating.

(Insulating resin layer)
As the insulating resin layer 7, it is possible to use any one of epoxy / phenol, polyimide, cycloolefin, PBO (polybenzoxazole) or a composite material thereof.

Since the insulating resin layer 7 has a coefficient of thermal expansion of 30 to 100 ppm / ° C. higher than that of the conductive material and a higher elastic modulus, covering the conductive layer 14 causes a stress applied between the conductive layer 14 and the glass substrate 1. Is reduced to some extent, and the effect of suppressing peeling of the conductive layer 14 is provided.
As the insulating resin layer 7, a dry film or a liquid resist can be used, and is not particularly limited.

<Method of manufacturing printed circuit board>
Next, a method for manufacturing the printed circuit board 100 of the present invention will be described with reference to FIG.
The method for manufacturing the printed circuit board 100 according to the present invention includes a step of forming a through hole 13 in the glass substrate 1 and a step of forming the inorganic adhesive layer 4 on the front and back surfaces of the glass substrate 1 and the inner wall of the through hole 13. Forming a first wiring pattern 5 made of a conductive material and a through-electrode pattern 3-1 on the inorganic adhesive layer 4, and a portion other than the first wiring pattern 5 and the through-electrode pattern 3-1. Forming the core substrate 10-1 by removing the inorganic adhesive layer 4 exposed on the substrate, step A of forming the insulating resin layer 7 on the front and back surfaces of the core substrate 10-1, A step B of forming a via hole serving as a conductive via 9 at a desired portion of the insulating resin layer 7 above, and forming a second or later wiring pattern 8 on the insulating resin layer 7 where the via hole is formed. Step C for forming the conductive via 9 and steps A to C are required. And a, a process repeated several.

(Method of forming via hole)
A method of forming a via hole serving as the conductive via 9 in the insulating resin layer 7 may be selected according to the insulating resin layer 7 to be used. If a thermosetting resin is used, a CO ₂ laser, a UV laser, or the like can be used. After laser processing, desmear processing may be performed to remove smear generated by laser processing.
In the case of a photosensitive resist, via holes may be formed by a photolithography method.

(Method of forming second and subsequent wiring patterns)
The method of forming the second and subsequent wiring patterns 8 on the insulating resin is not particularly specified, but the electroless plating or the sputtered film is used as a seed layer to form a thick layer by electrolytic plating, and the pattern is formed by a semi-additive method or a subtractive method. It may be formed.
Further, the number of layers of the insulating resin layer 7 and the wiring pattern 8 is not particularly limited, and may be set according to product design.
In addition to a wiring pattern, a capacitor component made of a dielectric material and an inductor component made of a coil structure can be formed as a pattern on a printed circuit board or embedded as a mounted component.

The printed circuit board 100 manufactured by the manufacturing method described above can realize high conduction reliability between the wiring patterns 5 and 8 on both front and back surfaces.
Further, the semiconductor device 200 (see FIG. 2) obtained by mounting the semiconductor element on the line circuit board 100 is obtained by optimizing the material of the conductive pad between the semiconductor element 11 to be connected and the printed board. High connection strength can be obtained, and high connection reliability can be realized by optimizing thermal deformation during mounting.

  Next, an embodiment of the wired circuit board of the present invention will be described.

<Example 1>
As the glass substrate 1, low-expansion glass having a thickness of 0.3 mm, a size of 200 × 200 mm, and a thermal expansion coefficient of 4 ppm / ° C. was used, and a through-hole 13 having a diameter of 70 μm was formed using a CO ₂ laser.

  Next, the inorganic adhesion layer 4 is formed by sputtering into a Ti film (coefficient of thermal expansion: 8.4 ppm / ° C., Young's modulus: 106 Gpa), and then a Cu film to a thickness of 0.1 μm and 0.2 μm, respectively. To form a laminate.

  Further, an electroless Ni plating film (coefficient of thermal expansion: 15 ppm / ° C., Young's modulus: 200 Gpa) was formed to a thickness of 0.1 μm on the Ni / Cu film formed by the sputtering apparatus. The test was performed so that the value of (stress × film thickness) of only the Ni film was 20 N / m.

  On the other hand, the above-mentioned laminated film was formed on a silicon wafer having a thickness of 525 μm, and the stress σ was calculated by measuring the radius of curvature of the warpage generated in the silicon wafer. To calculate the stress σ, the Stoney equation was used. The value of stress × film thickness was calculated by multiplying the stress σ by the film thickness.

The specific calculation is shown below.
First, stress σ was calculated as follows.
σ (stress) = 1.805 × 10 ¹¹ × (525 × 10 ⁻⁶ ) ² /(6×414×0.1×10 ⁻⁶ ) ≒ 200 (Mpa) (1 Pa = 1 N / m ² )
Next, a value of (stress × film thickness) was calculated by multiplying the calculated stress σ by the film thickness.
The value of (stress × film thickness) = 200 (MPa) × 0.1 × 10 ⁻⁶ (m) = 20 (N / m)

  Next, 8 μmt of electrolytic copper plating (thermal expansion coefficient: 16 ppm / ° C., Young's modulus: 110 Gpa) is formed on the glass substrate 1 on which the through hole 13 is formed and the inorganic adhesion layer 4 and the electroless Ni plating layer are formed. did.

  Next, the through electrode pattern 3 was formed in a cylindrical structure having a thickness of 8 μm by conformal plating. At this time, the total of (stress × film thickness) of the laminated film of the inorganic adhesion layer 4 and the conductive layer 14 was 870 N / m.

A laminated film having the same configuration as the above-mentioned laminated film was formed on a silicon wafer, the stress was calculated from the radius of curvature, and the stress σ applied to the thin film was calculated by multiplying the film thickness.
σ = 1.805 × 10 ¹¹ × (525 × 10 ⁻⁶ ) ² /(6×9.77×8×10 ⁻⁶ )
$ 106 (MPa)
Sum of (stress × film thickness) = (stress of inorganic adhesion layer 4 × value of film thickness) + (stress of conductive layer 14 × value of film thickness) = 20 (N / m) + 106 × 8 × 10 ⁻⁶ ( MPa)
= 20 + 848 (N / m)
≒ 870 (N / m)

An ABF film (an interlayer insulating resin film manufactured by Ajinomoto Co., Inc.) made of an epoxy resin is used for the insulating resin layer 7, and a second-layer wiring pattern 8 uses electroless copper plating for a seed layer, The thickness of the copper plating was 8 μm, the LS (Line & Space) value of the wiring pattern was 20 μm, and the wiring was formed by a semi-additive method.
At this time, the conductive via 9 was opened with a Top diameter of 50 μm using a UV-YAG laser, and the electrolytic copper plating was performed by conformal plating.

  The conductive pad portion was formed by Ni / Au plating. This is because it is assumed that the bonding with the semiconductor element is performed by soldering.

  Next, the manufacturing process of the printed circuit board 100-1 of the present invention will be described in more detail with reference to FIGS.

First, through holes 13 were formed in the glass substrate 1 by CO ² laser and hydrofluoric acid etching (FIG. 3A). Specifically, first, a through hole 13 having a diameter of 70 μm was formed at a predetermined position on the glass substrate 1 using a CO ² laser. Next, the residue by laser processing was removed by immersion in a glass etching solution using hydrofluoric acid.

  Next, a Ti film (thickness: 0.1 μm) and a Cu film (thickness: 0.2 μm) were continuously formed from both surfaces of the glass substrate 1 using a DC magnetron sputtering apparatus. Further, an electroless Ni plating film (thickness: 0.1 μm) was formed by lamination, and an inorganic adhesion layer 4 was formed on both surfaces and in the through holes (FIG. 3B).

  Next, a non-wiring pattern 16 made of a peelable photosensitive resist was formed on the inorganic adhesive layer 4. Next, electrolytic copper plating (first copper plating) was formed on both surfaces and on the inorganic adhesive layer 4 in the through holes 13. By this electrolytic copper plating, the wiring patterns 5 and the lands 6 are formed on the front and rear surfaces of the glass substrate 1 where the through holes 13 are formed, where the non-wiring patterns 16 are not formed. In FIG. 3, a through electrode pattern 3-1 having a cylindrical structure was formed (FIG. 3C).

Next, the non-wiring pattern 16 was removed. Next, the inorganic adhesive layer 4 in a portion other than the wiring pattern 5 and the land 6 exposed by removing the non-wiring pattern 16 is removed by wet etching, and the through-electrode pattern 3-1 is formed on the glass substrate 1. The core substrate 10-1 on which the wiring pattern 5 was arranged was formed (FIG. 3D).

  Next, the insulating resin layer 7 was laminated on both surfaces of the core substrate 10-1, and the central portion of the cylindrical structure of the through electrode pattern 3-1 was filled with the insulating resin layer 7. Next, a conductive via 9 is formed on the land portion 6 of the wiring pattern 5 by a UV-YAG laser, and dust in the conductive via 9 generated by the UV-YAG laser processing is desmeared with an alkaline aqueous solution. Cleaning (FIG. 3E).

Next, the wiring pattern 8 and the conductive via electrode 15 were formed on the insulating resin layer 7 by a semi-additive method.
Specifically, first, an electroless copper plating layer was formed on the entire surface as a seed layer. On the seed layer, a resist pattern in which the wiring pattern 8 and the conductive via 9 were opened was formed using a negative resist. Next, an electrolytic copper plating layer having a thickness of 8 μm was formed. Next, the resist pattern and the seed layer other than the second layer wiring pattern 8 were removed to form the wiring pattern 8 and the conductive via electrode 15.

  Next, a conductive solder portion 12 was formed on the front and back surfaces of the substrate by laminating a photosensitive solder resist 12 on the substrate prepared above, and performing exposure and development.

As described above, the conductive via electrode 15 connects the wiring patterns 5 formed on the front and back surfaces of the glass substrate 1 via the through electrode patterns 3-1 formed in the through holes 13 of the glass substrate 1. Further, the conduction pads 2 formed on the front and back surfaces are conducted through the conduction vias 9 which are conducted to the wiring pattern 5.
Finally, a surface treatment for forming a Ni / Au layer was performed on the surfaces of the conductive pad portions 2 on both surfaces, thereby producing a printed circuit board 100-1 of the present invention (FIG. 3F).

  In the present embodiment, the number of layers of the wiring pattern on one side is two, the coating layer on the surface is solder resist 12, and the surface treatment on the surface of the conductive pad portion 2 is Ni / Au. However, the present invention is not limited to these. Absent. The number of layers of the wiring pattern may be three or more, or the surface covering layer may be a layer made of a material other than the solder resist. Further, the surface treatment of the conductive pad portion 2 may be Ni / Pd / Au.

  As described above, the inorganic adhesion layer 4 having a smaller stress than the conductive layer 14 made of electrolytic copper plating is formed, and the thickness of the conductive layer 14 is set to a region in which the force applied to the thin film is equal to or less than the specified value, so that the glass substrate 1 The core substrate 10 having a sufficient adhesion between the wiring pattern 8 and the through-electrode pattern 3 in a heat history and a reliability test in a manufacturing process while avoiding a phenomenon in which the wiring pattern 8 and the through-electrode pattern 3 are separated from each other. -1 and the printed circuit board 100-1 were obtained.

  With these, the peeling of the wiring pattern 8 and the through electrode pattern 3 from the glass substrate 1 is prevented, and the semiconductor device 200 (see FIG. 2) using the wiring circuit board 100-1 having sufficient reliability is provided. It is possible.

<Example 2>
Embodiment 2 of the present invention will be described below with reference to FIG.

As the glass substrate 1, low-expansion glass having a thickness of 0.2 mm, a size of 200 × 200 mm, and a thermal expansion coefficient of 4 ppm / ° C. was used, and a through-hole 13 having a diameter of 40 μm was formed using a CO ² laser.

  Next, a Ti film (coefficient of thermal expansion: 8.4 ppm / ° C., Young's modulus: 106 GPa) and a Cu film were each formed to a thickness of 0.1 μm and a thickness of 0.1 μm using a DC magnetron sputtering apparatus. A layer was formed at a thickness of 0.2 μm.

Further, an electroless Ni plating film (thermal expansion coefficient: 15 ppm / ° C., Young's modulus: 200 GPa) is formed on the sputtered film to a thickness of 0.1 μm, and the value of (stress × film thickness) of the Ni film alone is set to 20 N / m. It was designed to be.
Further, a laminated film was formed on a silicon wafer, stress was calculated from the radius of curvature, and a value obtained by multiplying the stress by the film thickness was calculated as a force applied to the thin film.
σ (stress) = 1.805 × 10 ¹¹ × (525 × 10 ⁻⁶ ) ² /(6×414×0.1×10 ⁻⁶ ) ≒ 200 (Mpa) (1 Pa = 1 N / m ² )
Next, a value of (stress × film thickness) was calculated by multiplying the calculated stress σ by the film thickness.
The value of (stress × film thickness) = 200 (MPa) × 0.1 × 10 ⁻⁶ (m) = 20 (N / m)

Next, electrolytic copper plating (thermal expansion coefficient: 16 ppm / ° C., Young's modulus: 110 GPa) was formed as a conductive material to a thickness of 20 μm. Further, the through electrode pattern 3-2 was formed in a filling structure by filled plating.
From the laminated film of the inorganic adhesive layer 4 and the conductive layer 14 at this time, the sum of (stress × film thickness) was 1870 N / m.
A laminated film was formed on a silicon wafer, stress was calculated from the radius of curvature, and stress σ was calculated as the force applied to the thin film by multiplying the film thickness as follows.
σ = 1.805 × 10 ¹¹ × (525 × 10 ⁻⁶ ) ² /(6×4.48×20×10 ⁻⁶ )
= 92.5 (MPa)
Sum of (stress x film thickness) = (value of inorganic adhesion layer 4) + (value of conductive layer 14)
= 20 (N / m) + 92.5 × 20 × 10 ⁻⁶ (MPa)
= 1870 (N / m)

An ABF film made of an epoxy resin is used for the insulating resin layer 7, an electroless copper plating is used for the seed layer for the second wiring pattern 8, the thickness of the electrolytic copper plating is 8 μm, and the LS of the wiring pattern 8 is LS. The value was 20 μm, and the wiring was formed by a semi-additive method.
At this time, the conductive via 9 was opened with a Top diameter of 40 μm using a UV-YAG laser, and was formed by conformal plating.
The conductive pad portion 2 was plated with Ni / Au, and solder was used for connection with the semiconductor element.

  Next, the manufacturing process of the printed circuit board 200 of the present invention will be described in detail with reference to FIGS.

First, through holes were formed in the glass substrate 1 by a CO ² laser and hydrofluoric acid etching treatment (FIG. 4A). Specifically, first, a through hole 13 having a diameter of 70 μm was formed at a predetermined position on the glass substrate 1 using a CO ² laser. Next, the residue by laser processing was removed by immersion in a glass etching solution using hydrofluoric acid.

  Next, a Ti film (thickness: 0.1 μm) and a Cu film (thickness: 0.2 μm) were continuously formed from both surfaces of the glass substrate 1 using a DC magnetron sputtering apparatus. Further, an electroless Ni plating film (thickness: 0.1 μm) was formed by lamination, and an inorganic adhesion layer 4 was formed on both surfaces and in the through holes (FIG. 4B).

Next, a non-wiring pattern 16 made of a peelable photosensitive resist was formed on the inorganic adhesive layer 4. Next, electrolytic copper plating (first copper plating) was formed on both surfaces and on the inorganic adhesive layer 4 in the through holes 13. By this electrolytic copper plating, the wiring patterns 5 and the lands 6 are formed on the front and rear surfaces of the glass substrate 1 where the through holes 13 are formed, where the non-wiring patterns 16 are not formed. In FIG. 4, a through electrode pattern 3-2 having a filling structure was formed by filled electrolytic copper plating (FIG. 4C).

  Next, the non-wiring pattern 16 was removed. Next, the inorganic adhesive layer 4 in a portion other than the wiring pattern 5 and the land 6 exposed by removing the non-wiring pattern 16 is removed by wet etching, and the glass substrate 1 is provided with a through-electrode pattern 3-2. The core substrate 10-2 on which the wiring pattern 5 was arranged was formed (FIG. 4D).

  Next, the insulating resin layer 7 was laminated on both surfaces of the core substrate 10-2, and the central portion of the cylindrical structure of the through electrode pattern 3-2 was filled with the insulating resin 7. Next, a conductive via 9 is formed on the land portion 6 of the wiring pattern 5 by a UV-YAG laser, and dust in the conductive via 9 generated by the UV-YAG laser processing is desmeared with an alkaline aqueous solution. Cleaning (FIG. 4E).

Next, the wiring pattern 8 and the conductive via electrode 15 were formed on the insulating resin layer 7 by a semi-additive method.
Specifically, first, an electroless copper plating layer was formed on the entire surface as a seed layer. On the seed layer, a resist pattern in which the wiring pattern 8 and the conductive via 9 were opened was formed using a negative resist. Next, an electrolytic copper plating layer having a thickness of 8 μm was formed. Next, the resist pattern and the seed layer other than the second layer wiring pattern 8 were removed to form the wiring pattern 8 and the conductive via electrode 15 (FIG. 4F).

Next, a conductive solder portion 12 was formed on the front and back surfaces of the substrate by laminating a photosensitive solder resist 12 on the substrate prepared above, and performing exposure and development.
The surface of the conductive pad portions 2 on both surfaces was subjected to a surface treatment made of Ni / Au to produce a printed circuit board 100-2 of the present invention.

  In the present embodiment, the number of layers of the wiring pattern on one side is two, the coating layer on the surface is solder resist 12, and the surface treatment on the surface of the conductive pad portion 2 is Ni / Au. However, the present invention is not limited to these. Absent. The number of layers of the wiring pattern may be three or more, or the surface covering layer may be a layer made of a material other than the solder resist. Further, the surface treatment of the conductive pad portion 2 may be Ni / Pd / Au.

  As described above, the inorganic adhesion layer 4 having a smaller stress than the conductive layer 14 made of electrolytic copper plating is formed, and the thickness of the conductive layer 14 is designed in a region where the force applied to the thin film is equal to or less than a specified value. And the wiring pattern 8 and the penetrating electrode pattern 3-2 are prevented from peeling off, and the wiring pattern 8 and the penetrating electrode pattern 3-2 are sufficiently adhered to each other by a heat history and a reliability test in a manufacturing process. Core board 10-2 and printed circuit board 100-2 having

  Further, the wiring circuit board 100-2 and the wiring circuit board 100-2 which have sufficient reliability while preventing peeling of the wiring pattern 8 and the through-electrode pattern 3-2 from the glass substrate 1 are used. It is possible to provide an improved semiconductor device.

<Comparative example>
Next, a comparative example of the present invention will be described below with reference to FIG.

As the glass substrate 1, low-expansion glass having a thickness of 0.3 mm, a size of 200 × 200 mm, and a thermal expansion coefficient of 4 ppm / ° C. was used, and a through-hole 13 having a diameter of 70 μm was formed using a CO ² laser.

  The inorganic adhesion layer 4 is formed by laminating a Ti film (coefficient of thermal expansion: 8.4 ppm / ° C., Young's modulus: 106 GPa) and a Cu film to a thickness of 0.1 μm and 0.2 μm, respectively, using a DC magnetron sputtering apparatus. Formed.

  Further, an electroless Ni plating film (coefficient of thermal expansion: 15 ppm / ° C., Young's modulus: 200 GPa) is formed on the sputtered film to a thickness of 0.1 μm, and the value of (stress × film thickness) of the Ni film alone is 20 N / m.

  The conductive material was formed in a thickness of 30 μm by electrolytic copper plating (coefficient of thermal expansion: 16 ppm / ° C., Young's modulus: 110 GPa), and the through-electrode pattern 3-3 was formed in a cylindrical structure having a thickness of 30 μm by conformal plating. From the laminated film of the inorganic adhesive layer 4 and the conductive layer 14 at this time, the total value of (stress × film thickness) was 2620 N / m.

The force applied to the thin film was calculated as follows by forming a laminated film on a silicon wafer, calculating the stress σ from the radius of curvature, and multiplying the stress σ by the film thickness.
σ (stress) = 1.805 × 10 ¹¹ × (525 × 10 ⁻⁶ ) ² /(6×3.19×30×10 ⁻⁶ ) = 86.6 (MPa)
(Sum of stress × film thickness = 20 (N / m) +86.6 (MPa) × 30 × 10 ⁻⁶ (m)
≒ 2620 (N / m)

An ABF made of an epoxy resin is used for the insulating resin 7, an electroless copper plating is used for the seed layer of the second wiring pattern 8, the thickness of the electrolytic copper plating is 8 μm, and the LS value of the wiring pattern is 20 μm. The wiring was formed by a semi-additive method.
The conductive via 9 was opened with a Top diameter of 50 μm using a UV-YAG laser, and was formed by conformal plating.

First, a through hole 13 was formed in the glass substrate 1 by a CO ₂ laser and hydrofluoric acid etching treatment (FIG. 5A).

  Next, a sputtered Ti film and a sputtered Cu film are continuously formed on both sides of the glass substrate 1, and an electroless Ni plating film is further formed by lamination, and the inorganic adhesive layer 4 is formed on the front and back surfaces and in the through holes 13. (FIG. 5B).

  Next, after a non-wiring pattern 16 made of a peelable photosensitive resist is formed on the inorganic adhesive layer 4, the through-electrode pattern 3-3 is formed into a tubular structure by conformal electrolytic copper plating (FIG. 5 (c)).

  Next, the portions of the inorganic adhesive layer 4 other than the wiring pattern 5 on the front and back surfaces are removed by wet etching, and a core substrate 10-3 in which the through electrode pattern 3-3 and the wiring pattern 5 are arranged on the glass substrate 1 is formed. (FIG. 5D).

  Next, the insulating resin 7 was laminated on both surfaces of the core substrate 10-3, and the central portion of the cylindrical structure of the through electrode pattern 3-3 was filled with the insulating resin 7. A conductive via 9 is formed on the land pattern portion of the wiring pattern 5 with a UV-YAG laser, and dust in the hole of the conductive via 9 generated by the UV-YAG laser processing is swollen and decomposed with an alkaline aqueous solution. It was removed (FIG. 5 (e)).

  Next, electroless copper plating was formed on the insulating resin 7 as a seed layer. A resist pattern in which the wiring pattern 8 and the conductive via 9 are opened is formed thereon with a negative resist, and electrolytic copper plating is first formed as a conductive material to a thickness of 8 μm by a semi-additive method. The portion of the seed layer other than the second layer wiring pattern 8 was removed to form the wiring pattern 8 and the conductive via electrode 15 (FIG. 5F).

  In the manufacturing method described above, it was possible to obtain the printed circuit board 100-3 in which electrical continuity was obtained between the wiring patterns on the front and back surfaces. However, when the wiring pattern 5 of the core substrate 10-3 is formed, minute glass cracks are generated at the interface between the wiring pattern 5 and the core substrate 10-3, and thermal stress is applied to the wiring circuit substrate 100-3 in the high-temperature and low-temperature cycle test. In such a test, the compressive stress of the wiring pattern 5 becomes larger than the adhesion between the core substrate 10-3 and the wiring pattern 5, and the through-electrode pattern 3-3 and the wiring pattern 5 are higher than the core substrate 10-3. It peeled off, causing a problem of breaking the printed circuit board 100-3.

DESCRIPTION OF SYMBOLS 1 ... Glass substrate 2 ... Conductive pad parts 3-1 and 3-2 ... Through-electrode pattern 4 ... Inorganic adhesion layer 5 ... First wiring pattern 6 ... Land 7 ... Insulating resin layer 8 ... (2nd and subsequent layers) wiring Pattern 9 conductive vias 10-1, 10-2, 10-3 core substrate 11 semiconductor element 12 solder resist 13 through hole 14 conductive layer 15 conductive via electrode 16 (from a peelable photosensitive resist) ) Non-wiring patterns 100, 100-1, 100-2, 100-3 ... wiring circuit board 200 ... semiconductor device

Claims (8)

Wiring using a core substrate provided with a wiring pattern made of a conductive material on the front and back surfaces of a glass substrate provided with a through hole, wherein the wiring pattern is conducted by a through electrode pattern made of a conductive material provided in the through hole. On the circuit board,
The wiring pattern and the through electrode pattern are provided on the surface of the glass substrate and in the through hole via an inorganic adhesive layer made of a conductive material,
The sum of a value obtained by multiplying the stress generated in the inorganic adhesion layer by the film thickness and a value obtained by multiplying the stress generated in the wiring pattern by the film thickness is 2250 (N / m) or less. Printed circuit board.   The diameter of the through-hole is larger than twice the upper limit film thickness of the through-electrode pattern, and the form of the through-electrode pattern is a cylindrical shape in which the center line along the longitudinal direction of the through-hole is hollow. The printed circuit board according to claim 1, wherein:   The diameter of the through-hole is not more than twice the upper limit film thickness of the thickness of the through-electrode pattern, and the form of the through-electrode pattern is that the through-hole has a columnar shape filled with the conductive material. The printed circuit board according to claim 1, wherein:   The inorganic adhesion layer, tin oxide, indium oxide, zinc oxide, nickel, nickel phosphorus, chromium, chromium oxide, aluminum nitride, aluminum oxide, tantalum, titanium, any one material selected from copper or The printed circuit board according to any one of claims 1 to 3, wherein the printed circuit board comprises a single-layer body made of any two or more materials or a laminate of two or more layers.   The conductive material is any one material selected from copper, silver, gold, nickel, platinum, palladium, ruthenium, tin, tin silver, tin silver copper, tin copper, tin bismuth, tin lead or A single layer or a laminate of two or more layers of the compound, or any two or more materials or a compound thereof, or a mixture of a powder and a resin material including any one or more materials The printed circuit board according to any one of claims 1 to 4, wherein:   The printed circuit board according to any one of claims 1 to 5, wherein any one of epoxy / phenol, polyimide, cycloolefin, and PBO or a composite material thereof is used as the insulating resin layer.   A semiconductor device, wherein a semiconductor element is connected via a conductive pad portion provided on one surface of the printed circuit board according to claim 1. It is a manufacturing method of the printed circuit board in any one of Claims 1-6, Comprising:
Forming a through hole in the glass substrate,
Forming the inorganic adhesive layer on the front and back surfaces of the glass substrate and the inner wall of the through-hole,
Forming the first wiring pattern made of the conductive material and the through electrode pattern on the inorganic adhesion layer;
A step of manufacturing a core substrate by removing the inorganic adhesive layer exposed at a portion other than the first wiring pattern and the through electrode pattern;
A step A of forming the insulating resin layer on the front and back surfaces of the core substrate;
Forming a via hole serving as the conductive via at a desired portion of the insulating resin layer on the first wiring pattern;
A step C of forming the wiring pattern and the conductive via on the insulating resin layer in which the via hole is formed;
Repeating the steps A to C a required number of times.

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