JP2015207580A - Wiring board and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor package substrate and a manufacturing method of the same, which can improve adhesion of a core base material and a wiring pattern layer in a semiconductor package substrate using glass as the core base material, and which ease constraints of a wiring pattern layer due to diameters of a through hole and a land.SOLUTION: In a wiring board manufacturing method, by laminating a stress relaxation adhesion layer 3 and forming a via 4 on a core base material 1 after forming a through hole electrode 2 on the core base material 1, a diameter of a land 5 on the stress relaxation adhesion layer 3 is made smaller than a diameter of a through hole 2.

Description

    The present invention relates to a wiring board and a manufacturing method thereof.

  A semiconductor package substrate is used for electrical connection between the semiconductor chip and the motherboard. The semiconductor package substrate also serves to bridge the difference in thermal expansion coefficient between the semiconductor chip and the printed wiring board on which the semiconductor package is mounted, thereby increasing the bonding reliability of the system mounting. From such a role, the semiconductor package substrate is called an interposer substrate.

  In addition, the semiconductor package substrate is converted into a line width and pitch between the semiconductor chip and the mother board by changing the wiring width and pitch in the substrate in each layer to obtain electrical connection.

  By the way, with the recent miniaturization of the wiring of the semiconductor chip, it is required to produce a substrate that can cope with the semiconductor package substrate. Currently, semiconductor package substrates are generally made of organic materials. However, in semiconductor package substrates made of current organic materials, the substrate expands due to reflow during mounting, resulting in a pitch shift from the semiconductor chip. This raises the difficulty of implementation. As the wiring becomes finer, the effect of pitch deviation becomes greater, making mounting more difficult. Due to these factors, it is considered that there is a limit to the miniaturization of wiring from the viewpoint of mounting in organic materials. Further, since the substrate is warped due to the difference in thermal expansion coefficient between the semiconductor chip and the package substrate after mounting, the reliability of the bumps and the semiconductor chip is also lowered. In order to solve these problems, a new method for connecting to a semiconductor chip using a silicon interposer or a glass interposer has been proposed and actively developed. These interposers are expected to be used for 2.5D and 3D mounting. Since the linear expansion coefficient (CTE) of silicon and glass is the same as or close to that of a semiconductor chip, the stress generated by the difference in thermal expansion coefficient is reduced when the semiconductor chip and the semiconductor package substrate are flip-chip mounted. There are advantages you can do.

  When a package substrate is manufactured using silicon or glass, it is necessary to form wiring on the silicon or glass. However, silicon and glass are about 3 ppm / K, whereas the material used for the wiring is, for example, about 16 ppm / K for copper, which is several times different. When heating and cooling are performed in a temperature cycle test or the like, stress may be generated at the interface between silicon or glass and copper, and the wiring layer may be peeled off.

  FIG. 1 is a configuration diagram of a conventional semiconductor package substrate. It is an example of the structure using the buildup construction method which has a core layer.

  A core substrate 1 using glass or a silicon plate is formed at the center of the semiconductor package substrate. Further, the wiring pattern layer 7 and the insulating resin layer 6 are laminated in this order on the top and bottom of the core base material. Further, through-hole electrodes 2 or vias 4 are provided in the core layer and the build-up layer for conduction of each wiring pattern layer.

  A solder resist 9 is formed on the uppermost or lowermost insulating resin layer, and an electrode pad 8 is formed in a portion where no solder resist is present.

Here, when the core base material is glass or a silicon plate, the linear expansion coefficients of the core base material and the wiring pattern layer are different. For example, as described above, the glass or silicon has a density of about 3 ppm / K, and the wiring pattern material has a density of about 16 ppm / K. On the other hand, the glass epoxy resin used for the core layer of the organic package substrate is, for example, about 3 to 15 ppm / K, and the difference between the linear expansion coefficient and copper is larger when glass or silicon is used. Due to these reasons, stress may be generated at the interface between glass and silicon and copper in an environment with a large temperature difference such as a temperature cycle test, which may cause interface peeling or chipping or cracking in the glass or silicon. May not be reliable.

  As a solution to these problems, it has been proposed to form a wiring pattern after forming a stress relaxation layer and an adhesion layer on the surface of the core substrate in order to improve the adhesion between the wiring pattern and the core substrate (for example, , See Patent Document 1). In this method, a through-hole is formed by laminating the entire laminate after laminating a stress relaxation layer or adhesion layer on the surface of the glass substrate. However, in this method, when the land is formed on the stress relaxation layer and the adhesion layer, the land diameter is generally larger than that of the through hole. Therefore, the land diameter needs to be larger than the through hole diameter. Considering miniaturization of the wiring width, it is necessary to reduce the land diameter. However, with this method, it is impossible to manufacture a land diameter smaller than the through-hole diameter, and it is difficult to miniaturize the wiring.

JP 2013-521663 A

  The present invention has been made under the above circumstances, and an object of the present invention is to provide a manufacturing method that ensures adhesion between a core substrate and a wiring pattern layer and reduces restrictions on wiring pattern layer design due to a through-hole diameter.

  In order to achieve the above object in the present invention, a wiring board according to the present invention has a core base material, a wiring pattern layer and an insulating resin layer are laminated on the core base material, and stress is applied to the surface of the core base material. It has a relaxation adhesion layer, has no land on the core substrate surface, and has a land on the stress relaxation adhesion layer surface.

That is, the invention of claim 1 of the present invention is
A core base material; a wiring pattern layer; an insulating resin layer; a via; and a land, wherein the wiring pattern layer and the insulating resin layer are alternately stacked, and the wiring pattern layer and the via are electrically The land and the via are electrically connected wiring boards,
A stress relaxation adhesion layer is formed on a surface of the core base material, and a land is formed only on the surface of the stress relaxation adhesion layer.

The invention of claim 2 of the present invention
2. The wiring substrate according to claim 1, wherein glass is used for the core base material, and the glass has a structure having a plurality of through holes having an opening diameter of 10 to 500 [mu] m.

The invention of claim 3 of the present invention
The wiring board according to claim 1, wherein the stress relaxation adhesion layer has a plurality of vias.

The invention of claim 4 of the present invention
4. The wiring board according to claim 2, wherein a via diameter formed in the stress relaxation adhesion layer is smaller than the through hole diameter.

The invention of claim 5 of the present invention
5. The wiring board according to claim 2, wherein a diameter of the land is smaller than a diameter of the through hole.

The invention of claim 6 of the present invention
Forming a plurality of through holes in the core substrate;
Forming a through electrode in the through hole;
Forming a stress relaxation adhesion layer on the core substrate on which the through electrode is formed;
Providing a plurality of vias in the stress relaxation adhesion layer and forming lands on the surface of the stress relaxation adhesion layer;
A step of laminating a build-up layer on the stress relaxation adhesion layer on which the land is formed;
In this order, the method of manufacturing a wiring board is provided.

  According to the present invention, by forming the stress relaxation adhesion layer on the core substrate, the adhesion between the core substrate and the wiring pattern layer can be improved, and the stress generated at the interface can be relaxed. Furthermore, without forming a land on the core substrate, after forming a through hole, forming a via smaller than the through hole diameter in the stress relaxation adhesion layer and forming a land on the adhesion layer, the land diameter depending on the size of the through hole diameter Can be reduced. Thereby, the adhesiveness of a core base material and a wiring pattern layer is ensured, and the restriction | limiting of the wiring pattern layer design by a through-hole diameter can be reduced.

It is sectional drawing which shows the structure of the conventional wiring board. It is sectional drawing which shows the structure of the wiring board in the Example of this invention. It is sectional drawing which shows a part of manufacturing process of the wiring board in the Example of this invention. It is sectional drawing which shows the other part of the manufacturing process of the wiring board in the Example of this invention.

  Hereinafter, a method for manufacturing a semiconductor package substrate according to the present invention will be described based on an embodiment thereof, but the present invention is not limited to this.

  FIG. 2 is a sectional view showing the structure of the semiconductor package substrate of the present invention. The semiconductor package substrate has a core base material 1, a stress relaxation adhesion layer 3 formed on both surfaces of the core base material, vias 4, lands 5, and a wiring pattern layer 7 on both surfaces thereof. The core substrate has through-hole electrodes 2 in the thickness direction for connecting each wiring pattern layer. In addition, a build-up layer in which an insulating resin layer 6 is laminated is provided on the wiring pattern layer.

  The core substrate 1 is processed from a glass plate. As the material of the core base material, for example, a material selected from alkali-free glass and synthetic quartz glass can be used. It should be noted that the thermal expansion coefficient of glass should be close to the silicon value of the material used for the semiconductor chip. Thereby, the stress between the bumps generated due to the difference in linear expansion coefficient when the semiconductor chip and the semiconductor package substrate are flip-chip mounted can be reduced.

  Next, the stress relaxation adhesion layer 3 is a part formed on both surfaces of the core substrate. The material is a material with good adhesion between the core substrate and the wiring pattern layer, or a material that can relieve stress generated at the interface. For example, an epoxy resin or a polyimide resin is used. The land 5 and the wiring pattern layer 7 are portions formed on both surfaces of the stress relaxation adhesion layer 3 according to the wiring design. For example, copper is used as the material.

  The build-up layer is formed by a build-up method and has an insulating resin layer 6 and a wiring pattern layer 7. For example, an epoxy resin or a polyimide resin is used for the insulating resin layer, and a material obtained by adding a filler to the resin can also be used. The wiring pattern layer 7 is made of copper, for example. Note that the wiring pattern layers of each layer are electrically connected to each other by vias 4.

  Furthermore, electrode pads 8 are formed on the uppermost and lowermost wiring pattern layers to connect electrical signals to the outside. A solder resist 9 is formed on the outermost surface so as to open on the electrode pad. In addition, the material which added the filler to the photosensitive epoxy resin and resin can also be used for the material of a soldering resist, for example.

  Next, a method for manufacturing the semiconductor package substrate will be described.

  FIG. 3 is a cross-sectional view showing a manufacturing process of the semiconductor package substrate according to the embodiment.

  First, glass having a thickness in the range of 100 to 500 μm is prepared as the core substrate 1 (see FIG. 3A). The material of the glass is, for example, non-alkali glass or synthetic quartz glass. In addition, the glass shape is a plate shape in this embodiment, but the outer shape is not particularly limited, such as a square shape or a circular shape.

  In the present invention, glass is preferably used as the core base material, and the glass preferably has a plurality of through holes in the range of 10 to 500 μm.

  First, a through hole 10 having an opening diameter in the range of 10 to 500 μm is formed in a predetermined portion of the glass (see FIG. 3B). As a through hole forming method, for example, drilling and laser processing are used. The number and dimensions of the through holes are not particularly limited, and may be determined based on the design of the wiring pattern layer.

  A through electrode is formed in the through hole 10 on the glass surface (see FIG. 3C). First, an electroless copper plating film is formed on the entire surface of the glass surface and the side surface of the through hole by an electroless plating method (not shown in the figure). When the electroless plating film is not formed due to the smoothness of the glass surface, an electroless plating may be formed by providing an adhesion layer on the glass surface and in the through hole. Alternatively, a power feeding layer may be provided on the glass surface using a sputtering method or the like. In this case, for example, titanium and copper are sputtered on the glass surface and the side surface of the through hole on the power feeding layer. By doing so, the adhesiveness between glass, titanium, and copper can be improved. Thereafter, an electrolytic copper plating film in the range of 10 to 30 μm is formed by electrolytic plating.

  In this way, a through electrode is formed in the through hole. The copper plating forming method in the through hole is filled plating in this embodiment, but conformal plating may be performed, and a through electrode may be formed by inserting a resin into the through hole.

  Further, when the through electrode is formed in the through hole, there is a possibility that the surface position of the electrode is different from that of the glass surface or the conductive layer 11 formed by electrolytic plating is formed on the glass surface. Therefore, the conductive layer 11 is removed by removing a small amount of the glass and the conductive layer surface by chemical polishing and sandblasting, for example, on the front and back surfaces of the core base material portion to obtain flatness of the glass surface (see FIG. 3D).

Next, the stress relaxation adhesion layer 3 is formed on the core substrate (see FIG. 3E). First, the stress relaxation adhesion layer 3 is formed on both surfaces of the core substrate by using a vacuum laminating method, a spin coating method, or the like. Here, the material of the stress relaxation adhesion layer preferably has a smaller elastic modulus than the material of the core substrate and the wiring pattern layer, and the thermal expansion coefficient is preferably larger than the core substrate and smaller than the material of the wiring pattern layer, but is not limited thereto. . For example, an epoxy resin or a polyimide resin can be used. Thereafter, the resin is cured and cured.

  Next, the process of forming the land 5 on the stress relaxation adhesion layer will be described.

  In the present invention, a structure having a plurality of vias in the stress relaxation adhesion layer is preferable. A via hole 12 having an opening diameter of 20 to 100 μm is formed at a predetermined location of the stress relaxation adhesion layer (see FIG. 3F). As a forming method, for example, a UV laser, a carbon dioxide laser, or an excimer laser can be used. When the adhesion layer is a photosensitive resin, a photolithography method may be used.

  In the present invention, the via diameter formed in the stress relaxation adhesion layer is preferably smaller than the through-hole diameter.

Next, desmear treatment is performed on the smear of the via hole generated during laser processing, and an electroless copper plating film is formed on the stress relaxation adhesion layer and the via hole surface by an electroless plating method. Thereafter, a photoresist is formed on the electroless copper plating film (not shown in the drawing), and exposure and development are performed to form a land resist pattern.
Further, the relationship between the through hole diameter and the land diameter is such that the land diameter is smaller. Thereafter, an electrolytic copper plating film in the range of 10 to 30 μm is formed in the mask opening by electrolytic plating. Next, the resist pattern is peeled and removed. Next, the electroless copper plating film under the resist is removed by etching. In this way, the land 5 is formed (see FIG. 4G).

  Next, a buildup layer is stacked on the land (see FIG. 4H). First, a roughening process is performed on the stress relaxation adhesion layer and the land. By doing so, the adhesion between the stress relaxation adhesion layer and the insulating resin layer is improved. Thereafter, the insulating resin layer 6 is laminated on both surfaces of the substrate by a vacuum press and a roll laminator. Cure after lamination to cure the resin.

  Next, a via hole having an opening diameter of 20 to 100 μm is formed at a predetermined location of the buildup insulating resin layer 6. As a forming method, for example, a UV laser, a carbon dioxide laser, or an excimer laser can be used. Note that when the insulating resin layer is a photosensitive resin, a photolithography method may be used.

  Next, desmear treatment is performed on the smear of the via hole generated during laser processing, and an electroless copper plating film is formed on the surface of the insulating resin layer and the via hole by an electroless plating method. Thereafter, a photoresist is formed (not shown) on the electroless copper plating film, and a resist pattern is formed by performing exposure and development. Thereafter, an electrolytic copper plating film in the range of 10 to 30 μm is formed in the mask opening by electrolytic plating. Next, the resist pattern is peeled and removed. Next, the electroless copper plating film under the resist is removed by etching. In this way, the wiring pattern layer 7 is formed.

  Thereafter, the build-up layer of the semiconductor package substrate can be formed by repeating the steps from the formation of the insulating resin layer and the formation of the build-up layer including the via and the wiring pattern layer a predetermined number of times on both surfaces of the core base material. . In the present embodiment, a substrate having a structure having three wiring pattern layers on both surfaces of the core base material is formed by performing build-up layer formation twice.

Next, the electrode pad 8 is formed on the uppermost layer of the buildup layer (see FIG. 4 (h)). A solder resist 9 is formed on the top surface of the buildup layer by screen printing or vacuum laminating. Next, exposure and development are performed using a resist mask, the solder resist on the electrode pad is removed, and an opening is formed (see FIG. 4I). Thereafter, for example, solder bumps and gold bumps are formed for connection to the outside as necessary. In this manner, the semiconductor package substrate of this example is manufactured.

  Thus, by forming the stress relaxation adhesion layer on the core substrate, the adhesion between the core substrate and the wiring pattern layer can be improved, and the stress generated at the interface can be relaxed. Further, by forming a via smaller than the through-hole diameter in the stress relaxation adhesion layer without providing a land on the core base material and forming the land on the adhesion layer, the restriction of the land diameter due to the size of the through-hole diameter can be reduced. Thereby, the restriction | limiting of the wiring pattern layer design by a through-hole diameter can be reduced, ensuring the adhesiveness of a core base material and a wiring pattern layer.

  An embodiment of the present invention will be described below, but the present invention is not limited to this.

  An alkali-free glass having a size of 40 mm × 40 mm and a thickness of 300 μmt was prepared.

  Next, through holes having an opening diameter of 70 μm were formed at predetermined pitches of the glass using an excimer laser at a pitch of 200 μm.

  Next, a power feeding layer was provided on the side surface of the glass surface through hole by sputtering. For the power feeding layer, titanium sputtering (about 70 nm thick) and copper sputtering (about 250 nm thick) were performed on the glass. By doing so, the adhesiveness of glass, titanium, and copper was ensured. Thereafter, an electrolytic copper plating film was formed by an electrolytic plating method. The copper plating forming method in the through hole was filled plating.

  Next, a small amount of glass and conductive layer surfaces were ground on the front and back of the core base material portion by sandblasting, and the conductive layer was removed to flatten the glass surface.

Next, a 50 μmt epoxy-based insulating resin was laminated using a vacuum laminator apparatus at 100 ° C. and a load of 10 kg / cm ² . Thereafter, curing was performed under conditions of 100 ° C., 30 minutes, 170 ° C., 30 minutes to cure the resin, and a stress relaxation adhesion layer was formed on the core substrate.

  Next, a via hole having an opening diameter of 20 μm was formed at a predetermined location of the stress relaxation adhesion layer using a UV laser device. Next, desmear treatment was performed on the smear of the via hole generated during the laser processing, and an electroless copper plating film was formed on the stress relaxation adhesion layer and the via hole surface by an electroless plating method. Thereafter, a photoresist was formed on the electroless copper plating film, and a land resist pattern was formed by exposure and development. Thereafter, an electrolytic copper plating film having a thickness of about 17 μm was formed in the mask opening by electrolytic plating, the resist pattern was peeled and removed, and the electroless copper plating film under the resist was removed by etching. A land having a diameter of 50 μm was formed by such a method.

Thereafter, the stress relaxation adhesion layer and the land were subjected to a roughening treatment, and a 50 μmt epoxy insulating resin layer was laminated using a vacuum laminator apparatus at 100 ° C. and a load of 10 kg / cm ² . Thereafter, curing was performed under conditions of 100 ° C., 30 minutes, 170 ° C., 30 minutes to cure the resin.

A via hole having an opening diameter of 20 μm was formed at a predetermined location of the build-up insulating resin layer using a UV laser device. Next, desmear treatment was performed on the smear of the via hole generated during the laser processing, and an electroless copper plating film was formed on the build-up insulating layer and the via hole surface by an electroless plating method. Thereafter, a photoresist was formed on the electroless copper plating film, and a resist pattern was formed by performing exposure and development. Then, after forming an electrolytic copper plating film of about 17 μm in the mask opening by electrolytic plating, the resist pattern is peeled and removed, and the electroless copper plating film under the resist is removed by etching to form a wiring pattern layer. Formed.

  In this way, the process up to the formation of the insulating resin layer and the formation of the build-up layer including the via and the wiring pattern layer was repeated twice on both surfaces of the glass substrate, thereby having three wiring pattern layers on both surfaces of the core substrate. A semiconductor package substrate having a structure was produced.

  Next, a photosensitive solder resist was laminated on the uppermost layer of the build-up layer by a vacuum laminating apparatus, exposed and developed, the solder resist on the electrode pad was removed, and an opening was formed.

  Next, the tape peeling test of the land of the semiconductor package substrate manufactured by the above method was performed. The peel test was performed after the step of forming lands on the stress relaxation adhesion layer. The temperature was alternately changed in the range of −55 to 125 ° C. using a thermal cold impact tester, 500 cycles were performed, and then a tape peeling test was performed. As a result, no peeling was observed in the examples of the present invention.

<Comparative example>
Further, a conventional semiconductor package substrate shown in FIG. 1 in which a stress relaxation adhesion layer is not formed on the surface of the core substrate was produced by the same method. At the stage of the process of forming lands on the core substrate, the temperature was alternately changed in the range of −55 to 125 ° C. using a thermal cooling impact tester, 500 cycles were performed, and then a tape peeling test was performed. As a result, peeling was observed at the interface between the land and the core substrate.

  Compared with the comparative example, in the embodiment, by using the structure of the present invention, the adhesion between the core base material and the land of the semiconductor package substrate is increased, or the stress at the interface between the core base material and the land and the wiring pattern layer is relieved. Peeling or chipping of the substrate. It was confirmed that reliability against cracking was ensured.

  It can be used as a wiring board used for electrical connection between a semiconductor chip and a motherboard.

DESCRIPTION OF SYMBOLS 1 ... Core base material 2 ... Through-hole electrode 3 ... Stress relaxation adhesion layer 4 ... Via 5 ... Land 6 ... Insulating resin layer 7 ... Wiring pattern layer 8 ... Electrode pad 9 ... Solder resist

Claims (6)

A core base material; a wiring pattern layer; an insulating resin layer; a via; and a land, wherein the wiring pattern layer and the insulating resin layer are alternately stacked, and the wiring pattern layer and the via are electrically The land and the via are electrically connected wiring boards,
A wiring board, wherein a stress relaxation adhesion layer is formed on a surface of the core base material, and lands are formed only on the surface of the stress relaxation adhesion layer.   The wiring substrate according to claim 1, wherein glass is used for the core base material, and the glass has a plurality of through holes having an opening diameter of 10 to 500 μm.   The wiring board according to claim 1, wherein the stress relaxation adhesion layer has a plurality of vias.   The wiring board according to claim 2, wherein a via diameter formed in the stress relaxation adhesion layer is smaller than the through hole diameter.   The wiring board according to claim 2, wherein a diameter of the land is smaller than a diameter of the through hole. Forming a plurality of through holes in the core substrate;
Forming a through electrode in the through hole;
Forming a stress relaxation adhesion layer on the core substrate on which the through electrode is formed;
Providing a plurality of vias in the stress relaxation adhesion layer and forming lands on the surface of the stress relaxation adhesion layer;
A step of laminating a build-up layer on the stress relaxation adhesion layer on which the land is formed;
A method of manufacturing a wiring board, comprising:

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