JP6394136B2 - Package substrate and manufacturing method thereof - Google Patents

Description

  The present invention relates to a package substrate for mounting a semiconductor chip and a manufacturing method thereof, and more particularly to miniaturization of a circuit of the package substrate, improvement of dimensional stability, improvement of connection reliability, and cost reduction.

  In order to meet the recent demand for downsizing and higher functionality of electronic devices, a stacked multichip package in which a plurality of semiconductor chips are stacked in a semiconductor device has been developed. A stacked multichip package is suitable for miniaturization and high integration because a plurality of semiconductor chips are stacked to form a single package, and is mainly commercialized for memory products such as DRAM. However, in the conventional multi-chip package, each chip to be stacked and the package substrate are connected by wire bonding, so that the number of terminals that can be drawn from each chip is small. It is difficult to secure the wire bonding pads, and it is difficult to stack a large number of chips.

  On the other hand, recently, a chip stacking technique using a through silicon via (TSV; Through Silicon Via) as shown in FIG. TSV is a through electrode provided on a silicon substrate, and can be connected using TSV for electrical connection between stacked chips and between a chip and a package substrate. FIG. 2A shows an example of a stacked multichip package (also called a 3D package) in which a logic chip and a memory chip are three-dimensionally stacked by TSV. Reference numeral 101 denotes a memory chip. Here, a case where four memory chips are stacked is shown. Reference numeral 105 denotes a logic chip for the memory controller. The chips and the logic chip and the package substrate 104 are electrically connected via the TSV 102 and are connected by the bumps 103. The bump 103 is made of a metal such as solder or copper. With such chip stacking technology using TSV, it is possible to easily increase the number of chips to be stacked since wires that have been used conventionally are no longer necessary, and the connection distance between chips and between the chip and the package substrate can be increased. It is shortened and is advantageous for high-speed signal transmission. Furthermore, while conventional wire bonding wires have a diameter of 20-30 μm, TSVs can be formed with a diameter of 10 μm or less, so that more terminals can be drawn out and high capacity communication is possible. There are many advantages such as being possible.

  However, many processes are required for manufacturing a semiconductor chip with TSV, and therefore, it takes time and cost to manufacture. Further, in the case of the 3D package shown in FIG. 2A in which TSVs are formed on the logic chip, the memory and logic are connected with the TSV having the same pitch, so that the TSV bump pitch is unified between the logic and memory manufacturers. It is necessary to provide. In this case, the design restriction of the logic IC occurs, and there is a problem that the design cost is high. Further, in the case of a 3D package, it is necessary to join chips manufactured by a logic chip and a memory chip manufacturer, and then mount them on a semiconductor package substrate. If a failure occurs after assembling the semiconductor package, there are many problems such as quality assurance and manufacturing responsibility that it is not possible to clarify whether it is a failure at the assembly manufacturer or a manufacturing failure of any chip manufacturer. It has become.

  From the above, the multi-chip package (FIG. 2B) in which the three-dimensional chip of the DRAM memory and the logic chip that are relatively easy to stack with the TSV are mounted on the semiconductor package substrate 104 is most realistic. (So-called 2.5D package). In the 3D package, the signal wiring between the memory and the logic is connected by a minute TSV. However, in the case of the 2.5D package, the signal line connection between a plurality of semiconductor chips may be planarly connected on the semiconductor package substrate 104. Necessary. Therefore, since the number of wirings inevitably needs to be significantly increased on the semiconductor package substrate 104 side, the demand for fineness and multilayering has become more severe. Therefore, in the 2.5D package, it is mounted on a silicon interposer (106 in FIG. 2B) that can be finely connected to the three-dimensional stacked memory and the logic chip, A method of mounting a silicon interposer on which a semiconductor chip is mounted on a semiconductor package substrate 104 has been proposed ((b) of FIG. 2).

  However, in the 2.5D package shown in FIG. 2B, since the silicon interposer 106 is further interposed between the semiconductor package substrate 104 and the semiconductor chip, the efficiency is low and it is difficult to reduce the height. This causes a problem. Since the silicon interposer is manufactured by a wafer process, there is a problem that the cost is significantly higher than the price of a semiconductor package substrate manufactured with a panel size larger than that of the wafer. Since silicon is a semiconductor, in order to form a wiring circuit, it is necessary to form an oxide film once to insulate it, and to form a circuit wiring thereon. Therefore, there is a problem that the transmission characteristic of the wiring circuit formed on the silicon interposer is worse than the glass fiber reinforced resin substrate which is an insulator or a circuit formed on the glass substrate. Therefore, a semiconductor package substrate other than silicon, that is, a semiconductor package substrate (so-called organic interposer) having a glass interposer or a glass fiber reinforced resin substrate described in FIG. 3C as a core is desirable because it is more efficient and inexpensive. Research and development of glass interposers and organic interposers are becoming active as alternative technologies for silicon interposers.

  Here, a main manufacturing method of the semiconductor package substrate will be briefly described with an example of an organic interposer. The semiconductor package substrate is manufactured by a built-up method. First, a multilayer printed circuit board, which is a core substrate on which two or more layers of wiring circuits are formed, is prepared using a known printed wiring board manufacturing method. An interlayer insulating resin is laminated on the front and back surfaces of this wiring board by vacuum pressing, thermosetting and forming. Subsequently, via holes for conducting an interlayer circuit are formed on the front and back surfaces using a laser processing machine. After removing the laser smear by treating with a hot alkaline permanganate solution, the resin surface is made conductive by electroless plating. Further, a resist layer is formed on the front and back of the substrate, and a circuit pattern is formed using the resist by photolithography. Thereafter, electrolytic copper plating is performed using the electroless plating layer as a seed layer, thereby simultaneously forming vias as vertical holes for wiring and interlayer conduction using a resist pattern as a mold. A wiring circuit is formed by removing the resist and etching away unnecessary electroless plating layers. The built-up multilayer wiring layer is formed by repeating the etching removal of the electroless plating layer from the laminate of the interlayer insulating resin a plurality of times.

  As a technical problem to create a 2.5D semiconductor package substrate, a built-up formed on a core substrate that is a surface (first main surface) on which a plurality of semiconductor chips are mounted on the semiconductor package substrate. It is necessary to form fine and multilayer wiring layers. The reason is that, in the case of a 2.5D semiconductor package substrate, the number of semiconductor chips to be mounted increases, so that the number of signal lines for electrically connecting semiconductor elements to each other as compared with the conventional package substrate as described above. This is due to the significant increase. Specifically, in the conventional semiconductor package substrate, the line and space (L / S) = 10/10 μm was the limit, but in the 2.5D semiconductor package substrate, L / S = 5 μm / 5 μm or less fine multilayer wiring There is an increasing need to form layers. On the other hand, the wiring density of the built-up layer on the BGA side (second main surface) that is a connection terminal between the semiconductor package substrate and the mother board is not necessarily high, but the wiring density of the conventional semiconductor package substrate Can be handled by the manufacturing method. From the above, when manufacturing a 2.5D semiconductor package substrate, the second main surface side buildup layer that can be handled by a conventional method of manufacturing a semiconductor package substrate of L / S = 10 μm / 10 μm or more is It is necessary to form the wiring density of the built-up layer on the first main surface side to L / S = 5 μm / 5 μm or less and to form a multilayer than the second main surface.

  However, there is a problem of warping of the package substrate as a problem in that the build-up resin having the same layer thickness is formed in a multilayer and denser than the opposite side surface to make an asymmetric laminate layer structure centering on the core substrate. The main cause of warpage is thermosetting after laminating the built-up resin, which is a thermosetting resin, but when the insulating resin of the same thickness is laminated with the number of asymmetric layers on the front and back, the surface with the larger number of laminated layers, Residual stress due to curing shrinkage is accumulated in the resin layer. As a result, when a side having a larger number of laminate layers is arranged on the upper surface and a side having a smaller number of laminate layers is arranged on the lower surface, a downward curved curved warp is generated. The warpage in the semiconductor package substrate is a major factor causing poor connection with the semiconductor chip. In particular, in the case of a 2.5D semiconductor package substrate, since the terminal pitch with the semiconductor chip is required to be extremely narrow, the warpage problem is a major problem that determines the yield at the time of mounting. There is a need.

  Furthermore, there is a manufacturing problem as a problem of taking the number of laminate layers asymmetrical with the core substrate as the center. For example, when one layer is laminated on either the front or back side, a built-up resin layer is inevitably laminated on one side of the circuit board formed on the front and back sides, and the circuit pattern is exposed without laminating the opposite side. Leave it in the state. The laminated single-sided resin forms a via in a laser process and then enters a process of removing laser smear with a hot alkaline permanganate. In this case, the exposed single-sided circuit side on the non-resin laminated side is exposed to the permanganic acid solution, so that the resin is damaged. Damage to the resin causes deterioration of the adhesion of the formed circuit and resin deterioration, and causes deterioration in yield and electrical reliability. Although there is a method of forming a protective film on a single-sided circuit, it is necessary to select a film having heat alkaline permanganate resistance and to prepare a protective film that can be peeled without damaging the formed circuit. Therefore, it is difficult to say that a method for protecting a single-sided circuit using a protective film in realizing an asymmetric structure is practical in terms of cost and process. Due to the above-described warpage and process reasons, there is a demand for a package substrate structure and a method for manufacturing the same that can manufacture a substrate having a multilayer wiring on one side while avoiding the problem of warpage and with good yield and low cost.

  In recent years, the required characteristics of semiconductor package substrates are required not only for miniaturization but also for high connection reliability. A major factor of deterioration in connection reliability is a difference in thermal expansion coefficient between the semiconductor package substrate and the semiconductor chip. The thermal expansion coefficient of the semiconductor package must be able to maintain a good connection within the product life even in the thermal history during assembly and mounting processes (maximum 260 ° C) or in the operating thermal cycle when assembled as a semiconductor device after packaging. is there. In this problem, the material design is such that the thermal expansion coefficient of the semiconductor package substrate approaches 3 ppm of the semiconductor chip. Particularly in recent years, it has been desired that the thermal expansion coefficient of the semiconductor package substrate can be adjusted within 3 to 15 ppm with the narrowing of the pitch of the connection terminals of the semiconductor chip. On the other hand, in the connection (BGA side) between the semiconductor package substrate and the printed wiring board, the thermal expansion coefficient of the printed wiring board is still as high as 20 ppm or more. When the thermal expansion coefficient of the semiconductor package substrate is close to that of silicon to ensure connection reliability with the semiconductor chip (primary mounting reliability), on the other hand, connection reliability with the printed wiring board (secondary mounting reliability) There is a problem that it is difficult to maintain the property. Also in this respect, it is desirable from the viewpoint of connection reliability that the wiring circuit on the BGA side of the semiconductor package and the via hole should be L / S = 10 μm / 10 μm or more which is the wiring rule of the semiconductor package substrate so far. Also from the above viewpoint, the circuit on the first main surface on which the semiconductor chip is mounted is a fine multilayer circuit, and the BGA side circuit on the second main surface is preferably rough according to the conventional wiring rule from the viewpoint of reliability of secondary mounting. .

  By the way, semiconductor chips are becoming more highly functional and highly integrated, and the number of pins is steadily increasing. Flip chip connection is the mainstream for connecting semiconductor chips and semiconductor package substrates. Flip chip connection refers to a method in which a connection terminal formed on a semiconductor chip and a connection terminal on which a solder bump is formed on a semiconductor package substrate are held facing each other and thermally connected to perform solder connection. Needless to say, the number of pins in a semiconductor package substrate is increasing, and the number of pins, miniaturization, and narrowing of the pitch are also increasing, and new manufacturing methods are being developed.

  Conventionally, solder bumps, which are connection terminals with a semiconductor chip of a semiconductor package substrate, are formed by screen printing. In the screen printing method, the openings of the screen plate are aligned and placed on the external connection terminals, which are openings formed by applying a solder resist on the surface of the semiconductor package substrate, and the solder paste is printed with a squeegee. In this method, solder bumps are formed by melting the solder paste by thermal reflow. Solder paste printing is based on variations in the amount of solder paste supplied into the mask opening, variations in the ratio of the amount of paste remaining on the mask side when the mask is pulled away, and the amount of paste remaining on the substrate side, etc. There is a problem that volume variation is large, which leads to variation in bump height, and is not suitable for forming fine and narrow pitch bumps.

  When the volume variation of the solder printed bumps is large and a portion where the solder volume is reduced occurs partially, the height of the connection terminal is lowered, so that there is a problem that the connection cannot be made with the terminal on the semiconductor chip. When a bump having a large solder volume is partially generated, there is a problem that a short circuit occurs due to a combination with an adjacent bump at the time of melting. Therefore, the conventional screen printing method has a strict response to the recent narrowing of the bump pitch, and approaches the limit around 150 μm pitch and cannot cope with the further narrowing of the pitch.

  In recent years, a ball mounting method has been proposed to solve this problem. In this method, solder resist openings are formed by screen printing and flux is printed on the pads, which are connection terminals, and the metal mask openings and solder resist openings are aligned and solder balls are placed in the solder resist openings. It is a method of loading and forming on. Also in this method, the response to the narrowing of the pitch of the semiconductor chip is limited near the 90 μm pitch, and it is difficult to cope with the 50 μm pitch required for the 2.5D package substrate.

  Therefore, recently, as a method for forming a connection terminal of 150 μm or less, a method of forming a protruding electrode by electrolytic pattern plating using a photolithography method has been proposed. In this method, a metal that does not melt like electrolytic solder is formed by electrolytic plating, mainly a cylindrical protruding electrode is formed by electrolytic copper plating, and a small amount of solder is formed on the columnar electrode. A method of connecting a semiconductor chip and a semiconductor package substrate has been developed.

  A method for forming a bump electrode by electrolytic plating will be described. FIG. 3 is an enlarged cross-sectional view of the semiconductor chip connecting protruding electrode of the package substrate. FIG. 3A shows a state before the protruding electrode is formed. A metal electrode pad 203 is patterned on the insulating layer 201, and a solder resist layer or an insulating resin layer 202 is further formed. The metal wiring is formed of copper or the like, and an opening 204 is provided in the solder resist or insulating resin layer 202 so as to expose a part of the electrode pad 203. Next, as shown in FIG. 3B, a metal layer 205 to be a feeding layer for electrolytic plating is formed by a method such as electroless copper plating. Next, a plating resist layer 206 is formed as shown in FIG. 2C, and a resist opening 207 is formed by a method such as photolithography as shown in FIG. The resist opening 207 is formed so as to be aligned with the solder resist opening 204. Next, power is supplied to the power supply layer 205 and electroplating is performed to form metal bumps 209 to be projecting electrodes as shown in FIG. Copper plating or the like is used for electrolytic plating. Further, after various general surface treatments are performed after copper plating, the solder layer 208 is formed by electrolytic plating or other methods. Further, as shown in FIG. 3F, the plating resist layer 206 is removed, and the power supply layer 205 other than the lower portion of the metal bump 209 is removed, thereby completing the protruding electrode.

  According to this method, the height variation of the metal bump, which is a problem in the screen printing method of the solder paste, is solved. In addition, since the volume of solder to be melted is reduced, adjacent bumps are melted and bonded to each other, thereby preventing a short circuit. Therefore, connection terminals corresponding to miniaturization and narrow pitch can be formed. Therefore, it is desirable that the connection terminal with the semiconductor chip in the semiconductor package substrate is a protruding electrode. As a method for forming metal bump electrodes by such a method, a method as shown in Patent Document 1 has also been proposed.

  As described above, in the 2.5D semiconductor package substrate, the built-up layer formed on the second main surface side where the wiring density of the built-up layer on the first main surface on which the semiconductor chip is mounted is connected to the printed wiring board. Therefore, an asymmetric multilayer wiring structure in which the wiring density is higher and the number of wiring layers is larger is desired. Even if an asymmetric layer structure is adopted, the development of a manufacturing method with low warpage, low cost and good yield is desired. Furthermore, a protruding electrode is formed on the connection terminal with the semiconductor chip, and a method for manufacturing a package substrate that can cope with a narrow pitch accompanying an increase in the number of connection terminals has been desired.

JP 2009-295924 A

  The present invention has been made in order to solve the above-described problems, and an object of the present invention is a semiconductor package substrate that is built up on both sides with a core substrate as a center, on which a semiconductor chip is mounted. The semiconductor chip to be mounted with less warping even if it has an asymmetric structure in which the density of the built-up wiring on one side is significantly higher and the number of built-up layers on one side of the high-density wiring is larger than that on the other side The present invention provides a package substrate and a method for manufacturing the same that can be efficiently manufactured at a low cost while being compatible with a narrow pitch.

  One aspect of the present invention for solving the above problems includes a first main surface, a substrate having a second main surface opposite to the first main surface, a substrate having a through hole, and a first main surface. Laminated one or more insulating resin layers on the first main surface, one or more first main circuit wiring circuit layers laminated on the first main insulating resin layer, and laminated on the second main surface And one or more second main surface insulating resin layers, and one or more second main surface wiring circuit layers laminated on one of the second main surface insulating resin layers, The number of wiring circuit layers on the main surface is greater than the number of wiring circuit layers on the second main surface, and the thickness of the wiring circuit layer on the first main surface is greater than the thickness of the wiring circuit layer on the second main surface. In other words, the number of the insulating resin layers on the first main surface is the same as the number of the insulating resin layers on the second main surface.

  The insulating resin layer on the first main surface and the insulating resin layer on the second main surface further have via holes, and the via hole diameter of the insulating resin layer on the first main surface is equal to that of the insulating resin layer on the second main surface. It may be smaller than the via hole diameter.

  Further, the substrate may include a glass substrate on which two or more wiring circuit layers are formed, or a glass fiber reinforced resin substrate.

  The thickness of the metal layer, which is the connection terminal laminated on the outermost layer of the insulating resin layers on the first and second main surfaces, is thicker than the wiring circuit layer on the first main surface side, and the metal on the first main surface side. The layer may be a protruding electrode protruding from the outermost surface of the first main surface.

Another aspect of the present invention is a first insulating resin layer laminating step of laminating and forming an insulating resin layer on a first main surface of a substrate and a second main surface that is a surface opposite to the first main surface. When, a first wiring circuit laminating step the wiring circuit layer formed by lamination of the main surface, the wiring circuit layer of the first main surface which is formed on the first main surface and a second main insulating resin layer formed on the first main surface A protruding electrode is formed on the insulating resin layer on the first main surface by using a second insulating resin layer laminating step for further laminating an insulating resin layer on the insulating resin layer formed on the surface, and a semi-additive method. Forming a wiring circuit layer on the second main surface on the insulating resin layer on the second main surface, wherein the thickness of the wiring circuit layer on the first main surface is greater than the thickness of the wiring circuit layer on the second main surface. This is a thin manufacturing method for a package substrate.

  Further, after the first insulating resin layer laminating step, the wiring circuit laminating step and the second insulating resin layer laminating step may be repeated a plurality of times.

  According to the present invention, a semiconductor package substrate is built-up on both sides with a core substrate as a center, and the built-up wiring density on the side surface on which the semiconductor chip is mounted is remarkably high, and the high-density wiring side surface is on one side. Even with an asymmetrical wiring layer structure that has more built-up layers than the other side, it can be manufactured efficiently and at low cost with low warpage and a reduced pitch of the mounted semiconductor chip. Package substrate and manufacturing method thereof.

Manufacturing process schematic diagram of package substrate according to embodiment of the present invention ((a) schematic diagram of core substrate, (b) schematic diagram of substrate after formation of insulating resin layer and via hole, (c) schematic diagram of substrate after electrolytic plating (D) Schematic diagram of substrate after resist layer removal and seed layer removal) Schematic diagram of manufacturing process of package substrate according to an embodiment of the present invention ((e) Schematic diagram of a substrate in which an insulating resin layer is formed after a third build-up process, (f) Substrate after formation of via holes on the first and second main surfaces (G) Schematic diagram of substrate after resist formation and electrolytic plating) Manufacturing process schematic diagram of package substrate according to an embodiment of the present invention ((h) schematic diagram of package substrate after formation of solder resist, (i) schematic diagram of semiconductor package substrate) Schematic diagram of stacked multichip package ((a) 3D package, (b) 2.5D package via silicon interposer, (c) 2.5D package without silicon interposer) Schematic diagram of projecting electrode connection for semiconductor chip connection ((a) Schematic diagram before projecting electrode formation, (b) Schematic diagram with power feeding layer formed, (c) Schematic diagram after plating resist formation, (d) Resist opening Schematic diagram after formation, (e) Schematic diagram after bump electrode and solder layer formation, (f) Schematic diagram of bump electrode)

  Hereinafter, embodiments of a package substrate and a manufacturing method thereof according to the present invention will be described in detail with reference to FIGS. In the present embodiment, the build-up layer on the first main surface side on which the semiconductor chip is mounted is four layers, the core substrate is four layers, and the second main surface (BGA side) is the connection terminal side with the printed wiring board. The up layer will be described using a package substrate having a one-layer 4-4-1 layer structure. This embodiment is an example of the present invention, and this embodiment does not limit the layer structure of the package substrate of the present invention.

  First, a core substrate 301 shown in FIG. 1A is prepared. The core substrate 301 is a substrate produced by a conventional method for manufacturing a printed wiring board, that is, a glass fiber reinforced epoxy resin in which a through hole 302 as a through hole, an interlayer conduction via 303 and a wiring circuit 304 are formed. A substrate may be used. Alternatively, a substrate in which through holes and circuits are formed on a glass substrate may be used. As the core substrate, a substrate having a circuit pattern as a wiring circuit layer formed on the front and back of the substrate may be used, or a multilayer circuit in which a plurality of wiring circuit layers are formed may be formed. It is not limited by the form. The total thickness of the core substrate is preferably 0.05 mm or more and 3 mm or less. If the thickness is less than 0.05 mm, it may be difficult to manufacture because the conveyance becomes difficult. Further, since the rigidity is lost when the package substrate is used, a problem of warpage is likely to occur. When the thickness exceeds 3 mm, the package substrate is too thick and is not suitable for downsizing of electronic devices. More preferably, the thickness is 0.1 mm or more and 2 mm or less. The circuit metal of the core substrate is not limited in the present embodiment, but copper and its alloys are desirable because of its conductivity and easy formation.

  Subsequently, as described in FIG. 1A (b), the number of insulating resin layers 3115 is laminated on the upper and lower surfaces of the core substrate 301. For the insulating resin layer 305, an epoxy-phenol resin, a photosensitive polyimide resin, a benzocyclobutene resin, a polybenzoxazole resin, a cycloolefin resin, or a modified product thereof can be used. Furthermore, it may be a photosensitive or non-photosensitive resin, and may have a reinforced resin structure made of glass fiber or engineering plastic fiber as necessary, and is appropriately filled with an inorganic or organic filler. Also good. The kind of insulating resin is not limited by this embodiment.

  In the package substrate according to the present embodiment, the insulating resin layer 305 is formed on the front and back surfaces of the core substrate 301 so as to have the same thickness as shown in FIG. 1A (b). The thickness of the resin layer to be formed is preferably 3 μm to 40 μm from the surface of the metal wiring circuit on the core substrate 301. If it is thinner than 3 μm, there is a possibility that insulation reliability between layers cannot be secured. If the insulating resin layer 305 is thicker than 40 μm, a fine via hole cannot be formed because it is too thick, causing a problem that a fine wiring layer cannot be formed. More preferably, the insulating resin layer 305 is formed with a thickness of 5 μm to 15 μm. According to the present embodiment, the insulating resin layer 305 is formed on the first main surface and the second main surface so as to have the same thickness. It has been found by experiments of the present inventors that the warpage of the package substrate is due to the residual stress when the front and back resins are cured. Therefore, at least in the step of forming the insulating resin layer 305, it is necessary to form a resin layer having the same thickness on the front and back and perform a curing process simultaneously on the front and back. The curing treatment may be heat treatment or UV curing, and the treatment is appropriately performed at an appropriate stage depending on the resin.

  As a method for forming the insulating resin layer 305, laminating, vacuum laminating, and vacuum pressing can be applied as long as they are film-like resins. If it is liquid, it can be selected from slit coating, curtain coating, die coating, spray coating, electrostatic coating, inkjet coating, gravure coating, screen printing, gravure offset printing, spin coating and doctor coating. The method for forming the insulating resin layer 305 is not limited by this embodiment.

  A state in which the via 306 is formed only on the first main surface after the insulating resin layer 305 is formed on the front and back surfaces of the package substrate according to the present embodiment is shown in FIG. The via 306 is formed by laser processing, or may be formed by photolithography in the case of a photosensitive insulating resin. Laser processing is preferably a UV laser or excimer laser because a small diameter via can be formed. The package substrate of the present embodiment has a multi-layered structure in which the wiring density of the built-up layer on the first main surface is high. In order to make the wiring layer of the first main surface high-layered, it is first necessary to form vias only on the first main surface. In the manufacturing method of the semiconductor package substrate according to the present embodiment, the process of forming the via 306 and the wiring only on one side is performed at least once in the build-up process. The via diameter according to the present embodiment is desirably 5 μm or more and 40 μm or less. If the thickness is smaller than 5 μm, it is difficult to form, and it is difficult to ensure via connection reliability by thermal cycling. When the via diameter is larger than 40 μm, the wiring density of the built-up wiring layer on the first main surface cannot be made fine and high. A more preferable via diameter is 10 μm or more and 20 μm or less. After the via 306 is formed, a cleaning process inside the via 306 is performed by desmearing by immersion in a permanganate solution or by plasma treatment.

  Subsequently, as shown in FIG. 1A (c), after forming a seed layer made of metal on at least the first main surface side or both surfaces on the insulating resin layer 305, a resist layer 307 is formed on both surfaces. Further, a circuit pattern is formed on the resist layer 307 only on the first main surface by photolithography. A resist layer 307 is formed on the entire surface of the second main surface without forming a circuit pattern. Subsequently, the wiring circuit 308 is formed only on the first main surface side by electrolytic plating (semi-additive method) using the seed layer. The thickness of the seed layer in this embodiment is preferably 0.05 μm or more and 1 μm or less. If the thickness is less than 0.05 μm, the resistance of the seed layer becomes high, so that it is impossible to uniformly energize the substrate surface in the electrolytic plating process, and the wiring circuit 308 having a uniform height cannot be formed in the substrate surface. In addition, the seed layer may be dissolved before being immersed in the electrolytic plating solution and energized, resulting in a problem that a circuit cannot be formed. On the other hand, as a problem when the seed layer becomes thick, the circuit pattern may be etched at the same time in the subsequent seed layer removal process, and thus the circuit may be thinned. If it is too thick, the wiring circuit itself is lost or peeled off, resulting in a problem that the wiring cannot be formed. As a result of investigation by the present inventors, when the seed layer thickness is larger than 1 μm, it is impossible to form a fine wiring with L / S = 5 μm / 5 μm or less. Therefore, it is desirable that it is 0.05 μm or more and 1 μm or less. The seed metal is selected from copper, nickel, titanium, gold, and chrome, but is not limited by this embodiment. The seed layer forming method can be selected from vapor deposition, sputtering, and electroless plating. A resist layer 307 is formed on the seed thus formed. The formation of the resist layer 307 may be either a liquid resist or a dry film resist. As a method for forming the resist layer 307, a known method is appropriately used. The thickness of the resist layer 307 for forming the internal circuit on the first main surface side is preferably 15 μm or less. When it is thicker than 15 μm, it becomes impossible to form fine wiring with L / S = 5 μm / 5 μm or less. The resist pattern forming method can be formed by known photolithography. Further, the thickness of the wiring circuit 308 on the first main surface side formed by electrolytic plating is desirably 10 μm or less. If it is thicker than 10 μm, at least the thickness of the resist pattern is required to be 10 μm or more, so that the resolution of the resist cannot be secured, and it becomes impossible to form a fine circuit of L / S = 5 μm / 5 μm or less. Therefore, the circuit thickness is desirably 10 μm or less.

  Subsequently, the resist layer 307 on the front and back sides of the substrate shown in FIG. 1A in which the circuit pattern is formed only on the first main surface is peeled off, and then the unnecessary seed layer on the front and back sides is removed by an etching process. A substrate ((d) in FIG. 1A) having a built-up wiring layer formed only on the main surface is obtained. A wiring circuit 308 is formed only on the first main surface of the substrate.

  As described above, the formation of the insulating resin layer 305 on both surfaces of the substrate and the circuit formation only on the first main surface are repeated three times in the same manner, and the insulating resin layer 305 is further laminated to describe (e) in FIG. 1B. A built-up multilayer wiring board having an asymmetric layer structure of 3-4-0 is prepared. As a result, the number of insulating resin layers on the first main surface is equal to the number of insulating resin layers on the second main surface. According to the method according to the present embodiment, the total thickness of the built-up wiring layer on the first main surface side of the multilayer wiring board and the built-up of the second main surface even in an asymmetric layer structure in which the number of built-up layers is significantly biased. Since the thickness of the wiring layer is substantially equal, the amount of cure shrinkage is balanced, so that package warpage can be minimized. Furthermore, since the resin etching process such as desmear or plasma process is performed only once for each insulating resin layer, the resin on the surface of the insulating resin layer is not deteriorated. Therefore, a package substrate having excellent insulation reliability can be created.

  Subsequently, as shown in FIG. 1B (f), a small diameter via 306 having a diameter of 5 μm or more and 40 μm or less is formed on the first main surface side, and the second main surface side is more than the via formed on the first main surface. A via 309 having a large diameter is formed. In the structure of the package substrate according to the present embodiment, the via 309 formed on the second main surface is formed to penetrate to a predetermined via receiving pad surface through a plurality of insulating resin layers. In FIG. 1B, (f) describes four layers as an example, but according to the present embodiment, it is characterized by penetrating a plurality of layers, and the total number is not limited by this example. The diameter of the via 309 on the second main surface side is desirably larger than the diameter of the first main surface side via 306 and has a via diameter of 20 μm or more and 100 μm or less. When the thickness is smaller than 20 μm, there is a possibility that the via receiving pad cannot be penetrated depending on the thickness of the insulating resin layer laminated on the second main surface. When the via diameter is larger than 100 μm, the metal plating may not be filled in the via because the diameter is too large in the subsequent electrolytic copper plating process. Therefore, it is desirable to be 20 μm or more and 100 μm or less. Although it is a via formation method of the 2nd principal surface, it is desirable that it is laser processing. The laser can be selected from a carbon dioxide laser and an ultraviolet laser. According to the semiconductor package substrate according to the present embodiment, a fine circuit having L / S = 5 μm / 5 μm or less may be formed only on one side, and the process can be simplified. In particular, it is possible to eliminate the pattern exposure process on the back surface several times, so that a fine circuit can be efficiently manufactured with a high yield. Subsequently, after the via is formed, a cleaning process inside the via is performed by desmearing by immersion in a permanganic acid solution or by plasma processing. Subsequently, a seed metal layer is formed on the surface of the insulating resin layer 305 by electroless plating or sputtering film formation. Although the thickness of the seed metal layer is not defined by the present embodiment, it is preferably 0.05 μm or more and 1 μm or less as in the above.

  Subsequently, in (g) of FIG. 1B, a resist layer 307 is formed on the seed metal layer, a pattern is formed by photolithography, and then electroplating is performed, and the first main surface has protrusions that are connection terminals to the semiconductor chip. In the case of the electrode 310, the second main surface, a substrate on which a BGA pad and / or a wiring circuit 311 (hereinafter referred to as a wiring circuit 311) serving as a connection terminal with a printed wiring board is described. As shown in FIG. 1B (g), according to the manufacturing method according to the present embodiment, the wiring circuit 311 formed on the second main surface is rougher than the wiring circuit 308 formed on the first main surface side. The thickness of the wiring circuit 308 layer on the main surface is thinner than the thickness of the wiring circuit 311 layer on the second main surface. Also, the number of layers of the wiring circuit 308 on the first main surface is larger than the number of layers of the wiring circuit 311 layer on the second main surface. Since the diameter of the via 309 is also large, the plating thickness must be increased in order to fill the via with a plating film. Although depending on the diameter of the via 309, when the via diameter is 20 μm or more and 100 μm or less, the thickness of the wiring circuit 311 on the second main surface is preferably 10 μm or more and 40 μm or less. More preferably, it is 10 μm or more and 25 μm or less. On the other hand, the protruding electrode 310 that is a connection terminal to the semiconductor chip can absorb the expansion and contraction due to the thermal shock of the substrate as the protruding height is higher. The thickness of the protruding electrode 310 is preferably thicker than the wiring circuit 308 formed on the first main surface side, and more preferably, the thickness is the same as the circuit height with the second main surface. Since it can form simultaneously, it is suitable. That is, the protruding electrode 310 formed on the first main surface is desirably 10 μm or more and 40 μm or less. According to the present embodiment, the projecting electrode 310 on the first main surface that requires a thick plating thickness and the circuit on the second main surface are formed at the same time, which is efficient. Further, a surface treatment layer may be formed on the bump electrode 310 or the BGA pad in the state after the electrolytic plating shown in FIG. As the type of surface treatment, Ni—Au plating, Ni—Pd—Au plating, OSP, tin plating, Sn—Ag plating, molten solder plating, or the like may be performed. Further, a solder layer may be formed after the surface treatment. Conventionally known techniques can be used for the surface treatment and the solder forming method.

  Subsequently, after removing the resist pattern 307 shown in FIG. 1B (g), the unnecessary metal seed layer is removed by etching. Further, a solder resist layer is formed on the front and back of the substrate in the step (h) of FIG. 1C, and a solder resist pattern 314 is formed by photolithography, whereby the package substrate according to this embodiment is manufactured.

  A schematic diagram of the semiconductor package substrate in which the semiconductor chip 312 is formed on the bump electrode 310 and the solder ball 313 is formed on the BGA pad is shown in FIG.

Example 1
Examples of the present invention are shown below. In Example 1, a package substrate having a 4-4-1 layer structure shown in FIG. 1C (h) was manufactured. Example 1 will be described based on the steps (a) to (d) in FIG. 1A. First, an insulating resin of 15 μmt is laminated by vacuum lamination on both surfaces of the core substrate 301 on which a four-layer wiring circuit manufactured by a conventional printed wiring board manufacturing method is formed, and is then thermally cured. Layer 305 was formed. Subsequently, a via 306 with a via diameter of 20 μm was formed only on the first main surface side of the package substrate by a UV-YAG laser. At this time, no via hole for interlayer connection is formed in the resin on the second main surface side. Subsequently, the substrate was immersed in an alkaline permanganate bath to remove laser smear, and an electroless plating layer was formed at 0.5 μm. Subsequently, a dry film resist having a thickness of 10 μm was formed on the first and second main surfaces by a laminating method. Subsequently, only the first main surface was exposed with a stepper exposure machine using a photomask having a minimum circuit pattern of L / S = 5 μm / 5 μm. The entire surface of the dry film resist on the second main surface was exposed to form a resist layer 307 on the entire surface of the second main surface. Subsequently, spray development was generated with a 1% sodium carbonate solution. Furthermore, circuit wiring was prepared with a circuit thickness of 7 μm by electrolytic plating.

  Next, the production of the package substrate of Example 1 will be described based on the steps (e) to (g) of FIG. 1B and the step (h) of 1C. As shown in FIG. 1B (e), the build-up process was repeated three times until the fourth resin laminate was completed. Subsequently, as described in FIG. 1B (f), a 20 μm via 306 is formed on the first main surface using a UV-YAG laser, and the second main surface is formed on the first main surface using a laser processing machine. A via 309 was formed with a via diameter. Subsequently, it was immersed in a permanganic acid solution, and after removing smear, electroless plating was formed to a thickness of 1 μm. Further, as shown in FIG. 1B (g), a dry film resist was formed at 25 μm on both sides. A protruding electrode pattern was formed on the first main surface side with a diameter of 30 μm and a pitch of 50 μm, and a BGA pad and a circuit pattern were formed on the second main surface. Subsequently, electrolytic copper plating was formed on the front and back surfaces with a thickness of 20 μm. Subsequently, Sn—Ag solder plating was performed at a height of 3 μm after electrolytic Ni—Ag plating on both surfaces. After removing the resist, the seed layer was removed by etching. Subsequently, after forming a solder resist as described in FIG. 1C (h), an opening was formed by photolithography.

(Comparative Example 1)
Comparative Example 1 is an example in which only one layer is formed without laminating the four-layer resin on the second main surface. After laminating an insulating resin of 15 μm on both surfaces of the core substrate, vias are formed with a thickness of 20 μm only on the first main surface, and desmear treatment, electroless plating, and photoresist patterning are performed. A circuit is formed on the first main surface, and a resist layer is formed on the second main surface by exposing the resist entirely. After removing the resist and electrolytic plating, the seed layer is removed. Further, a resin layer was formed only on the first main surface, and no resin was formed on the second main surface, and the same procedure as in Example 1 was performed. The outermost layer was formed in the same manner as in Example 1.

(Comparative Example 2)
Comparative Example 2 is an example in which solder bumps are formed by a conventional ball mounting method without forming protruding electrodes on the first main surface. The solder bumps were formed by mounting solder balls having a pitch of 50 μm and a diameter of 30 μm by a ball mounting method.

(Comparative Example 3)
Comparative Example 3 is an example of a semiconductor package substrate in which a wiring having a minimum pattern width of L / S = 5 μm / 5 μm is also formed on the second main surface. The layer structure has a contrasting layer structure of 2-4-2. The wiring formed on the second main surface was prepared in the same process as in Example 1 except that the wiring was formed with the same construction method and wiring width as the first main surface.

  Table 1 shows the results of the semiconductor package substrates according to Example 1 and the comparative example.

  In Example 1, the production yield can be improved. Since Comparative Example 2 was the same process as Example 1 except that no protruding electrode was formed on the first main surface, the yield was good. In Comparative Example 1, since desmear treatment was performed four times for one resin layer on the second main surface, peeling of the wiring circuit and the BGA pad was observed, resulting in a low yield. Comparative Example 3 is a structure in which the built-up layer configuration of the first and second main surfaces is symmetric, and has a configuration in which fine wiring is formed on both sides. Comparative Example 3 is due to the contact of the apparatus transport conveyor. The yield is low due to the observation of wiring peeling.

  As a result of evaluation of the amount of warpage of the package, Example 1 and Comparative Examples 2 and 3 show good results because the total thickness of the resin layer formed on the front and back sides is symmetric. When the total layer thickness was asymmetrical, the warpage was large and was as large as 320.1 μm. Note that a minus sign indicates a warping direction that protrudes upward when the first main surface is disposed on the upper surface, and a plus sign indicates a warping direction that protrudes downward.

  Although the primary mounting evaluation shows a pass rate when the temperature cycle test is performed after mounting the Teg chip, Example 1 showed a good result, but Comparative Example 1 could not be mounted due to package warpage. In Comparative Example 2, since the solder bump diameter manufacturing method on the first main surface was the ball mounting method, shorts occurred frequently immediately after mounting the Teg chip, resulting in NG. As a result of failure analysis, it has been found that this is caused by the soldering between the solders causing a short circuit.

The secondary mounting evaluation indicates a pass rate after a semiconductor package substrate is mounted on a printed wiring board and a temperature cycle test is performed. Example 1 and Comparative Example 2 having a similar structure showed good results.
Comparative Example 1 has a low pass rate due to large package warpage and large deformation of the temperature cycle. Regarding Comparative Example 3, there was no problem with the BGA connection part of the secondary mounting, but the stress concentration due to the difference in thermal expansion coefficient between the printed wiring board and the semiconductor package substrate was 20 μm, and the stress concentration on the fine via bottom was small The result was aggravated due to what happened.

  As a result of Example 1 and the comparative example, the semiconductor package substrate according to the present invention can contribute to miniaturization and high reliability of the semiconductor chip. That is, it is possible to efficiently form a fine multilayer wiring required only on the first main surface with a high yield. Further, by forming the relatively thick wiring as before on the second main surface, it is possible to ensure the secondary mounting reliability. Although the total number of wirings on the front and back sides is asymmetric, the total thickness of the laminated resin is symmetric, so that warpage can be effectively suppressed. Therefore, it is possible to prevent a decrease in yield due to a decrease in mountability due to warpage, and further a decrease in reliability.

  As described above, according to the present invention, it is a semiconductor package substrate that is built up on the front and back with the core substrate as the center, and the built-up wiring density on the side surface on which the semiconductor chip is mounted is remarkably high, Even with an asymmetrical wiring layer structure where the number of built-up layers on one side of the high-density wiring side is greater than that on the other side, the yield is low while warping and narrowing the pitch of the mounted semiconductor chip. It is possible to provide a package substrate that can be efficiently manufactured at low cost and a manufacturing method thereof.

  The present invention is applicable to package substrates for mounting various semiconductor chips.

101 Memory chip 102 TSV; Through Silicon Via
103 Bump 104 Package substrate 105 Logic chip 106 Silicon interposer 201 Insulating resin layer 202 Insulating resin layer or solder resist 203 Electrode pad 204 Solder resist or insulating resin opening 205 Metal layer 206 Resist layer 207 Resist opening 208 Solder layer 209 Metal bump 301 Core Substrate 302 Through-hole 303 Via of core substrate 304 Wiring circuit of core substrate 305 Insulating resin layer 306 Via hole formed on first main surface 307 Resist layer 308 Wiring circuit formed on first main surface 309 formed on second main surface Via hole 310 Protruding electrode 311 BGA pad and / or wiring circuit on second main surface 312 Semiconductor chip 313 Solder ball 314 Solder resist pattern

Claims (6)

A substrate having a first main surface, a second main surface opposite to the first main surface, and a through hole;
One or more insulating resin layers on the first main surface laminated on the first main surface;
One or more first main surface wiring circuit layers laminated on the first main surface insulating resin layer;
One or more second main surface insulating resin layers laminated on the second main surface;
One or more second main surface wiring circuit layers laminated on any of the second main surface insulating resin layers,
The number of wiring circuit layers on the first main surface is greater than the number of wiring circuit layers on the second main surface,
The thickness of the wiring circuit layer on the first main surface is smaller than the thickness of the wiring circuit layer on the second main surface,
The number of insulating resin layers on the first main surface is equal to the number of insulating resin layers on the second main surface,
Package substrate.   The insulating resin layer on the first main surface and the insulating resin layer on the second main surface further have via holes, and the via hole diameter of the insulating resin layer on the first main surface is the insulating resin on the second main surface. The package substrate according to claim 1, wherein the package substrate is smaller than a via hole diameter of the layer.   The package substrate according to claim 1, wherein the substrate includes a glass substrate on which two or more wiring circuit layers are formed, or a glass fiber reinforced resin substrate. The thickness of the metal layer which is a connection terminal laminated on the outermost layer of the insulating resin layer on the first and second main surfaces is thicker than the wiring circuit layer on the first main surface side,
4. The package substrate according to claim 1, wherein the metal layer on the first main surface side is a protruding electrode protruding from the outermost surface of the first main surface. A first insulating resin layer laminating step of laminating and forming an insulating resin layer on a first main surface of the substrate and a second main surface opposite to the first main surface;
A wiring circuit laminating step of laminating forming the wiring circuit layer of the first main surface in the insulating resin layer formed on the first main surface,
A second insulating resin layer laminating step of further laminating an insulating resin layer on the wiring circuit layer of the first main surface formed on the first main surface and the insulating resin layer formed on the second main surface ;
Forming a protruding electrode on the insulating resin layer on the first main surface and forming a wiring circuit layer on the second main surface on the insulating resin layer on the second main surface using a semi-additive method. ,
The method of manufacturing a package substrate , wherein a thickness of the wiring circuit layer on the first main surface is thinner than a thickness of the wiring circuit layer on the second main surface .   6. The method for manufacturing a package substrate according to claim 5, wherein the wiring circuit laminating step and the second insulating resin layer laminating step are repeated a plurality of times after the first insulating resin layer laminating step.

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