JP2016225331A - Wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board capable of improving reliability by preventing disconnection of the wiring of a wiring layer.SOLUTION: A wiring board 1 of the present invention comprises a laminated portion and a solder resist layer. In the laminated portion, a mounting region 23 having a plurality of corner portions 61 is set on the surface of the uppermost resin insulating layer. The solder resist layer is formed on the back surface of the lowermost resin insulating layer 42 and has openings 47 at a plurality of locations. The laminated portion has a structure in which a wiring layer 43 is disposed between a plurality of resin insulating layers, and at least one resin insulating layer is an inorganic fiber containing layer. Among wiring 81 of the wiring layer 43 arranged between the lowermost resin insulating layer 42 and the lowermost inorganic fiber containing layer and disposed in a lower region A1 including a part just under the corner portion 61, a part of the wiring 81 disposed immediately above the opening edge of the opening 47 is a wide portion 82.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a wiring board including a laminated portion having a structure in which a plurality of resin insulating layers are laminated and a solder resist layer formed on the back surface of the lowermost resin insulating layer.

  In recent years, with the miniaturization of electrical equipment and electronic equipment, miniaturization and high density are also required for wiring boards mounted on these equipment. As such a wiring board, for example, as shown in FIGS. 9 and 10, build-up layers 104 formed by alternately laminating wiring layers 102 and resin insulating layers 103 are provided on both surfaces of the core board 101. A wiring substrate 100 is known (see, for example, Patent Document 1). An electronic component such as an IC chip 111 is mounted on the mounting region 110 set on the surface of the uppermost resin insulating layer 103, and an underfill material 112 is formed in the gap between the IC chip 111 and the wiring substrate 100. Filled. As a result, the interface between the wiring substrate 100 and the IC chip 111 is fixed to each other in a sealed state. On the back surface of the lowermost resin insulating layer 103, solder resist layers 107 having openings 106 for connecting terminals 105 are formed at a plurality of locations. On the surface of the connection terminal 105, a plurality of solder bumps 108 for electrical connection with a mother board (not shown) are disposed. The wiring board 100 is mounted on the mother board by the solder bumps 108.

Japanese Patent No. 4267660 (FIG. 3 etc.)

  Incidentally, the IC chip 111 is generally formed using a semiconductor material (for example, silicon) having a thermal expansion coefficient of about 2.0 ppm / ° C. to 5.0 ppm / ° C. On the other hand, the wiring board 100 is formed using a material having a considerably larger thermal expansion coefficient than that of the semiconductor material, for example, a resin material of 10.0 ppm / ° C. or higher. Therefore, when the IC chip 111 is mounted on the wiring board 100, stress is likely to occur due to the difference in thermal expansion coefficient between the IC chip 111 and the wiring board 100. Furthermore, even when the wiring board 100 is mounted on a mother board, stress may be generated due to a difference in thermal expansion coefficient between the wiring board 100 and the mother board.

  These stresses are concentrated on the lower region A3 including the region immediately below the corner portion 113 of the mounting region 110, particularly on the opening edge of the opening portion 106 of the solder resist layer 107. As a result, the crack 114 starting from the opening edge of the opening 106 is generated, and the generated crack 114 progresses to the inner layer side, so that the wiring of the wiring layer 102 disposed immediately above the opening edge is electrically disconnected. Problems are likely to occur. As a result, since the yield of the wiring board 100 is lowered, there is a problem that the predetermined reliability required for the wiring board 100 cannot be given.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a wiring board capable of improving reliability by preventing disconnection of wiring in a wiring layer.

  As means (means 1) for solving the above-described problems, a structure in which a plurality of resin insulation layers are stacked is provided, and a mounting region in which a semiconductor chip can be mounted is set on the surface of the uppermost resin insulation layer. And a solder resist layer formed on the back surface of the lowermost resin insulation layer and having openings for connecting terminals at a plurality of locations, and the mounting region is from the thickness direction of the stacked portion. A wiring board having a shape having a plurality of corner portions when viewed, wherein the stacked portion has a structure in which a wiring layer is disposed between the plurality of resin insulation layers, At least one of the resin insulating layers is an inorganic fiber-containing layer including an inorganic fiber layer, and is disposed between the lowermost resin insulating layer and the lowermost inorganic fiber-containing layer, and the corner portion. Located in the lower area including directly under Among the wirings of the wiring layer, a part of the wiring arranged immediately above the opening edge of the opening is a wide part formed wider than a part continuous with a part of the wiring. There is a wiring board.

  Therefore, according to the structure described in the means 1, the wiring of the wiring layer disposed between the lowermost resin insulating layer and the lowermost inorganic fiber-containing layer and disposed in the lower region including directly under the corner portion Among them, a part of the wiring arranged just above the opening edge of the opening of the solder resist layer is a wide portion. Therefore, cracks starting from the opening edge of the opening occur, and even if the generated crack reaches the wiring arranged immediately above the opening edge, the crack reaches the wide part that is the reinforcing part, It becomes difficult to cause a problem of electrical disconnection. As a result, since the yield of the wiring board is improved, the reliability of the wiring board can be improved.

  In addition, the wiring of the wiring layer disposed between the lowermost resin insulating layer and the lowermost inorganic fiber-containing layer and disposed in the lower region including immediately below the corner portion is directly above the opening edge of the opening. May be laid to avoid. In this way, cracks starting from the opening edge of the opening are generated, and the risk of the generated crack reaching the wiring arranged immediately above the opening edge is reduced, so that the wiring is electrically disconnected. Is less likely to occur. Also in this case, since the yield of the wiring board is improved, the reliability of the wiring board can be improved.

  The laminated portion constituting the wiring board has a structure in which a plurality of resin insulating layers are laminated. The resin insulation layer can be appropriately selected in consideration of insulation, heat resistance, moisture resistance, and the like. Specific examples of the material for forming the resin insulation layer include thermosetting resins such as epoxy resins, phenol resins, urethane resins, silicone resins, and polyimide resins, cycloolefin resins, polycarbonate resins, acrylic resins, polyacetal resins, and polypropylene resins. A thermoplastic resin etc. are mentioned. In addition, at least one of the plurality of resin insulating layers is an inorganic fiber-containing layer including an inorganic fiber layer. Preferable examples of the inorganic fiber constituting the inorganic fiber layer include glass fiber (glass cloth), ceramic fiber, metal fiber, paper and the like.

  In addition, a semiconductor chip can be mounted in a mounting region set on the surface of the uppermost resin insulating layer. Examples of the semiconductor chip (IC chip) include a DRAM (Dynamic Random Access Memory) and an SRAM (Static Random Access Memory).

  Note that the laminated portion has a structure in which a wiring layer is disposed between a plurality of resin insulating layers. Here, the wiring layer can be formed using various conductive metals such as copper, silver, gold, platinum, nickel, titanium, aluminum, and chromium. It is good to be configured as. As a method for forming the wiring layer, a known method such as a subtractive method, a semi-additive method, or a full additive method is employed. Specifically, for example, techniques such as etching of copper foil, electroless copper plating, and electrolytic copper plating are applied. It is also possible to form a wiring layer by etching after forming a thin film by a technique such as sputtering or CVD, or to form a wiring layer by printing a conductive paste or the like.

  Of the wiring of the wiring layer disposed between the lowermost resin insulating layer and the lowermost inorganic fiber-containing layer and disposed in the lower region including directly under the corner portion, the opening edge of the opening portion A part of the wiring arranged immediately above is a wide part formed wider than a part continuing to a part of the wiring. Here, the line width of the wide portion is preferably not less than 2 times and not more than 10 times that of the portion continuing to the wide portion. If the line width of the wide portion is less than twice that of the portion that continues to the wide portion, the wide portion (part of the wiring) may be electrically disconnected when the crack reaches the wide portion. . On the other hand, if the line width of the wide portion is larger than 10 times that of the portion continuing to the wide portion, the wiring formation area of the wiring layer becomes large, and the wiring board is likely to be enlarged.

  The solder resist layer constituting the wiring board is formed on the back surface of the lowermost resin insulating layer, and has openings for connection terminals at a plurality of locations. The “solder resist layer” is made of a resin having insulating properties and heat resistance, and is essentially a protective film that prevents the adhesion of solder to the conductor by covering the conductor. In the present invention, it is preferable to use a solder resist layer made of a resin having at least photosensitivity, and specifically, use of an epoxy resin or a polyimide resin is preferable.

  Further, it is preferable that a connection terminal exposed from the opening is formed on the back surface of the lowermost resin insulating layer, and the thickness of the connection terminal is larger than the thickness of the wiring layer. If it does in this way, progress of a crack from the opening end of an opening to the inner layer side of a wiring board can be controlled.

The top view which shows the wiring board in 1st Embodiment. Explanatory drawing which shows the relationship between a wiring board and an IC chip. AA sectional view taken on the line AA of FIG. The principal part top view which shows the arrangement | positioning aspect of the wiring of the wiring layer in a downward area | region. The schematic sectional drawing which shows the process of forming a resin insulating layer on the 1st main surface and the 2nd main surface. The schematic sectional drawing which shows the process of forming the 2nd resin insulation layer. The schematic sectional drawing which shows the wiring board in 2nd Embodiment. The principal part top view which shows the arrangement | positioning aspect of the wiring of the wiring layer in a downward area | region. The top view which shows the wiring board in a prior art. BB sectional drawing of FIG.

[First Embodiment]
Hereinafter, a first embodiment in which the wiring substrate 1 of the present invention is embodied will be described in detail with reference to the drawings.

  As shown in FIGS. 1 to 4, the wiring board 1 of this embodiment is a wiring board for mounting the IC chip 21. The laminated portion 10 constituting the wiring substrate 1 includes a substantially rectangular plate-shaped core substrate 11 and a first buildup layer 30 provided on the first main surface 12 (the upper surface in FIGS. 2 and 3) of the core substrate 11. And a second buildup layer 40 provided on the second main surface 13 (the lower surface in FIGS. 2 and 3) of the core substrate 11.

  The core substrate 11 of the present embodiment has a substantially rectangular shape in plan view of 40 mm length × 40 mm width × 0.8 mm thickness (= 800 μm). The core substrate 11 is a resin insulating layer that becomes a glass cloth-containing layer (inorganic fiber-containing layer) made of a thermosetting resin (epoxy resin) including a glass cloth (inorganic fiber layer). The core substrate 11 has a thermal expansion coefficient in the plane direction (XY direction) of about 10 to 30 ppm / ° C. (specifically, 18 ppm / ° C.). In addition, the thermal expansion coefficient of the core board | substrate 11 says the average value of the measured value between 0 degreeC-glass transition temperature (Tg).

  As shown in FIG. 3, a through-hole conductor 14 is formed in the core substrate 11 so as to penetrate the first main surface 12 and the second main surface 13. The through-hole conductor 14 connects and connects the first main surface 12 side and the second main surface 13 side of the core substrate 11. Note that the inside of the through-hole conductor 14 is filled with a closing body 15 such as an epoxy resin. The first main surface 12 of the core substrate 11 is patterned with a first wiring layer 16 made of copper having a thickness of 15 μm, and the second main surface 13 of the core substrate 11 is also made of copper having a thickness of 15 μm. The second wiring layer 17 is patterned. A part of each wiring layer 16, 17 is electrically connected to the through-hole conductor 14.

  As shown in FIGS. 2 and 3, the first buildup layer 30 is composed of two resin insulating layers 31 and 32 made of a thermosetting resin (epoxy resin) having a thickness of 30 μm and copper having a thickness of 15 μm. The wiring layers 33 are stacked alternately. Therefore, the thickness (800 μm) of the core substrate 11 that becomes the inorganic fiber-containing layer is larger than the thickness of the resin insulating layers 31 and 32 that do not become the inorganic fiber-containing layer. The first buildup layer 30 includes the first wiring layer 16 disposed between the core substrate 11 and the resin insulating layer 31, and the wiring layer 33 disposed between the resin insulating layer 31 and the resin insulating layer 32. It has an arranged structure. In the present embodiment, the thermal expansion coefficient of the resin insulating layers 31 and 32 in a completely cured state is about 10 to 60 ppm / ° C. (specifically, about 20 ppm / ° C.). In addition, the thermal expansion coefficient of the resin insulating layers 31 and 32 means an average value of measured values between 30 ° C. and the glass transition temperature (Tg).

  As shown in FIG. 3, via conductors 34 formed by copper plating are provided in the resin insulating layers 31 and 32, respectively. Further, terminal pads 35 made of copper having a thickness of 15 μm are formed in an array at a plurality of locations on the surface of the second layer (uppermost layer) resin insulation layer 32. The terminal pad 35 is electrically connected to the wiring layer 33 via the via conductor 34. Further, the surface of the resin insulating layer 32 is almost entirely covered with a solder resist layer 36. In the solder resist layer 36, openings 37 for exposing the central portion of the terminal pad 35 are formed at a plurality of locations. Therefore, the outer peripheral portion of the terminal pad 35 is covered with the solder resist layer 36. A plurality of solder bumps 51 are disposed on the surface of the terminal pad 35.

  As shown in FIGS. 1 to 3, each solder bump 51 is electrically connected to the surface connection terminal 22 of the IC chip 21 (semiconductor chip). The IC chip 21 having a function as an MPU is a plate-like object having a rectangular shape in plan view of 13.0 mm in length, 16.0 mm in width, and 0.9 mm in thickness, and has a thermal expansion coefficient of about 3 to 4 ppm / ° C. It is made of silicon (specifically about 3.5 ppm / ° C.). Circuit elements (not shown) are formed on the back surface side surface of the IC chip 21. A plurality of surface connection terminals 22 are provided in a grid pattern on the back surface side of the IC chip 21. Note that an area including the terminal pads 35 and the solder bumps 51 is a mounting area 23 on which the IC chip 21 can be mounted. The mounting area 23 is set on the surface of the uppermost resin insulation layer 32. The mounting area 23 is a rectangular area having a length of 13.0 mm and a width of 16.0 mm having four corner portions 61 when viewed from the thickness direction of the stacked portion 10.

  As shown in FIG. 3, the gap between the wiring substrate 1 and the IC chip 21 is filled with an underfill material 71 made of an epoxy resin. As a result, the wiring board 1 and the IC chip 21 are fixed to each other with the interface sealed.

  As shown in FIGS. 2 and 3, the second buildup layer 40 has substantially the same structure as the first buildup layer 30 described above. That is, the second buildup layer 40 is formed by alternately laminating two resin insulating layers 41 and 42 made of a thermosetting resin (epoxy resin) having a thickness of 30 μm and a wiring layer 43 made of copper having a thickness of 15 μm. It has the structure. Therefore, the thickness (800 μm) of the core substrate 11 that becomes the inorganic fiber-containing layer is larger than the thickness of the resin insulating layers 41 and 42 that do not become the inorganic fiber-containing layer. In the second buildup layer 40, the second wiring layer 17 is disposed between the core substrate 11 and the resin insulating layer 41, and the wiring layer 43 is disposed between the resin insulating layer 41 and the resin insulating layer 42. It has an arranged structure. In the present embodiment, the coefficient of thermal expansion of the resin insulating layers 41 and 42 in a completely cured state is about 10 to 60 ppm / ° C. (specifically, about 20 ppm / ° C.). In addition, the thermal expansion coefficient of the resin insulating layers 41 and 42 means the average value of the measured value between 30 degreeC-glass transition temperature (Tg).

  As shown in FIG. 3, via conductors 44 formed by copper plating are provided in the resin insulating layers 41 and 42, respectively. Furthermore, BGA pads 45 (connection terminals) made of copper having a thickness of 20 μm are formed in an array at a plurality of locations on the back surface of the second layer (lowermost layer) resin insulation layer 42. Therefore, the thickness of the BGA pad 45 is larger than the thickness (15 μm) of the wiring layers 16, 17, 33, and 43. Further, the BGA pad 45 is electrically connected to the wiring layer 43 through the via conductor 44. Further, the back surface of the resin insulating layer 42 is almost entirely covered with a solder resist layer 46. In the solder resist layer 46, openings 47 for exposing the central portion of the BGA pad 45 are formed at a plurality of locations. Therefore, the outer peripheral portion of the BGA pad 45 is covered with the solder resist layer 46. Further, a plurality of solder bumps 52 are provided on the back surface (lower surface) of the BGA pad 45 for electrical connection with a mother board (not shown). The wiring board 1 is mounted on the mother board by the solder bumps 52.

  Next, it is disposed between the lowermost resin insulation layer 42 and the lowermost inorganic fiber-containing layer (core substrate 11 in the present embodiment), and is disposed in the lower region A1 including directly under the corner portion 61. The wiring layers 17 and 43 will be described. As shown in FIGS. 3 and 4, the lower region A <b> 1 of the present embodiment includes three from the apex P <b> 1 of the corner portion 61 (see FIG. 4) to the BGA pad 45 (or the opening 47 of the solder resist layer 46). An area extending toward the center of the mounting area 23 and an area extending from the apex P1 to the outside of the mounting area 23 by four BGA pads 45 are formed. In addition, it can be said that the lower region A1 of the present embodiment is a region having a radius of 5 mm with an axis passing through the apex P1 and penetrating the laminated portion 10 in the thickness direction. Of the wiring 81 of the wiring layers 17, 43, a part of the wiring 81 arranged immediately above the opening edge of the opening 47 (in other words, the opening of the opening 47 when viewed from the thickness direction of the stacked portion 10). A portion intersecting the edge) is a wide portion 82 formed wider than a portion continuing to a part of the wiring 81. In the present embodiment, the line width of the portion that continues to the wide portion 82 in the wiring 81 (that is, the portion that is not the wide portion 82) is set to 25 μm. The line width of the wide portion 82 is set to 95 μm and is not less than 2 times and not more than 10 times (3.8 times in this embodiment) that of the portion continuous with the wide portion 82. Further, the length of all the wide portions 82 is not less than 400 μm and not more than 1200 μm (800 μm in this embodiment).

  Next, the manufacturing method of the wiring board 1 of this embodiment is demonstrated.

  First, an intermediate product of the core substrate 11 is prepared by a conventionally known method and prepared in advance. The intermediate product of the core substrate 11 is manufactured as follows. First, a copper clad laminate (not shown) in which a copper foil is pasted on both sides of a base having a length of 400 mm, a width of 400 mm, and a thickness of 0.8 mm is prepared. And a laser drilling process is performed using a drill and the through-hole which penetrates a copper clad laminated board is previously formed in the predetermined position. Next, after the through-hole conductor 14 is formed by performing electroless copper plating and electrolytic copper plating according to a conventionally known method, the closing body 15 is filled and formed in the through-hole conductor 14. Further, the wiring layers 16 and 17 are patterned by, for example, a semi-additive method. Specifically, after the electroless copper plating, electrolytic copper plating is performed using the electroless copper plating layer as a common electrode. Further, the dry film is laminated, and the dry film is exposed and developed to form a dry film in a predetermined pattern. In this state, unnecessary electrolytic copper plating layer, electroless copper plating layer and copper foil are removed by etching. Thereafter, the dry film is peeled off to obtain an intermediate product of the core substrate 11. The intermediate product of the core substrate 11 is a multi-piece core substrate having a structure in which a plurality of regions to be the core substrate 11 are arranged vertically and horizontally along the plane direction.

  Next, the first buildup layer 30 is formed on the first main surface 12 and the second buildup layer 40 is formed on the second main surface 13 based on a conventionally known method. Specifically, first, a resin insulating layer 31 is formed by depositing (attaching) a thermosetting epoxy resin on the first main surface 12 (see FIG. 5). Further, a resin insulating layer 41 is formed by applying (sticking) a thermosetting epoxy resin on the second main surface 13 (see FIG. 5). Instead of depositing a thermosetting epoxy resin, a photosensitive epoxy resin, an insulating resin, or a liquid crystal polymer (LCP) may be deposited.

  Further, laser drilling is performed using a YAG laser or a carbon dioxide gas laser to form via holes at positions where the via conductors 34 and 44 are to be formed. Specifically, a via hole penetrating the resin insulating layer 31 is formed to expose the surface of the first wiring layer 16, and a via hole penetrating the resin insulating layer 41 is formed to form the surface of the second wiring layer 17. To expose. Next, after performing electroless copper plating on the surface of the resin insulating layer 31, the back surface of the resin insulating layer 41, and the inner surface of the via hole, electrolytic copper plating is performed. As a result, via conductors 34 and 44 are formed inside the via hole, a wiring layer 33 is formed on the resin insulating layer 31, and a wiring layer 43 is formed on the resin insulating layer 41 (see FIG. 5). .

  Next, a second layer (uppermost layer) resin insulation layer 32 is formed by applying (sticking) a thermosetting epoxy resin on the surface of the resin insulation layer 31, and on the back surface of the resin insulation layer 41. A second layer (lowermost layer) of resin insulation layer 42 is formed by applying (sticking) a thermosetting epoxy resin to (see FIG. 6). Instead of depositing the thermosetting epoxy resin, a photosensitive epoxy resin, an insulating resin, or a liquid crystal polymer may be deposited. Further, laser drilling is performed using a YAG laser or a carbon dioxide gas laser to form via holes at positions where the via conductors 34 and 44 are to be formed. Specifically, a via hole penetrating the resin insulating layer 32 is formed to expose the surface of the wiring layer 33, and a via hole penetrating the resin insulating layer 42 is formed to expose the surface of the wiring layer 43. Next, electroless copper plating and electrolytic copper plating are performed according to a conventionally known method to form via conductors 34 and 44 inside the via hole, and a terminal pad 35 is formed on the resin insulating layer 32, and the resin insulating layer is formed. A BGA pad 45 is formed on 42 (see FIG. 6).

  Next, the solder resist layer 36 is formed by applying and curing a photosensitive epoxy resin on the surface of the uppermost resin insulation layer 32. Also, a solder resist layer 46 is formed by applying and curing a photosensitive epoxy resin on the back surface of the lowermost resin insulation layer 42. Next, exposure and development are performed in a state in which a predetermined mask is arranged to form an opening 37 in the solder resist layer 36 and an opening 47 in the solder resist layer 46.

  Further, the solder paste is printed on the surface of the terminal pad 35 exposed from the opening 37, and the solder paste is printed on the surface of the BGA pad 45 exposed from the opening 47. Next, the wiring board on which the solder paste is printed is placed in a reflow furnace and heated to a temperature 10 to 40 ° C. higher than the melting point of the solder. At this point, the solder paste is melted to form the solder bumps 51 for mounting the IC chip 21 in a hemispherical shape, and the solder bumps 52 for mounting the motherboard in the same hemispherical shape are formed. The It can be understood that the product in this state is a multi-cavity wiring board in which a plurality of product regions to be the wiring board 1 are arranged vertically and horizontally along the plane direction. Furthermore, when the multi-piece wiring board is divided, a large number of wiring boards 1 as individual products can be obtained simultaneously.

  Thereafter, the IC chip 21 is mounted on the mounting area 23 of the wiring board 1. At this time, the surface connection terminals 22 on the IC chip 21 side and the solder bumps 51 are aligned. Then, each solder bump 51 is reflowed by heating to a temperature of about 220 ° C. to 240 ° C., thereby joining each solder bump 51 and the surface connection terminal 22 to electrically connect the wiring board 1 side and the IC chip 21 side. Connect. As a result, the IC chip 21 is mounted on the mounting area 23. Further, the gap between the wiring board 1 and the IC chip 21 is filled with an underfill material 71 and subjected to a curing process, and the gap is sealed with resin. As a result, the wiring board 1 shown in FIG. 3 is completed.

  Therefore, according to the present embodiment, the following effects can be obtained.

  (1) In the wiring substrate 1 of the present embodiment, the wiring of the wiring layers 17 and 43 disposed between the resin insulating layer 42 and the core substrate 11 and disposed in the lower region A1 including immediately below the corner portion 61. 81, a part of the wiring 81 arranged immediately above the opening edge of the opening 47 of the solder resist layer 46 is a wide portion 82. Therefore, even if a crack 114 (see FIG. 10) starting from the opening edge of the opening 47 is generated and the generated crack 114 reaches the wiring 81 arranged immediately above the opening edge, the crack 114 is a reinforcing portion. Since it reaches a certain wide portion 82, it is difficult to cause a problem that the wiring 81 is electrically disconnected. As a result, since the yield of the wiring board 1 is improved, the reliability of the wiring board 1 can be improved.

  (2) In the present embodiment, a part of the wiring 81 of the wiring layers 17 and 43 is formed as the wide portion 82, thereby preventing electrical disconnection of the wiring 81. That is, since it is not necessary to control the shape of the underfill material 71 in order to obtain the wiring substrate 1 having excellent reliability, the mounting of the IC chip 21 is facilitated, and the productivity of the wiring substrate 1 is improved. . In addition, since the wiring board 1 of the present embodiment is the one in which the shape of the wiring 81 is only changed, the disconnection of the wiring 81 can be prevented without changing the process conventionally used for manufacturing the wiring board 1. can do.

  (3) The IC chip 21 of the present embodiment is highly rigid, has a smaller thermal expansion coefficient than the resin insulating layers 31, 32, 41, and 42, and is supported by the core substrate 11 having a thermal expansion coefficient close to that of the IC chip 21. Is done. Therefore, since the core substrate 11 is difficult to deform, the IC chip 21 mounted on the wiring substrate 1 including the core substrate 11 can be supported more stably. Therefore, it is possible to prevent the IC chip 21 from cracking and poor connection due to large thermal stress. Therefore, as the IC chip 21, the stress (strain) due to the difference in thermal expansion coefficient is large, the influence of the thermal stress is large, the heat generation is large, the thermal shock during use is severe, and the large 10 mm square or more IC chip or A low-k (low dielectric constant) IC chip can be used.

[Second Embodiment]
Hereinafter, a second embodiment of the present invention will be described in detail with reference to the drawings. Here, it demonstrates centering on the part which is different from 1st Embodiment. In this embodiment, the wiring arrangement of the wiring layer is different from the first embodiment in a part of the lower region.

  Specifically, the wiring substrate 121 shown in FIGS. 7 and 8 is disposed between the lowermost resin insulating layer 162 and the core substrate 131 (resin insulating layer, inorganic fiber-containing layer), and the corner portion 181. Wiring layers (second wiring layer 137 and wiring layer 163) disposed in the lower region A2 including immediately below are provided. The wiring 201 of these wiring layers 137 and 163 is laid so as to avoid a position directly above the opening edge of the opening 167 of the solder resist layer 166 (see the avoidance section 202 shown in FIG. 8). Note that the lower region A2 of the present embodiment has a mounting region 143 corresponding to three BGA pads 165 (or openings 167 of the solder resist layer 166) that are connection terminals from the apex P2 of the corner portion 181 (see FIG. 8). This is a wiring avoidance area constituted by an area extending toward the center of the area and an area extending from the apex P2 to the outside of the mounting area 143 by four BGA pads 165. In addition, it can be said that the lower region A2 of the present embodiment is a region having a radius of 5 mm with an axis passing through the apex P2 and penetrating the stacked portion 10 in the thickness direction.

  Therefore, in the present embodiment, the wiring 201 of the wiring layers 137 and 163 disposed between the lowermost resin insulating layer 162 and the core substrate 131 and disposed in the lower region A2 including immediately below the corner portion 181 is provided. , And is laid so as to avoid the position directly above the opening edge of the opening 167. Therefore, even if the crack 114 (see FIG. 10) starting from the opening edge of the opening 167 occurs, and the generated crack 114 progresses directly above the opening edge, the risk that the crack 114 reaches the wiring 201 is reduced. Therefore, it is difficult to cause a problem that the wiring 201 is electrically disconnected. In this case, since the yield of the wiring board 121 is improved, the reliability of the wiring board 121 can be improved.

  In addition, you may change as follows of this embodiment.

  In each of the above embodiments, the wirings 81 and 201 of the wiring layers 43 and 163 disposed in the regions below the corner portions 61 and 181 included in the mounting regions 23 and 143 are disposed immediately above the opening edge of the opening 47. You may have both the structure of 1st Embodiment in which a part becomes the wide part 82, and the structure of 2nd Embodiment laid so that the opening edge of the opening part 167 may be avoided.

  -The connection terminal of each said embodiment was the BGA pad 45 for BGA (ball grid array). However, the connection terminal is not limited to the BGA pad 45 alone, and may be, for example, a PGA pad for PGA (pin grid array).

  -Although the wiring board of each said embodiment was embodied in the wiring boards 1 and 121 which have the core substrates 11 and 131, you may be actualized in the coreless wiring board which does not have the core substrates 11 and 131.

  Next, the technical ideas grasped by the embodiment described above are listed below.

  (1) In the above means 1, the wide substrate has a length of 400 μm or more and 1200 μm or less.

  (2) In the above means 1, the wiring board is characterized in that the resin insulating layer that becomes the inorganic fiber-containing layer is a core substrate that is thicker than the resin insulating layer that does not become the inorganic fiber-containing layer.

  (3) In the said means 1, the said inorganic fiber content layer is a glass cloth content layer containing the glass cloth which is the said inorganic fiber layer, The wiring board characterized by the above-mentioned.

  (4) In the above means 1, the connection board is a BGA pad or a PGA pad.

  (5) In the above means 1, the solder resist layer covers an outer peripheral portion of the connection terminal, while exposing a central portion of the connection terminal from the opening.

  (6) In the above means 1, the lower region includes an area extending from the apex of the corner part to the center side of the mounting area by three of the connection terminals, and four of the connection terminals from the apex of the corner part. And a region extending outward from the mounting region.

DESCRIPTION OF SYMBOLS 1,121 ... Wiring board 10 ... Lamination | stacking part 11,131 ... Core board | substrate 16 as a resin insulation layer and an inorganic fiber containing layer ... 1st wiring layer 17,137 as a wiring layer ... 2nd wiring layer 21 as a wiring layer ... IC chips 23, 143 as semiconductor chips, mounting regions 31, 32, 41, 42, 162 ... resin insulation layers 33, 43, 163 ... wiring layers 45, 165 ... BGA pads 46, 166 as soldering contact layers, solder resist layers 47,167 ... openings 61,181 ... corner portions 81,201 ... wiring 82 in the wiring layer ... wide portions A1, A2 ... lower region

Claims (4)

A stacked portion having a structure in which a plurality of resin insulating layers are stacked, and a mounting area where a semiconductor chip can be mounted is set on the surface of the uppermost resin insulating layer, and on the back surface of the lowermost resin insulating layer And a solder resist layer having openings for connection terminals at a plurality of locations,
The mounting region is a wiring board having a shape having a plurality of corner portions when viewed from the thickness direction of the stacked portion,
The laminated portion has a structure in which a wiring layer is disposed between the plurality of resin insulating layers,
In the inner layer of the laminated part, at least one of the plurality of resin insulation layers is an inorganic fiber-containing layer including an inorganic fiber layer,
Of the wiring of the wiring layer disposed between the lowermost resin insulation layer and the lowermost inorganic fiber-containing layer and disposed in a lower region including directly under the corner portion, A wiring board characterized in that a part of a wiring arranged immediately above an opening edge is a wide part formed wider than a part continuous with a part of the wiring.   The wiring of the wiring layer disposed between the lowermost resin insulating layer and the lowermost inorganic fiber-containing layer and disposed in a lower region including directly under the corner portion is an opening of the opening. The wiring board according to claim 1, wherein the wiring board is laid so as to avoid a position directly above the edge.   3. The wiring board according to claim 1, wherein a line width of the wide portion is not less than 2 times and not more than 10 times a portion continuous with the wide portion.   The connection terminal exposed from the opening is formed on the back surface of the lowermost resin insulating layer, and the thickness of the connection terminal is larger than the thickness of the wiring layer. The wiring board according to any one of claims.

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