JP2003318179A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device uniform in product performance and a method of manufacturing the same, wherein an interlayer insulating film uniform in thickness can be obtained in a multilayer interconnection structure. <P>SOLUTION: The semiconductor device is equipped with a lower actual wiring layer 2a and a lower dummy wiring layer 2b formed on a semiconductor substrate 1, an interlayer insulating film 6 formed on the lower actual wiring layer pattern 2a, a plurality of holes 4a bored in the interlayer insulating film 6, W plugs 3a electrically connected to the lower actual wiring layer pattern 2a by filling the holes 4a with W3, dummy holes 4b bored in a region 7b which is low in hole density so as to make the region 7b nearly as high in hole density as a region 7a which is high in hole density, metal plugs 3a formed by filling the dummy holes 4b with W3, an upper actual wiring 5a which is formed on the top surface of the interlayer insulating film 6 and electrically connected to the lower actual wiring pattern 2a through the intermediary of the W plugs 3a, and an upper dummy wiring electrically connected to the lower dummy wiring 2b through the intermediary of the W plugs 3a. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a multilayer wiring structure via a metal plug provided in an interlayer insulating film and a method for manufacturing the same.

[0002]

2. Description of the Related Art As semiconductor integrated circuit elements have become highly integrated and have large capacities, wiring patterns on semiconductor devices have become denser, and wiring formation technology has become more and more miniaturized and multilayered. Technology is becoming more and more important.

In the case of forming a multilayer wiring structure, for example, an element such as a memory cell and a first layer of aluminum wiring are formed on a semiconductor substrate such as a silicon substrate, and an interlayer insulating film is formed on the first layer of aluminum wiring. A second layer of aluminum wiring is formed via the first layer of aluminum wiring and the second layer of aluminum wiring is buried in an opening such as a contact hole or a via hole formed in the interlayer insulating film. The structure is to be electrically connected with the metal plug of.

In order to connect the first layer aluminum wiring and the second layer aluminum wiring with a metal plug,
In the interlayer insulating film formed on the first layer of aluminum wiring,
An opening such as a contact hole or a via hole is formed by photolithography of a photoresist, a metal such as W is formed on the interlayer insulating film including the opening, and chemical mechanical polishing (Chemical Mechanical Pol
The metal on the interlayer insulating film is removed by the shing (hereinafter, referred to as CMP) method, the metal is left in the opening to form the metal plug, and the second-layer aluminum wiring is formed on the metal plug.

FIG. 4 shows a metal plug (W
It is sectional drawing explaining the state of the interlayer insulation film in plug formation. In the figure, 1 is a semiconductor substrate, 2 is a first layer of aluminum wiring, 3 is W, 3a is a W plug, 6 is an interlayer insulating film, 7a is a W plug 3a where the number is dense, and 7b is W.
This is a part where the number of plugs 3a is sparse.

As shown in FIG. 4A, the semiconductor substrate 1
An interlayer insulating film 6 is formed on the first-layer aluminum wiring 2 formed above, a via hole 4 is formed in a portion of the interlayer insulating film 6 where a W plug 3a is formed, and a tungsten (W) 3 film is formed. .

Next, W3 is removed by the CMP method. At this time, in order to leave W3 in the via hole 4 and not W3 in other portions, polishing is continued even after the surface of the interlayer insulating film 6 is exposed, and a predetermined amount is over-polished. The polishing rate during this over-polishing differs between the dense portion 7a of the W plug 3a and the sparse portion 7b of the W plug 3a, and the polishing rate of the dense portion 7a of the W plug 3a is the sparse portion of the W plug 3a. It is faster than the polishing rate of 7b.

Due to this difference in polishing rate, as shown in FIG. 4B, a thinned portion 8 of the interlayer insulating film 6 (a portion having a large number of W plugs 3a) is formed.

[0009]

As described above, when forming a multilayer wiring structure, the polishing rate in the CMP method is different between the dense W plug portion and the sparse W plug 3 portion.
Since the polishing rate of the dense W plug portion is higher than the polishing rate of the sparse W plug portion, the interlayer insulating film in the dense W plug portion becomes thin, and the process margin in the post-process decreases. Further, there is a problem that the interlayer capacitance varies and the product operation also varies.

The present invention solves the above-mentioned problems, and when a multilayer wiring structure is formed, an interlayer insulating film having a uniform thickness can be obtained, and a semiconductor device having less variation in product operation and its manufacture. The purpose is to provide the law.

[0011]

A semiconductor device according to the present invention includes a semiconductor substrate on which elements are formed, a lower layer main wiring pattern formed on the semiconductor substrate, and a lower layer main wiring pattern formed on the semiconductor substrate. An interlayer insulating film, a plurality of holes formed in the interlayer insulating film, a metal plug electrically connected to the pattern of the lower layer main wiring by embedding a metal in the holes, and formed in the interlayer insulating film Formed by forming dummy holes in a region where the number of holes is low so that the number of holes formed in the interlayer insulating film is approximately the same as the number density of regions where the number of holes is high, and burying metal in the dummy holes. And a metal plug formed on the upper surface of the interlayer insulating film and electrically connected to the metal plug electrically connected to the lower layer main wiring pattern.

The diameter of the dummy hole is substantially the same as the diameter of the hole.

Further, the dummy hole is provided up to the middle of the interlayer insulating film and has a dummy wiring formed on the upper surface of the metal plug buried in the dummy hole.

Further, the dummy hole is formed so as to penetrate through the interlayer insulating film, and is buried in the dummy hole and the lower layer dummy wiring electrically connected to the lower surface of the metal plug buried in the dummy hole. The upper layer dummy wiring electrically connected to the upper surface of the metal plug is provided.

A memory unit is provided as the above element,
The dummy holes are formed so that the number density of holes in the low-density region is about the same as the number density of holes in the memory section.

The method of manufacturing a semiconductor device according to the present invention comprises a first step of forming an element and a lower layer main wiring pattern on a semiconductor substrate, an interlayer insulating film covering the lower layer main wiring pattern, and an interlayer capacitance having a desired value. CM to obtain the thickness
The second step of forming a thickness to be added by polishing by the P method, forming holes above the lower main wiring pattern of the interlayer insulating film, and reducing the number density of the holes to a low density. Dummy holes are formed in the density region so that the number density of the holes is the same as the number density of the high density regions, and a metal is embedded in the holes and the dummy holes by the CMP method. Forming a metal plug to electrically connect the lower-layer main wiring pattern to the metal plug embedded in the hole, and to form the lower-layer main wiring pattern on the upper surface of the interlayer insulating film. Fourth forming an upper-layer main wiring pattern electrically connected to an electrically connected metal plug
The process of.

A first step of forming a memory portion and a lower-layer main wiring pattern on a semiconductor substrate, a second step of forming an interlayer insulating film covering the lower-layer main wiring pattern, and a lower-layer wiring of the interlayer insulating film. Holes are formed in the upper portion of the wiring pattern, dummy holes are formed in a low-density hole number low-density region having a similar number density of holes in the memory section, and the dummy holes are formed by the CMP method. Third step of electrically connecting the lower main wiring pattern and the metal plug buried in the hole by forming a metal plug by burying metal in the hole and the dummy hole, the upper surface of the interlayer insulating film And a fourth step of forming an upper-layer main wiring pattern electrically connected to the metal plug electrically connected to the lower-layer main wiring pattern. .

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below. Embodiment 1. 1 is a cross-sectional view illustrating a first embodiment of a semiconductor device and a method of manufacturing the same according to the present invention.

In the figure, 1 is a semiconductor substrate on which a memory portion or the like is formed as an element, 2a is a lower main wiring (lower wiring pattern) electrically connected to the element, and 2b is electrically connected to the element. Not lower dummy wiring, 3 is W
Metal such as (tungsten), 3a is a metal plug such as a W plug, 4a is a hole, 4b is a dummy hole, 5a is an upper-layer main wiring (upper-layer main wiring) electrically connected to the lower-layer wiring 2a through the metal plug 3a. Pattern) 5b is an upper layer dummy wiring electrically connected to the lower layer dummy wiring 2b, 6
Is an interlayer insulating film, 7a is a high hole number density region, and 7b is a low hole number density region.

In this embodiment, the hole number low density region 7
so that the number density of holes in b is approximately the same as the number density of holes in the high hole number area 7a,
The dummy holes 4b are provided in the low density region 7b.

As shown in FIG. 1A, a lower dummy wiring 2b is formed together with a lower main wiring 2a on a semiconductor substrate 1 on which an element has been formed, and an interlayer insulating film 6 is formed. A hole 4a is formed above the lower-layer main wiring 2a of the film 6, and a dummy hole 4b is formed above the lower-layer dummy wiring 2b of the interlayer insulating film 6 as well, and W3 is formed, as shown in FIG. As described above, by the CMP method, W3
Is polished to leave W3 in the holes 4a and the dummy holes 4b to form W plugs 3a electrically connected to the lower main wiring 2a and W plugs 3a electrically connected to the lower dummy wiring 2b. .

After CMP polishing, as shown in FIG. 1C, the upper-layer main wiring 5a electrically connected to the lower-layer main wiring 2a via the W plug 3a and the lower-layer dummy wiring via the W plug 3a. Upper layer dummy wiring 5 electrically connected to the wiring 2b
and b.

According to the present embodiment, the dummy holes 4b are provided as described above, and the number density of holes in the low hole number low density region 7b is made approximately the same as the number density of holes in the high hole number high density region 7a. Since the W plug 3a is formed, the CM in the low density region 7b
P polishing rate is CM in the hole number high density region 7a
The P polishing rate is almost the same, the interlayer insulating film 6 can be uniformly polished, the variation in product operation can be prevented, and the process margin can be expanded.

Although the lower layer dummy wiring 2b and the upper layer dummy wiring 5b are not always necessary, the lower layer dummy wiring 2b is provided on the lower surface of the W plug 3a formed in the dummy hole 4b penetrating the interlayer insulating film 6. Further, by providing the upper layer dummy wiring 5b on the upper surface, the W plug 3a
Can be prevented from falling out, and the yield is improved.

Further, the diameter of the dummy hole 4b is changed to the hole 4a.
By setting the diameter to be approximately the same, the uniformity of the etching rate of the holes can be increased, the openings of the holes 4a and the dummy holes 4b can be stabilized, and the yield can be improved.

Further, between the lower-layer main wiring 2a and the upper-layer main wiring 5a.
A dummy wiring for suppressing variations in the capacitance between the lower-layer main wiring 2a and the capacitance between the upper-layer main wiring 5a or the interlayer capacitance between the lower-layer main wiring 2a and the upper-layer main wiring 5a is provided between the dummy wirings. Is utilized as the lower layer dummy wiring 2b and the upper layer dummy wiring 5b, the load of the wiring layout can be reduced.

Embodiment 2. 2 is a cross-sectional view showing a second embodiment of a semiconductor device according to the present invention. In the figure, the same symbols as those in FIG. 1 indicate the same or corresponding portions.

In the first embodiment described above, the dummy hole 4b penetrating the interlayer insulating film 6 is provided, but in the present embodiment, the dummy hole 4b opened halfway through the interlayer insulating film 6 is provided. The W plug 3a is formed by setting the number density of holes in the low number density region to be approximately the same as the number density of holes in the high number hole number region, and the CMP of the interlayer insulating film 6 in the low hole number density region and the high hole number density region is performed. The polishing rate is set to be about the same.

According to the present embodiment, the dummy holes 4b are provided as described above, and the number density of holes in the low density region of holes is set to be approximately the same as the density of holes in the high density region of holes. Since 3a is formed, the CMP polishing rate in the low hole number density region becomes approximately the same as the CMP polishing rate in the hole number high density region, the interlayer insulating film 6 can be uniformly polished, and variations in product operation can be prevented. It can be prevented and the process margin can be expanded.

By providing a dummy wiring (not shown) on the upper surface of the W plug 3a formed in the dummy hole 4b, the W plug 3a can be prevented from coming off and the yield can be improved.

Embodiment 3. 3 is a sectional view for explaining a third embodiment of the method for manufacturing a semiconductor device according to the present invention, in which the same reference numerals as those in FIG.

In the present embodiment, the interlayer insulating film 6 is thickened by the thickness t2 removed by CMP polishing so that the thickness of the interlayer insulating film 6 finally becomes the thickness t1 at which a desired interlayer capacitance is obtained. Is formed.

According to the present embodiment, the thickness of the interlayer insulating film after CMP polishing can be set to a thickness at which a desired interlayer capacitance can be obtained.

Fourth Embodiment In this embodiment, the memory cell portion is provided as an element in the first to third embodiments, and the number density of holes in the low hole number density region is set to be approximately the same as the number density of holes in the memory cell portion. A dummy hole is formed.

Usually, the highest hole number density in the semiconductor chip is in the memory cell portion. Therefore, the hole number density in the low hole number low density region should be approximately the same as the hole number density in the memory cell portion. By forming the dummy holes, it is possible to reduce the load required for determining the number density of the dummy holes and layout.

[0036]

According to the semiconductor device of the present invention, the semiconductor substrate on which the element is formed, the pattern of the lower layer main wiring formed on the semiconductor substrate, and the interlayer insulation formed on the pattern of the lower layer main wiring Film, a plurality of holes are formed in the interlayer insulating film, a metal plug electrically connected to the pattern of the lower layer main wiring by burying metal in the holes, and the number of holes formed in the interlayer insulating film Is formed in the low-density region so that the number of holes formed in the interlayer insulating film is approximately the same as the number density of high-density regions in the high-density region, and the dummy holes are formed in the dummy holes. A metal plug formed by embedding a metal, an upper-layer main wiring pattern formed on the upper surface of the interlayer insulating film and electrically connected to a metal plug electrically connected to the lower-layer main wiring pattern Since those having a can be uniformly polished interlayer insulation film, it is possible to prevent variations in the product operation, it is possible to enlarge the process margin.

Further, since the diameter of the dummy holes is substantially the same as the diameter of the holes, the openings of the holes and the dummy holes are stabilized and the yield can be improved.

Further, since the dummy hole is formed up to the middle of the interlayer insulating film and has the dummy wiring formed on the upper surface of the metal plug buried in the dummy hole, the metal plug is prevented from coming off. The yield can be improved.

Further, the dummy hole is formed through the interlayer insulating film, and is buried in the dummy hole and the lower layer dummy wiring electrically connected to the lower surface of the metal plug buried in the dummy hole. Since the upper layer dummy wiring electrically connected to the upper surface of the metal plug is provided, the metal plug can be prevented from coming off and the yield can be improved.

A memory section is provided as the above element,
The number density of holes in the low density region of the number of holes is about the same as the number density of holes in the memory part,
Since the dummy holes are formed, the load required for determining the number density of dummy holes and layout can be reduced.

According to the method of manufacturing a semiconductor device of the present invention, the first step of forming the element and the lower main wiring pattern on the semiconductor substrate, the interlayer insulating film covering the lower main wiring pattern, and the interlayer capacitance are desired. In order to obtain the thickness of
The second step of forming a thickness to be added by polishing by the CMP method, forming holes above the lower main wiring pattern of the interlayer insulating film, and reducing the number density of the holes to a low density. Dummy holes are formed in the density region so that the number density of the holes is the same as the number density of the high density regions, and a metal is embedded in the holes and the dummy holes by the CMP method. Forming a metal plug to electrically connect the lower-layer main wiring pattern to the metal plug embedded in the hole, and to form the lower-layer main wiring pattern on the upper surface of the interlayer insulating film. A fourth step of forming an electrically connected metal plug and an electrically connected upper layer main wiring pattern, so that the interlayer insulating film is uniformly polished. Can, it is possible to prevent variations in the product operation, it is possible to enlarge the process margin.

A first step of forming a memory portion and a lower layer main wiring pattern on a semiconductor substrate, a second step of forming an interlayer insulating film covering the lower layer main wiring pattern, the lower layer main layer of the interlayer insulating film. Holes are formed in the upper portion of the wiring pattern, dummy holes are formed in a low-density hole number low-density region having a similar number density of holes in the memory section, and the dummy holes are formed by the CMP method. Third step of electrically connecting the lower main wiring pattern and the metal plug buried in the hole by forming a metal plug by burying metal in the hole and the dummy hole, the upper surface of the interlayer insulating film And a fourth step of forming an upper-layer main wiring pattern electrically connected to the metal plug electrically connected to the lower-layer main wiring pattern. Since, it is possible to reduce the determination of the number density of the dummy hole, the load required for the layout.

[Brief description of drawings]

FIG. 1 is a cross-sectional view illustrating a first embodiment of a semiconductor device and a manufacturing method thereof according to the present invention.

FIG. 2 is a sectional view showing a second embodiment of a semiconductor device according to the present invention.

FIG. 3 is a cross-sectional view illustrating a third embodiment of the method of manufacturing a semiconductor device according to the present invention.

FIG. 4 is a cross-sectional view illustrating a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

1 semiconductor substrate, 2a lower layer main wiring, 2b lower layer dummy wiring, 3 W (tungsten), 3a W plug, 4a
Hole, 4b Dummy hole, 5a Upper layer main wiring, 5
b Upper layer dummy wiring, 6 interlayer insulating film, 7a hole number high density region, 7b hole density low density region.

Claims (7)

[Claims] 1. A semiconductor substrate on which an element is formed, a pattern of a lower-layer main wiring formed on the semiconductor substrate, an interlayer insulating film formed on the pattern of the lower-layer main wiring, and a plurality of layers on the interlayer insulating film. A hole is formed and a metal plug is electrically connected to the pattern of the lower-layer main wiring by burying a metal in the hole, and the interlayer insulating film is formed in a region where the number of holes formed in the interlayer insulating film is low. Dummy holes are formed so that the number of holes formed in the film is approximately the same as the number density of high-density regions, and a metal plug is formed by embedding metal in the dummy holes, formed on the upper surface of the interlayer insulating film. And a metal plug electrically connected to the lower layer main wiring pattern, and an upper layer main wiring pattern electrically connected to the semiconductor device. 2. The semiconductor device according to claim 1, wherein the diameter of the dummy hole is substantially the same as the diameter of the hole. 3. The semiconductor according to claim 1, wherein the dummy hole is provided up to the middle of the interlayer insulating film, and a dummy wiring is formed on the upper surface of the metal plug buried in the dummy hole. apparatus. 4. The lower dummy wiring, which is formed by penetrating the interlayer insulating film and is electrically connected to a lower surface of a metal plug buried in the dummy hole, and the dummy hole, and is buried in the dummy hole. The semiconductor device according to claim 1, further comprising an upper layer dummy wiring electrically connected to the upper surface of the metal plug. 5. The dummy hole is formed so that a memory portion is provided as the element, and the number density of holes in the low-density region is approximately the same as the number density of holes in the memory portion. The semiconductor device according to any one of claims 1 to 4. 6. A first step of forming an element and a lower-layer main wiring pattern on a semiconductor substrate, wherein an interlayer insulating film covering the lower-layer main wiring pattern has a thickness such that an interlayer capacitance has a desired value. A second step of forming a thickness to be added by polishing by a CMP method, wherein holes are formed above the lower main wiring pattern of the interlayer insulating film, and the number density of the holes is low. Dummy holes are formed in the density region so that the number density of the holes is the same as the number density of the high density regions, and a metal is embedded in the holes and the dummy holes by the CMP method. Forming a metal plug to electrically connect the lower-layer main wiring pattern and the metal plug embedded in the hole to each other. A third step of electrically connecting the lower-layer main wiring pattern to the upper surface of the interlayer insulating film. A fourth step of forming an upper-layer main wiring pattern electrically connected to a metal plug electrically connected to the line pattern, and a semiconductor device manufacturing method. 7. A first step of forming a memory part and a lower layer main wiring pattern on a semiconductor substrate, a second step of forming an interlayer insulating film covering the lower layer main wiring pattern, the lower layer book of the interlayer insulating film Holes are formed in the upper portion of the wiring pattern, dummy holes are formed in the low density hole number area having a low density so as to be approximately the same as the density of holes in the memory portion, and the dummy holes are formed by the CMP method. Third step of electrically connecting the lower-layer main wiring pattern and the metal plug buried in the hole by forming a metal plug by burying metal in the hole and the dummy hole, the upper surface of the interlayer insulating film And a fourth step of forming an upper-layer main wiring pattern electrically connected to the metal plug electrically connected to the lower-layer main wiring pattern. Of manufacturing a semiconductor device.