JP2006049534A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make uniform the processed shape of a via (via contact). <P>SOLUTION: A semiconductor device comprises a first wiring layer; a second wiring layer formed above the first wiring layer; a via 20 disposed on a via layer located between the first wiring layer and the second wiring layer, and permitting a conductive material to be deposited from the lower surface of the second wiring layer to the upper surface of the first wiring layer; and a via 22 having a smaller diameter than the via 20, and permitting a conductive material to be deposited from the lower surface to the halfway of the via layer. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a method for forming a semiconductor device using Cu (copper) wiring.

  In recent years, new microfabrication techniques have been developed along with higher integration and higher performance of semiconductor integrated circuits (LSIs). The chemical mechanical polishing (CMP) method is one of them, and is frequently used in the LSI manufacturing process, particularly in the flattening of the interlayer insulating film, the formation of the metal plug, or the embedding process in the multilayer wiring forming process. This technology is used in

  In particular, recently, in order to achieve high-speed performance of LSIs, there has been a movement to replace the wiring technology from conventional aluminum (Al) alloy to low resistance Cu or Cu alloy (hereinafter collectively referred to as Cu). . Since Cu is difficult to finely process by the dry etching method frequently used in the formation of Al alloy wiring, Cu film is deposited on the insulating film subjected to the groove processing, and other than the portion embedded in the groove A so-called damascene method is mainly employed, in which the Cu film is removed by CMP to form a buried wiring. In general, a Cu film is formed by forming a thin seed layer by sputtering or the like and then forming a laminated film having a thickness of about several hundreds of nanometers by electrolytic plating.

Furthermore, recently, it has been studied to use a low-k film having a low relative dielectric constant as an interlayer insulating film. That is, by using a low-k film having a relative dielectric constant k of 3.5 or less from a silicon oxide film (SiO ₂ film) having a relative dielectric constant k of about 4.2, the parasitic capacitance between wirings is reduced. It has been tried. In addition, low-k film materials having a relative dielectric constant k of 2.5 or less have been developed, and many of these materials are porous materials having pores in the material. A method of manufacturing a semiconductor device having a multilayer wiring structure in which such a low-k film (or porous low-k film) and a Cu wiring are combined is as follows.

FIG. 9 is a process sectional view showing a method of manufacturing a semiconductor device having a multilayer wiring structure in which a conventional low-k film and a Cu wiring are combined.
In FIG. 9, a method for forming a device portion or the like is omitted.
In FIG. 9A, a first insulating film 221 is formed on a substrate 200 made of a silicon substrate by a method such as chemical vapor deposition (CVD).
In FIG. 9B, a groove structure (opening H) for forming a Cu metal wiring or a Cu contact plug is formed in the first insulating film 221 by a photolithography process and an etching process.
In FIG. 9C, a barrier metal film 240, a Cu seed film, and a Cu film 260 are formed in this order on the first insulating film 221, and annealed at a temperature of 150 ° C. to 400 ° C. for about 30 minutes.
In FIG. 9D, the Cu film 260 and the barrier metal film 240 are removed by CMP to form a Cu wiring in the opening H that is a groove.
In FIG. 9E, after the reducing plasma treatment is performed on the surface of the Cu film 260, a second insulating film 281 is formed.
Furthermore, when forming multilayer Cu wiring, it is common to repeat these processes and to laminate. Here, most of the first insulating film 221 and the second insulating film 281 are low-k films.

In addition, a technique is disclosed in which a dummy wiring layer is formed in the wiring layer, and the distribution density of the wiring layer and the dummy wiring layer is reduced (see, for example, Patent Document 1). In addition to the hole penetrating to the lower wiring layer in the interlayer insulating film below the upper wiring layer, the interlayer insulating film below the dummy wiring formed in the upper wiring layer was opened partway without penetrating to the lower wiring layer, A technique for embedding metal in a dummy hole having the same diameter as the hole is disclosed (for example, see Patent Document 2).
JP 2001-148421 A Japanese Patent Laying-Open No. 2003-318179 (FIG. 2)

FIG. 10 is a cross-sectional view of the semiconductor device showing the upper wiring layer in which the dummy pattern and the main pattern are formed, the lower wiring layer in which the dummy pattern and the main pattern are formed, and the intermediate layer.
In FIG. 10, a first wiring layer serving as a lower wiring layer is formed on a substrate 200 according to this pattern serving as a lower wiring on an insulating film composed of a base film 212, a p-lowk film 220, and a cap film 222. Wiring and wiring with a dummy pattern for reducing the density of the pattern when forming the lower layer wiring are formed. A Cu film 260 is deposited as the wiring by this pattern and the wiring by the dummy pattern, and the barrier metal film 240 covers the wall surface and the bottom surface. As the second wiring layer that becomes the upper wiring layer, the pattern according to this pattern that becomes the upper layer wiring and the pattern density when the upper layer wiring is formed on the insulating film composed of the base film 284, the p-lowk film 285, and the cap film 290 are formed. Wiring with a dummy pattern for reduction is formed. A Cu film 264 is deposited as the wiring of this pattern and the wiring of the dummy pattern, and the barrier metal film 244 covers the wall surface and the bottom surface. As an intermediate layer to be a via layer, vias formed by a base pattern 275, a p-lowk film 280, and a cap film 282 are formed on the insulating layer composed of the base film 275, the via layer by the dummy pattern for reducing the density of the pattern when the via layer is formed. And are formed. A Cu film 262 is deposited as a via of this pattern and a via of a dummy pattern, and the barrier metal film 242 covers the wall surface and bottom surface. On the cap film 290, a diffusion prevention film 292 for preventing the diffusion of the Cu film 264 is formed, and on the diffusion prevention film 292, another layer 295 is formed.
Here, since a short circuit between the wirings does not cause a problem between the wiring by the dummy pattern in the upper wiring layer and the wiring by the dummy pattern in the lower wiring layer, a dummy via can be formed. However, there is no via contact pattern at a location where the upper and lower wirings are not connected between the wiring according to the main pattern of the upper wiring layer and the wiring according to the main pattern of the lower wiring layer. Therefore, in the formation of the intermediate layer serving as the via layer, there is a problem that pattern density occurs and the processed shape does not become uniform.

FIG. 11 is a diagram for explaining a problem that occurs during pattern exposure due to pattern density.
As shown in FIG. 11, in a region where the pattern density is rough, there is a problem that the pattern diameter becomes small during pattern exposure. As a result, there is a problem that the diameter of the via hole to be formed is reduced and the via diameter after Cu deposition is also reduced. As the via diameter decreases, the cross-sectional area of the via decreases, resulting in an increase in wiring resistance and via resistance, thereby reducing the operating speed of the semiconductor device. Furthermore, since the wiring resistance and the via resistance increase, a high power supply voltage is required for the operation of the semiconductor device, resulting in an increase in power consumption.

FIG. 12 is a diagram for explaining a problem that occurs during CMP processing due to pattern density.
FIG. 12A shows a state in which Cu is deposited on a dense opening portion, a coarse opening portion and a surface of the insulating film formed in the insulating film on the substrate. If Cu deposited on the surface of the insulating film is removed by CMP from such a state, as shown in FIG. 12B, in the region where the pattern density is rough, there is a problem that a recess is formed in the Cu deposited on the opening. there were. A recess in the via Cu causes a connection failure with the upper layer wiring, resulting in a decrease in yield.

  On the other hand, in Patent Document 2, a dummy via hole having the same diameter as the via hole is formed partway through the insulating film in order to eliminate the pattern density of the via layer under the wiring by the dummy pattern in the upper wiring layer. Although it is conceivable to form this pattern under the wiring, in such a case, since the etching of the dummy via hole must be stopped in the middle of the insulating film, it is a separate process from the original via hole formation (lithography process and etching). In addition, it is necessary to form dummy via holes (lithography process and etching), and it is necessary to newly prepare a mask to be used at the time of exposure.

  An object of the present invention is to overcome the above-described problems and make the processed shape of a via (via contact) uniform.

A method for manufacturing a semiconductor device of the present invention includes:
An insulating film forming step of forming an insulating film on the lower wiring layer;
An exposure step of exposing the insulating film with a first opening pattern and a second opening pattern having a smaller diameter or width than the first opening pattern;
Etching the insulating film until an opening based on the first opening pattern reaches a lower layer wiring formed in the lower wiring layer, and forming an opening based on the first and second opening patterns Process,
A deposition step of depositing a conductive material in the openings based on the first and second opening patterns;
It is provided with.

  The insulating film is etched until an opening based on the first opening pattern reaches a lower layer wiring formed in the lower layer wiring layer, so that the second exposed with a diameter or width smaller than that of the first opening pattern. The opening portion based on the opening pattern can be formed so as to be opened only halfway through the insulating film without reaching the lower layer wiring.

  Furthermore, in the exposure step, when only the first opening pattern is exposed, the second opening pattern is exposed to an area where the pattern density becomes coarse.

  By exposing the second opening pattern to a rough region, the density of the pattern density can be eliminated.

  Furthermore, in the exposure step, the first opening pattern and the second opening pattern are exposed using the same mask.

  By exposing the first opening pattern and the second opening pattern using the same mask, the number of steps can be prevented from increasing.

In the deposition step, a conductive material is deposited on the insulating film together with the openings based on the first and second opening patterns.
The method for manufacturing the semiconductor device further includes a polishing step of polishing and removing the conductive material deposited on the insulating film.

  By providing the second opening pattern in a region where the pattern density is coarse, no recess is generated in the conductive material deposited in the opening based on the first and second opening patterns in the polishing step. Can be.

The manufacturing method of the semiconductor device further includes an upper layer wiring forming step of forming an upper layer wiring on the insulating film,
In the exposure step, the second opening pattern is exposed at a position corresponding to the lower region of the upper wiring layer.

  Since the exposure is performed in the region below the upper layer wiring, it is possible to prevent a short circuit with the wiring adjacent to the upper layer wiring layer. Further, since the opening based on the second opening pattern does not penetrate to the lower wiring layer, it is formed at a position where a hole pattern penetrating between the upper wiring layer and the lower wiring layer cannot be provided. be able to.

  The second opening pattern is particularly effective when exposed to a diameter or width of 70% or less with respect to the diameter or width of the first opening pattern.

The semiconductor device of the present invention is
A first wiring layer;
A second wiring layer formed above the first wiring layer;
An intermediate layer formed between the first wiring layer and the second wiring layer;
With
In the intermediate layer,
An insulating film using an insulating material;
A first conductive material deposition section using a conductive material connected to the first wiring layer and the second wiring layer;
A second conductive material deposition portion having a diameter or width smaller than that of the first conductive material deposition portion, using a conductive material surrounded by the second wiring layer and the insulating film;
It is provided with.

  The second conductive material deposition portion is surrounded by the second wiring layer and the insulating film. In other words, the first wiring layer is disposed at a predetermined distance. Furthermore, in other words, the conductive material is deposited only from the lower surface of the second wiring layer to the middle of the intermediate layer. Therefore, the second conductive material deposition portion can be formed also in a region where it is not desired to connect between the first wiring layer and the second wiring layer.

  In particular, the second conductive material deposition portion is formed in a region of the intermediate layer where a pattern density becomes coarse when the first conductive material deposition portion is formed.

  By providing the second conductive material deposition portion in a region where the pattern density is rough, it is possible to suppress dimensional variations, and in particular, to secure the diameter of the first conductive material deposition portion. Furthermore, it is possible to prevent a recess from being formed in the first conductive material deposition portion.

  In the present invention, the second conductive material deposition portion is formed at a position corresponding to a second wiring lower region formed in the second wiring layer.

  Since it is formed in a region below the upper layer wiring, it is possible to prevent a short circuit with a wiring adjacent to the same layer.

  In the present invention, the second conductive material deposition portion disconnects the first wiring formed in the first wiring layer and the second wiring formed in the second wiring layer. It is formed in the area | region which carries out.

  Conventionally, in the circuit configuration, the second conductive property is not formed in a region that cannot be formed because the wires are not short-circuited, in other words, a region in which the first wire and the second wire are not connected, that is, a region that is not connected. By forming the material deposition portion, pattern density can be eliminated.

  As described above, according to the present invention, a pattern can be formed as a dummy at a position where it cannot be connected between the upper and lower wirings, so that the pattern density can be eliminated. Since the density of the pattern can be eliminated, variations in exposure dimensions can be suppressed, and further, the formation of recesses can be suppressed.

Embodiment 1 FIG.
FIG. 1 is a cross-sectional view of the semiconductor device according to the first embodiment.
In FIG. 1, a first wiring layer serving as a lower wiring layer is formed on a substrate 200 according to this pattern serving as a lower wiring on an insulating film composed of a base film 212, a p-lowk film 220, and a cap film 222. Wiring and wiring with a dummy pattern for reducing the density of the pattern when forming the lower layer wiring are formed. A Cu film 260 is deposited as the wiring by this pattern and the wiring by the dummy pattern, and the barrier metal film 240 covers the wall surface and the bottom surface. As the second wiring layer that becomes the upper wiring layer, the pattern according to this pattern that becomes the upper layer wiring and the pattern density when the upper layer wiring is formed on the insulating film composed of the base film 284, the p-lowk film 285, and the cap film 290 are formed. Wiring with a dummy pattern for reduction is formed. A Cu film 264 is deposited as the wiring of this pattern and the wiring of the dummy pattern, and the barrier metal film 244 covers the wall surface and the bottom surface. Via 20 and via layer formation by this via pattern connecting wirings by upper and lower main patterns to be vias to an insulating film composed of base film 275, p-lowk film 280 and cap film 282 as an intermediate layer to be a via layer Sometimes, vias 24 are formed by the first dummy via patterns that connect the upper and lower dummy patterns in order to reduce the density of the patterns. A Cu film 262 is deposited as a via of this via pattern and a via of the first dummy via pattern, and the barrier metal film 242 covers the wall surface and bottom surface. On the cap film 290, a diffusion prevention film 292 for preventing the diffusion of the Cu film 264 is formed, and on the diffusion prevention film 292, another layer 295 is formed.

  A short circuit between the wirings does not cause a problem between the wiring by the dummy pattern in the upper wiring layer and the wiring by the dummy pattern in the lower wiring layer, so that the via 24 by the first dummy via pattern can be formed. The via 24 by the first dummy via pattern is preferably formed to have the same diameter or the same width as the diameter or width dimension A of the via 20 by this via pattern.

  Furthermore, between the wiring according to the main pattern of the upper wiring layer and the wiring according to the main pattern of the lower wiring layer, the location where the short circuit between the wirings becomes a problem on the circuit configuration, in other words, the location where the upper and lower wirings are disconnected, That is, a portion that is not connected (or a portion that cannot be connected) does not reach the first wiring layer, that is, is surrounded by the upper wiring layer and the insulating film and separated from the lower wiring layer by a predetermined distance. A via 22 having a via pattern is formed. The Cu film 262 is also deposited on the via 22 having the second dummy via pattern, and the barrier metal film 242 covers the wall surface and the bottom surface. By forming the via 22 by the second dummy via pattern in a region where the pattern density is coarse at a location where the upper and lower wirings are not connected, the density of the pattern can be eliminated. The via 22 by the second dummy via pattern is formed to have a diameter or width dimension B smaller than the diameter or width dimension A of the via 20 by the present via pattern. By making the diameter or width of the via 22 of the second dummy via pattern smaller than the diameter or width of the via 20 of the present via pattern, the etching rate during etching is an opening for forming the via 20 by the present via pattern. It can be made slower than the etching rate. As a result, even if the opening for forming the via 20 by this via pattern penetrates, the etching of the opening for forming the via 22 by the second dummy via pattern can be stopped in the middle of the intermediate layer. .

  At a position where the upper wiring layer and the lower wiring layer are not connected, the pattern density is coarser than that of other regions. Therefore, the via 22 by the second dummy via pattern is a position where the upper wiring layer and the lower wiring layer are not connected. It is particularly effective when formed into. For example, it is desirable to form in a region where the main pattern is formed in both the upper wiring layer and the lower wiring layer, or in a region where the wiring which becomes the main pattern is formed in one of the upper wiring layer and the lower wiring layer. . Further, it is desirable to form in a region under one wiring so as not to contact both adjacent wiring portions formed in the upper wiring layer. By being formed in a region under one wiring, a short circuit between adjacent wirings can be prevented.

FIG. 2 is a flowchart showing a main part of the semiconductor device manufacturing method according to the first embodiment.
In FIG. 2, in the present embodiment, a lower layer wiring forming step (S102), an SiC film forming step (S104) for forming an SiC film as a via interlayer insulating film forming step when vias are formed on the lower layer wiring layer. ), P-lowk film forming step (S106) for forming a p-lowk film using a porous insulating material, helium (He) plasma processing step (S108) for plasma-treating the surface of the p-lowk film, SiO ₂ SiO ₂ film forming process for forming a film (S110), exposure process for exposing an opening pattern (s112), developing process (S114), opening forming process for forming an opening (S116), and via forming process As a conductive material deposition process for depositing a conductive material to be used, a barrier metal film forming process (S118), a seed film forming process (S120), and a plating process And S122), carried out the polishing step (S124), a series of steps of upper layer wiring forming step (S126).

FIG. 3 is a process sectional view showing a process performed corresponding to the flowchart of FIG.
3 shows from the SiC film formation step (S104) to the SiO ₂ film formation step (S110) in FIG. Subsequent steps will be described later.

In FIG. 3A, first, a lower layer wiring is formed as a lower layer wiring forming step. On the substrate 200, an insulating film composed of a base film 212, a p-lowk film 220, and a cap film 222 is formed as a first wiring layer serving as a lower wiring layer. Then, an opening portion (groove portion) serving as a dummy pattern for reducing the density of the pattern when forming the main layer serving as the lower layer wiring and the lower layer wiring is formed in the insulating film. Then, a barrier metal film 240 is formed on the wall surface and bottom surface of the opening, and a Cu film 260 is deposited in the remaining space. The method for forming the lower layer wiring may be the same as the method for forming the via layer to be described below, and thus the description thereof is omitted.
Next, an insulating film in the via layer is formed. First, as a SiC film forming step, a base silicon carbide (SiC) film having a thickness of 50 nm using SiC is deposited on the substrate 200 on which the lower wiring layer is formed by a CVD method to form a base film 275. Here, the film is formed by the CVD method, but other methods may be used. The base film 275 also has a function as an etching stopper. Since it is difficult to generate the SiC film, a silicon carbonate (SiOC) film may be used instead of the SiC film. Alternatively, a silicon carbonitride (SiCN) film or a silicon nitride (SiN) film can be used.

  Here, as the substrate 200, for example, a substrate such as a silicon wafer having a diameter of 300 mm is used. The substrate 200 may be formed with contact plugs or other layers. Further, as the material of the base film 212 of the lower wiring layer, SiC, SiOC, SiCN, or SiN can be used as in the base film 275.

In FIG. 3B, as a porous low-k (p-lowk) film forming process, a porous insulating property is formed on the base film 275 formed by the SiC insulating film forming process formed on the substrate 200. A p-lowk film 280 using a material is formed with a thickness of 250 nm. By forming the p-lowk film 280, an interlayer insulating film having a relative dielectric constant k lower than 3.5 can be obtained. As a material of the p-lowk film 280, for example, porous methylsilsesquioxane (MSQ) can be used. As the formation method, for example, a SOD (spin on selective coating number and name, name of agent) method of forming a thin film by spin-coating a solution and heat-treating can be used. For example, the film is formed at a rotation speed of the spinner of 900 min ⁻¹ (900 rpm). The wafer is baked on a hot plate at a temperature of 250 ° C. in a nitrogen atmosphere, and finally cured on a hot plate at a temperature of 450 ° C. in a nitrogen atmosphere for 10 minutes. A porous insulating film having a predetermined physical property value can be obtained by appropriately adjusting the MSQ material, formation conditions, and the like. For example, the density is 0.7 g / cm ³ and the relative dielectric constant k is 1.8. The composition ratio of Si, O, and C in the low-k film is p-lowk having physical properties in which Si is in the range of 25 to 35%, O is in the range of 45 to 57%, and C is in the range of 13 to 24%. A membrane 280 is obtained. Here, the p-lowk film 220 of the lower wiring layer may be the same as the p-lowk film 280.

Then, as a He plasma treatment process, the surface of the p-lowk film 280 is modified by helium (He) plasma irradiation. By modifying the surface by He plasma irradiation, the adhesion between the p-lowk film 280 and a cap film 282 (described later) formed on the p-lowk film 280 can be improved. For example, the gas flow rate is 1.7 Pa · m ³ / s (1000 sccm), the gas pressure is 1000 Pa, the high frequency power is 500 W, the low frequency power is 400 W, and the temperature is 400 ° C. When the cap CVD film is formed on the p-lowk film, it is effective to improve the adhesion with the cap CVD film by performing plasma treatment on the surface of the p-lowk film. As types of plasma gas, ammonia (NH ₃ ), nitrous oxide (N ₂ O), hydrogen (H ₂ ), He, oxygen (O ₂ ), silane (SiH ₄ ), argon (Ar), nitrogen (N ₂ ) Among these, He plasma is particularly effective because it causes little damage to the p-lowk film. The plasma gas may be a mixture of these gases. For example, it is effective to use He gas mixed with other gases.

In FIG. 3C, as the SiO ₂ film formation step, after performing the He plasma treatment, a cap film is deposited as a cap film by depositing SiO ₂ on the p-lowk film 280 by a CVD method to a thickness of 50 nm. 282 is formed. By forming the cap film 282, the p-lowk film 280 that cannot be directly subjected to lithography can be protected, and a pattern can be formed in the p-lowk film 280. Such cap CVD films include SiO ₂ films, SiC films, SiOC films, SiCN films, etc., but from the viewpoint of reducing damage, the SiO ₂ film is excellent, and from the viewpoint of reducing the dielectric constant, the SiOC film has improved breakdown voltage. From the viewpoint, the SiC film and the SiCN film are excellent. Furthermore, it is possible to use SiO ₂ film and the SiC film laminated film of, or SiO ₂ film and the SiCO film laminated film of, or a laminated film of SiO ₂ film and SiCN film. Further, a part or all of the cap CVD film may be removed by chemical mechanical polishing (CMP) in a planarization step described later. The dielectric constant can be further reduced by removing the cap film. The thickness of the cap film is preferably 10 nm to 150 nm, and 10 nm to 50 nm is effective in reducing the effective relative dielectric constant. Here, the cap film 222 of the lower wiring layer may be the same as the cap film 282.

  In the above description, the interlayer insulating film may not be a low-k film having a relative dielectric constant of 3.5 or less, but is a low-k film, particularly a relative dielectric constant k of 2.5 or less, This is particularly effective when a porous p-lowk film having a rate of 30% or more is included.

FIG. 4 is a process sectional view showing a process performed corresponding to the flowchart of FIG.
FIG. 4 shows from the exposure step (S112) to the development step (S114) in FIG. Subsequent steps will be described later.

  4A, first, a resist material is applied onto the cap film 282, and a desired pattern is exposed as an exposure process. For example, an electron beam resist is used as the resist material, and exposure is performed by irradiating the electron beam resist film 270 with the electron beam 271. The electron beam resist is applied by a spin coating method or the like. By using an electron beam resist, a fine pattern can be processed. Here, electron beam exposure is performed using an electron beam resist, but light exposure may be performed using a resist film that is sensitive to light such as ultraviolet rays. Then, the applied electron beam resist is exposed. In the exposure, an electron beam is irradiated onto a selective region of the resist film using an electron beam drawing apparatus.

  Here, in the mask used for exposure, a via pattern having a predetermined diameter A is formed at a position corresponding to the main pattern region to be connected in the upper and lower wiring layers in consideration of the positional relationship with the upper layer wiring described later. deep. Then, in the position where both the upper and lower wiring layers are dummy pattern regions, there is no problem between upper and lower continuity. Therefore, a dummy via pattern having a diameter A is similarly formed in order to eliminate the density of the pattern density. On the other hand, a dummy via pattern having a diameter B smaller than the diameter A is formed in a region (a region where connection is not allowed) in the upper and lower wiring layers. Using this mask, the electron beam resist film 270 is irradiated with an electron beam. Conventionally, a dummy pattern could not be arranged in a region that should not be connected in the upper and lower wiring layers, so that the pattern density was coarse. However, a dummy via pattern having a diameter B is arranged in the rough region. Thus, the density of the pattern density to be exposed can be eliminated. The dummy via pattern having a diameter B is desirably provided at a position where adjacent upper layer wirings do not short in consideration of the positional relationship of upper layer wirings described later. For example, the diameter B may be made smaller than the width of the upper layer wiring, and the vias formed by one dummy via pattern may be placed under one upper layer wiring, in other words, at a position that does not protrude in the direction parallel to the layer. Here, the via pattern is not limited to a circle having a predetermined diameter, and may be a rectangle having a predetermined width.

  In FIG. 4B, as a developing step, the electron beam resist film 270 is developed to form an opening having an exposed pattern. Development is performed by dipping in a developer. By being developed, the resist film is selectively patterned by distinguishing between a resist region and a non-resist region. In the electron beam resist developing process, when a positive resist is applied as the electron beam resist, the electron beam resist is dissolved in the developer in the region irradiated with the electron beam, and the cap film 282 is exposed. In the region where the electron beam is not irradiated, the electron beam resist is not dissolved in the developer, so that the electron beam resist pattern remains.

FIG. 5 is a process sectional view showing a process performed corresponding to the flowchart of FIG.
FIG. 5 shows from the opening forming step (S116) to the seed film forming step (S120) in FIG. Subsequent steps will be described later.

  In FIG. 5A, as an opening forming process, the exposed electron beam resist film 270 is used as a mask, the exposed cap film 282 and the p-lowk film 280 located therebelow are used as an etching stopper, and the base film 275 is used as an etching stopper. The openings may be formed by removing by an isotropic etching method, and the base film 275 may be removed by etching. By using the anisotropic etching method, the opening can be formed substantially perpendicular to the surface of the substrate 200. For example, as an example, the opening may be formed by a reactive ion etching method. Here, in the via pattern having the diameter dimension A and the diameter dimension B, a difference occurs in the etching rate. That is, the etching of the via pattern having the diameter A is faster than the etching of the via pattern having the diameter B having a small diameter. Therefore, when the opening (via hole) by the via pattern having the diameter A penetrates to the lower wiring layer, the etching is terminated, so that the opening (via hole) having the diameter B becomes in the middle of the insulating film. Can be stopped. The remaining electron beam resist film 270 may be removed by ashing.

  As described above, by using the via pattern having the diameter dimension A and the diameter dimension B, one of them can be stopped in the middle of the insulating film, so that an opening can be formed at the same time without increasing the number of etchings. Can do. In addition, since etching can be performed together, lithography processes such as the exposure process and the development process described above can be performed simultaneously without increasing the number of times. In addition, the mask reticle used in the exposure process can be prevented from increasing. By not increasing the number of steps, the throughput can be prevented from decreasing.

  Here, the diameter dimension B is desirably 70% or less of the diameter dimension A. By setting it to 70% or less, even if 10% in-plane uniformity and 10% etching variation are taken into consideration, 10% or more of the insulating film can be left under the opening of the via pattern having the diameter B. By securing an insulating film of 10% or more, dielectric breakdown can be prevented.

  In FIG. 5B, as a barrier metal film forming step, a barrier metal film 242 using a barrier metal material is formed on the opening formed in the opening forming step and the surface of the cap film 282. For example, a tantalum nitride (TaN) film having a thickness of 10 nm and a tantalum (Ta) film having a thickness of 15 nm are deposited in a sputtering apparatus using a sputtering method, which is one of physical vapor deposition (PVD) methods. Then, the barrier metal film 240 is formed. By stacking the TaN film and the Ta film, the TaN film can prevent diffusion of Cu into the p-lowk film 280, and the Ta film can improve the adhesion of Cu. As a deposition method of the barrier metal material, for example, an atomic layer deposition (ALD method or an atomic layer chemical vapor deposition: ALCVD method), a CVD method, or the like can be used. The coverage can be improved as compared with the case of using the PVD method.

  In FIG. 5C, as a seed film formation process, a barrier metal film 242 is formed by using a Cu thin film serving as a cathode electrode in a subsequent electroplating process as a seed film 252 by a physical vapor deposition (PVD) method such as sputtering. Are deposited (formed) on the inner wall of the opening and the surface of the base 200. For example, the seed film 250 is deposited with a film thickness of 75 nm.

FIG. 6 is a process sectional view showing a process performed corresponding to the flowchart of FIG.
FIG. 6 shows from the plating step (S122) to the upper layer wiring formation step (S126) in FIG.

  In FIG. 6A, as a plating process, a Cu film 262 is deposited on the opening and the surface of the substrate 200 by electrochemical growth such as electrolytic plating using the seed film 252 as a cathode electrode. For example, a Cu film 262 having a thickness of 500 nm is deposited, and after the deposition, annealing is performed at a temperature of 250 ° C. for 30 minutes.

  In FIG. 6B, as a polishing process, the Cu film 262, the seed film 252 and the barrier metal film 242 that are wiring layers as conductive portions deposited on the surface of the cap film 282 by CMP are polished and removed. Then, a buried structure as shown in FIG. 6B is formed. In order to reduce the density of the pattern when forming the via 24 and via layer by the first dummy via pattern for connecting the upper and lower dummy patterns in order to reduce the density of the pattern when forming the via 20 and the via layer by the present via pattern. A via 22 having a second dummy via pattern that does not connect the upper and lower wiring layers is formed.

  In FIG. 6C, upper layer wiring is formed as an upper layer wiring forming step. An insulating film composed of a base film 284, a p-lowk film 285, and a cap film 290 is formed on the via layer as a second wiring layer to be an upper wiring layer. Then, an opening (groove) serving as a dummy pattern for reducing the density of the pattern when forming the upper layer wiring and the main pattern serving as the upper layer wiring is formed in the insulating film. Then, a barrier metal film 244 is formed on the wall surface and bottom surface of the opening, and a Cu film 264 is deposited in the remaining space. The method for forming the upper layer wiring may be the same as the method for forming the via layer described above, and the description thereof is omitted. Then, a diffusion prevention film 292 of the Cu film 264 is formed on the upper wiring layer. For example, a SiC film is used as the diffusion preventing film 292.

FIG. 7 is a diagram for explaining a pattern state at the time of exposure.
As shown in FIG. 7A, in the conventional technique, the pattern diameter C is smaller than the original dimension A at the time of pattern exposure in an area where the pattern density is rough. As a result, the diameter of the via hole formed in the insulating film is reduced, and the processing dimension cannot be maintained at the design value. On the other hand, in the present embodiment, since the dummy via pattern having the pattern diameter smaller than the dimension A is arranged in the mask in the region where the pattern density is not able to be formed conventionally, the dummy via pattern can be formed. The density density can be eliminated, and exposure can be performed with the original pattern dimension A during pattern exposure. In other words, dimensional variations can be eliminated or suppressed by eliminating the density of the pattern density. Since variations in pattern dimensions are small or eliminated, subsequent variations in etching can also be eliminated or suppressed.

FIG. 8 is a diagram for explaining the shape of the Cu film during the CMP process.
In FIG. 8A, the pattern density is eliminated from coarse to dense by forming an opening having a dense pattern density formed in the insulating film on the substrate and a dummy via pattern having a small diameter according to the present embodiment. A state is shown in which Cu is deposited on the opening and the insulating film surface. When Cu deposited on the surface of the insulating film is removed by CMP from such a state, a recess is formed in the Cu deposited in the opening in the region where the pattern density is eliminated from coarse to dense as shown in FIG. 8B. No variation in recesses due to pattern density and density is suppressed. Therefore, it is possible to eliminate the poor connection with the upper layer wiring and improve the yield by preventing the Cu serving as the via from causing a recess or suppressing the recess variation.

  As described above, the contact pattern is formed without connecting the upper and lower wirings at a position where the contact pattern cannot be formed conventionally. Therefore, in the formation of the intermediate layer as the via layer, the density of the pattern is eliminated and the processing shape is made uniform Can be made.

Embodiment 2. FIG.
In the first embodiment, a single damascene method in which vias and upper layer wirings are separately formed is used, but a dual damascene method in which vias are formed together with upper layer wirings may be used. When the dual damascene method is used, when the via pattern is exposed, similarly, the density of the pattern density can be eliminated and the dimensional variation of the exposure pattern can be suppressed.

  Here, as a material of the wiring layer in the above embodiment, in addition to Cu, a material mainly composed of Cu used in the semiconductor industry, such as a Cu—Sn alloy, a Cu—Ti alloy, and a Cu—Al alloy is used. Similar effects can be obtained.

  In the above-described embodiment, when the relative dielectric constant k of the p-lowk film is 2.6 or less, the sidewall of the p-lowk film is covered with a CVD film that becomes a sidewall having a thickness of 20 nm or less. desirable. This is because when the relative dielectric constant is 2.6 or less, the film is often a porous film, and it is desirable to perform pore sealing on the side wall of the Cu wiring. In particular, when a barrier metal film is formed by an ALD method or a CVD method, it is desirable to provide a sidewall. As the kind of the pore sealing CVD film, a SiC film, a SiCN film, a SiCO film, and a SiN film are desirable. In particular, a SiC film is optimal from the viewpoint of a low dielectric constant.

  Further, the barrier metal is not limited to Ta and TaN, but a nitride or carbon nitride film of a refractory metal such as TaCN (tantalum carbonitride), WN (tungsten nitride), WCN (tungsten carbonitride), or TiN (titanium nitride) It does not matter. Alternatively, titanium (Ti), WSiN, or the like may be used. Moreover, you may be these laminated films.

  The embodiments have been described above with reference to specific examples. However, the present invention is not limited to these specific examples.

  For example, the substrate 200 on which an interlayer insulating film is formed in each embodiment can have various semiconductor elements or structures not shown. Further, an interlayer insulating film may be further formed on a wiring structure having an interlayer insulating film and a wiring layer instead of the semiconductor substrate. The opening may be formed so that the semiconductor substrate is exposed, or may be formed on the wiring structure.

  Further, the film thickness of the interlayer insulating film and the size, shape, number, and the like of the opening can be appropriately selected from those required in the semiconductor integrated circuit and various semiconductor elements.

  In addition, any semiconductor device manufacturing method that includes the elements of the present invention and whose design can be changed as appropriate by those skilled in the art is included in the scope of the present invention.

  Further, for the sake of simplicity of explanation, techniques usually used in the semiconductor industry, such as cleaning before and after the photolithography process, are omitted, but it goes without saying that these techniques are included.

FIG. 3 is a cross-sectional view of the semiconductor device in the first embodiment. 3 is a flowchart showing a main part of a method for manufacturing a semiconductor device in the first embodiment. FIG. 3 is a process cross-sectional view illustrating a process performed corresponding to the flowchart in FIG. 2. FIG. 3 is a process cross-sectional view illustrating a process performed corresponding to the flowchart in FIG. 2. FIG. 3 is a process cross-sectional view illustrating a process performed corresponding to the flowchart in FIG. 2. FIG. 3 is a process cross-sectional view illustrating a process performed corresponding to the flowchart in FIG. 2. It is a figure for demonstrating the pattern state at the time of exposure. It is a figure for demonstrating the Cu film | membrane shape at the time of CMP process. It is process sectional drawing which shows the manufacturing method of the semiconductor device which has the multilayer wiring structure which combined the conventional Low-k film | membrane and Cu wiring. It is sectional drawing of the semiconductor device which showed the upper layer wiring layer in which the dummy pattern and this pattern were formed, the lower layer wiring layer in which the dummy pattern and this pattern were formed, and the intermediate | middle layer. It is a figure for demonstrating the malfunction which arises at the time of pattern exposure by the density of a pattern. It is a figure for demonstrating the malfunction which arises at the time of CMP process by the density of a pattern.

Explanation of symbols

20, 22, 24 Via 200 Base 212, 275, 284 Base film 220, 280, 285 P-lowk film 221, 281 Insulating film 222, 282, 290 Cap film 240, 242, 244 Barrier metal film 250, 252 Seed film 260 , 262, 264 Cu film 270 Electron beam resist film 271 Electron beam 292 Diffusion prevention film 295 Other layers

Claims (10)

An insulating film forming step of forming an insulating film on the lower wiring layer;
An exposure step of exposing the insulating film with a first opening pattern and a second opening pattern having a smaller diameter or width than the first opening pattern;
Etching the insulating film until an opening based on the first opening pattern reaches the lower wiring layer, and forming an opening based on the first and second opening patterns; and
A deposition step of depositing a conductive material in the openings based on the first and second opening patterns;
A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein, in the exposure step, the second opening pattern is exposed to a region where a pattern density is coarse when only the first opening pattern is exposed. 3. .   2. The method of manufacturing a semiconductor device according to claim 1, wherein in the exposure step, the first opening pattern and the second opening pattern are exposed using the same mask. In the deposition step, a conductive material is deposited on the insulating film together with the openings based on the first and second opening patterns,
3. The method of manufacturing a semiconductor device according to claim 2, further comprising a polishing step of polishing and removing the conductive material deposited on the insulating film. The manufacturing method of the semiconductor device further includes an upper layer wiring forming step of forming an upper layer wiring on the insulating film,
2. The method of manufacturing a semiconductor device according to claim 1, wherein, in the exposure step, the second opening pattern is exposed at a position corresponding to a region under the upper wiring.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the second opening pattern is exposed to a diameter or width of 70% or less with respect to the diameter or width of the first opening pattern. A first wiring layer;
A second wiring layer formed above the first wiring layer;
An intermediate layer formed between the first wiring layer and the second wiring layer;
With
In the intermediate layer,
An insulating film using an insulating material;
A first conductive material deposition section using a conductive material connected to the first wiring layer and the second wiring layer;
A second conductive material deposition portion having a diameter or width smaller than that of the first conductive material deposition portion, using a conductive material surrounded by the second wiring layer and the insulating film;
A semiconductor device characterized in that is formed.   8. The second conductive material deposition portion is formed in a region where a pattern density becomes coarse in the intermediate layer when the first conductive material deposition portion is formed. The semiconductor device described.   9. The semiconductor device according to claim 8, wherein the second conductive material deposition portion is formed at a position corresponding to a second wiring lower region formed in the second wiring layer.   The second conductive material deposition portion is formed in a region where the first wiring formed in the first wiring layer and the second wiring formed in the second wiring layer are not connected. The semiconductor device according to claim 8.

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