JP2006060011A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a void due to concentration of point defect from being formed inside a Cu wiring. <P>SOLUTION: The method has insulating film formation steps (S102 to S110) for forming an insulating film on a base; an opening formation step (S112) for forming an opening in the insulating film; a seed film formation step (S116) for forming a seed film in the surface of the insulating film and the opening; a first plating step (S118) for making a current which becomes a first current density flow using the seed film as an electrode, and depositing a conductive material in the opening by a plating method; a second plating step (S120) for making a current of a second current density smaller than the first current density flow after the first plating process, and for depositing the conductive material on the insulating film surface by a plating method; and an annealing step (S124) for performing annealing treatment for the base wherein the conductive material is deposited after the second plating process. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to wiring formation using copper or the like by plating.

  Copper (Cu) wiring having low resistance and high electromigration (EM) resistance is expected as a highly reliable material for highly integrated and miniaturized LSI wiring.

As semiconductor integrated circuits become highly integrated and operate at higher speeds, the delay of signals propagating through wiring between semiconductor elements has been governed by the operating speed of integrated circuits.
In particular, recently, in order to achieve high-speed performance of such LSI, there has been a movement to replace the wiring technology from conventional aluminum (Al) alloy to low resistance Cu or Cu alloy (hereinafter collectively referred to as Cu). It is out. Since Cu is difficult to finely process by the dry etching method frequently used in the formation of Al alloy wiring, Cu film is deposited on the insulating film subjected to the groove processing, and other than the portion embedded in the groove A so-called damascene method, in which the Cu film is removed by chemical mechanical polishing (CMP) to form a buried wiring, is mainly employed. In general, a Cu film is formed by forming a thin seed layer by sputtering or the like and then forming a laminated film having a thickness of about several hundreds of nanometers by electrolytic plating.

  Further, since Cu easily diffuses into the Si-based insulating film, the periphery of Cu must be covered with a diffusion preventing film. Therefore, as described above, when a Cu wiring is formed using the damascene process, titanium (Ti), tantalum (Ta), tungsten (W) is formed in an opening pattern such as a groove or a hole formed in the insulating film. Alternatively, a refractory metal film such as a nitride or an alloy thereof is formed. In general, after forming a refractory metal film, Cu is buried and a barrier metal film made of a refractory metal film for preventing Cu diffusion is disposed around the Cu wiring.

Further, recently, it has been studied to use a low dielectric constant (low-k) film having a low relative dielectric constant as an interlayer insulating film. That is, by using a low-k film having a relative dielectric constant k of 3.5 or less from a silicon oxide film (SiO ₂ film) having a relative dielectric constant k of about 4.2, the parasitic capacitance between wirings is reduced. It has been tried. A method of manufacturing a semiconductor device having a multilayer wiring structure in which such a low-k film and a Cu wiring are combined is as follows.

FIG. 13 is a process cross-sectional view illustrating a method of manufacturing a semiconductor device having a multilayer wiring structure in which a conventional low-k film and a Cu wiring are combined.
In FIG. 13, a method for forming a device portion or the like is omitted.
In FIG. 13A, a first insulating film 221 is formed on a substrate 200 made of a silicon substrate by a method such as CVD (chemical vapor deposition).
In FIG. 13B, a groove structure (opening H) for forming a Cu metal wiring or a Cu contact plug is formed in the first insulating film 221 by photolithography and dry etching.
In FIG. 13C, a barrier metal film 240 and a Cu seed film are formed on the first insulating film 221 by PVD or CVD, and a Cu film 260 is formed in this order by plating. Annealing is performed at a temperature of about 30 minutes.
In FIG. 13D, the Cu film 260 and the barrier metal film 240 are removed by CMP and planarized to form a buried wiring made of Cu in the opening H that is a groove.
In FIG. 13E, a second insulating film 281 is formed after the surface of the Cu film 260 is subjected to reducing plasma treatment.
Furthermore, when forming multilayer Cu wiring, it is common to repeat these processes and to laminate. Here, most of the first insulating film 221 and the second insulating film 281 are low-k films.

  Also, regarding the plating method, in order to prevent the opening of the trench or via hole from being closed before the trench or via hole is completely filled, the plating current is interrupted or reduced during the filling of the trench or via hole. The technique to do is disclosed (for example, refer patent document 1).

In addition, in order to prevent the generation of voids, a technique is disclosed in which plating is first performed at a low current, metal is deposited inside the wiring trench, and then plating is performed to a predetermined film thickness by increasing the current (for example, patents). References 2 and 3). In addition, a technique is disclosed in which the plating current is gradually increased during the embedding in the via hole (see, for example, Patent Document 4).
JP 2000-195822 A JP 2000-80496 A JP 2003-110241 A JP 2003-318544 A

FIG. 14 is a processing sequence diagram of plating used conventionally.
The plating process is usually composed of two steps: an embedding step in a wiring groove and an overplate step for forming a certain film thickness thereon. As a first step, a metal film is embedded in fine wiring grooves and via holes. By keeping the current flowing from the anode electrode to the substrate low, the Cu deposition rate on the side walls of the trenches and via holes is slowed down, and embedding is performed by bottom-up growth from the bottom. Thereafter, as a second step, a desired film thickness is formed thereon, and the current used in this step is the same as or higher than the current used in the embedding step. However, the plating current affects the grain growth of the metal after plating. The higher the current, the faster the grain growth proceeds, and the shorter the time until the growth is completed and stabilized.

FIG. 15 is a graph comparing the average particle size of metal immediately after plating and after self-annealing when the film is formed in one step of only the plating current used in the embedding step and one step of only the current used in the overplate step. It is.
Immediately after plating, the film size was the same for both the deposition with the embedded current and the deposition with the overplate current. On the other hand, after self-annealing for a certain period of time, the film formation by the overplate current had a faster grain growth, and the grain size was about 10 times that immediately after plating.

FIG. 16 is a cross-sectional view for explaining a semiconductor device formed by plating in two steps of an embedding step and an overplate step.
FIG. 16A shows a state where plating is performed in two steps of an embedding step and an overplate step in an opening such as a hole. In the Cu film, there are small vacant point defects of, for example, 5 nm or less, which cannot be observed with an SEM (scanning electron microscope). In the case of a plurality of current steps, the overplate step film formed at a relatively high current is more likely to grow and stabilize faster than the embedding step film, and therefore exists in the embedding step film. The vacancies cannot be efficiently moved out of the film, and after the self-annealing for a certain period of time, the point defects existing in the buried step region cannot move to the overplate step region where the grains have grown. For this reason, as shown in FIG. 16B, the point defects existing in the embedding step region gather and form voids, so-called voids. Then, after flattening by CMP, voids remain in the Cu wiring as shown in FIG. Therefore, the embedding failure and conduction failure caused by the voids are caused.

  As described above, in the conventional plating method, the plating process is composed of the embedding step and the overplate step, and the plating current used in the overplate step is the same as or equal to the current used in the embedding step. Higher than. Therefore, the plated metal film formed in the overplate step is faster in the grain growth than the film in the embedding step, and it takes less time to complete and stabilize, so it exists in the film in the embedding step. Therefore, there is a problem in that the vacancies to be moved cannot be efficiently moved out of the film, and therefore, the embedding defect and the conduction defect due to the vacancies are caused.

  An object of the present invention is to overcome the above-described problems and prevent such voids from being formed in the Cu wiring.

A method for manufacturing a semiconductor device of the present invention includes:
An insulating film forming step of forming an insulating film on the substrate;
An opening forming step of forming an opening in the insulating film;
A seed film forming step of forming a seed film on the insulating film surface and the opening;
A first plating step of flowing a current having a first current density using the seed film as an electrode and depositing a conductive material in the opening by a plating method;
A second plating step of depositing the conductive material on the surface of the insulating film by a plating method by passing a current having a second current density lower than the first current density after the first plating step;
An annealing step of annealing the substrate on which the conductive material is deposited after the second plating step;
It is provided with.

  After the conductive material is embedded in the opening by the first plating step, the conductive material embedded in the opening is changed to a plating current having a second current density lower than the first current density. A conductive material film with slow progress of grain growth can be formed on the film. Therefore, it is possible to efficiently move the vacancies, which are point defects existing in the conductive material film embedded in the opening, to the upper portion, and as a result, move out of the film.

  Furthermore, in the second plating step, it is particularly effective that the second current density is 25 to 40% of the first current density.

In terms of current density, it is particularly effective when the first current density is ² to 5 A / cm ² and the second current density is 1.5 to 3 A / cm ² .

  In the method of manufacturing the semiconductor device, after the second plating step, a current having a third current density higher than the second current density is passed, and the conductive material is deposited on the insulating film surface by a plating method. A third plating step is further provided.

  By depositing the conductive material with a plating current having a third current density higher than the second current density, a desired film thickness is formed while ensuring a void escape field by the second plating step. The entire plating time can be shortened.

  In the third plating step, it is particularly effective to set the third current density to be twice or more the second current density.

  Furthermore, in the third plating step, the third current density is made larger than the first current density.

  The plating time can be further shortened by making the third current density larger than the first current density, which is larger than the second current density.

  Furthermore, in the second plating step, after the deposition, the conductive material deposited on the surface of the insulating film has a thickness equal to or greater than a value corresponding to the depth of the opening. It is characterized by depositing a functional material.

  A film plated by the second plating step outside the opening in the opening by depositing the conductive material so as to have a film thickness equal to or greater than a value corresponding to the depth of the opening. Can exist. Since the film plated by the second plating step can be present, the holes in the conductive material film deposited in the opening can move to the outside of the opening.

  In the third plating step, after deposition, the film thickness of the conductive material deposited on the surface of the insulating film is twice or more the value corresponding to the depth of the opening. Further, the conductive material is deposited on the surface of the insulating film after the second plating step.

  After the first, second, and third plating, the conductive material deposited on the surface of the insulating film has a film thickness that is twice or more the value corresponding to the depth of the opening. By doing so, filling leakage to the opening can be prevented when the semiconductor device is completed.

  After the conductive material is deposited on the entire opening by the first plating step, the process proceeds to the second plating step.

  By depositing the conductive material over the entire opening by the first plating step using a plating current having a high current density, the process proceeds to the second plating step using a plating current having a low current density, It is possible to form a hole escape field outside the opening and to shorten the plating time.

  In the first plating step, after depositing the conductive material in the opening, the conductive material having a predetermined thickness is further deposited on the surface of the insulating film.

  By further depositing the conductive material having a predetermined film thickness on the surface of the insulating film, even when openings having different dimensions exist, the openings to the openings having different dimensions by the first plating step are provided. Filling leakage can be prevented.

  According to the present invention, it is possible to efficiently move the vacancies, which are point defects existing in the conductive material film embedded in the opening, to the upper portion, and as a result, move out of the film. Formation of voids due to the collection of point defects can be suppressed. Since the formation of voids can be suppressed, poor filling and poor conduction can be reduced.

Embodiment 1 FIG.
In the first embodiment, a method for manufacturing a semiconductor device using a plating method in which a low current step is provided after an embedding step will be described.
FIG. 1 is a flowchart showing the main part of the semiconductor device manufacturing method according to the first embodiment.
In Figure 1, in this embodiment, as the insulating film formation step, the SiO ₂ film forming step (S102) of forming the SiO ₂ film, SiC film forming step (S104) of forming a SiC film, a porous insulating material A low-k film forming step (S106) for forming a low-k film using Hf, a helium (He) plasma processing step (S108) for plasma-treating the surface of the low-k film, and an SiO ₂ film forming step for forming an SiO ₂ film As a step (S110), an opening forming step (S112) for forming an opening, and a conductive material deposition step for depositing a conductive material, a barrier metal film forming step (S114), a seed film forming step (S116), A first plating step (S118), a second plating step (S120), a third plating step (S122), an annealing step (S124),
A series of steps called a planarization step (S126) is performed.

FIG. 2 is a process sectional view showing a process performed corresponding to the flowchart of FIG.
FIG. 2 shows from the SiO ₂ film forming step (S102) to the SiO ₂ film forming step (S110) in FIG. Subsequent steps will be described later.

In FIG. 2A, as a SiO ₂ film formation step, a base SiO ₂ film having a film thickness of, for example, 500 nm is deposited on the substrate 200 by a CVD method to form a SiO ₂ film 210. Here, the film is formed by the CVD method, but other methods may be used. As the substrate 200, for example, a substrate such as a silicon wafer having a diameter of 300 mm is used. Here, the formation of the device portion is omitted. Instead of the SiO ₂ film 210, a layer in which a device portion is formed, such as a metal wiring or a contact plug, may be formed. Alternatively, other layers may be formed. Similarly, a layer in which a device portion is formed, such as a metal wiring or a contact plug, may be formed on the base body 200. Alternatively, other layers may be formed.

In FIG. 2B, as a SiC film forming step, a base SiC film having a film thickness of 25 nm using SiC is deposited on the SiO ₂ film 210 by a CVD method to form a SiC film 212. Here, the film is formed by the CVD method, but other methods may be used. The SiC film 212 also has a function as an etching stopper. Since it is difficult to generate the SiC film, a silicon carbonate (SiOC) film may be used instead of the SiC film. Alternatively, a silicon carbonitride (SiCN) film or a silicon nitride (SiN) film can be used.

In FIG. 2C, as a low-k film forming step, a low-k using a porous insulating material on the SiC film 212 formed by the SiC insulating film forming step formed on the substrate 200. The k film 220 is formed with a thickness of 200 nm. By forming the low-k film 220, an interlayer insulating film having a relative dielectric constant k lower than 3.5 can be obtained. As a material of the low-k film 220, for example, porous methyl silsesquioxane (MSQ) can be used. As the formation method, for example, a SOD (spin on selective coating number and name, name of agent) method of forming a thin film by spin-coating a solution and heat-treating can be used. For example, the film is formed at a rotation speed of the spinner of 900 min ⁻¹ (900 rpm). The wafer is baked on a hot plate at a temperature of 250 ° C. in a nitrogen atmosphere, and finally cured on a hot plate at a temperature of 450 ° C. in a nitrogen atmosphere for 10 minutes. A porous insulating film having a predetermined physical property value can be obtained by appropriately adjusting the MSQ material, formation conditions, and the like. For example, the density is 0.7 g / cm ³ and the relative dielectric constant k is 1.8. The composition ratio of Si, O, and C in the low-k film is low-k having a physical property value in which Si is in the range of 25 to 35%, O is in the range of 45 to 57%, and C is in the range of 13 to 24%. A membrane 220 is obtained.

Then, as a He plasma treatment step, the surface of the low-k film 220 is modified by helium (He) plasma irradiation in a CVD apparatus. By modifying the surface by He plasma irradiation, the adhesion between the low-k film 220 and a CVD-SiO ₂ film 222 as a cap film to be described later formed on the low-k film 220 can be improved. . For example, the gas flow rate is 1.7 Pa · m ³ / s (1000 sccm), the gas pressure is 1000 Pa, the high frequency power is 500 W, the low frequency power is 400 W, and the temperature is 400 ° C. When the cap CVD film is formed on the low-k film, it is effective to improve the adhesion with the cap CVD film by subjecting the surface of the low-k film to plasma treatment. As types of plasma gas, ammonia (NH ₃ ), nitrous oxide (N ₂ O), hydrogen (H ₂ ), He, oxygen (O ₂ ), silane (SiH ₄ ), argon (Ar), nitrogen (N ₂ ) Among these, He plasma is particularly effective because it causes little damage to the low-k film. The plasma gas may be a mixture of these gases. For example, it is effective to use He gas mixed with other gases.

In FIG. 2 (d), the as SiO ₂ film forming step, said after the He plasma treatment, as a cap film, the SiO ₂ by a thickness of 100nm is deposited on the low-k film 220 by the CVD method, SiO ₂ A film 222 is formed. By forming the SiO ₂ film 222, the low-k film 220 that cannot be directly lithographically protected can be protected, and a pattern can be formed in the low-k film 220. Such cap CVD films include SiO ₂ films, SiC films, SiOC films, SiCN films, etc., but from the viewpoint of reducing damage, the SiO ₂ film is excellent, and from the viewpoint of reducing the dielectric constant, the SiOC film has improved breakdown voltage. From the viewpoint, the SiC film and the SiCN film are excellent. Furthermore, it is possible to use SiO ₂ film and the SiC film laminated film of, or SiO ₂ film and the SiCO film laminated film of, or a laminated film of SiO ₂ film and SiCN film. Further, a part or all of the cap CVD film may be removed by CMP in a planarization step described later. The dielectric constant can be further reduced by removing the cap film. The thickness of the cap film is preferably 10 nm to 150 nm, and 10 nm to 50 nm is effective in reducing the effective relative dielectric constant.

In the above description, the interlayer insulating film in the lower layer wiring may not be a low-k film having a relative dielectric constant of 3.5 or less, but is particularly effective when a low-k film is included.
Further, here, as a sample for confirming the effect of the plating method in which the low current step is provided after the embedding step, the total film of the insulating film composed of the SiO ₂ film 222, the low-k film 220 and the base SiC film 212. Although the thickness is 325 nm, the total thickness of the insulating film is desirably about 150 to 250 nm for a semiconductor device in which a wiring layer, a device, or the like is separately formed below the insulating film.

FIG. 3 is a process sectional view showing a process performed corresponding to the flowchart of FIG.
FIG. 3 shows from the opening forming step (S112) to the seed film forming step (S116) in FIG. Subsequent steps will be described later.

In FIG. 3A, as the opening forming process, the opening 150 which is a wiring groove structure for producing a damascene wiring by a lithography process and a dry etching process is formed by using an SiO ₂ film 222, a low-k film 220, and a base SiC film. 212. An exposed SiO ₂ film 222 and its underlying layer are formed on a substrate 200 on which a resist film is formed on the SiO ₂ film 222 through a resist coating process (not shown) and a lithography process such as forming a resist pattern by photolithography. The opening 150 may be formed by removing the positioned low-k film 220 by anisotropic etching using the underlying SiC film 212 as an etching stopper. By using the anisotropic etching method, the opening 150 can be formed substantially perpendicular to the surface of the substrate 200. For example, as an example, the opening 150 may be formed by a reactive ion etching method. Here, a via hole is formed as the opening 150. The diameter of the via hole was 100 nm at the bottom. By selecting dry etching conditions such that the SiC film almost stops, via holes having a depth of 300 nm can be formed in the uppermost Si oxide film and low-k film 220 with good controllability. Thus, a via hole having a via hole of 100 nm and a depth of 300 nm was formed. When a wiring, a device portion, or the like is separately provided below the underlying SiC film 212 as the semiconductor device, the underlying SiC film 212 may be further etched to form the opening 150 thereafter.

In FIG. 3B, as a barrier metal film forming step, a barrier metal film 240 using a barrier metal material is formed on the surface of the opening 150 and the SiO ₂ film 222 formed by the opening forming step. A laminated film of tantalum nitride (TaN) and tantalum (Ta) film is deposited in a thickness of 13 nm in a sputtering apparatus using a sputtering method which is one of physical vapor deposition (PVD) methods, and a barrier metal A film 240 is formed. By stacking the TaN film and the Ta film, the TaN film can prevent diffusion of Cu into the low-k film 220, and the Ta film can improve the adhesion of Cu. As a deposition method of the barrier metal material, for example, an atomic layer deposition (ALD method or an atomic layer chemical vapor deposition: ALCVD method), a CVD method, or the like can be used. The coverage can be improved as compared with the case of using the PVD method.

  In FIG. 3C, as a seed film forming process, a barrier metal film 240 is formed by using a Cu thin film serving as a cathode electrode in an electroplating process as a next process as a seed film 250 by a physical vapor deposition (PVD) method such as sputtering. Are deposited (formed) on the inner wall of the opening 150 and the surface of the substrate 200. Here, the seed film 250 is deposited to a thickness of 75 nm.

FIG. 4 is a process sectional view showing a process performed corresponding to the flowchart of FIG.
FIG. 4 shows from the first plating step (S118) to the annealing step (S124) in FIG. Subsequent steps will be described later.

In FIG. 4A, as a filling step which is a first plating process, a Cu film 260 is deposited on the surface of the opening 150 and the base 200 by electrochemical growth such as electrolytic plating using the seed film 250 as a cathode electrode. Here, for example, plating is performed at a current density of 3 A / cm ² . The current density is desirably ² to 5 A / cm ² . The plating time is desirably 50 to 60 seconds. By burying Cu at a current density of ² to 5 A / cm ² , Cu can be embedded in the opening without first closing the mouth of the opening.

In FIG. 4B, as a low current step which is the second plating step, a Cu film 262 is deposited on the opening 150 by electrochemical growth such as electrolytic plating by reducing the current density following the first plating step. Deposited on the Cu film 260 and the surface of the substrate 200. Here, plating is performed at a current density smaller than the current density in the first plating step, for example, at a current density of 2 A / cm ² . The current density is smaller than the current density in the first plating step, and is preferably 1.5 to 3 A / cm ² . The plating time is desirably 120 to 300 seconds. By plating at a current density smaller than the current density of the first plating step, a void escape field that is a point defect in the Cu film 260 formed in the first plating step can be formed. Therefore, it is desirable that the layer of the Cu film 262 formed in the second plating step is formed above the opening and outside the opening, but the layer of the Cu film 262 is formed inside the opening. It doesn't matter if it takes some. Even if the layer of the Cu film 262 partially covers the inside of the opening, if the layer of the Cu film 262 exists above the opening and outside the opening, a point defect in the Cu film 260 may occur. It is possible to form an escape space for a certain hole.

In the low current step, the total film thickness (the film thickness on the surface of the SiO ₂ film 222 in the embedding step and the low current step) on the substrate (on the surface of the SiO ₂ film 222) after Cu is deposited by the low current step is Plating is desirable so that the film thickness is equal to or greater than the depth of the opening 150. Depending on the width and diameter of the opening, the entire opening may not be filled unless a film thickness equal to or greater than the depth of the opening 150 is deposited on the substrate other than the opening. Therefore, by depositing a film thickness equal to or greater than the depth of the opening 150 on the substrate other than the opening, a layer of the Cu film 262 by the low current step can exist outside the opening. For example, assuming that the opening depth of a viable semiconductor device is 150 to 250 nm, it is desirable that Cu having a thickness of 150 to 250 nm is formed on the surface of the SiO ₂ film 222.

In FIG. 4C, as an overplate step which is the third plating step, the Cu film 264 is formed in the opening 150 and the substrate by electrochemical growth such as electrolytic plating by increasing the current density following the second plating step. It is deposited on the Cu film 262 deposited on the surface of 200. Here, the plating is performed at a current density higher than that of the first and second plating steps, for example, a current density of 6 A / cm ² . The current density is smaller than the current density in the first plating step, and is preferably 6 A / cm ² or more. The plating time is preferably 30 to 40 seconds. Plating time can be shortened by plating at a current density higher than that of the second plating step. Furthermore, the plating time can be further shortened by plating at a current density higher than that of the first plating step. Since the evacuation field of vacancies as point defects in the Cu film 260 has already been formed by the second plating step, it is desirable here to increase the current density in order to reduce the plating time. In the overplate step, it is effective to move after Cu is completely deposited in the opening.

In the manufacturing process of the effective semiconductor device, the total film thickness of the Cu film 260, the Cu film 262, and the Cu film 264 deposited on the surface of the insulating film after the deposition in the overplate step corresponds to the depth of the opening. Further, it is desirable to deposit a Cu film 264 on the surface of the insulating film after the low current step so that the film thickness is twice or more the value to be applied. By making the total film thickness at least twice the value corresponding to the depth of the opening, it is possible to prevent Cu filling leakage into the opening when the semiconductor device is completed. For example, assuming that the opening depth of a viable semiconductor device is 150 to 250 nm, Cu having a thickness of 300 to 500 nm is formed on the surface of the SiO ₂ film 222 after the final plating. desirable.

FIG. 5 is a conceptual diagram showing the configuration of the plating apparatus.
The plating apparatus includes a plating tank 650 having a substantially cylindrical shape and containing a plating solution 670 therein, and a holder 652 disposed above the plating tank 650 and detachably holding the substrate 101 with the plating surface facing downward. ing. As the plating solution 670, a solution containing copper sulfate as a main component and an additive may be used. FIG. 5A shows a state in which the holder 652 holds the substrate 101 at a position raised from the liquid surface of the plating solution 670. An anode electrode 654 having an upper surface exposed to the plating solution 670 is disposed at the bottom of the plating solution 670 in the plating tank 650. As the anode electrode 654, for example, a soluble anode such as phosphorous copper may be used. A plating solution 670 is supplied from the liquid injection nozzle 660 into the plating tank 650. The liquid injection nozzles 660 are preferably arranged at equal intervals in the circumferential direction. In the plating tank 650, the plating solution 670 sprayed from the liquid spray nozzle 660 collides at the central portion of the plating tank and forms a rising flow. The plating solution overflowing from the inside of the plating tank 650 is discharged from the discharge port 666. The discharge port 666 and the liquid injection nozzle 660 are connected to a plating solution management device (not shown), and the plating solution discharged from the discharge port 666 is subjected to component adjustment again by the plating solution management device and then plated from the liquid injection nozzle 660. Circulate into tank 650. The holder 652 is provided with a packing 684 in which a collar-shaped member is in contact with the outer peripheral portion of the substrate 101 so that the outer peripheral portion of the substrate 101 does not come into contact with the plating solution, and a seed layer is formed in an area where the plating solution does not touch the plating solution. A cathode side contact is connected to the outer periphery of the substrate 101. Then, as shown in FIG. 5 (b), the surface is immersed in the plating solution 670 while rotating the substrate 101, an anode electrode 654 is used as an anode, and a substrate 101 serving as a plating surface is used as a cathode, and a current having a predetermined current density is passed. Electrolytic plating is performed.

FIG. 6 is a plating processing sequence diagram according to the first embodiment.
As shown in FIG. 6, plating is performed while changing the current density in three steps: an embedding step, a low current step having a lower current density than the embedding step, and an overplate step having a higher current density than the embedding step.

  Here, for the purpose of confirming the effect of the low current step, the Cu film was formed by plating Cu having a total film thickness of 500 nm from the bottom surface of the groove to the top surface of the Cu film formed in the groove. That is, after filling the opening, Cu having a thickness of about 200 nm was deposited by a low current step and an overplate step. Of such about 200 nm, about half may be embedded at a low current step. Similarly, a sample plated by only the embedding step and the overplate step excluding the low current step was also prepared.

Then, as an annealing step, heat treatment was performed at a temperature of 150 ° C. in a 3% hydrogen (H ₂ ) / nitrogen (N ₂ ) atmosphere. In the annealing step, it is desirable to perform the treatment at a temperature of 150 ° C. to 400 ° C.

FIG. 7 is a process sectional view showing a process performed corresponding to the flowchart of FIG.
FIG. 7 shows the planarization step (S126) of FIG. As a planarization step, a Cu film 264, a Cu film 262, a Cu film 260, a seed film 250, and a barrier metal serving as a wiring layer as a conductive portion deposited on the surface of the SiO ₂ film 222 in addition to the opening by CMP. By polishing and removing the film 240, the film 240 is planarized to form a buried structure that becomes a Cu wiring as shown in FIG.

FIG. 8 is a cross-sectional view for explaining a semiconductor device formed by plating in two steps of an embedding step and an overplate step.
FIG. 8A shows a state where plating is performed in three steps of an embedding step, a low current step, and an overplate step in an opening such as a hole. In the plated Cu film, there exist small vacant point defects of, for example, 5 nm or less that cannot be observed with an SEM (scanning electron microscope). In the case of a plurality of current steps, the film of the low current step formed with a relatively low current is less likely to grow the grains than the film of the embedding step and is stabilized later, and as shown in FIG. In addition, vacancies existing in the film of the embedding step can be efficiently moved out of the film, and the point defects existing in the embedding step region are less likely to grow after self-annealing for a certain period of time. Move to the current step region. Therefore, after the point defects existing in the embedding step region are gathered and flattened by CMP without forming voids, so-called voids, voids are formed in the Cu wiring as shown in FIG. The formation of can be suppressed.

FIG. 9 is a diagram showing the void generation rate of the sample in the present embodiment.
As shown in FIG. 9A, in the conventional case where the low current step is not introduced, the void generation rate at the center portion of the substrate shown in FIG. 9B is 1%, and the void generation rate at the end portion is 2%. It was.
FIG. 10 is a diagram for comparing the occurrence locations of voids.
In the conventional case in which the low current step is not introduced, as shown in FIG. 10 (a), the void is generated at the center portion and at the end portion in the vicinity of the opening surface of the via hole and not at the side wall of the via hole. On the other hand, when the low current step was introduced, as shown in FIG. 10B, the void generation rate was 0% at both the center and the end, and satisfactory Cu plating embedding could be achieved.

FIG. 11 is a diagram showing the results of plating with and without low current steps.
Here, a comparison was made with vias having a diameter of 100 nm. As shown in FIG. 11A, in the conventional case where a low current step is not introduced, a void is formed. In contrast, as shown in FIG. 11B, no void was observed when the low current step was introduced.

  These results can be explained as follows. When the low current step is not introduced, there is a film formed at a higher current in the overplate step immediately above the plating film formed in the embedding step. Grain growth progresses faster and stabilizes faster in the overplate step film, so that the vacancies existing in the embedding step film where the grain growth is slow cannot move upward, so that the film is in the film, that is, in the via hole. Will stay on. Even if grain growth is promoted by the heat treatment, vacancies gather and remain as voids. On the other hand, when the low current step is introduced, the film formed at a lower current is directly above the plating film formed in the embedding step. The holes in the film of the embedding step can be moved upward, and as a result, the holes in the via hole can be reduced. Since the number of holes in the via hole can be reduced, it is possible to prevent generation of a void which is a set of such holes.

  As described above, after the filling step into the wiring trench is completed, by introducing a film formed with a current lower than the plating current value used in the filling step, the vacancies in the metal film after plating are made efficient. It is possible to move well out of the membrane and prevent defects due to intra-membrane vacancies.

Embodiment 2. FIG.
In the second embodiment, a method for manufacturing a semiconductor device in the case where a wide groove and a fine groove are present in the same layer will be described.
FIG. 12 is a cross-sectional view for explaining the semiconductor device in which Cu is plated in the second embodiment.
In FIG. 12, a via layer and an upper wiring layer are formed on the lower wiring 8. Here, the case where the via hole is buried by the dual damascene method together with the narrow groove 11 located in the upper wiring layer is shown. Moreover, the case where the narrow groove | channel 11 and the wide groove | channel 10 are formed in the upper wiring layer is shown. In the lower wiring layer, the lower wiring 8 is formed on an insulating film composed of an SiC film 212 serving as a base film, a low-k film 220, and an SiO ₂ film 222 serving as a cap film. In the via layer, a via hole is formed in an insulating film composed of an SiC film 275 and a low-k film 280 as a base film and an SiC film 286 as a cap film. In the upper wiring layer, an insulating film composed of a low-k film 285 and a SiO ₂ film 290 serving as a cap film on a SiC film 275 serving as a via layer serving as a base film, a narrow groove 11 and a wide groove 10 are formed. And are formed. A barrier metal film 242 and a seed film 252 are formed in the narrow groove 11, the wide groove 10, and the via hole under the narrow groove 11, and Cu is buried by a dual damascene method. Since the manufacturing method may be the same as that described in the first embodiment except that the dual damascene method is used, the description thereof is omitted.

As a first plating step, that is, an embedding step, Cu is embedded at a current density of ² to 5 A / cm ² . In such a case, a predetermined film thickness may be further deposited on the narrow groove 11 after the narrow groove 11 is buried. For example, when the narrow groove 11 is a hole-shaped hole, in order to fill the wide groove 10 having a width of about 3 μm with respect to the hole diameter of 100 to 200 nm, a film thickness of 100 to 150 nm is further formed on the narrow groove 11. It is good to deposit.

As a second plating step, that is, a low current step, Cu is embedded at a current density of 1.5 to 3 A / cm ² . In such a case, at the end of the low current step, the upper surface of Cu deposited by the low current step completely fills the outside of the wide groove 10, in other words, the wide groove 10 and further forms above the opening surface. It would be nice to have it. By forming also above the opening surface of the wide groove | channel 10, the area | region for the void | hole which is a point defect in Cu deposited inside the wide groove | channel 10 by the embedding step to move outside can be formed.

Then, as a third plating step, that is, an overplate step, Cu is embedded at a current density of 6 A / cm ² or more.

  As described above, in the filling step, it is desirable to fill the entire opening of the wide groove 10 with Cu. However, as shown in FIG. 12, the upper surface of Cu deposited by the low current step is larger than the opening of the wide groove 10. If it is also formed on the upper side, Cu may be filled at a low current step.

  Here, as the barrier metal in each of the above embodiments, in addition to TaN and Ta, refractory metals such as tantalum carbonitride (TaCN), tungsten nitride (WN), tungsten carbonitride (WCN), titanium nitride (TiN), etc. A nitride film or a carbon nitride film, or titanium (Ti) or tungsten (W) alone may be used. Alternatively, WSiN or the like may be used. Alternatively, a zirconium (Zr) -based barrier metal film may be used. Alternatively, a laminated film made of a plurality of these materials may be used.

  Here, as a material of the wiring layer in each of the above embodiments, a material mainly containing Cu used in the semiconductor industry, such as a Cu—Sn alloy, a Cu—Ti alloy, and a Cu—Al alloy, is used in addition to Cu. The same effect can be obtained.

  The embodiments have been described above with reference to specific examples. However, the present invention is not limited to these specific examples.

  For example, the substrate 200 on which an interlayer insulating film is formed in each embodiment can have various semiconductor elements or structures not shown. Further, an interlayer insulating film may be further formed on a wiring structure having an interlayer insulating film and a wiring layer instead of the semiconductor substrate. The opening may be formed so that the semiconductor substrate is exposed, or may be formed on the wiring structure.

  Further, the film thickness of the interlayer insulating film and the size, shape, number, and the like of the opening can be appropriately selected from those required in the semiconductor integrated circuit and various semiconductor elements.

  In addition, any semiconductor device manufacturing method that includes the elements of the present invention and whose design can be changed as appropriate by those skilled in the art is included in the scope of the present invention.

  In addition, for the sake of simplicity of explanation, techniques usually used in the semiconductor industry, such as a photolithography process, cleaning before and after processing, are omitted, but it goes without saying that these techniques are included.

3 is a flowchart showing a main part of a method for manufacturing a semiconductor device in the first embodiment. It is process sectional drawing showing the process implemented corresponding to the flowchart of FIG. It is process sectional drawing showing the process implemented corresponding to the flowchart of FIG. It is process sectional drawing showing the process implemented corresponding to the flowchart of FIG. It is a conceptual diagram which shows the structure of a plating apparatus. It is a processing sequence diagram of plating in the first embodiment. It is process sectional drawing showing the process implemented corresponding to the flowchart of FIG. It is sectional drawing for demonstrating the semiconductor device formed by plating in two steps, an embedding step and an overplate step. It is a figure which shows the void generation rate of the sample in this Embodiment. It is a figure for comparing the generation | occurrence | production location of a void. It is a figure which shows the result of plating by the presence or absence of a low current step. It is sectional drawing for demonstrating the semiconductor device of the state plated with Cu in Embodiment 2. FIG. It is process sectional drawing which shows the manufacturing method of the semiconductor device which has the multilayer wiring structure which combined the conventional low-k film | membrane and Cu wiring. It is a processing sequence figure of plating used conventionally. It is the graph which compared the average particle diameter of the metal immediately after plating and the self-annealing at the time of forming into a film by 1 step of only the plating current used at an embedding step, and 1 step of only the current used at an overplate step, respectively. It is sectional drawing for demonstrating the semiconductor device formed by plating in two steps, an embedding step and an overplate step.

Explanation of symbols

8 Lower layer wiring 10, 11 Groove 101 Substrate 150 Opening 200 Base 210, 222 SiO ₂ film 212, 275, 286 SiC film 220, 280, 285 Low-k film 221, 281 Insulating film 240, 242 Barrier metal film 250 Seed film 260, 262, 264 Cu film 650 Plating tank 652 Holder 654 Anode electrode 660 Liquid injection nozzle 666 Discharge port 670 Plating liquid 684 Packing

Claims (10)

An insulating film forming step of forming an insulating film on the substrate;
An opening forming step of forming an opening in the insulating film;
A seed film forming step of forming a seed film on the insulating film surface and the opening;
A first plating step of flowing a current having a first current density using the seed film as an electrode and depositing a conductive material in the opening by a plating method;
A second plating step of depositing the conductive material on the surface of the insulating film by a plating method by passing a current having a second current density lower than the first current density after the first plating step;
An annealing step of annealing the substrate on which the conductive material is deposited after the second plating step;
A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein, in the second plating step, the second current density is set to 25 to 40% of the first current density. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the first current density is ² to 5 A / cm < ² > and the second current density is 1.5 to 3 A / cm < ² >.   A third plating step of depositing the conductive material on the surface of the insulating film by a plating method by passing a current having a third current density higher than the second current density after the second plating step; 2. The method of manufacturing a semiconductor device according to claim 1, further comprising:   5. The method of manufacturing a semiconductor device according to claim 4, wherein, in the third plating step, the third current density is set to be twice or more the second current density.   5. The method of manufacturing a semiconductor device according to claim 4, wherein, in the third plating step, the third current density is made larger than the first current density.   In the second plating step, after deposition, the conductive material deposited on the surface of the insulating film has a thickness equal to or greater than a value corresponding to the depth of the opening. The method of manufacturing a semiconductor device according to claim 1, wherein: is deposited.   In the third plating step, after deposition, the film thickness of the conductive material deposited on the surface of the insulating film is twice or more the value corresponding to the depth of the opening. The method of manufacturing a semiconductor device according to claim 4, further comprising depositing the conductive material on the surface of the insulating film after the second plating step.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the conductive material is deposited on the entire opening by the first plating step, and then the process proceeds to the second plating step.   10. The method according to claim 9, wherein, in the first plating step, after the conductive material is deposited in the opening, the conductive material having a predetermined thickness is further deposited on the surface of the insulating film. A method for manufacturing a semiconductor device.