WO2005076351A1 - 部品内蔵モジュールおよびその製造方法 - Google Patents
部品内蔵モジュールおよびその製造方法 Download PDFInfo
- Publication number
- WO2005076351A1 WO2005076351A1 PCT/JP2005/000052 JP2005000052W WO2005076351A1 WO 2005076351 A1 WO2005076351 A1 WO 2005076351A1 JP 2005000052 W JP2005000052 W JP 2005000052W WO 2005076351 A1 WO2005076351 A1 WO 2005076351A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- resin
- multilayer substrate
- cavity
- ceramic multilayer
- main surface
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Definitions
- the present invention relates to a component built-in module formed by providing a cavity on the bottom side of a ceramic multilayer substrate, accommodating a circuit component therein, and then performing resin molding, and a method of manufacturing the module.
- Various high-frequency modules such as a chip antenna, a delay line, a high-frequency composite switch module, and a receiving device are mounted inside an information communication device such as a mobile terminal.
- a high-frequency module is used in a state mounted on a mounting board such as a printed wiring board.
- a circuit element is generally mounted on a multilayer substrate.
- Patent Document 1 a crystal resonator is mounted on a ceramic multilayer substrate, a cavity is formed on the bottom surface of the ceramic multilayer substrate, an IC chip is accommodated in the cavity, and a surface mounting is performed by resin molding.
- Type crystal oscillators have been proposed.
- the external terminal electrodes are formed in a frame portion around the cavity on the mounting surface of the ceramic multilayer substrate.
- FIG. 9 (a) is a view of such a ceramic multilayer substrate as viewed from the back side.
- the ceramic multilayer substrate 50 has a cavity 51 on the bottom surface, and a mold resin 52 is molded in the cavity 51. It has the structure which was done.
- An external terminal electrode 54 is formed in a frame 53 around the cavity 51.
- Patent Document 1 JP-A-2000-77942
- the width of the frame portion 53 must be reduced as shown in FIG. 9 (b). This is because the number and size of circuit components cannot be changed in the circuit design, so that the area of the cavity 51 cannot be reduced. Therefore, the area of the external terminal electrodes 54 cannot be sufficiently secured, and connection failure easily occurs when the external terminal electrodes 54 are mounted on a mounting board such as a mother board. In addition, even if the connection is made normally, the connection area is small due to the small impact area, and the connection part peels off due to the impact of an external force, and immediately causes a problem in connection reliability.
- the mold resin 52 is formed by pouring a liquid resin and then pouring the resin. Since the resin is cured, the surface may be dented due to cure shrinkage or the like, or the resin may rise, making it difficult to form a flat surface. Therefore, it is suitable for forming the external terminal electrode 54! /, Na! / ,.
- an object of the present invention is to provide a cavity on the mounting surface side of a ceramic multilayer substrate, accommodate a circuit component therein, and then perform a resin-molded component built-in module having a sufficient area.
- An object of the present invention is to provide a small module with a built-in component, which can stably form an external terminal electrode and has excellent mountability, and a method of manufacturing the module.
- the invention according to claim 1 includes a plurality of ceramic layers laminated, one main surface and the other main surface, and the one main surface has a cavity and the cavity.
- a ceramic multilayer substrate having a surrounding frame-shaped portion formed therein, a first circuit component housed and fixed in the cavity, and a second mold molded in the cavity so as to bury the first circuit component.
- the first resin portion and the first main surface of the ceramic multilayer substrate, the frame portion and the first resin portion so as to continuously cover the frame portion and the first resin portion.
- a second resin part joined to the resin part and having an external terminal electrode on a main surface exposed to the outside.
- the invention according to claim 7 is characterized in that a plurality of ceramic layers are laminated, one main surface and the other main surface are provided, and the one main surface includes a cavity and a frame-shaped portion surrounding the cavity.
- a second resin portion that covers the cavity and the frame-shaped portion is provided.
- external terminal electrodes are formed. Even if the surface of the first resin part molded into the cavity has a concave part and a convex part, the second resin part can absorb these irregularities and flatten the surface, so that the external terminal electrode It is suitable as a site for forming. Therefore, the external terminal electrode can be formed regardless of the size of the cavity, and the external terminal electrode having a sufficient area can be formed.
- the circuit component may be an active element such as a transistor, an IC, or an LSI, or a passive element such as a chip capacitor, a chip resistor, a chip thermistor, or a chip inductor.
- the land electrode and the circuit component may be electrically connected by wire bonding, or the electrode of the circuit component may be soldered to the land electrode or conductive. It may be directly mounted with a conductive adhesive, or may be flip-chip mounted. The mounting method is optional.
- the formation site of the external terminal electrode was limited to the frame-shaped portion of the ceramic multilayer substrate.
- the external terminal electrode is formed on the surface of the second resin portion. Even if the portion protrudes to the region facing the cavity, no problem occurs, and it is possible to form the external terminal electrode having a wider area.
- an external terminal electrode entirely disposed in a region facing the cavity. That is, it is possible to form the external terminal electrode even in a region where it could not be formed conventionally.
- an internal circuit element is formed inside the ceramic multilayer substrate, and a relay electrode electrically connected to the internal circuit element at an interface between the frame-shaped portion and the second resin portion. Is formed, and a via conductor for electrically connecting the relay electrode and the external terminal electrode is formed inside the second resin portion.
- the internal circuit element is a general term for an internal conductor disposed between layers of the ceramic multilayer substrate and a via conductor penetrating the ceramic multilayer substrate in the thickness direction.
- an electric connection with the internal circuit elements is provided at an interface between the frame-shaped portion and the second resin portion. If the relay electrode is formed and a via conductor for electrically connecting the relay electrode and the external terminal electrode is formed inside the second resin portion, the connection can be made easily and reliably. Also, no electrodes are formed on the outer peripheral surfaces of the ceramic multilayer substrate and the second resin layer. Then, the first resin layer can be molded and the second resin layer can be joined to the ceramic multi-layer substrate in the parent substrate state, and then divided by cutting or breaking into individual pieces. A manufacturing method excellent in mass productivity can be provided.
- an internal circuit element is formed inside the ceramic multilayer substrate, and a land electrode electrically connected to the internal circuit element is formed on the other main surface of the ceramic multilayer substrate.
- the second circuit component may be mounted on the land electrode.
- a case that covers the second circuit component may be placed on the other main surface of the ceramic multilayer substrate.
- a third resin portion molded so as to bury the second circuit component on the other main surface of the ceramic multilayer substrate may be provided.
- the mold resin can protect the circuit component, and can also be attracted by the mounter.
- the second resin portion includes a resin sheet made of a thermosetting resin in a semi-cured state on one main surface of the ceramic multilayer substrate. It is formed by press-bonding so as to continuously cover the resin portion.
- the semi-cured state refers to a B-stage state or a pre-prepared state.
- the second resin portion has not yet been cured, so that the unevenness of the first resin portion can be absorbed and the outer surface thereof can be flattened.
- An external terminal electrode is formed on the outer surface of the second resin layer.
- the external terminal electrode may be formed after the second resin layer is cured, or may be formed simultaneously with the pressure bonding.
- a support plate with external terminal electrodes such as copper foil Prepare, press-fit the support plate to one main surface of the ceramic multilayer substrate with the semi-cured second resin part in between, and peel off the support plate after the second resin part is cured, so that the external terminals It is possible to transfer the electrode to the second resin part.
- the curing order of the first resin portion and the second resin portion is as described in claim 8, after the first resin portion is cured first, and then the second resin portion is press-bonded. After joining, the second resin part may be cured, or the second resin part may be press-bonded while the first resin part is in an uncured state, as in claim 9. Thereafter, the first and second resin parts may be simultaneously cured.
- the second resin portion is pressure-bonded after the first resin portion has hardened, so that the second resin portion can easily absorb irregularities of the first resin portion.
- the curing step only needs to be performed once.
- the second resin covering the first resin portion and the frame-shaped portion is formed. Since the resin portion was provided and the external terminal electrodes were formed on the surface, even if the surface of the first resin portion had a concave portion or a convex portion, the second resin portion absorbed the unevenness, and the surface was removed. Can be flat. Therefore, the external terminal electrode can be formed regardless of the size of the cavity, and the external terminal electrode having a required size can be formed.
- the second resin layer can remove irregularities in the first resin part. Since the resin can be absorbed, the amount of resin injected into the cavity can be easily controlled, and the production yield can be improved.
- FIG. 1 is a cross-sectional view of a first embodiment of a component built-in module according to the present invention.
- FIG. 2 is a bottom view of the component built-in module shown in FIG. 1.
- FIG. 3 is a sectional view of a module with a built-in component according to a second embodiment of the present invention.
- FIG. 4 is a cross-sectional view of a module with a built-in component according to a third embodiment of the present invention.
- FIG. 5 is a sectional view of a module with a built-in component according to a fourth embodiment of the present invention.
- FIG. 6 is a sectional view of a module with a built-in component according to a fifth embodiment of the present invention.
- FIG. 7 is a view showing a manufacturing process of the component built-in module shown in FIG. 1.
- FIG. 8 is a bottom view of another embodiment of the component built-in module according to the present invention.
- FIG. 9 is a bottom view of a conventional component built-in module.
- FIG. 1 and 2 show a first embodiment of a component built-in module according to the present invention.
- This component built-in module includes a ceramic multilayer substrate 1 having a plurality of ceramic layers, a first resin portion 15 molded in a cavity 4 formed on the lower surface of the ceramic multilayer substrate 1, and a lower surface of the ceramic multilayer substrate 1. It is composed of a second resin part 20 fixed on the entire surface.
- the ceramic multilayer substrate 1 is, for example, a low-temperature fired ceramic multilayer substrate (LTCC), in which the internal electrodes 2 are provided between a plurality of ceramic layers, and the via conductors 3 penetrating the ceramic layers in the thickness direction are provided. And are integrally fired.
- LTCC low-temperature fired ceramic multilayer substrate
- a multilayer capacitor, a multilayer inductor, and the like can be integrally formed in the ceramic multilayer substrate 1.
- a cavity 4 and a frame 5 surrounding the cavity 4 are formed on the lower surface of the ceramic multilayer substrate 1.
- a first circuit component 6 is fixed to the bottom of the cavity 4, and the circuit component 6 is electrically connected to an electrode 7 formed on a step portion inside the cavity 4 by a bonding wire 8.
- a first resin part 15 made of a thermosetting resin is molded in the cavity 4.
- the surface of the first resin portion 10 is concave compared to the surface of the frame portion 5.
- a plurality of relay electrodes 9 are formed on the lower surface of the frame portion 5, and the relay electrodes 9 are electrically connected to the internal electrodes 2 via the via conductors 3.
- a plurality of land electrodes 10 are formed on the upper surface of the ceramic multilayer substrate 1, and these land electrodes 10 are also electrically connected to the internal electrodes 2 via the via conductors 3.
- the second circuit component 11 is mounted on the land electrode 10.
- a second resin portion 20 is joined to the lower surface of the ceramic multilayer substrate 1 so as to continuously cover the frame portion 5 and the first resin portion 15.
- the second resin part 20 it is desirable to use a thermosetting resin having a composition close to that of the first resin part 15.
- the same thermosetting resin is used. Yes.
- the adhesion between the resin parts 15 and 20 is improved, and peeling of the resin parts 15 and 20 and intrusion of moisture into the interface can be prevented.
- the second resin part 20 fills the recess of the first resin part 15, and the outer surface of the second resin part 20 is formed almost flat.
- a plurality of external terminal electrodes 21 are provided on a flat outer surface of the second resin part 20.
- a part of the external terminal electrode 21 is formed so as to protrude by a dimension A in a region facing the cavity 4 as shown in the figure. That is, it protrudes inward from the frame portion 5. Therefore, the external terminal electrode 21 having a sufficient size can be formed even if the width dimension force S of the frame portion 5 is small.
- Each external terminal electrode 21 is electrically connected to the relay electrode 9 via a via conductor 22 formed in the second resin layer 20 in the thickness direction.
- the circuit components 6 fixed in the cavity 4 and the circuit components 11 mounted on the upper surface of the ceramic multilayer substrate 1 include active elements such as ICs and LSIs, chip capacitors, chip resistors, chip thermistors, chip inductors, and the like. , A passive element such as a filter can be used.
- the mounting method of the circuit component 6 is not limited to the connection method by wire bonding, but may be mounting by solder or conductive adhesive, or flip-chip mounting using bumps.
- the method of mounting the circuit component 11 is not limited to mounting using solder or a conductive adhesive, but may be connection by wire bonding or flip-chip mounting using bumps.
- the second resin portion 20 is a mixture of a thermosetting resin and an inorganic filler as appropriate.
- the lower surface of the frame portion 5 and the lower surface of the first resin portion 15 are semi-hardened. It is pressed and hardened.
- the via conductor 22 formed in the second resin part 20 is obtained by embedding and curing a conductive resin in a through hole provided in the resin part 20.
- the external terminal electrode 21 is provided on the lower surface of the resin portion 20. By connecting the external terminal electrode 21 to a printed circuit board or the like, the component built-in module can be mounted on a printed circuit board or the like. Can be.
- the resin portion 20 can function as a shock absorbing layer for protecting the ceramic multilayer substrate 1 against a drop impact and a thermal shock.
- FIG. 3 shows a second embodiment of the component built-in module.
- the component built-in module shown in FIG. 1 is an example in which the surface of the molded first resin portion 15 is dented in a concave shape due to hardening shrinkage. May go up.
- FIG. 3 shows a case where the first resin portion 15 is cured while being raised from the surface of the frame portion 5.
- the second resin portion 20 absorbs the unevenness of the first resin portion 15, and the outer surface of the second resin portion 20 is formed almost flat.
- a plurality of external terminal electrodes 21 are provided on a flat outer surface of the second resin portion 20.
- the second resin portion 20 absorbs the unevenness, so that the second resin portion 20 absorbs the unevenness.
- the surface of the resin portion 20 can be flattened. Therefore, the external terminal electrode 21 having an arbitrary size can be easily formed.
- FIG. 4 shows a third embodiment of the component built-in module.
- the second resin portion 20 is formed of a multilayer resin substrate, and the internal electrodes 23 are provided between the layers, thereby integrally forming elements such as a multilayer capacitor and a multilayer inductor inside. .
- the internal electrode 23 is a ground electrode, it is useful to use it as a shield for the circuit component 6 in the cavity.
- an individual element such as an SMD may be embedded.
- FIG. 5 shows a fourth embodiment of the component built-in module.
- a case 30 that covers the circuit element 11 is placed on the surface of the ceramic multilayer substrate 1.
- a resin case or a metal case can be used.
- a nickel-white phosphor bronze or the like is preferable in view of processing simplicity and cost.
- FIG. 6 shows a fifth embodiment of the component built-in module.
- a resin 31 is molded on the surface of the ceramic multilayer substrate 1 to cover the circuit element 11.
- ceramic multilayer substrate 1 When molding resin 31 on the surface of ceramic multilayer substrate 1, ceramic multilayer substrate 1 If the thermal expansion coefficients of the resin layer 31 on the front side and the resin layers 15 and 20 on the back side differ, the ceramic multilayer substrate 1 may warp or break due to thermal history. Are of the same composition or have similar thermal expansion coefficients, and it is preferable to use a material.
- the ceramic multilayer substrate 1 is prepared.
- the ceramic multilayer substrate 1 is manufactured as follows.
- a ceramic slurry is applied on a resin film such as PET and dried to obtain a ceramic green sheet with a thickness of about 10 to 200 m.
- a ceramic powder contained in the ceramic slurry for example, a mixture of BaO, SiO 2, A 1 O, B O, CaO, etc. can be used.
- the same conductive paste as described above is printed in a desired pattern on the green sheet by screen printing or the like, and dried. This is the internal electrode 2.
- the relay electrode 9 and the land electrode 10 are formed on the front and back surfaces of the pressed laminate using the same conductive paste as described above.
- the conductive paste is Ag-based, it is around 850 ° C in air.
- the thickness of the laminate is, for example, about lmm. After baking, a film of NiZSn or NiZAu is formed on the electrodes exposed on the front and back surfaces as required.
- the ceramic multilayer substrate 1 is manufactured as described above, the circuit component 6 is fixed to the bottom of the cavity 4 of the ceramic multilayer substrate 1, and the electrode 7 and the circuit component 6 are electrically connected by wire bonding 8. The result is as shown in FIG. Next, the cavity 4 of the ceramic multilayer substrate 1 is filled with a liquid resin 15 and cured to form a first resin portion 15 as shown in FIG. 7B.
- the liquid resin 15 is made of a thermosetting resin (epoxy, phenol, cyanate, etc.). Note that the surface of the resin portion 15 in the cured state may be dented.
- FIG. 7 (c) shows that after the first resin portion 15 is cured, the ceramic multilayer substrate 1 is turned over, and a semi-cured resin sheet 20A and a support 25 are disposed below the ceramic multilayer substrate 1. It shows the state where it was done.
- the resin sheet 20A is made of a thermosetting resin (epoxy, phenol, cyanate, etc.) mixed with an inorganic filler (Al 2 O 3, SiO 2, TiO 2, etc.).
- the semi-cured state refers to the B-stage state or pre-predator state.
- the via hole 22 is filled with a conductive resin (a mixture of metal particles such as Au, Ag, Cu, and Ni and a thermosetting resin such as epoxy, phenol, and cyanate).
- a conductive resin a mixture of metal particles such as Au, Ag, Cu, and Ni and a thermosetting resin such as epoxy, phenol, and cyanate.
- solder may be filled by reflow or the like after pressure bonding with the ceramic multilayer substrate 1.
- the support 25 is made of a metal plate or the like, and a copper foil having a thickness of about 10 to 40 m is plated or adhered on the upper surface thereof, and the copper foil is subjected to the steps of photoresist coating, exposure, development etching, and resist peeling, and then the copper foil is removed. Pattern. This becomes the external terminal electrode 21.
- the resin sheet 20A and the support body 25 prepared as described above are positioned with respect to the ceramic multilayer substrate 1, and are heated and pressed.
- the semi-cured resin sheet 20A was pressed against the upper surface of the support 25 and simultaneously molded with the lower surface of the ceramic multilayer substrate 1, that is, the lower surface of the frame portion 5 on which the relay electrode 9 was formed. It is pressed against the surface of the first resin part 15. At this time, a part of the resin sheet 20A is embedded in the surface of the concave first resin part 15. With the support 25 pressed, the resin sheet 20A is cured by heating.
- the via conductors 22 provided on the resin sheet 20A are cured by the heat and pressure bonding, and are electrically connected to the external terminal electrodes 21 on the support 25, and at the same time, the relay electrodes 9 formed on the lower surface of the frame portion 5 are formed. Are electrically connected to each other.
- the ceramic multilayer substrate 1 and the resin layer 20 are laminated and pressure-bonded in a parent substrate state, and then the individual components are joined in order to enhance the productivity described in the method of manufacturing a single component built-in module. You can cut or break into pieces! / ,.
- the second resin portion 20 in the semi-cured state is pressure-bonded to the first resin portion 15 in the cured state.
- the second resin portion 20 in a semi-cured state may be press-bonded, and both resin portions 15, 20 may be simultaneously heated and cured.
- the two-stage cavity described above may be a one-stage cavity or a three-stage cavity or more. Further, a plurality of cavities may be formed side by side.
- FIG. 2 shows an example in which the external terminal electrodes 21 are arranged around the second resin portion 20. As shown in FIG. 8, the external terminal electrodes 21 can be arranged on the entire surface.
- the second resin portion 20 is formed of a multilayer substrate, a circuit is formed inside the second resin portion 20 or at the interface with the first resin portion 15 so that the external terminal electrode 21 can be arbitrarily formed as shown in FIG. Can be arranged at the position.
- the surface of the first resin portion 15 is concave or convex
- the surface may be flat.
- the surface of the first resin portion 15 can be made flat by controlling the resin type and the amount of the resin, and furthermore, by hot pressing or surface polishing of the first resin portion 15.
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005517630A JP4367414B2 (ja) | 2004-02-09 | 2005-01-06 | 部品内蔵モジュールおよびその製造方法 |
US11/462,395 US7569925B2 (en) | 2004-02-09 | 2006-08-04 | Module with built-in component |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004-031595 | 2004-02-09 | ||
JP2004031595 | 2004-02-09 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/462,395 Continuation US7569925B2 (en) | 2004-02-09 | 2006-08-04 | Module with built-in component |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2005076351A1 true WO2005076351A1 (ja) | 2005-08-18 |
Family
ID=34836055
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2005/000052 WO2005076351A1 (ja) | 2004-02-09 | 2005-01-06 | 部品内蔵モジュールおよびその製造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7569925B2 (ja) |
JP (1) | JP4367414B2 (ja) |
CN (1) | CN100472764C (ja) |
WO (1) | WO2005076351A1 (ja) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007158228A (ja) * | 2005-12-08 | 2007-06-21 | Nichicon Corp | 温度補償回路基板 |
JP2007318076A (ja) * | 2006-05-25 | 2007-12-06 | Samsung Electro Mech Co Ltd | Sipモジュール |
JP2009088339A (ja) * | 2007-10-01 | 2009-04-23 | Denso Corp | 電子装置 |
JPWO2007049417A1 (ja) * | 2005-10-24 | 2009-04-30 | 株式会社村田製作所 | 回路モジュールの製造方法および回路モジュール |
JP2017195708A (ja) * | 2016-04-20 | 2017-10-26 | 株式会社村田製作所 | Icチップ実装基板 |
WO2020071021A1 (ja) * | 2018-10-05 | 2020-04-09 | 株式会社村田製作所 | 高周波モジュールおよび通信装置 |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005317861A (ja) * | 2004-04-30 | 2005-11-10 | Toshiba Corp | 半導体装置およびその製造方法 |
US8335084B2 (en) * | 2005-08-01 | 2012-12-18 | Georgia Tech Research Corporation | Embedded actives and discrete passives in a cavity within build-up layers |
DE102006007381A1 (de) * | 2006-02-15 | 2007-08-23 | Infineon Technologies Ag | Halbleiterbauelement für einen Ultraweitband-Standard in der Ultrahochfrequenz-Kommunikation und Verfahren zur Herstellung desselben |
US7592202B2 (en) * | 2006-03-31 | 2009-09-22 | Intel Corporation | Embedding device in substrate cavity |
TWI292947B (en) * | 2006-06-20 | 2008-01-21 | Unimicron Technology Corp | The structure of embedded chip packaging and the fabricating method thereof |
TWI360207B (en) | 2007-10-22 | 2012-03-11 | Advanced Semiconductor Eng | Chip package structure and method of manufacturing |
KR101438826B1 (ko) * | 2008-06-23 | 2014-09-05 | 엘지이노텍 주식회사 | 발광장치 |
CN101986540A (zh) * | 2009-06-15 | 2011-03-16 | Tdk兰达美国股份有限公司 | 电源装置及其制造方法 |
US9072204B2 (en) * | 2009-07-17 | 2015-06-30 | Panasonic Intellectual Property Management Co., Ltd. | Electronic module and production method therefor |
KR20110019536A (ko) * | 2009-08-20 | 2011-02-28 | 삼성전기주식회사 | 세라믹 기판 및 그 제조방법 |
US8569894B2 (en) | 2010-01-13 | 2013-10-29 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with single sided substrate design and manufacturing methods thereof |
TWI411075B (zh) | 2010-03-22 | 2013-10-01 | Advanced Semiconductor Eng | 半導體封裝件及其製造方法 |
US9077344B2 (en) * | 2010-12-07 | 2015-07-07 | Atmel Corporation | Substrate for electrical component and method |
US9406658B2 (en) | 2010-12-17 | 2016-08-02 | Advanced Semiconductor Engineering, Inc. | Embedded component device and manufacturing methods thereof |
CN103608915B (zh) * | 2011-06-21 | 2016-09-07 | 株式会社村田制作所 | 电路模块 |
JP5870808B2 (ja) | 2012-03-28 | 2016-03-01 | 富士通株式会社 | 積層モジュール |
US9392695B2 (en) * | 2014-01-03 | 2016-07-12 | Samsung Electro-Mechanics Co., Ltd. | Electric component module |
CN106463465B (zh) * | 2014-05-28 | 2019-02-15 | 日本特殊陶业株式会社 | 布线基板 |
US9190367B1 (en) | 2014-10-22 | 2015-11-17 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure and semiconductor process |
CN105047632B (zh) * | 2014-11-25 | 2017-07-28 | 成都振芯科技股份有限公司 | 一种小型化高隔离度陶瓷封装结构 |
WO2018110393A1 (ja) * | 2016-12-14 | 2018-06-21 | 株式会社村田製作所 | スイッチic、フロントエンドモジュール及び通信装置 |
WO2019181589A1 (ja) * | 2018-03-23 | 2019-09-26 | 株式会社村田製作所 | 高周波モジュールおよび通信装置 |
WO2019181590A1 (ja) * | 2018-03-23 | 2019-09-26 | 株式会社村田製作所 | 高周波モジュールおよび通信装置 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63114240A (ja) * | 1986-10-31 | 1988-05-19 | Mitsubishi Electric Corp | 半導体装置 |
JP2000077942A (ja) * | 1998-08-31 | 2000-03-14 | Kyocera Corp | 表面実装型水晶発振器 |
JP2002246507A (ja) * | 2000-12-15 | 2002-08-30 | Ibiden Co Ltd | 多層プリント配線板 |
JP2004259714A (ja) * | 2003-02-24 | 2004-09-16 | Murata Mfg Co Ltd | 多層セラミック基板を備える電子部品およびその製造方法 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3793547B2 (ja) * | 1997-05-28 | 2006-07-05 | 京セラ株式会社 | 積層セラミック回路基板の製造方法 |
JP3426574B2 (ja) | 1997-07-24 | 2003-07-14 | 協和化成株式会社 | 表面実装部品及びその製造方法 |
JPH11150202A (ja) | 1997-11-18 | 1999-06-02 | Kyocera Corp | 電子部品収納用パッケージ |
JP3582460B2 (ja) * | 2000-06-20 | 2004-10-27 | 株式会社村田製作所 | 高周波モジュール |
JP2002026187A (ja) * | 2000-07-07 | 2002-01-25 | Sony Corp | 半導体パッケージ及び半導体パッケージの製造方法 |
JP4234889B2 (ja) | 2000-07-31 | 2009-03-04 | 京セラ株式会社 | 電子部品 |
JP4507452B2 (ja) | 2001-05-17 | 2010-07-21 | パナソニック株式会社 | 電子部品、その製造方法及び電子回路装置 |
JPWO2002079114A1 (ja) * | 2001-03-28 | 2004-07-22 | 株式会社村田製作所 | 絶縁体セラミック組成物およびそれを用いた絶縁体セラミック |
JP4243922B2 (ja) * | 2001-06-26 | 2009-03-25 | イビデン株式会社 | 多層プリント配線板 |
JP3890947B2 (ja) | 2001-10-17 | 2007-03-07 | 松下電器産業株式会社 | 高周波半導体装置 |
TW557521B (en) * | 2002-01-16 | 2003-10-11 | Via Tech Inc | Integrated circuit package and its manufacturing process |
JP4373121B2 (ja) * | 2003-04-17 | 2009-11-25 | 日本ミクロン株式会社 | 半導体装置の製造方法 |
JP4208631B2 (ja) * | 2003-04-17 | 2009-01-14 | 日本ミクロン株式会社 | 半導体装置の製造方法 |
-
2005
- 2005-01-06 WO PCT/JP2005/000052 patent/WO2005076351A1/ja active Application Filing
- 2005-01-06 CN CNB2005800019083A patent/CN100472764C/zh active Active
- 2005-01-06 JP JP2005517630A patent/JP4367414B2/ja active Active
-
2006
- 2006-08-04 US US11/462,395 patent/US7569925B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63114240A (ja) * | 1986-10-31 | 1988-05-19 | Mitsubishi Electric Corp | 半導体装置 |
JP2000077942A (ja) * | 1998-08-31 | 2000-03-14 | Kyocera Corp | 表面実装型水晶発振器 |
JP2002246507A (ja) * | 2000-12-15 | 2002-08-30 | Ibiden Co Ltd | 多層プリント配線板 |
JP2004259714A (ja) * | 2003-02-24 | 2004-09-16 | Murata Mfg Co Ltd | 多層セラミック基板を備える電子部品およびその製造方法 |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPWO2007049417A1 (ja) * | 2005-10-24 | 2009-04-30 | 株式会社村田製作所 | 回路モジュールの製造方法および回路モジュール |
JP4702370B2 (ja) * | 2005-10-24 | 2011-06-15 | 株式会社村田製作所 | 回路モジュールの製造方法 |
JP2007158228A (ja) * | 2005-12-08 | 2007-06-21 | Nichicon Corp | 温度補償回路基板 |
JP2007318076A (ja) * | 2006-05-25 | 2007-12-06 | Samsung Electro Mech Co Ltd | Sipモジュール |
JP2009088339A (ja) * | 2007-10-01 | 2009-04-23 | Denso Corp | 電子装置 |
JP2017195708A (ja) * | 2016-04-20 | 2017-10-26 | 株式会社村田製作所 | Icチップ実装基板 |
WO2020071021A1 (ja) * | 2018-10-05 | 2020-04-09 | 株式会社村田製作所 | 高周波モジュールおよび通信装置 |
US11348887B2 (en) | 2018-10-05 | 2022-05-31 | Murata Manufacturing Co., Ltd. | Radio-frequency module and communication device |
Also Published As
Publication number | Publication date |
---|---|
CN100472764C (zh) | 2009-03-25 |
JP4367414B2 (ja) | 2009-11-18 |
JPWO2005076351A1 (ja) | 2007-08-02 |
US7569925B2 (en) | 2009-08-04 |
US20060284300A1 (en) | 2006-12-21 |
CN1906759A (zh) | 2007-01-31 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2005076351A1 (ja) | 部品内蔵モジュールおよびその製造方法 | |
US7446262B2 (en) | Laminated electronic component and method for producing the same | |
KR100753499B1 (ko) | 전자 부품 및 그 제조 방법 | |
US7488897B2 (en) | Hybrid multilayer substrate and method for manufacturing the same | |
EP1304909B1 (en) | High-frequency semiconductor device | |
JP3709882B2 (ja) | 回路モジュールとその製造方法 | |
JP4453702B2 (ja) | 複合型電子部品及びその製造方法 | |
JP4725817B2 (ja) | 複合基板の製造方法 | |
WO2010067508A1 (ja) | 多層基板およびその製造方法 | |
JP4503349B2 (ja) | 電子部品実装体及びその製造方法 | |
WO2006011508A1 (ja) | 複合型電子部品及びその製造方法 | |
JP2005026573A (ja) | 部品内蔵モジュールの製造方法 | |
JP2004055967A (ja) | 電子部品内蔵基板の製造方法 | |
JP2005235807A (ja) | 積層型電子部品およびその製造方法 | |
JP4403820B2 (ja) | 積層型電子部品およびその製造方法 | |
JP2002026244A (ja) | 多層モジュールおよびその製造方法 | |
EP1369919A1 (en) | Flip chip package | |
US20030201544A1 (en) | Flip chip package | |
WO2005071742A1 (ja) | 積層型電子部品の製造方法 | |
JP2004014651A (ja) | 配線基板、それを用いた半導体装置及び配線基板の製造方法 | |
JP2002335081A (ja) | 多層配線基板及びその製造方法 | |
JPH09270578A (ja) | 多層配線基板の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 200580001908.3 Country of ref document: CN |
|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): BW GH GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWE | Wipo information: entry into national phase |
Ref document number: 2005517630 Country of ref document: JP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 11462395 Country of ref document: US |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
WWW | Wipo information: withdrawn in national office |
Ref document number: DE |
|
WWP | Wipo information: published in national office |
Ref document number: 11462395 Country of ref document: US |
|
122 | Ep: pct application non-entry in european phase |