JPWO2007049417A1 - 回路モジュールの製造方法および回路モジュール - Google Patents
回路モジュールの製造方法および回路モジュール Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 239000000463 material Substances 0.000 claims abstract description 234
- 229920005989 resin Polymers 0.000 claims abstract description 221
- 239000011347 resin Substances 0.000 claims abstract description 221
- 229920001187 thermosetting polymer Polymers 0.000 claims description 24
- 230000005855 radiation Effects 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 13
- 239000004020 conductor Substances 0.000 claims description 12
- 239000000919 ceramic Substances 0.000 claims description 9
- 239000011256 inorganic filler Substances 0.000 claims description 9
- 229910003475 inorganic filler Inorganic materials 0.000 claims description 9
- 230000002093 peripheral effect Effects 0.000 claims description 7
- 230000001678 irradiating effect Effects 0.000 claims description 3
- 238000010030 laminating Methods 0.000 claims description 3
- 239000011342 resin composition Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 description 24
- 229910000679 solder Inorganic materials 0.000 description 18
- 238000001723 curing Methods 0.000 description 7
- 238000000576 coating method Methods 0.000 description 6
- 238000007789 sealing Methods 0.000 description 6
- 238000003847 radiation curing Methods 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000005304 joining Methods 0.000 description 4
- 238000009413 insulation Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 239000003985 ceramic capacitor Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 230000003014 reinforcing effect Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 235000019219 chocolate Nutrition 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- XLJMAIOERFSOGZ-UHFFFAOYSA-M cyanate Chemical compound [O-]C#N XLJMAIOERFSOGZ-UHFFFAOYSA-M 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 230000009974 thixotropic effect Effects 0.000 description 1
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Abstract
Description
図1〜図4は本発明にかかる回路モジュールの第1実施形態を示す。この回路モジュールAは、平板状の配線基板1に枠状の端子板10を接合した構造となっている。
前記実施形態では、図3,図6の(a)に示すように、第1の樹脂材料21が接合材20間の隙間δを満たした位置で終端となるように塗布した例を示したが、図7の(a)に示すように、第1の樹脂材料21が接合材20に到達することなく、端子板10と配線基板1との間で終端となるように塗布してもよい。第1の樹脂材料21としてさらに高粘度の材料あるいはチキソ性を有する材料を使用した場合、樹脂材料21が塗布時の形態を保持するため、上述のように接合材20に到達することなく端子板10と配線基板1との間で終端とさせることができる。また、図7の(b)は、第1の樹脂材料21が接合材20を完全に取り巻くように塗布した例である。これは、第1の樹脂材料21として比較的粘度の低い材料を用いた場合であり、第1の樹脂材料21が必要以上に広がらないように、熱風や熱線を用いて第1の樹脂材料(熱硬化性樹脂の場合)21の流動を止めてもよい。
図8は、第1の樹脂材料21の塗布方法の他の例を示す。この実施形態では、第1の樹脂材料21として、放射線硬化型または放射線硬化・熱硬化両用型樹脂材料を使用したものである。例えば、紫外線照射型樹脂または紫外線・熱硬化両用型樹脂を使用すればよい。なお、第2の樹脂材料は上述と同様に熱硬化型樹脂材料を使用している。
図9は、枠状の端子板として種々の変形例を示したものである。図9の(a)は、端子板10Aの表面の接続電極12と裏面の端子電極(図示せず)とを側面に形成した接続用パターン電極15によって接続した例である。接続用パターン電極15は、端子板10Aの外側面または内側面のいずれに形成してもよい。図9の(b)は、端子板10Bの表面の接続電極12と裏面の端子電極13とをスルーホール16によって接続した例である。スルーホール16は、端子板10Bを厚み方向に貫通する穴の内面に電極を形成したものである。図9の(c)は、端子板10Cの表面の接続電極12と裏面の端子電極(図示せず)とを側面に形成した接続用パターン電極17によって接続した例であるが、接続用パターン電極17が凹溝の内面に形成されたものである。図9の(d)は、端子板10Dの表面の接続電極12と裏面の端子電極(図示せず)とを、ビアホール導体(図示せず)と、側面に形成した凹溝構造の接続用パターン電極18とで接続した例である。特に、グランド電極などのはんだ量の多い電極(ランドの大きい電極)12aに接続用パターン電極18を適用した例である。グランド電極などの広い面積の電極は、はんだ溶融による熱膨張の影響を最も受けやすいからである。
Claims (11)
- 表面に配置された複数の接続電極を有する平板状の配線基板と、前記複数の接続電極に対応する複数の接続電極を有する枠状の端子板とを準備する工程と、
前記配線基板の複数の接続電極と前記端子板の複数の接続電極とをそれぞれ個別に導電性接合材を介して接合する工程と、
前記端子板の内側面と前記配線基板の表面とで構成されるキャビティ内に、回路部品を搭載する工程と、
前記端子板の内側面と前記配線基板の表面との間に、両者の隙間を埋める第1の樹脂材料を塗布する工程と、
前記第1の樹脂材料を塗布した後、前記回路部品を覆うように、第2の樹脂材料を前記キャビティに充填する工程と、
を有する回路モジュールの製造方法。 - 前記第1の樹脂材料は、前記第2の樹脂材料に比べて、硬化前における同一温度・同一雰囲気下での粘度が高く、かつ前記導電性接合材間の隙間を通って外部へ流れ出すのを防止できる程度の粘度を有することを特徴とする請求項1に記載の回路モジュールの製造方法。
- 前記第1の樹脂材料と前記第2の樹脂材料は共に熱硬化型樹脂材料よりなり、前記第1の樹脂材料と前記第2の樹脂材料とを同時に熱硬化させる工程をさらに有することを特徴とする請求項2に記載の回路モジュールの製造方法。
- 前記第1の樹脂材料と前記第2の樹脂材料は、熱硬化型樹脂と無機フィラーとの混合樹脂組成物であり、前記第1の樹脂材料に含まれる無機フィラーの含有率は前記第2の樹脂材料に含まれる無機フィラーの含有率より高いことを特徴とする請求項3に記載の回路モジュールの製造方法。
- 前記第1の樹脂材料は放射線硬化型または放射線硬化・熱硬化両用型樹脂材料であり、前記第2の樹脂材料は熱硬化型樹脂材料であり、前記第1の樹脂材料を塗布する工程と前記第2の樹脂材料を充填する工程との間に、前記第1の樹脂材料に放射線を照射して硬化させる工程を有することを特徴とする請求項1に記載の回路モジュールの製造方法。
- 前記第1の樹脂材料を、前記導電性接合材間の隙間を満たし、かつ前記導電性接合材の周面の少なくとも一部が外部に開放された位置で終端となるように塗布することを特徴とする請求項1ないし5のいずれか1項に記載の回路モジュールの製造方法。
- 前記第1の樹脂材料は、塗布後に流動しないようなチキソ性を有することを特徴とする請求項1に記載の回路モジュールの製造方法。
- 前記端子板の裏面には、前記端子板の厚み方向に延びる導電体を介して前記接続電極と電気的に接続された端子電極が形成されていることを特徴とする請求項1ないし7のいずれか1項に記載の回路モジュールの製造方法。
- 前記配線基板の裏面には、別の回路部品が実装されていることを特徴とする請求項1ないし8のいずれか1項に記載の回路モジュールの製造方法。
- 前記配線基板は複数のセラミック層を積層してなるセラミック多層基板であり、前記端子板は樹脂基板であることを特徴とする請求項1ないし9のいずれか1項に記載の回路モジュールの製造方法。
- 表面に配置された複数の接続電極を有する平板状の配線基板と、前記複数の接続電極に対応する複数の接続電極を有する枠状の端子板とを備え、
前記配線基板の前記複数の接続電極と前記端子板の前記複数の接続電極とが導電性接合材を介してそれぞれ接続されており、
前記端子板の内側面と前記配線基板の表面とで構成されるキャビティ内に回路部品が収納されており、
前記端子板の内側面と前記配線基板の表面との間に、両者の隙間を生める第1の樹脂材料が設けられており、かつ、前記キャビティ内に、前記回路部品を覆うように、第2の樹脂材料が充填されている、
ことを特徴とする回路モジュール。
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JP2004259714A (ja) * | 2003-02-24 | 2004-09-16 | Murata Mfg Co Ltd | 多層セラミック基板を備える電子部品およびその製造方法 |
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