WO2005043615A1 - Procede de transfert autoentretenu d'une couche fine par impulsion apres implantation ou co-implantation - Google Patents

Procede de transfert autoentretenu d'une couche fine par impulsion apres implantation ou co-implantation Download PDF

Info

Publication number
WO2005043615A1
WO2005043615A1 PCT/FR2004/002779 FR2004002779W WO2005043615A1 WO 2005043615 A1 WO2005043615 A1 WO 2005043615A1 FR 2004002779 W FR2004002779 W FR 2004002779W WO 2005043615 A1 WO2005043615 A1 WO 2005043615A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
species
source substrate
heat treatment
implantation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/FR2004/002779
Other languages
English (en)
French (fr)
Inventor
Nguyet-Phuong Nguyen
Ian Cayrefourcq
Christelle Lagahe-Blanchard
Konstantin Bourdelle
Aurélie Tauzin
Franck Fournel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA, Soitec SA filed Critical Commissariat a lEnergie Atomique CEA
Priority to US10/577,175 priority Critical patent/US8309431B2/en
Priority to EP04805334.2A priority patent/EP1678754B1/fr
Priority to JP2006537358A priority patent/JP5244315B2/ja
Publication of WO2005043615A1 publication Critical patent/WO2005043615A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19Preparing inhomogeneous wafers
    • H10P90/1904Preparing vertically inhomogeneous wafers
    • H10P90/1906Preparing SOI wafers
    • H10P90/1914Preparing SOI wafers using bonding
    • H10P90/1916Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00Ion implantation into wafers, substrates or parts of devices
    • H10P30/20Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00Ion implantation into wafers, substrates or parts of devices
    • H10P30/20Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00Ion implantation into wafers, substrates or parts of devices
    • H10P30/20Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/208Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00Cutting or separating of wafers, substrates or parts of devices
    • H10P54/50Cutting or separating of wafers, substrates or parts of devices by scoring, breaking or cleaving
    • H10P54/52Cutting or separating of wafers, substrates or parts of devices by scoring, breaking or cleaving by cleaving
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01Manufacture or treatment
    • H10W10/011Manufacture or treatment of isolation regions comprising dielectric materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10Isolation regions comprising dielectric materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10Isolation regions comprising dielectric materials
    • H10W10/181Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Definitions

  • the invention relates to a method for transferring an ultra-thin layer (we also speak of a thin or ultra-thin layer) using the self-sustaining propagation of a fracture initiated by an energy pulse. It finds applications in particular in the fields of microelectronics, micro-mechanics, optics and integrated electronics.
  • the detachment of a thin layer can be obtained by implantation of chemical species in a source substrate, for example made of silicon, to induce the formation of a zone of defects at a certain depth.
  • defects can be micro-bubbles and / or platelets and / or micro-cavities and / or dislocation loops and / or other crystalline defects, locally disturbing the crystalline quality of the material; their nature, density and size depend very much on the implanted species (typically hydrogen) as well as on the nature of the source substrate.
  • a heat treatment can then be applied to allow the development of specific defects present in the weakened zone, which makes it possible to obtain the subsequent detachment of the thin layer from the source substrate.
  • hetero-structures comprising a superposition of substrates made of different materials
  • another technological problem encountered is the presence of a very strong stress field in the various layers in contact, during the heat treatment, due the difference in the coefficients of thermal expansion of the various materials brought into contact.
  • This can induce the degradation of heterostructures if the thermal detachment takes place at a temperature higher than a critical temperature.
  • This degradation can typically be the breakage of one or two substrates brought into contact and / or the separation of the substrates at the bonding interface. This is why it may be desired to obtain detachment at a lower temperature.
  • One way to obtain this type of detachment is to "play" with the conditions of establishment.
  • an overdose of the implanted species increases the embrittlement of the implanted area and causes detachment at low temperatures by the contribution of an external force.
  • the detachment can also be done by applying, generally following the heat treatment, an external force which causes the fracture in the weakened zone until the detachment of the thin layer.
  • This type of mechanical detachment therefore consists in introducing a blade from the edges of the structure and advancing this blade over almost all of the bonded structure, as for "cutting" the edge of the weakened area; we sometimes speak of assisted posting, since the role of the tool (such an ilame) is to propagate the fracture wave from one edge to the other of the structure.
  • This type of fracture brings the following defects, at the level of the future surface released by the detachment of the thin layer: - crown defect (non-transferred area, at the periphery of the final product), for example linked to local bonding energy too low compared to the rest of the interface, and the introduction of tools to initiate the transfer, - non-uniformity (roughness at low frequency) of the thickness of the transferred thin layer, in particular due to the wave of fracture assisted mechanically, therefore irregularly, by blows, which then requires treatments, such as polishing, which we nevertheless seek to avoid in general, - difficult industrial deployment, given the use of a tool that accompanies the propagation of the fracture, which involves individual treatment of each structure (or plate).
  • the heat treatments envisaged in this article are 450 ° C for 20 min or 750 ° C for 20 s, which necessarily involves the aforementioned drawbacks with regard to detachment at high temperature.
  • This hydrogen-helium combination has also been studied, more theoretically, by Cerofolini et al. (2000) [3], who noted that the pressurization of the defects was stronger with the implantation of helium than with that of hydrogen, and that the heat treatment could have different effects depending on the temperature.
  • the object of the invention is to overcome the aforementioned drawbacks. More specifically, the subject of the invention is a process for transferring a thin layer which can be carried out at low temperature (in order to limit the high mechanical stresses when using materials having large differences in expansion coefficients), which can be carried out collectively and limiting the faults previously mentioned during the detachment of the thin layer, in particular avoiding jolts of the fracture wave.
  • the invention aims to obtain, for a moderate cost, thin layers of high quality, thus avoiding, at the same time, the drawbacks of a heat treatment at high temperature and those linked to the use of '' a tool for assisted detachment, and those linked to an additional treatment to reduce roughness after detachment.
  • the invention proposes for this purpose a self-sustained transfer process of a thin layer according to which:
  • At least one first species of ion or gas is implanted in this source substrate in a first dose at a given depth with respect to one face of this source substrate, this first species being capable of generating defects
  • a heat treatment is applied to this source substrate, at a given temperature for a given time, so as to create, substantially at the given depth, a weakened buried zone, without initiating the thermal detachment of the thin layer,
  • a self-maintained detachment is a complete and almost instantaneous detachment, similar to that obtained by a simple heat treatment at high temperature, but caused by a possible tool without it having to follow any wave of fracture (if there is a tool, it therefore comes at most into contact with the substrate and the layer, without skirting the detachment interface); it is therefore, in other words, the opposite of assisted detachment.
  • a self-maintained detachment as being a complete and almost instantaneous detachment, similar to that obtained by a simple heat treatment at high temperature, but caused by a possible tool without it having to follow any wave of fracture (if there is a tool, it therefore comes at most into contact with the substrate and the layer, without skirting the detachment interface); it is therefore, in other words, the opposite of assisted detachment.
  • the heat treatment temperature is advantageously chosen so as to favor the development of crystalline defects in the weakened zone without inducing spontaneous thermal detachment. This temperature will be low enough not to generate excessive mechanical stresses in the substrate in the event that the source substrate and / or a possible target substrate would include materials having very different coefficients of expansion. This is why the process is a transfer process occurring at a relatively low temperature (no more than 500 ° C. in the case of a hetero structure Silicon / Quartz for example).
  • the fracture is obtained by propagation of a self-sustaining fracture wave, after it has been initiated by an energy pulse applied to a fragile area (this pulse can be local or global ).
  • this pulse can be local or global .
  • implantation conditions dose, energy, nature of the species (or species), current, order of implantations (if there are several) and relative positions in the depth of the substrate of the species implanted (in the case of implantation of several species), implantation temperature, etc.
  • adapted treatment for example a heat treatment
  • the invention consists in favoring the conditions of embrittlement close, in their nature, to the conditions obtained during the thermal fracture, without however leading them to this point.
  • the additional energy is then supplied by impulse complement at the end or during the heat treatment, and induces the propagation of a self-sustained fracture.
  • self-sustained propagation of the fracture wave it is understood that it is not necessary to assist the propagation of the wave by advancing a tool or by repeating the initiation energy pulse.
  • an important characteristic of the invention is that the fracture wave is propagated over the entire surface of the plate in less than 1 second, or even of the order of a millisecond (speeds greater than 100 m / sec) for diameters up to 'at 300mm.
  • a possible origin of the self-sustaining (or catastrophic) fracture comes from the nature of the buried defects.
  • the studies carried out (in Germanium, but applicable to Silicon) have shown that under self-sustaining fracture conditions the density of defects (micro-cracks, cavities, platelets, micro and macro bubbles, ...) is estimated between 0.03 and 0.035 per square micron, their sizes are of the order of 7 to 8 square microns, and the area open by these defects relative to the total area of the plate is estimated between 25 and 32%.
  • characteristic values of the weakened area may appear similar to the characteristic values observed when the fracture is obtained thermally, but differ from those obtained after a weakening treatment which requires an assisted mechanical fracture (in which case, the value of open area is more like 10%).
  • the value of open area is more like 10%.
  • at least the above condition on the open surface is fulfilled (it seems to be the most important; it seems to be able to be generalized to a range of 20% to 35%), possibly supplemented by one and / or the other conditions on the density or size of the defects.
  • other effects or causes are not excluded by this interpretation, in particular the chemical nature of the bonds in the substrate can also favor the appearance of the phenomenon of self-sustained fracture wave.
  • the invention seems to consist in promoting the conditions of embrittlement close, in their nature, to the conditions obtained during the thermal fracture, without however leading them to this point.
  • the additional energy is then supplied by impulse complement.
  • impulse energy can be global (thermal shock, ultra sound, etc.) or localized (laser, mechanical shock, tensile force, etc.).
  • this pulse is localized, advantageously applied by a tool driven by a brief movement and of small amplitude.
  • This energy supply is advantageously applied in the immediate vicinity of the buried layer, limited to only a part thereof, preferably to a peripheral portion thereof.
  • This pulse can also consist in particular of a localized thermal contribution (for example applied by a laser pulse) or of an external stress (for example in the immediate vicinity of the weakened zone, in an edge of this one).
  • the fracture can be obtained around ambient temperature (0 to 50 ° C), for example by application of a mechanical shock located at the edge of the assembly.
  • this particular implementation does not limit the invention, and it may be, in certain situations, preferable to initiate the fracture at a higher temperature, for example around 300 ° C. It has been observed that the energy pulse has all its effectiveness in initiating the fracture wave when it leads to a very localized opening of the interface at the level of the fragile layer.
  • a shock provided by a blade type tool induces the propagation of a self-sustaining fracture very effectively.
  • the additional treatment is carried out in the form of the contribution of a thermal budget, this is less than the thermal budget necessary for obtaining the fracture.
  • the surface condition of the substrate formed after fracture has improved high and low frequency roughness compared to the prior art. This result is particularly pronounced for low frequencies with in particular the absence of fracture waves. It is assumed that this result is linked to the fact that, in the context of the invention, the fracture wave propagates continuously, smoothly and within a very weakened layer (which would facilitate the propagation of the 'wave in a preferred area within the weakened layer), compared to what is obtained in the prior art.
  • the phenomenon of self-sustaining fracture is observed only for points of narrow functioning, which can be difficult to reproduce systematically.
  • the operating window for obtaining the self-sustaining fracture phenomenon is wide, which means that this phenomenon can be observed for a wide variation in the parameters for obtaining the fragile layer (parameters implantation and additional heat treatment, in particular). This is for example the case, when the implantation is a co-implantation under defined conditions (see below), and / or when the temperature profile of the additional treatment comprises adapted phases.
  • the latter proposes a method for manufacturing a batch of substrates comprising the following steps: - implantation of each of the substrates, - treatment of embrittlement, in batch, substrates, - application of energy pulses simultaneously to each of the substrates, (collective processing).
  • the substrate is embrittled and the embrittlement "energy” does not need to be maintained until the moment of application of the energetic pulse.
  • We can even add that provoking a self-sustaining propagation in hot is not recommended in the case of hetero structures, because the constraints resulting from the differences of coefficient of thermal expansion, which are released during the fracture, could lead to breakage substrates.
  • the operating window of the annealing step can be very large: the maximum limit for the duration of this pre-embrittlement annealing is strongly pushed back (or even no longer exists); this is entirely favorable to the industrialization of the process, • there is no assisted detachment since the self-sustaining fracture makes it possible to propagate the fracture wave instantly and without jerks over the entire surface of the plate ; It is not necessary for any blade to penetrate between the substrate and the future thin layer, which prevents damage to the layer transferred by the release tool.
  • the self-healing fracture also significantly improves the topology of the surfaces thus released (with, for example, lower roughness (especially at low frequency)), and avoids crown defects, which makes the entire thin layer usable, including its periphery • the fact of no longer having to introduce tools is also favorable to the industrialization of the process and to a collective treatment of substrates in batches of plates.
  • the source substrate is brought into intimate contact by said face with a stiffener or target substrate, the heat treatment contributes to improving the bonding energy between these substrates.
  • This target substrate or stiffener is advantageously chosen from monocrystalline or polycrystalline materials, such as silicon or sapphire in particular, or in the form of an amorphous material, such as for example in the form of fused silica.
  • an implantation of several species is carried out in concomitant or non-concomitant ways.
  • it may be a co-location of hydrogen and helium.
  • the hydrogen preferably in H + form
  • a relatively low dose typically of the order of a few 10 16 H / cm 2
  • helium can be implanted with a relatively low dose (typically of the order of 10 16 He / cm 2 , or of some 10 16 He / cm 2 ).
  • a relatively low dose typically of the order of 10 16 He / cm 2 , or of some 10 16 He / cm 2 .
  • the advantage of I ac o-implantation is to obtain the maximum embrittlement of this zone at the temperature sufficient for the solidity of the bonding interfaces without having to reach temperatures too high that heterostructures could not possibly be able to support and without being either obliged to use very high doses of implantation (which is a known means of limiting the value of the temperature necessary for the development of the weakened zone).
  • the two species are implanted at the same level but a variant consists of shifting the implantation profiles.
  • the two species can be implanted in any order, but advantageously, in the case of a silicon substrate and a hydrogen-helium co-implantation, it is preferable to implant the deepest profile in first.
  • the source substrate e is made of a material chosen by semiconductors and insulators, monocrystalline, polycrystalline or amorphous. This is how it can be chosen by IV semiconductors; a particularly interesting example is silicon, but it can also be germanium or Si-Ge alloys. It can also be materials from the family of 111-iV or ll-Vi such as As-Ga or InP or an insulating material such as ferroelectric materials, for example LiNb03 and Li Ta03.
  • the airtight treatment can cheerfully present a profile so as to reduce the time of this treatment, as for example disclosed in European patent application 02-293049 filed on December 10, 2002.
  • the temperature range depends mainly on the nature of the species (or species) implanted (s) and the nature of the material constituting the source substrate as well as the nature of the stiffening substrate in particular in the case of a heterostructure.
  • FIG. 1 thus represents a substrate 1, for example of silicon advantageously oxidized on its surface 4, in the process of being subjected to a treatment of implantation, shown diagrammatically by arrows 2, for example by bombardment, of ions or gaseous species.
  • This implantation implies, at a given depth, the implantation of a first species which is capable of generating defects, for example hydrogen, preferably in the form of H + ions.
  • this implantation can be a co-implantation of two species, for example Hydrogen - Helium.
  • the two species are implanted at the same depth, but as a variant, it is preferable that the first implanted species is the one with the deepest profile, for example helium before hydrogen.
  • the first implanted species is the one with the deepest profile, for example helium before hydrogen.
  • the reverse order of the layouts may be preferable, even if the two layouts are not made at the same depth.
  • FIG. 2 represents a step during which the source substrate, containing the weakened buried zone 3, by its face 4, is brought into intimate contact with a corresponding face of a target substrate 7, typically by direct molecular bonding, the function is that of a stiffener.
  • a heat treatment is then applied which will, on the one hand, allow development of the embrittlement of the buried layer 3, and on the other hand, when a bonding step has taken place, allow consolidation of the bonding bonds between source substrate and target substrate.
  • the temperature of this heat treatment is chosen within a range of temperatures suitable for developing the weakened zone. This treatment is advantageously carried out at a temperature chosen in the range 200 ° C-400 ° C, preferably in the range 300 ° C-
  • FIG. 3 is shown the step of detaching the thin layer 3 vis-à-vis the rest of the source substrate, by means of the application of a pulse energy supply, preferably brief and of limited amplitude , for example in the form of a shock or an impulse. It is for example made up of a mechanical stress shown diagrammatically by the arrow 10. The detachment obtained is self-maintained in this sense, in particular, that there is no movement of a tool along the weakened layer.
  • This localized contribution of energy is here limited to a part of the buried layer, shown diagrammatically in the form of a wedge effect corresponding to a shock applied by a tool such as a blade on (or near) a portion. of this weakened buried layer; but it can be of any other nature, for example a torque parallel to the plane of the weakened buried zone advantageously applied in the form of a pulse of low angular amplitude.
  • the face of the thin layer which is released by the self-maintained detachment in the weakened buried zone has a much lower roughness than according to conventional solutions, without it it was necessary to provide for a particular treatment of the transferred surface or for significant polishing ("coarse”) after detachment.
  • the source substrate 1 can be not only made of silicon, but more generally of any suitable known material, for example semiconductor
  • this source substrate can be: • another semiconductor from column IV of the periodic table of the elements, for example made of germanium, • a semiconductor of the type ll-V or I I-VI such that eu AsGa or I nP, in particular, • an insulator, for example of the niobate or tantalate type, such as LiNbO3 or LiTaO3, in particular.
  • the target substrate it can be produced in a wide variety of materials, to be chosen according to requirements, monocrystalline or polycrystalline (for example semiconductors, for example from the same materials as for the source substrate) or even amorphous (for example glasses or polymers); thus it can in particular be: • a crystalline material such as sapphire, • fused silica or another glass, • a simple stiffening layer, for example an oxide a few microns thick, deposited by any suitable known technique (this no longer corresponds, it is true, to a massive target substrate of the type shown in the drawings). It should be noted that the target substrate may be only an intermediate substrate, the thin layer of which is then transferred to a final substrate.
  • monocrystalline or polycrystalline for example semiconductors, for example from the same materials as for the source substrate
  • amorphous for example glasses or polymers
  • the target substrate may be only an intermediate substrate, the thin layer of which is then transferred to a final substrate.
  • an Si substrate (-700 ⁇ m) comprising a thermal SiO 2 layer on the surface can be implanted initially with helium atoms under implantation conditions 70keV - 10 16 He / cm 2 , then implanted with hydrogen atoms under implantation conditions 30keV - 4.25.10 16 H / cm 2 .
  • This source substrate can then be joined to a target Si substrate (-700 ⁇ m) by molecular bonding.
  • a heat treatment around 350 ° C for a certain time (2 hours for example) is then applied to the structure.
  • the window for obtaining the self-sustaining fracture phenomenon is of the order of a few hours (i.e. an embrittlement annealing of between 2 and 6 hours). Then, with barely the beginning of insertion of a blade between the bonding interfaces in the form of a shock, the self-sustained detachment at the level of the maximum hydrogen concentration leads to the transfer of the thin layer of If on the target substrate.
  • the roughness of the transferred surface measured at high frequency (by atomic force microscopy), of the order of 45 to 50 Angstroms RMS, and at low frequency (by mechanical profilometry), of the order of 10 Angstroms RMS, of this transferred surface are much lower than those which can be obtained in the case of H-implanted alone (32keV-5.5.10 16 H / cm 2 ) followed by a heat treatment at 500 ° C (roughness at high frequency of the order of 75 Angstroms RMS and roughness at low frequency of the order of 26 Angstroms RMS).
  • a Si substrate (approximately 700 ⁇ m) comprising a layer of thermal Si0 2 on the surface (for example 200 nm) is first implanted with helium atoms under the conditions of implantation 70keV-2.10 16 He / cm 2 , then implanted with hydrogen atoms under conditions 30keV-3.10 16 H / cm 2 .
  • This source substrate is then attached to a target substrate of molten silica (approximately 1000 ⁇ m) by direct bonding.
  • a heat treatment around 300 ° C for a certain time (3 hours for example or more if the embrittlement treatment is suitable) is then applied to the structure.
  • the self-detachment detachment at the maximum of the hydrogen profile leads to the transfer of the thin layer of Si onto the molten silica substrate, without breakage or degradation of either of the substrates derived from the heterostructure after detachment (the molten silica substrate comprising the layer thin Si on the one hand and the initial Si substrate peeled from the thin surface layer on the other).
  • the roughness of the transferred surface measured at low frequency by the profilometry (of the order of 14 Angstroms RMS at low frequency) and in atomic force microscopy ((of the order of 75 Angstroms at high frequency) of this transferred surface are much lower than those which can be obtained in the case of H-implanted alone (32keV-5.5.10 16 H / cm 2 ) annealed at 400 ° C for 2 hours and according to the progressive mechanical detachment mode at room temperature (roughness at high frequency on the order of 90 Angstroms RMS and on the order of 40 Angstroms at low frequency RMS).
  • Germanium on insulator The above information can be generalized in the case of a source substrate which is made of solid Germanium, with the following embrittlement parameters: dose 7. 10 16 H / cm ⁇ 2 with an energy between 30 and 200 keV depending on the thickness to be transferred, and annealing at 300 ° C - for a certain time (typically from 30 min to 1 hour, i.e. an operating window of 30 min). After this heat treatment specific to these implantation conditions, the density of the microcracks present in the implanted area is estimated between 0.03 and 0.035 per square micron, their sizes are Twist from 7 to 8 square microns, and the area open by these defects relative to the total area of the plate is between 25 and 32%.
  • the characteristics of the weakened area may appear similar to the characteristics observed when the fracture is obtained thermally, but differ from those obtained after a weakening treatment of 280 ° C - 15 min which implies a mechanical fracture assisted in which case these values are lower: for example, the surface opened by the microcracks represents less than 10% of the total surface of the plate. Silicon on insulator
  • AsGa on insulator The following conditions are applied: - Layout 5. 10 16 at / cm 2 ; at around 100 keV, - Annealing at 250 ° C between 3 and 30 minutes. The phenomenon of self-sustaining fracture can be observed when the embrittlement annealing is carried out in a window of 3 to 30 minutes

Landscapes

  • Element Separation (AREA)
  • Physical Vapour Deposition (AREA)
  • Recrystallisation Techniques (AREA)
  • Micromachines (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
PCT/FR2004/002779 2003-10-28 2004-10-28 Procede de transfert autoentretenu d'une couche fine par impulsion apres implantation ou co-implantation Ceased WO2005043615A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US10/577,175 US8309431B2 (en) 2003-10-28 2004-10-28 Method for self-supported transfer of a fine layer by pulsation after implantation or co-implantation
EP04805334.2A EP1678754B1 (fr) 2003-10-28 2004-10-28 Procede de transfert auto-entretenu d'une couche fine par impulsion apres implantation ou co-implantation
JP2006537358A JP5244315B2 (ja) 2003-10-28 2004-10-28 注入又は共注入後のパルスによる薄膜層の自立転写方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0312621A FR2861497B1 (fr) 2003-10-28 2003-10-28 Procede de transfert catastrophique d'une couche fine apres co-implantation
FR0312621 2003-10-28

Publications (1)

Publication Number Publication Date
WO2005043615A1 true WO2005043615A1 (fr) 2005-05-12

Family

ID=34400866

Family Applications (2)

Application Number Title Priority Date Filing Date
PCT/FR2004/002779 Ceased WO2005043615A1 (fr) 2003-10-28 2004-10-28 Procede de transfert autoentretenu d'une couche fine par impulsion apres implantation ou co-implantation
PCT/FR2004/002781 Ceased WO2005043616A1 (fr) 2003-10-28 2004-10-28 Procede de transfert catastrophique d'une couche fine apres co­-implantation

Family Applications After (1)

Application Number Title Priority Date Filing Date
PCT/FR2004/002781 Ceased WO2005043616A1 (fr) 2003-10-28 2004-10-28 Procede de transfert catastrophique d'une couche fine apres co­-implantation

Country Status (8)

Country Link
US (1) US8309431B2 (enExample)
EP (2) EP1678754B1 (enExample)
JP (2) JP5244315B2 (enExample)
KR (2) KR20060122830A (enExample)
CN (2) CN100474557C (enExample)
FR (1) FR2861497B1 (enExample)
TW (1) TWI349303B (enExample)
WO (2) WO2005043615A1 (enExample)

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007251172A (ja) * 2006-03-13 2007-09-27 Soi Tec Silicon On Insulator Technologies Sa 薄膜を製造する方法
US7485545B2 (en) 2004-12-28 2009-02-03 S.O.I.Tec Silicon On Insulator Technologies Method of configuring a process to obtain a thin layer with a low density of holes
US7514341B2 (en) 2005-12-22 2009-04-07 S.O.I.Tec Silicon On Insulator Technologies Finishing process for the manufacture of a semiconductor structure
US8048766B2 (en) 2003-06-24 2011-11-01 Commissariat A L'energie Atomique Integrated circuit on high performance chip
US8142593B2 (en) 2005-08-16 2012-03-27 Commissariat A L'energie Atomique Method of transferring a thin film onto a support
US8252663B2 (en) 2009-06-18 2012-08-28 Commissariat A L'energie Atomique Et Aux Energies Alternatives Method of transferring a thin layer onto a target substrate having a coefficient of thermal expansion different from that of the thin layer
US8389379B2 (en) 2002-12-09 2013-03-05 Commissariat A L'energie Atomique Method for making a stressed structure designed to be dissociated
US8470712B2 (en) 1997-12-30 2013-06-25 Commissariat A L'energie Atomique Process for the transfer of a thin film comprising an inclusion creation step
US8664084B2 (en) 2005-09-28 2014-03-04 Commissariat A L'energie Atomique Method for making a thin-film element
US8778775B2 (en) 2006-12-19 2014-07-15 Commissariat A L'energie Atomique Method for preparing thin GaN layers by implantation and recycling of a starting substrate
EP2933828A1 (en) 2014-04-16 2015-10-21 Soitec Method for transferring a useful layer
US9922867B2 (en) 2015-02-10 2018-03-20 Soitec Method for transferring a useful layer
FR3093716A1 (fr) 2019-03-15 2020-09-18 Soitec systeme de fracture d'une pluralitÉ d'assemblages de tranches.
FR3093859A1 (fr) 2019-03-15 2020-09-18 Soitec Procédé de transfert d’une couche utile sur une substrat support
FR3093860A1 (fr) 2019-03-15 2020-09-18 Soitec Procédé de transfert d’une couche utile sur un substrat support
FR3093858A1 (fr) 2019-03-15 2020-09-18 Soitec Procédé de transfert d’une couche utile sur un substrat support

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2748851B1 (fr) 1996-05-15 1998-08-07 Commissariat Energie Atomique Procede de realisation d'une couche mince de materiau semiconducteur
US7772087B2 (en) 2003-12-19 2010-08-10 Commissariat A L'energie Atomique Method of catastrophic transfer of a thin film after co-implantation
US9362439B2 (en) * 2008-05-07 2016-06-07 Silicon Genesis Corporation Layer transfer of films utilizing controlled shear region
FR2912259B1 (fr) * 2007-02-01 2009-06-05 Soitec Silicon On Insulator Procede de fabrication d'un substrat du type "silicium sur isolant".
FR2912258B1 (fr) 2007-02-01 2009-05-08 Soitec Silicon On Insulator "procede de fabrication d'un substrat du type silicium sur isolant"
JP4967842B2 (ja) * 2007-06-18 2012-07-04 セイコーエプソン株式会社 シリコン基材の接合方法、液滴吐出ヘッド、液滴吐出装置および電子デバイス
JP4858491B2 (ja) * 2007-06-18 2012-01-18 セイコーエプソン株式会社 シリコン基材の接合方法、液滴吐出ヘッド、液滴吐出装置および電子デバイス
WO2008156056A1 (ja) * 2007-06-18 2008-12-24 Seiko Epson Corporation シリコン基材の接合方法、液滴吐出ヘッド、液滴吐出装置および電子デバイス
FR2925221B1 (fr) 2007-12-17 2010-02-19 Commissariat Energie Atomique Procede de transfert d'une couche mince
TWI492275B (zh) * 2008-04-10 2015-07-11 信越化學工業股份有限公司 The method of manufacturing the bonded substrate
JP5643509B2 (ja) * 2009-12-28 2014-12-17 信越化学工業株式会社 応力を低減したsos基板の製造方法
JP5926887B2 (ja) * 2010-02-03 2016-05-25 株式会社半導体エネルギー研究所 Soi基板の作製方法
FR2961948B1 (fr) * 2010-06-23 2012-08-03 Soitec Silicon On Insulator Procede de traitement d'une piece en materiau compose
FR2968121B1 (fr) 2010-11-30 2012-12-21 Soitec Silicon On Insulator Procede de transfert d'une couche a haute temperature
US8841203B2 (en) * 2011-06-14 2014-09-23 International Business Machines Corporation Method for forming two device wafers from a single base substrate utilizing a controlled spalling process
US9257339B2 (en) * 2012-05-04 2016-02-09 Silicon Genesis Corporation Techniques for forming optoelectronic devices
US9092187B2 (en) 2013-01-08 2015-07-28 Apple Inc. Ion implant indicia for cover glass or display component
US9623628B2 (en) 2013-01-10 2017-04-18 Apple Inc. Sapphire component with residual compressive stress
KR101641807B1 (ko) 2013-02-12 2016-07-21 애플 인크. 다단계 이온 주입
US9416442B2 (en) 2013-03-02 2016-08-16 Apple Inc. Sapphire property modification through ion implantation
WO2015035331A1 (en) * 2013-09-06 2015-03-12 Veeco Instruments, Inc. Tensile separation of a semiconducting stack
US10160849B1 (en) 2014-10-01 2018-12-25 Basell Poliolefine Italia S.R.L. Propylene-based copolymer composition for pipes
US10280504B2 (en) 2015-09-25 2019-05-07 Apple Inc. Ion-implanted, anti-reflective layer formed within sapphire material
WO2017141103A1 (en) * 2016-02-16 2017-08-24 G-Ray Switzerland Sa Structures, systems and methods for electrical charge transport across bonded interfaces
JP6970109B2 (ja) 2016-03-08 2021-11-24 アリゾナ・ボード・オブ・リージェンツ・オン・ビハーフ・オブ・アリゾナ・ステイト・ユニバーシティーArizona Board of Regents on behalf of Arizona State University 半導体ウェハ成形のための音響促進の亀裂伝播
JP6563360B2 (ja) * 2016-04-05 2019-08-21 信越化学工業株式会社 酸化物単結晶薄膜を備えた複合ウェーハの製造方法
WO2017209251A1 (ja) * 2016-06-01 2017-12-07 シャープ株式会社 基板の製造方法、太陽電池の製造方法、基板および太陽電池
FR3055063B1 (fr) * 2016-08-11 2018-08-31 Soitec Procede de transfert d'une couche utile
KR101866348B1 (ko) * 2016-12-28 2018-06-12 한국에너지기술연구원 수소 헬륨 공동 주입을 통한 박형 실리콘 기판 제조 방법
FR3078822B1 (fr) * 2018-03-12 2020-02-28 Soitec Procede de preparation d’une couche mince de materiau ferroelectrique a base d’alcalin
US11784050B2 (en) * 2021-04-27 2023-10-10 Micron Technology, Inc. Method of fabricating microelectronic devices and related microelectronic devices, tools, and apparatus
FR3134229B1 (fr) * 2022-04-01 2024-03-08 Commissariat Energie Atomique Procede de transfert d’une couche mince sur un substrat support

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0994503A1 (fr) * 1998-10-16 2000-04-19 Commissariat A L'energie Atomique Structure comportant une couche mince de matériau composée de zones conductrices et de zones isolantes et procédé de fabrication d'une telle structure
WO2000063965A1 (en) * 1999-04-21 2000-10-26 Silicon Genesis Corporation Treatment method of cleaved film for the manufacture of substrates
US20020025604A1 (en) * 2000-08-30 2002-02-28 Sandip Tiwari Low temperature semiconductor layering and three-dimensional electronic circuits using the layering
US20030077885A1 (en) * 2000-05-30 2003-04-24 Bernard Aspar Embrittled substrate and method for making same
US6593212B1 (en) * 2001-10-29 2003-07-15 The United States Of America As Represented By The Secretary Of The Navy Method for making electro-optical devices using a hydrogenion splitting technique

Family Cites Families (263)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3915757A (en) 1972-08-09 1975-10-28 Niels N Engel Ion plating method and product therefrom
US3913520A (en) 1972-08-14 1975-10-21 Precision Thin Film Corp High vacuum deposition apparatus
US3993909A (en) 1973-03-16 1976-11-23 U.S. Philips Corporation Substrate holder for etching thin films
FR2245779B1 (enExample) 1973-09-28 1978-02-10 Cit Alcatel
US3901423A (en) 1973-11-26 1975-08-26 Purdue Research Foundation Method for fracturing crystalline materials
US4170662A (en) 1974-11-05 1979-10-09 Eastman Kodak Company Plasma plating
US4121334A (en) 1974-12-17 1978-10-24 P. R. Mallory & Co. Inc. Application of field-assisted bonding to the mass production of silicon type pressure transducers
US3957107A (en) 1975-02-27 1976-05-18 The United States Of America As Represented By The Secretary Of The Air Force Thermal switch
US4039416A (en) 1975-04-21 1977-08-02 White Gerald W Gasless ion plating
GB1542299A (en) 1976-03-23 1979-03-14 Warner Lambert Co Blade shields
US4028149A (en) 1976-06-30 1977-06-07 Ibm Corporation Process for forming monocrystalline silicon carbide on silicon substrates
US4074139A (en) 1976-12-27 1978-02-14 Rca Corporation Apparatus and method for maskless ion implantation
US4108751A (en) 1977-06-06 1978-08-22 King William J Ion beam implantation-sputtering
US4179324A (en) 1977-11-28 1979-12-18 Spire Corporation Process for fabricating thin film and glass sheet laminate
DE2849184A1 (de) 1978-11-13 1980-05-22 Bbc Brown Boveri & Cie Verfahren zur herstellung eines scheibenfoermigen silizium-halbleiterbauelementes mit negativer anschraegung
JPS55104057A (en) 1979-02-02 1980-08-09 Hitachi Ltd Ion implantation device
US4324631A (en) * 1979-07-23 1982-04-13 Spin Physics, Inc. Magnetron sputtering of magnetic materials
CH640886A5 (de) 1979-08-02 1984-01-31 Balzers Hochvakuum Verfahren zum aufbringen harter verschleissfester ueberzuege auf unterlagen.
US4244348A (en) 1979-09-10 1981-01-13 Atlantic Richfield Company Process for cleaving crystalline materials
FR2506344B2 (fr) 1980-02-01 1986-07-11 Commissariat Energie Atomique Procede de dopage de semi-conducteurs
FR2475068B1 (fr) 1980-02-01 1986-05-16 Commissariat Energie Atomique Procede de dopage de semi-conducteurs
US4342631A (en) 1980-06-16 1982-08-03 Illinois Tool Works Inc. Gasless ion plating process and apparatus
US4471003A (en) 1980-11-25 1984-09-11 Cann Gordon L Magnetoplasmadynamic apparatus and process for the separation and deposition of materials
FR2501727A1 (fr) 1981-03-13 1982-09-17 Vide Traitement Procede de traitements thermochimiques de metaux par bombardement ionique
US4361600A (en) 1981-11-12 1982-11-30 General Electric Company Method of making integrated circuits
US4412868A (en) 1981-12-23 1983-11-01 General Electric Company Method of making integrated circuits utilizing ion implantation and selective epitaxial growth
US4486247A (en) 1982-06-21 1984-12-04 Westinghouse Electric Corp. Wear resistant steel articles with carbon, oxygen and nitrogen implanted in the surface thereof
FR2529383A1 (fr) 1982-06-24 1983-12-30 Commissariat Energie Atomique Porte-cible a balayage mecanique utilisable notamment pour l'implantation d'ioris
FR2537768A1 (fr) 1982-12-08 1984-06-15 Commissariat Energie Atomique Procede et dispositif d'obtention de faisceaux de particules de densite spatialement modulee, application a la gravure et a l'implantation ioniques
FR2537777A1 (fr) 1982-12-10 1984-06-15 Commissariat Energie Atomique Procede et dispositif d'implantation de particules dans un solide
DE3246480A1 (de) 1982-12-15 1984-06-20 Wacker-Chemitronic Gesellschaft für Elektronik-Grundstoffe mbH, 8263 Burghausen Verfahren zur herstellung von halbleiterscheiben mit getternder scheibenrueckseite
US4500563A (en) 1982-12-15 1985-02-19 Pacific Western Systems, Inc. Independently variably controlled pulsed R.F. plasma chemical vapor processing
US4468309A (en) 1983-04-22 1984-08-28 White Engineering Corporation Method for resisting galling
GB2144343A (en) 1983-08-02 1985-03-06 Standard Telephones Cables Ltd Optical fibre manufacture
US4567505A (en) 1983-10-27 1986-01-28 The Board Of Trustees Of The Leland Stanford Junior University Heat sink and method of attaching heat sink to a semiconductor integrated circuit and the like
JPS6088535U (ja) 1983-11-24 1985-06-18 住友電気工業株式会社 半導体ウエハ
FR2558263B1 (fr) 1984-01-12 1986-04-25 Commissariat Energie Atomique Accelerometre directif et son procede de fabrication par microlithographie
GB2155024A (en) 1984-03-03 1985-09-18 Standard Telephones Cables Ltd Surface treatment of plastics materials
FR2563377B1 (fr) 1984-04-19 1987-01-23 Commissariat Energie Atomique Procede de fabrication d'une couche isolante enterree dans un substrat semi-conducteur, par implantation ionique
US4542863A (en) 1984-07-23 1985-09-24 Larson Edwin L Pipe-thread sealing tape reel with tape retarding element
US4566403A (en) 1985-01-30 1986-01-28 Sovonics Solar Systems Apparatus for microwave glow discharge deposition
US4837172A (en) 1986-07-18 1989-06-06 Matsushita Electric Industrial Co., Ltd. Method for removing impurities existing in semiconductor substrate
US4717683A (en) 1986-09-23 1988-01-05 Motorola Inc. CMOS process
US4764394A (en) 1987-01-20 1988-08-16 Wisconsin Alumni Research Foundation Method and apparatus for plasma source ion implantation
JPS63254762A (ja) 1987-04-13 1988-10-21 Nissan Motor Co Ltd Cmos半導体装置
US4847792A (en) 1987-05-04 1989-07-11 Texas Instruments Incorporated Process and apparatus for detecting aberrations in production process operations
FR2616590B1 (fr) 1987-06-15 1990-03-02 Commissariat Energie Atomique Procede de fabrication d'une couche d'isolant enterree dans un substrat semi-conducteur par implantation ionique et structure semi-conductrice comportant cette couche
US4956698A (en) 1987-07-29 1990-09-11 The United States Of America As Represented By The Department Of Commerce Group III-V compound semiconductor device having p-region formed by Be and Group V ions
US4846928A (en) 1987-08-04 1989-07-11 Texas Instruments, Incorporated Process and apparatus for detecting aberrations in production process operations
US4887005A (en) 1987-09-15 1989-12-12 Rough J Kirkwood H Multiple electrode plasma reactor power distribution system
US5015353A (en) 1987-09-30 1991-05-14 The United States Of America As Represented By The Secretary Of The Navy Method for producing substoichiometric silicon nitride of preselected proportions
US5138422A (en) 1987-10-27 1992-08-11 Nippondenso Co., Ltd. Semiconductor device which includes multiple isolated semiconductor segments on one chip
GB8725497D0 (en) 1987-10-30 1987-12-02 Atomic Energy Authority Uk Isolation of silicon
US5200805A (en) 1987-12-28 1993-04-06 Hughes Aircraft Company Silicon carbide:metal carbide alloy semiconductor and method of making the same
US4904610A (en) 1988-01-27 1990-02-27 General Instrument Corporation Wafer level process for fabricating passivated semiconductor devices
DE3803424C2 (de) 1988-02-05 1995-05-18 Gsf Forschungszentrum Umwelt Verfahren zur quantitativen, tiefendifferentiellen Analyse fester Proben
JP2666945B2 (ja) 1988-02-08 1997-10-22 株式会社東芝 半導体装置の製造方法
US4894709A (en) 1988-03-09 1990-01-16 Massachusetts Institute Of Technology Forced-convection, liquid-cooled, microchannel heat sinks
US4853250A (en) 1988-05-11 1989-08-01 Universite De Sherbrooke Process of depositing particulate material on a substrate
NL8802028A (nl) 1988-08-16 1990-03-16 Philips Nv Werkwijze voor het vervaardigen van een inrichting.
JP2670623B2 (ja) 1988-09-19 1997-10-29 アネルバ株式会社 マイクロ波プラズマ処理装置
US4952273A (en) 1988-09-21 1990-08-28 Microscience, Inc. Plasma generation in electron cyclotron resonance
US4996077A (en) 1988-10-07 1991-02-26 Texas Instruments Incorporated Distributed ECR remote plasma processing and apparatus
US4891329A (en) 1988-11-29 1990-01-02 University Of North Carolina Method of forming a nonsilicon semiconductor on insulator structure
NL8900388A (nl) 1989-02-17 1990-09-17 Philips Nv Werkwijze voor het verbinden van twee voorwerpen.
JPH02302044A (ja) 1989-05-16 1990-12-14 Fujitsu Ltd 半導体装置の製造方法
US4929566A (en) 1989-07-06 1990-05-29 Harris Corporation Method of making dielectrically isolated integrated circuits using oxygen implantation and expitaxial growth
JPH0355822A (ja) 1989-07-25 1991-03-11 Shin Etsu Handotai Co Ltd 半導体素子形成用基板の製造方法
US4948458A (en) 1989-08-14 1990-08-14 Lam Research Corporation Method and apparatus for producing magnetically-coupled planar plasma
US5036023A (en) 1989-08-16 1991-07-30 At&T Bell Laboratories Rapid thermal processing method of making a semiconductor device
US5013681A (en) 1989-09-29 1991-05-07 The United States Of America As Represented By The Secretary Of The Navy Method of producing a thin silicon-on-insulator layer
US5310446A (en) 1990-01-10 1994-05-10 Ricoh Company, Ltd. Method for producing semiconductor film
JPH0650738B2 (ja) 1990-01-11 1994-06-29 株式会社東芝 半導体装置及びその製造方法
US5034343A (en) 1990-03-08 1991-07-23 Harris Corporation Manufacturing ultra-thin wafer using a handle wafer
CN1018844B (zh) 1990-06-02 1992-10-28 中国科学院兰州化学物理研究所 防锈干膜润滑剂
JPH0719739B2 (ja) 1990-09-10 1995-03-06 信越半導体株式会社 接合ウェーハの製造方法
US5198371A (en) 1990-09-24 1993-03-30 Biota Corp. Method of making silicon material with enhanced surface mobility by hydrogen ion implantation
US5618739A (en) 1990-11-15 1997-04-08 Seiko Instruments Inc. Method of making light valve device using semiconductive composite substrate
US5300788A (en) 1991-01-18 1994-04-05 Kopin Corporation Light emitting diode bars and arrays and method of making same
DE4106288C2 (de) 1991-02-28 2001-05-31 Bosch Gmbh Robert Sensor zur Messung von Drücken oder Beschleunigungen
JP2812405B2 (ja) 1991-03-15 1998-10-22 信越半導体株式会社 半導体基板の製造方法
US5110748A (en) 1991-03-28 1992-05-05 Honeywell Inc. Method for fabricating high mobility thin film transistors as integrated drivers for active matrix display
US5442205A (en) 1991-04-24 1995-08-15 At&T Corp. Semiconductor heterostructure devices with strained semiconductor layers
US5256581A (en) 1991-08-28 1993-10-26 Motorola, Inc. Silicon film with improved thickness control
FR2681472B1 (fr) 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
JP3416163B2 (ja) 1992-01-31 2003-06-16 キヤノン株式会社 半導体基板及びその作製方法
JPH05235312A (ja) 1992-02-19 1993-09-10 Fujitsu Ltd 半導体基板及びその製造方法
US5614019A (en) 1992-06-08 1997-03-25 Air Products And Chemicals, Inc. Method for the growth of industrial crystals
US5234535A (en) 1992-12-10 1993-08-10 International Business Machines Corporation Method of producing a thin silicon-on-insulator layer
WO1994017558A1 (en) 1993-01-29 1994-08-04 The Regents Of The University Of California Monolithic passive component
US5400458A (en) 1993-03-31 1995-03-28 Minnesota Mining And Manufacturing Company Brush segment for industrial brushes
FR2714524B1 (fr) 1993-12-23 1996-01-26 Commissariat Energie Atomique Procede de realisation d'une structure en relief sur un support en materiau semiconducteur
DE69423594T2 (de) 1993-12-28 2000-07-20 Honda Giken Kogyo K.K., Tokio/Tokyo Gaszufuhrmechanismus für Gasbrennkraftmaschine
DE4400985C1 (de) 1994-01-14 1995-05-11 Siemens Ag Verfahren zur Herstellung einer dreidimensionalen Schaltungsanordnung
FR2715501B1 (fr) 1994-01-26 1996-04-05 Commissariat Energie Atomique Procédé de dépôt de lames semiconductrices sur un support.
FR2715503B1 (fr) 1994-01-26 1996-04-05 Commissariat Energie Atomique Substrat pour composants intégrés comportant une couche mince et son procédé de réalisation.
FR2715502B1 (fr) 1994-01-26 1996-04-05 Commissariat Energie Atomique Structure présentant des cavités et procédé de réalisation d'une telle structure.
JP3293736B2 (ja) 1996-02-28 2002-06-17 キヤノン株式会社 半導体基板の作製方法および貼り合わせ基体
JP3352340B2 (ja) 1995-10-06 2002-12-03 キヤノン株式会社 半導体基体とその製造方法
US5880010A (en) 1994-07-12 1999-03-09 Sun Microsystems, Inc. Ultrathin electronics
JPH0851103A (ja) 1994-08-08 1996-02-20 Fuji Electric Co Ltd 薄膜の生成方法
US5524339A (en) 1994-09-19 1996-06-11 Martin Marietta Corporation Method for protecting gallium arsenide mmic air bridge structures
FR2725074B1 (fr) 1994-09-22 1996-12-20 Commissariat Energie Atomique Procede de fabrication d'une structure comportant une couche mince semi-conductrice sur un substrat
US5567654A (en) 1994-09-28 1996-10-22 International Business Machines Corporation Method and workpiece for connecting a thin layer to a monolithic electronic module's surface and associated module packaging
EP0749500B1 (en) 1994-10-18 1998-05-27 Koninklijke Philips Electronics N.V. Method of manufacturing a thin silicon-oxide layer
EP0799495A4 (en) 1994-11-10 1999-11-03 Lawrence Semiconductor Researc Silicon-germanium-carbon compositions and processes thereof
KR960026128A (enExample) 1994-12-12 1996-07-22
JP3381443B2 (ja) 1995-02-02 2003-02-24 ソニー株式会社 基体から半導体層を分離する方法、半導体素子の製造方法およびsoi基板の製造方法
FR2736934B1 (fr) 1995-07-21 1997-08-22 Commissariat Energie Atomique Procede de fabrication d'une structure avec une couche utile maintenue a distance d'un substrat par des butees, et de desolidarisation d'une telle couche
FR2738671B1 (fr) 1995-09-13 1997-10-10 Commissariat Energie Atomique Procede de fabrication de films minces a materiau semiconducteur
FR2744285B1 (fr) 1996-01-25 1998-03-06 Commissariat Energie Atomique Procede de transfert d'une couche mince d'un substrat initial sur un substrat final
FR2747506B1 (fr) 1996-04-11 1998-05-15 Commissariat Energie Atomique Procede d'obtention d'un film mince de materiau semiconducteur comprenant notamment des composants electroniques
FR2748851B1 (fr) 1996-05-15 1998-08-07 Commissariat Energie Atomique Procede de realisation d'une couche mince de materiau semiconducteur
FR2748850B1 (fr) 1996-05-15 1998-07-24 Commissariat Energie Atomique Procede de realisation d'un film mince de materiau solide et applications de ce procede
US5863832A (en) 1996-06-28 1999-01-26 Intel Corporation Capping layer in interconnect system and method for bonding the capping layer onto the interconnect system
US5897331A (en) 1996-11-08 1999-04-27 Midwest Research Institute High efficiency low cost thin film silicon solar cell design and method for making
US6127199A (en) 1996-11-12 2000-10-03 Seiko Epson Corporation Manufacturing method of active matrix substrate, active matrix substrate and liquid crystal display device
SG65697A1 (en) 1996-11-15 1999-06-22 Canon Kk Process for producing semiconductor article
US6054363A (en) 1996-11-15 2000-04-25 Canon Kabushiki Kaisha Method of manufacturing semiconductor article
DE19648501A1 (de) 1996-11-22 1998-05-28 Max Planck Gesellschaft Verfahren für die lösbare Verbindung und anschließende Trennung reversibel gebondeter und polierter Scheiben sowie eine Waferstruktur und Wafer
KR100232886B1 (ko) 1996-11-23 1999-12-01 김영환 Soi 웨이퍼 제조방법
DE19648759A1 (de) 1996-11-25 1998-05-28 Max Planck Gesellschaft Verfahren zur Herstellung von Mikrostrukturen sowie Mikrostruktur
FR2756847B1 (fr) 1996-12-09 1999-01-08 Commissariat Energie Atomique Procede de separation d'au moins deux elements d'une structure en contact entre eux par implantation ionique
SG67458A1 (en) 1996-12-18 1999-09-21 Canon Kk Process for producing semiconductor article
FR2758907B1 (fr) 1997-01-27 1999-05-07 Commissariat Energie Atomique Procede d'obtention d'un film mince, notamment semiconducteur, comportant une zone protegee des ions, et impliquant une etape d'implantation ionique
JP3114643B2 (ja) 1997-02-20 2000-12-04 日本電気株式会社 半導体基板の構造および製造方法
CA2233096C (en) * 1997-03-26 2003-01-07 Canon Kabushiki Kaisha Substrate and production method thereof
JPH10275752A (ja) 1997-03-28 1998-10-13 Ube Ind Ltd 張合わせウエハ−及びその製造方法、基板
US6013954A (en) 1997-03-31 2000-01-11 Nec Corporation Semiconductor wafer having distortion-free alignment regions
US6251754B1 (en) 1997-05-09 2001-06-26 Denso Corporation Semiconductor substrate manufacturing method
US5994207A (en) 1997-05-12 1999-11-30 Silicon Genesis Corporation Controlled cleavage process using pressurized fluid
US6033974A (en) 1997-05-12 2000-03-07 Silicon Genesis Corporation Method for controlled cleaving process
US6150239A (en) 1997-05-31 2000-11-21 Max Planck Society Method for the transfer of thin layers monocrystalline material onto a desirable substrate
US5877070A (en) 1997-05-31 1999-03-02 Max-Planck Society Method for the transfer of thin layers of monocrystalline material to a desirable substrate
US6054369A (en) 1997-06-30 2000-04-25 Intersil Corporation Lifetime control for semiconductor devices
JP4473349B2 (ja) 1997-06-30 2010-06-02 マクス−プランク−ゲゼルシャフト ツル フォルデルング デル ヴァイセンシャフト エー ファウ 層状構造体製造方法、及び半導体基板
US6097096A (en) 1997-07-11 2000-08-01 Advanced Micro Devices Metal attachment method and structure for attaching substrates at low temperatures
US6534380B1 (en) 1997-07-18 2003-03-18 Denso Corporation Semiconductor substrate and method of manufacturing the same
US6103599A (en) 1997-07-25 2000-08-15 Silicon Genesis Corporation Planarizing technique for multilayered substrates
US6316820B1 (en) 1997-07-25 2001-11-13 Hughes Electronics Corporation Passivation layer and process for semiconductor devices
US6255731B1 (en) 1997-07-30 2001-07-03 Canon Kabushiki Kaisha SOI bonding structure
FR2767416B1 (fr) 1997-08-12 1999-10-01 Commissariat Energie Atomique Procede de fabrication d'un film mince de materiau solide
FR2767604B1 (fr) 1997-08-19 2000-12-01 Commissariat Energie Atomique Procede de traitement pour le collage moleculaire et le decollage de deux structures
US5882987A (en) 1997-08-26 1999-03-16 International Business Machines Corporation Smart-cut process for the production of thin semiconductor material films
JP3697034B2 (ja) 1997-08-26 2005-09-21 キヤノン株式会社 微小開口を有する突起の製造方法、及びそれらによるプローブまたはマルチプローブ
US5981400A (en) 1997-09-18 1999-11-09 Cornell Research Foundation, Inc. Compliant universal substrate for epitaxial growth
US5920764A (en) 1997-09-30 1999-07-06 International Business Machines Corporation Process for restoring rejected wafers in line for reuse as new
JP2998724B2 (ja) 1997-11-10 2000-01-11 日本電気株式会社 張り合わせsoi基板の製造方法
FR2771852B1 (fr) 1997-12-02 1999-12-31 Commissariat Energie Atomique Procede de transfert selectif d'une microstructure, formee sur un substrat initial, vers un substrat final
FR2773261B1 (fr) 1997-12-30 2000-01-28 Commissariat Energie Atomique Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions
SG87916A1 (en) 1997-12-26 2002-04-16 Canon Kk Sample separating apparatus and method, and substrate manufacturing method
JP3501642B2 (ja) 1997-12-26 2004-03-02 キヤノン株式会社 基板処理方法
US6071795A (en) 1998-01-23 2000-06-06 The Regents Of The University Of California Separation of thin films from transparent substrates by selective optical processing
FR2774510B1 (fr) 1998-02-02 2001-10-26 Soitec Silicon On Insulator Procede de traitement de substrats, notamment semi-conducteurs
JPH11233449A (ja) * 1998-02-13 1999-08-27 Denso Corp 半導体基板の製造方法
US6120597A (en) * 1998-02-17 2000-09-19 The Trustees Of Columbia University In The City Of New York Crystal ion-slicing of single-crystal films
TW437078B (en) 1998-02-18 2001-05-28 Canon Kk Composite member, its separation method, and preparation method of semiconductor substrate by utilization thereof
JP3809733B2 (ja) 1998-02-25 2006-08-16 セイコーエプソン株式会社 薄膜トランジスタの剥離方法
JPH11307747A (ja) 1998-04-17 1999-11-05 Nec Corp Soi基板およびその製造方法
US6057212A (en) 1998-05-04 2000-05-02 International Business Machines Corporation Method for making bonded metal back-plane substrates
JP3456521B2 (ja) * 1998-05-12 2003-10-14 三菱住友シリコン株式会社 Soi基板の製造方法
CN1241803A (zh) * 1998-05-15 2000-01-19 佳能株式会社 半导体衬底、半导体薄膜以及多层结构的制造工艺
US5909627A (en) 1998-05-18 1999-06-01 Philips Electronics North America Corporation Process for production of thin layers of semiconductor material
DE19840421C2 (de) 1998-06-22 2000-05-31 Fraunhofer Ges Forschung Verfahren zur Fertigung von dünnen Substratschichten und eine dafür geeignete Substratanordnung
US6054370A (en) 1998-06-30 2000-04-25 Intel Corporation Method of delaminating a pre-fabricated transistor layer from a substrate for placement on another wafer
US6271101B1 (en) 1998-07-29 2001-08-07 Semiconductor Energy Laboratory Co., Ltd. Process for production of SOI substrate and process for production of semiconductor device
US6118181A (en) 1998-07-29 2000-09-12 Agilent Technologies, Inc. System and method for bonding wafers
FR2781925B1 (fr) 1998-07-30 2001-11-23 Commissariat Energie Atomique Transfert selectif d'elements d'un support vers un autre support
WO2000019500A1 (en) * 1998-09-25 2000-04-06 Asahi Kasei Kabushiki Kaisha Semiconductor substrate and its production method, semiconductor device comprising the same and its production method
EP0989593A3 (en) 1998-09-25 2002-01-02 Canon Kabushiki Kaisha Substrate separating apparatus and method, and substrate manufacturing method
FR2784800B1 (fr) 1998-10-20 2000-12-01 Commissariat Energie Atomique Procede de realisation de composants passifs et actifs sur un meme substrat isolant
CA2293040C (en) 1998-12-23 2006-10-24 Kohler Co. Dual fuel system for internal combustion engine
US6346458B1 (en) 1998-12-31 2002-02-12 Robert W. Bower Transposed split of ion cut materials
FR2789518B1 (fr) 1999-02-10 2003-06-20 Commissariat Energie Atomique Structure multicouche a contraintes internes controlees et procede de realisation d'une telle structure
GB2347230B (en) 1999-02-23 2003-04-16 Marconi Electronic Syst Ltd Optical slow-wave modulator
JP3532788B2 (ja) 1999-04-13 2004-05-31 唯知 須賀 半導体装置及びその製造方法
US6171965B1 (en) * 1999-04-21 2001-01-09 Silicon Genesis Corporation Treatment method of cleaved film for the manufacture of substrates
JP2001015721A (ja) 1999-04-30 2001-01-19 Canon Inc 複合部材の分離方法及び薄膜の製造方法
US6310387B1 (en) 1999-05-03 2001-10-30 Silicon Wave, Inc. Integrated circuit inductor with high self-resonance frequency
US6664169B1 (en) 1999-06-08 2003-12-16 Canon Kabushiki Kaisha Process for producing semiconductor member, process for producing solar cell, and anodizing apparatus
US6362082B1 (en) 1999-06-28 2002-03-26 Intel Corporation Methodology for control of short channel effects in MOS transistors
FR2796491B1 (fr) 1999-07-12 2001-08-31 Commissariat Energie Atomique Procede de decollement de deux elements et dispositif pour sa mise en oeuvre
US6323108B1 (en) 1999-07-27 2001-11-27 The United States Of America As Represented By The Secretary Of The Navy Fabrication ultra-thin bonded semiconductor layers
US6287940B1 (en) 1999-08-02 2001-09-11 Honeywell International Inc. Dual wafer attachment process
FR2797347B1 (fr) 1999-08-04 2001-11-23 Commissariat Energie Atomique Procede de transfert d'une couche mince comportant une etape de surfragililisation
US6263941B1 (en) 1999-08-10 2001-07-24 Silicon Genesis Corporation Nozzle for cleaving substrates
JP2003506883A (ja) 1999-08-10 2003-02-18 シリコン ジェネシス コーポレイション 低打ち込みドーズ量を用いて多層基板を製造するための劈開プロセス
EP1077475A3 (en) 1999-08-11 2003-04-02 Applied Materials, Inc. Method of micromachining a multi-part cavity
CN1118087C (zh) * 1999-09-27 2003-08-13 中国科学院半导体研究所 一种制备半导体衬底的方法
US6500694B1 (en) 2000-03-22 2002-12-31 Ziptronix, Inc. Three dimensional device integration method and integrated device
KR100413789B1 (ko) 1999-11-01 2003-12-31 삼성전자주식회사 고진공 패키징 마이크로자이로스코프 및 그 제조방법
DE19958803C1 (de) 1999-12-07 2001-08-30 Fraunhofer Ges Forschung Verfahren und Vorrichtung zum Handhaben von Halbleitersubstraten bei der Prozessierung und/oder Bearbeitung
JP2001196566A (ja) 2000-01-07 2001-07-19 Sony Corp 半導体基板およびその製造方法
US6306720B1 (en) 2000-01-10 2001-10-23 United Microelectronics Corp. Method for forming capacitor of mixed-mode device
JP3975634B2 (ja) 2000-01-25 2007-09-12 信越半導体株式会社 半導体ウェハの製作法
US6521477B1 (en) 2000-02-02 2003-02-18 Raytheon Company Vacuum package fabrication of integrated circuit components
US6902987B1 (en) 2000-02-16 2005-06-07 Ziptronix, Inc. Method for low temperature bonding and bonded structure
US6586841B1 (en) 2000-02-23 2003-07-01 Onix Microsystems, Inc. Mechanical landing pad formed on the underside of a MEMS device
US6548375B1 (en) 2000-03-16 2003-04-15 Hughes Electronics Corporation Method of preparing silicon-on-insulator substrates particularly suited for microwave applications
JP2003531492A (ja) 2000-04-14 2003-10-21 エス オー イ テク シリコン オン インシュレータ テクノロジース 特に半導体材料製の基板又はインゴットから少なくとも一枚の薄層を切り出す方法
KR20010112507A (ko) * 2000-06-05 2001-12-20 이구택 압연 롤 세정 장치
US6407929B1 (en) 2000-06-29 2002-06-18 Intel Corporation Electronic package having embedded capacitors and method of fabrication therefor
JP2002016150A (ja) * 2000-06-29 2002-01-18 Nec Corp 半導体記憶装置及びその製造方法
JP3440057B2 (ja) 2000-07-05 2003-08-25 唯知 須賀 半導体装置およびその製造方法
FR2811807B1 (fr) 2000-07-12 2003-07-04 Commissariat Energie Atomique Procede de decoupage d'un bloc de materiau et de formation d'un film mince
KR100984585B1 (ko) 2000-08-22 2010-09-30 프레지던트 앤드 펠로우즈 오브 하버드 칼리지 반도체 성장 방법 및 디바이스 제조 방법
FR2816445B1 (fr) 2000-11-06 2003-07-25 Commissariat Energie Atomique Procede de fabrication d'une structure empilee comprenant une couche mince adherant a un substrat cible
FR2818010B1 (fr) 2000-12-08 2003-09-05 Commissariat Energie Atomique Procede de realisation d'une couche mince impliquant l'introduction d'especes gazeuses
US7139947B2 (en) 2000-12-22 2006-11-21 Intel Corporation Test access port
FR2819099B1 (fr) 2000-12-28 2003-09-26 Commissariat Energie Atomique Procede de realisation d'une structure empilee
US6774010B2 (en) 2001-01-25 2004-08-10 International Business Machines Corporation Transferable device-containing layer for silicon-on-insulator applications
DE10104868A1 (de) 2001-02-03 2002-08-22 Bosch Gmbh Robert Mikromechanisches Bauelement sowie ein Verfahren zur Herstellung eines mikromechanischen Bauelements
JP2002270553A (ja) 2001-03-13 2002-09-20 Mitsubishi Gas Chem Co Inc 電子部品の製造法
JP2002305293A (ja) 2001-04-06 2002-10-18 Canon Inc 半導体部材の製造方法及び半導体装置の製造方法
US6734762B2 (en) 2001-04-09 2004-05-11 Motorola, Inc. MEMS resonators and method for manufacturing MEMS resonators
FR2823373B1 (fr) 2001-04-10 2005-02-04 Soitec Silicon On Insulator Dispositif de coupe de couche d'un substrat, et procede associe
FR2823599B1 (fr) 2001-04-13 2004-12-17 Commissariat Energie Atomique Substrat demomtable a tenue mecanique controlee et procede de realisation
FR2823596B1 (fr) 2001-04-13 2004-08-20 Commissariat Energie Atomique Substrat ou structure demontable et procede de realisation
US6759282B2 (en) 2001-06-12 2004-07-06 International Business Machines Corporation Method and structure for buried circuits and devices
FR2828428B1 (fr) 2001-08-07 2003-10-17 Soitec Silicon On Insulator Dispositif de decollement de substrats et procede associe
US6744114B2 (en) 2001-08-29 2004-06-01 Honeywell International Inc. Package with integrated inductor and/or capacitor
JP2003078117A (ja) * 2001-08-31 2003-03-14 Canon Inc 半導体部材及び半導体装置並びにそれらの製造方法
FR2830983B1 (fr) 2001-10-11 2004-05-14 Commissariat Energie Atomique Procede de fabrication de couches minces contenant des microcomposants
DE10153319B4 (de) 2001-10-29 2011-02-17 austriamicrosystems AG, Schloss Premstätten Mikrosensor
TWI251813B (en) 2001-11-09 2006-03-21 Via Tech Inc Method for protecting phase lock loop in optical data-reading system
FR2833106B1 (fr) 2001-12-03 2005-02-25 St Microelectronics Sa Circuit integre comportant un composant auxiliaire, par exemple un composant passif ou un microsysteme electromecanique, dispose au-dessus d'une puce electronique, et procede de fabrication correspondant
KR100442105B1 (ko) 2001-12-03 2004-07-27 삼성전자주식회사 소이형 기판 형성 방법
FR2834820B1 (fr) 2002-01-16 2005-03-18 Procede de clivage de couches d'une tranche de materiau
FR2835097B1 (fr) 2002-01-23 2005-10-14 Procede optimise de report d'une couche mince de carbure de silicium sur un substrat d'accueil
US6887769B2 (en) 2002-02-06 2005-05-03 Intel Corporation Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same
US6762076B2 (en) 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
US6596569B1 (en) 2002-03-15 2003-07-22 Lucent Technologies Inc. Thin film transistors
US6607969B1 (en) 2002-03-18 2003-08-19 The United States Of America As Represented By The Secretary Of The Navy Method for making pyroelectric, electro-optical and decoupling capacitors using thin film transfer and hydrogen ion splitting techniques
US6767749B2 (en) 2002-04-22 2004-07-27 The United States Of America As Represented By The Secretary Of The Navy Method for making piezoelectric resonator and surface acoustic wave device using hydrogen implant layer splitting
US6632082B1 (en) 2002-05-01 2003-10-14 Colibri Corporation Lighter and method of use
US6645831B1 (en) 2002-05-07 2003-11-11 Intel Corporation Thermally stable crystalline defect-free germanium bonded to silicon and silicon dioxide
US7157119B2 (en) 2002-06-25 2007-01-02 Ppg Industries Ohio, Inc. Method and compositions for applying multiple overlying organic pigmented decorations on ceramic substrates
FR2842349B1 (fr) 2002-07-09 2005-02-18 Transfert d'une couche mince a partir d'une plaquette comprenant une couche tampon
US6953736B2 (en) 2002-07-09 2005-10-11 S.O.I.Tec Silicon On Insulator Technologies S.A. Process for transferring a layer of strained semiconductor material
US7176108B2 (en) * 2002-11-07 2007-02-13 Soitec Silicon On Insulator Method of detaching a thin film at moderate temperature after co-implantation
FR2847075B1 (fr) 2002-11-07 2005-02-18 Commissariat Energie Atomique Procede de formation d'une zone fragile dans un substrat par co-implantation
FR2848336B1 (fr) 2002-12-09 2005-10-28 Commissariat Energie Atomique Procede de realisation d'une structure contrainte destinee a etre dissociee
FR2850487B1 (fr) 2002-12-24 2005-12-09 Commissariat Energie Atomique Procede de realisation de substrats mixtes et structure ainsi obtenue
WO2004061944A1 (en) 2003-01-07 2004-07-22 S.O.I.Tec Silicon On Insulator Technologies Recycling of a wafer comprising a multi-layer structure after taking-off a thin layer
US7018909B2 (en) 2003-02-28 2006-03-28 S.O.I.Tec Silicon On Insulator Technologies S.A. Forming structures that include a relaxed or pseudo-relaxed layer on a substrate
US7348260B2 (en) 2003-02-28 2008-03-25 S.O.I.Tec Silicon On Insulator Technologies Method for forming a relaxed or pseudo-relaxed useful layer on a substrate
FR2856844B1 (fr) 2003-06-24 2006-02-17 Commissariat Energie Atomique Circuit integre sur puce de hautes performances
FR2857953B1 (fr) 2003-07-21 2006-01-13 Commissariat Energie Atomique Structure empilee, et procede pour la fabriquer
US7052978B2 (en) * 2003-08-28 2006-05-30 Intel Corporation Arrangements incorporating laser-induced cleaving
US7029980B2 (en) 2003-09-25 2006-04-18 Freescale Semiconductor Inc. Method of manufacturing SOI template layer
WO2005059979A1 (en) 2003-12-16 2005-06-30 Koninklijke Philips Electronics N.V. Method for forming a strained si-channel in a mosfet structure
US7772087B2 (en) 2003-12-19 2010-08-10 Commissariat A L'energie Atomique Method of catastrophic transfer of a thin film after co-implantation
US7521292B2 (en) 2004-06-04 2009-04-21 The Board Of Trustees Of The University Of Illinois Stretchable form of single crystal silicon for high performance electronics on rubber substrates
US6893936B1 (en) 2004-06-29 2005-05-17 International Business Machines Corporation Method of Forming strained SI/SIGE on insulator with silicon germanium buffer
EP1650794B1 (en) 2004-10-19 2008-01-16 S.O.I. Tec Silicon on Insulator Technologies S.A. A method for fabricating a wafer structure with a strained silicon layer and an intermediate product of this method
FR2889887B1 (fr) 2005-08-16 2007-11-09 Commissariat Energie Atomique Procede de report d'une couche mince sur un support
FR2891281B1 (fr) 2005-09-28 2007-12-28 Commissariat Energie Atomique Procede de fabrication d'un element en couches minces.
FR2899378B1 (fr) 2006-03-29 2008-06-27 Commissariat Energie Atomique Procede de detachement d'un film mince par fusion de precipites
EP1928020B1 (en) 2006-11-30 2020-04-22 Soitec Method of manufacturing a semiconductor heterostructure
FR2910179B1 (fr) 2006-12-19 2009-03-13 Commissariat Energie Atomique PROCEDE DE FABRICATION DE COUCHES MINCES DE GaN PAR IMPLANTATION ET RECYCLAGE D'UN SUBSTRAT DE DEPART
FR2922359B1 (fr) 2007-10-12 2009-12-18 Commissariat Energie Atomique Procede de fabrication d'une structure micro-electronique impliquant un collage moleculaire
FR2925221B1 (fr) 2007-12-17 2010-02-19 Commissariat Energie Atomique Procede de transfert d'une couche mince
FR2947098A1 (fr) 2009-06-18 2010-12-24 Commissariat Energie Atomique Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0994503A1 (fr) * 1998-10-16 2000-04-19 Commissariat A L'energie Atomique Structure comportant une couche mince de matériau composée de zones conductrices et de zones isolantes et procédé de fabrication d'une telle structure
WO2000063965A1 (en) * 1999-04-21 2000-10-26 Silicon Genesis Corporation Treatment method of cleaved film for the manufacture of substrates
US20030077885A1 (en) * 2000-05-30 2003-04-24 Bernard Aspar Embrittled substrate and method for making same
US20020025604A1 (en) * 2000-08-30 2002-02-28 Sandip Tiwari Low temperature semiconductor layering and three-dimensional electronic circuits using the layering
US6593212B1 (en) * 2001-10-29 2003-07-15 The United States Of America As Represented By The Secretary Of The Navy Method for making electro-optical devices using a hydrogenion splitting technique

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
AGARWAL A ET AL: "EFFICIENT PRODUCTION OF SILICON-ON-INSULATOR FILMS BY CO- IMPLANTATION OF HE+ WITH H+", APPLIED PHYSICS LETTERS, AMERICAN INSTITUTE OF PHYSICS. NEW YORK, US, vol. 72, no. 9, 2 March 1998 (1998-03-02), pages 1086 - 1088, XP000742819, ISSN: 0003-6951 *

Cited By (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8609514B2 (en) 1997-12-10 2013-12-17 Commissariat A L'energie Atomique Process for the transfer of a thin film comprising an inclusion creation step
US8470712B2 (en) 1997-12-30 2013-06-25 Commissariat A L'energie Atomique Process for the transfer of a thin film comprising an inclusion creation step
US8389379B2 (en) 2002-12-09 2013-03-05 Commissariat A L'energie Atomique Method for making a stressed structure designed to be dissociated
US8048766B2 (en) 2003-06-24 2011-11-01 Commissariat A L'energie Atomique Integrated circuit on high performance chip
US7485545B2 (en) 2004-12-28 2009-02-03 S.O.I.Tec Silicon On Insulator Technologies Method of configuring a process to obtain a thin layer with a low density of holes
US8142593B2 (en) 2005-08-16 2012-03-27 Commissariat A L'energie Atomique Method of transferring a thin film onto a support
US8664084B2 (en) 2005-09-28 2014-03-04 Commissariat A L'energie Atomique Method for making a thin-film element
DE112006003447B4 (de) 2005-12-22 2013-03-07 Soitec Prozess zur Ausbildung einer Anordnung, die eine Dünnschicht aufweist
US7514341B2 (en) 2005-12-22 2009-04-07 S.O.I.Tec Silicon On Insulator Technologies Finishing process for the manufacture of a semiconductor structure
JP2007251172A (ja) * 2006-03-13 2007-09-27 Soi Tec Silicon On Insulator Technologies Sa 薄膜を製造する方法
US8778775B2 (en) 2006-12-19 2014-07-15 Commissariat A L'energie Atomique Method for preparing thin GaN layers by implantation and recycling of a starting substrate
US8252663B2 (en) 2009-06-18 2012-08-28 Commissariat A L'energie Atomique Et Aux Energies Alternatives Method of transferring a thin layer onto a target substrate having a coefficient of thermal expansion different from that of the thin layer
TWI648765B (zh) * 2014-04-16 2019-01-21 法商梭意泰科公司 用於轉移有用層之方法
EP2933828A1 (en) 2014-04-16 2015-10-21 Soitec Method for transferring a useful layer
US9589830B2 (en) 2014-04-16 2017-03-07 Soitec Method for transferring a useful layer
US9922867B2 (en) 2015-02-10 2018-03-20 Soitec Method for transferring a useful layer
FR3093716A1 (fr) 2019-03-15 2020-09-18 Soitec systeme de fracture d'une pluralitÉ d'assemblages de tranches.
FR3093859A1 (fr) 2019-03-15 2020-09-18 Soitec Procédé de transfert d’une couche utile sur une substrat support
FR3093860A1 (fr) 2019-03-15 2020-09-18 Soitec Procédé de transfert d’une couche utile sur un substrat support
FR3093858A1 (fr) 2019-03-15 2020-09-18 Soitec Procédé de transfert d’une couche utile sur un substrat support
WO2020188167A1 (fr) 2019-03-15 2020-09-24 Soitec Procede de transfert d'une couche utile sur un substrat support
WO2020188168A1 (fr) 2019-03-15 2020-09-24 Soitec Procede de transfert d'une couche utile sur un substrat support
WO2020188169A1 (fr) 2019-03-15 2020-09-24 Soitec Procede de transfert d'une couche utile sur une substrat support
WO2020188170A1 (fr) 2019-03-15 2020-09-24 Soitec Système de fracture d'une pluralité d'assemblages de tranches
US11876015B2 (en) 2019-03-15 2024-01-16 Soitec Method for transferring a useful layer to a carrier substrate
US11881429B2 (en) 2019-03-15 2024-01-23 Soitec Method for transferring a useful layer onto a support substrate
US12002690B2 (en) 2019-03-15 2024-06-04 Soitec System for fracturing a plurality of wafer assemblies
US12142517B2 (en) 2019-03-15 2024-11-12 Soitec Method for transferring a useful layer from a donor substrate onto a support substrate by applying a predetermined stress

Also Published As

Publication number Publication date
KR20060122830A (ko) 2006-11-30
WO2005043616A1 (fr) 2005-05-12
CN100474556C (zh) 2009-04-01
EP1678755A1 (fr) 2006-07-12
JP2007510298A (ja) 2007-04-19
EP1678754B1 (fr) 2015-07-15
KR20070051765A (ko) 2007-05-18
FR2861497B1 (fr) 2006-02-10
EP1678755B1 (fr) 2012-10-17
US8309431B2 (en) 2012-11-13
JP5142528B2 (ja) 2013-02-13
US20070281445A1 (en) 2007-12-06
TWI349303B (en) 2011-09-21
JP2007511069A (ja) 2007-04-26
TW200524010A (en) 2005-07-16
CN100474557C (zh) 2009-04-01
KR101120621B1 (ko) 2012-03-16
CN1864256A (zh) 2006-11-15
EP1678754A1 (fr) 2006-07-12
JP5244315B2 (ja) 2013-07-24
CN1868053A (zh) 2006-11-22
FR2861497A1 (fr) 2005-04-29

Similar Documents

Publication Publication Date Title
EP1678754B1 (fr) Procede de transfert auto-entretenu d'une couche fine par impulsion apres implantation ou co-implantation
EP1285461B1 (fr) Procede de fabrication d'une couche mince
EP1010198B1 (fr) Procede de fabrication d'un film mince de materiau solide
EP1051739B1 (fr) Substrat compliant en particulier pour un depot par hetero-epitaxie
EP1733423A1 (fr) TRAITEMENT THERMIQUE D’AMELIORATION DE LA QUALITE D’UNE COUCHE MINCE PRELEVEE
EP2259302B1 (fr) Procédé d'obtention d'une couche mince de qualité accrue par co-implantation et recuit thermique.
FR2855909A1 (fr) Procede d'obtention concomitante d'au moins une paire de structures comprenant au moins une couche utile reportee sur un substrat
EP2342744A1 (fr) Procede de formation d'une couche monocristalline dans le domaine micro-electronique
EP2002474A2 (fr) Procede de detachement d'un film mince par fusion de precipites
FR2842650A1 (fr) Procede de fabrication de substrats notamment pour l'optique, l'electronique ou l'opto-electronique
WO2008031980A1 (fr) Procede de transfert d'une couche a haute temperature
FR2938119A1 (fr) Procede de detachement de couches semi-conductrices a basse temperature
FR2880988A1 (fr) TRAITEMENT D'UNE COUCHE EN SI1-yGEy PRELEVEE
FR2889887A1 (fr) Procede de report d'une couche mince sur un support
FR2907966A1 (fr) Procede de fabrication d'un substrat.
EP2023380A1 (fr) Procédé et installation pour la fracture d'un substrat composite selon un plan de fragilisation
WO2020188169A1 (fr) Procede de transfert d'une couche utile sur une substrat support
FR2912550A1 (fr) Procede de fabrication d'une structure ssoi.
EP4473553B1 (fr) Procede de transfert d'une couche mince sur un substrat support
WO2026027548A1 (fr) Procede de preparation d'une couche mince de materiau ferroelectrique monodomaine
EP1861873A1 (fr) Procede de fabrication d'une hetero-structure comportant au moins une couche epaisse de materiau semi-conducteur
WO2006077216A2 (fr) Formation et traitement d'une structure en sige
FR2843827A1 (fr) Recyclage mecanique d'une plaquette comprenant une couche tampon, apres y avoir preleve une couche mince
FR2886457A1 (fr) Procede de fabrication d'une structure a couche d'oxyde d'epaisseur desiree,notammentt sur substrat de ge ou sige

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200480029823.1

Country of ref document: CN

AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): BW GH GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 2004805334

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 1020067007012

Country of ref document: KR

WWE Wipo information: entry into national phase

Ref document number: 2006537358

Country of ref document: JP

WWP Wipo information: published in national office

Ref document number: 2004805334

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 1020067007012

Country of ref document: KR

WWE Wipo information: entry into national phase

Ref document number: 10577175

Country of ref document: US

WWP Wipo information: published in national office

Ref document number: 10577175

Country of ref document: US