WO2005004047A1 - マルチファンクションカードデバイス - Google Patents
マルチファンクションカードデバイス Download PDFInfo
- Publication number
- WO2005004047A1 WO2005004047A1 PCT/JP2003/008434 JP0308434W WO2005004047A1 WO 2005004047 A1 WO2005004047 A1 WO 2005004047A1 JP 0308434 W JP0308434 W JP 0308434W WO 2005004047 A1 WO2005004047 A1 WO 2005004047A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- terminal
- card device
- antenna
- interface
- semiconductor
- Prior art date
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
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- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
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- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
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- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/0772—Physical layout of the record carrier
- G06K19/07732—Physical layout of the record carrier the record carrier having a housing or construction similar to well-known portable memory devices, such as SD cards, USB or memory sticks
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- H01L2924/3025—Electromagnetic shielding
Definitions
- the present invention relates to a multi-function card device such as a multi-function memory card that can support several types of memory card standards and support security processing.
- MMC MultiMediaCard
- HSMMC High Speed MultiMediaCard
- R SMMC Reduced Size Multi Media Card
- SD card Memory Stick, Memory Stick Pro, etc.
- MMC MultiMediaCard
- HSMMC High Speed MultiMediaCard
- R SMMC Reduced Size Multi Media Card
- SD card Memory Stick, Memory Stick Pro, etc.
- MMC MultiMediaCard
- HSMMC High Speed MultiMediaCard
- R SMMC Reduced Size Multi Media Card
- SD card Memory Stick
- Memory Stick Pro Memory Stick Pro
- Japanese Unexamined Patent Publication No. 2003-31613 describes a storage device having a plurality of controller chips, supporting interface modes corresponding to the respective controller chips, and enabling mode switching.
- Japanese Patent Application Laid-Open No. 2003-9174 discloses a flash memory chip. It describes an IC card chip that performs security processing and a storage device that has a controller chip that controls them according to external instructions.
- the inventor has studied a multi-function card device capable of supporting several types of memory card standards and supporting one security process. According to this, it is clear that if there are three or more corresponding standards, it is necessary to consider multiple aspects such as guaranteeing reliability and suppressing an increase in physical scale by partially commonizing and individualizing terminals.
- security processing it is assumed that the security controller performs an interface by itself or uses a memory card interface, and it is necessary to be able to cope with various interface possibilities.
- not only contact interfaces but also non-contact interfaces such as transformer coupling have become widespread, and it is necessary to consider antenna characteristics improvement and EMI (Electro magnetic interference) measures from the viewpoint of ensuring the reliability of the interface. become.
- EMI Electro magnetic interference
- the operating power is obtained from the electromotive force (induced electromotive force) generated by electromagnetic induction due to transformer coupling.
- electromotive force induced electromotive force
- the operating power must be obtained by induced electromotive force in the same way, especially for mode selection switches and power switches that are always on or off, power is required to maintain the switch state. He recognized the advantages of considering low power consumption, which does not require consumption.
- An object of the present invention is to provide a multi-function card device or the like capable of complying with several types of memory card standards and performing security processing, and the like. It is to provide a means.
- a multifunction card device a plurality of semiconductor chips are mounted on a wiring board on which external connection terminals are formed, one semiconductor chip constitutes an interface controller connected to the external connection terminals, and the other semiconductor chip comprises And a memory connected to the interface controller.
- the interface controller has a plurality of interface control modes, and controls an external interface operation and a memory interface operation in accordance with a control mode in accordance with an external instruction or an internal setting determined in advance.
- the external connection terminal has an individual terminal that is individualized for each of the interface control modes, and a common terminal that is common for each of the interface control modes.
- the common terminal includes a quick input terminal, a power supply terminal, and a ground terminal.
- the individual terminals include data terminals. With respect to several types of interface control modes, partial commonality and individualization of external connection terminals can satisfy both aspects of guaranteeing interface reliability and suppressing an increase in physical scale.
- a security controller constituted by the same or different semiconductor chip as the interface controller is further provided.
- the security controller is connected to the interface controller and an external connection terminal.
- the individual terminal further includes a dedicated terminal of the security controller. Security processing can be assured by the security controller's single interface.
- the security controller is a so-called IC card microcomputer, Multifunctional card devices can function in the same way as conventional IC cards.
- the security controller has a clock terminal, a data input / output terminal, a reset terminal, a power supply terminal, and a ground terminal as dedicated terminals.
- the external card host can independently recognize the security controller according to the signal state of the dedicated terminal.
- the security controller performs a security process according to a signal state of the external terminal or an operation command given from an interface controller. This makes it possible to use the memory card interface to function together with the memory while ensuring that the security controller functions alone.
- the security controller further includes an internal antenna, and the security controller can perform a non-contact interface using the antenna.
- the induced electromotive force generated by the transformer coupling can be used independently as the operating power supply. This is meaningful when the multifunction card device is removed from the card host or used when the power of the card host is turned off.
- the device further includes an external antenna connection terminal to which an external antenna can be connected, and a switch circuit which can selectively connect an external antenna connection terminal to the security controller instead of the internal antenna.
- the switch circuit includes a nonvolatile memory element interposed between corresponding connection terminals and capable of controlling the interruption or conduction of a path according to a threshold voltage that can be electrically changed, and a switching terminal viewed from a selection terminal of the nonvolatile memory element. Threshold voltage in the first state And a control circuit for interrupting the path, setting the threshold voltage of the path to the second state, and conducting the path. In the second state of the threshold voltage, the selection terminal is connected to a circuit ground voltage. As a result, power consumption is not required to maintain the on-state switch state for conducting the path.
- a pair of separating switches may be arranged in series with the nonvolatile memory element interposed therebetween.
- the separation switch is turned on when its selection terminal is connected to the ground voltage of the circuit.
- the control circuit controls the separation switch to an off state when changing the threshold voltage of the nonvolatile storage element.
- the non-volatile memory element includes, for example, a bipolar transistor portion, and a non-volatile MOS transistor portion having a drain and a source connected between the base and the collector of the bipolar transistor portion, and the non-volatile MOS transistor portion has a source A charge storage region is formed on the channel between the drains via an insulating film, and the threshold voltage is varied according to the charge stored in the charge storage region.
- the security controller has a dedicated external power supply terminal as the individual terminal, the security controller alone can perform power-on reset without resetting the entire multifunction card device, thereby improving usability.
- an external power supply terminal common to the security controller and the interface controller is provided as the external connection terminal, and a power supply path from the common external power supply terminal to the power supply terminal of the security controller cuts off power supply under the control of the interface controller. It may have a possible power switch. This also enables power-on reset by the security controller alone.
- the security controller and the interface controller have an external power supply terminal common to the security controller and the interface controller as the external connection terminal, and the security controller has a reset signal input terminal for instructing power-on reset from the interface controller. .
- the external connection terminal has an external power terminal
- the interface controller is supplied with operating power from the external power terminal
- the security controller is a power source generated using the operating power source, for example, a step-down power source.
- the security controller has an input terminal for a reset signal for instructing power-on reset from the interface controller. This also enables the power-on reset by the security controller alone. This is particularly effective when the security controller and the interface controller are formed on separate chips and the operating power supply voltages are different.
- the wiring is performed.
- the substrate is divided into a plurality of parts as a ground pattern to which the ground potential of the circuit is applied and connected without forming a closed circuit. It is desirable to have a ground pattern. On the surface of the large ground pattern, eddy current loss caused by fluctuating magnetic flux can be reduced, and deterioration or deterioration of antenna characteristics can be prevented or mitigated.
- the antenna is a semiconductor
- the semiconductor chip is arranged on the outer region of the chip, and the semiconductor chip is preferably stacked on a ferrite plate. Since the ferrite plate, which is a ferromagnetic material, has a high magnetic permeability, the magnetic flux tries to take a path along the ferrite plate without penetrating it. Therefore, since the antenna is arranged on the outer periphery of the ferrite plate, it is possible to obtain a large magnetic flux near the antenna, thereby improving the inductance performance of the antenna, that is, the antenna performance here. Can help.
- the semiconductor chip is superimposed on the ferrite plate, it is possible to reduce the transmission of magnetic flux to the semiconductor chip, and an undesired eddy current or induced electromotive force is generated in the semiconductor chip to cause a malfunction.
- the possibility of occurrence can be prevented beforehand.
- the ferrite plate is a ferrite chip, an applied ferrite paste, or an affixed ferrite film.
- the Fuerai bets collectively referred to herein ferromagnetic oxide represented by MQ ⁇ F e 2 ⁇ 3.
- the antenna should be arranged on the side of the semiconductor chip. I just need to. Also in this case, from the viewpoint of improving antenna performance, the antenna It is desirable to place a ferrite plate in the center of the corner.
- the antenna is, for example, a coil pattern formed on a wiring board or a coil wound on the wiring board.
- the coil pattern on the wiring board is superior in terms of cost. In terms of non-contact interface by transformer coupling, it is desirable that the coil padder has multiple layers.
- the antenna may be a dielectric antenna chip. It is desirable that the dielectric antenna chip be stacked on a ferrite plate in terms of antenna characteristics. At this time, the semiconductor chip may be stacked on the ferrite plate on the surface opposite to the stack surface of the dielectric antenna chip.
- a ferrite-mixed cap or a metal cap is provided in the cap.
- Adopt ⁇ is good.
- the cap is EMI (Electro Magnetic Interference).
- a semiconductor chip having an antenna and constituting the security controller is connected to the antenna to enable non-contact interface, and the external connection terminal is connected to the antenna.
- the antenna is formed in an outer region (for example, an outer peripheral region) of the semiconductor chip, and the semiconductor chip is stacked on a ferrite plate, and a receiving surface by the antenna is formed. It is desirable to provide an electromagnetic shield on the opposite side.
- the electromagnetic shield may be, for example, a ferrite mixed layer of a casing, a metal mixed layer of a casing, a coated surface of a ferrite mixed paint applied to a casing, a coated surface of a metal mixed paint applied to a casing, or a metal bonded to a casing. It is a vapor deposition label.
- the casing is a cap or a resin mold.
- the tuning capacitor may be composed of a chip capacitor, a varicap capacitor, a nonvolatile MOS capacitor, or the like.
- the multifunction card device when exposing the external connection terminals and sealing the whole in a package, at least two steps to be locked to the socket in the thickness direction of the package. Form them in places.
- the package is formed in a batch mold or MAP (mold 'array ⁇ package) form, and the steps are also integrally formed in the batch mold. Since the socket locks a step that is thinner than the package thickness, it is easier to minimize the thickness of the socket.
- the two step portions are not targeted, it is possible to prevent a situation where the socket is mounted on the package with the upper and lower sides or the left and right edges directed in opposite directions. This prevents a situation in which the socket terminal and the package terminal are in electrical contact with each other and the circuit / terminal is deteriorated or broken. it can.
- the external connection terminal exposed outside the package is considered. It may be non-symmetric with respect to the center of the package. Further, external connection terminals exposed outside the package may be arranged in a plurality of rows, and the plurality of rows may be biased with respect to a step portion of the package. Alternatively, the external connection terminals exposed outside the package may be arranged in a plurality of rows in parallel, and the plurality of rows may be mutually biased in the parallel direction.
- a plurality of semiconductor chips stacked on a wiring substrate or a ferrite plate are formed thinner as the surface area is smaller, and are arranged in an upper layer as the semiconductor chip is thinner. Good.
- the external connection terminals when the external connection terminals are exposed and the whole is sealed in a package, the external connection terminals are exposed outside the package as card sockets.
- a plurality of test terminals connected to the plurality of first external terminals and having a larger pitch and surface area than the first external terminal are arranged. Good.
- the plurality of first external terminals are spaced apart from each other and arranged in a plurality of rows, and the plurality of second external terminals are arranged in an entire region between the plurality of rows. . ⁇
- a semiconductor integrated circuit has a power switch circuit capable of selectively shutting off an operation power supply of the circuit.
- the power The switch circuit includes a non-volatile storage element interposed in a transmission path of an operating power supply, the threshold voltage of which is electrically changeable, and a threshold voltage as viewed from a selected terminal of the non-volatile storage element as a first state.
- a control circuit that cuts off the path, sets the threshold voltage of the path to the second state, and turns on the transmission path. In the second state of the threshold voltage, the selection terminal is connected to the ground voltage of the circuit. This eliminates the need for power consumption to maintain the on-state switch state for conducting the path.
- a pair of separating switches may be arranged in series with the nonvolatile memory element interposed therebetween.
- the separation switch is turned on when its selection terminal is connected to a fixed potential such as a circuit ground voltage.
- the control circuit controls the separation switch to be in an off state when changing the threshold voltage of the nonvolatile memory element. It is not necessary to make all circuits connected to the path high withstand voltage.
- a semiconductor integrated circuit has a switch circuit that can selectively cut off between circuits. By adopting the same configuration as the power switch circuit in the switch circuit, power consumption is not required to maintain the on-state switch state in which the path is conducted.
- the present invention can also be applied to a semiconductor device, such as a semiconductor device, and a semiconductor card device in which a semiconductor chip mounted on a wiring board is sealed in a package.
- FIG. 1 is a schematic explanatory diagram of a communication portable terminal device such as a mobile phone to which MFM C according to an example of the present invention is applied.
- FIG. 2 is a block diagram illustrating the configuration of the MFMC.
- FIG. 3 is an explanatory view showing an example of an external terminal of the MFM.
- FIG. 4 is an explanatory diagram exemplifying external connection terminals that are enabled when the SD card or MMC interface function is realized by the MFMC and corresponding SD card terminals.
- FIG. 5 is an explanatory diagram exemplifying external connection terminals that are enabled when the interface function of the HSMMC is realized by the MFMC and terminals of the corresponding HSMMC card.
- FIG. 6 is an explanatory diagram exemplifying the external connection terminals and the corresponding memory stick terminals that are enabled when the memory stick interface function is realized by the MFMC. .
- FIG. 7 is an explanatory diagram exemplifying an external connection terminal enabled when the contact interface function of the IC card microcomputer is realized by the MFMC and a corresponding terminal of the IC card microcomputer.
- FIG. 8 is an explanatory diagram exemplifying the external connection terminals enabled when the contact and non-contact interface functions of the IC card microcomputer are realized by the MFMC and the corresponding terminals of the IC card microcomputer.
- FIG. 9 is a flowchart showing a procedure of recognizing the interface function by the MFMC.
- Figure 10 is a block diagram illustrating the details of the interface controller. It is a figure
- FIG. 11 is a block diagram illustrating details of the IC card microcomputer.
- FIG. 12 is an explanatory diagram showing some uses for MFM C.
- FIG. 11 is a block diagram illustrating details of the IC card microcomputer.
- FIG. 12 is an explanatory diagram showing some uses for MFM C.
- FIG. 13 is a block diagram showing a first example of a power-on reset mechanism for the IC card microcomputer 11.
- FIG. 14 is a block diagram showing a second example of a power-on reset mechanism for the IC card microcomputer 11.
- FIG. 15 is a block diagram showing a third example of a power-on reset mechanism for the IC card microcomputer 11.
- FIG. 16 is a block diagram showing a fourth example of the power-on reset mechanism for the IC card microcomputer 11.
- FIG. 17 is a circuit diagram illustrating an internal antenna and its tuning capacitor.
- FIG. 18 is a longitudinal sectional view of a flash memory sensor transistor used as a nonvolatile MS capacitor.
- FIG. 19 is a circuit diagram showing an example in which an external antenna is detachably connected to an internal antenna.
- FIG. 20 is a circuit diagram illustrating a nonvolatile switch for path switching.
- FIG. 21 is a circuit diagram illustrating a nonvolatile switch in which a separating switch MOS transistor is arranged with a nonvolatile memory element interposed therebetween.
- FIG. 22 is an internal equivalent circuit diagram of a switch for selecting a path having the NVCBT structure.
- FIG. 23 is a longitudinal sectional view showing the element structure of the switch circuit shown in FIG.
- Fig. 24 is a circuit diagram in which a gate bias resistor is added to Fig. 22. It is.
- FIG. 25 is a block diagram showing an example in which a nonvolatile memory element represented by the NVC BT structure is applied to a power switch of a circuit.
- FIG. 26 is a block diagram in the case where a switch circuit and a control circuit using a nonvolatile memory element are applied to selectively disconnect an IC card microcomputer and an interface controller.
- FIG. 27 is a plan view illustrating a plane structure of the MFMC.
- FIG. 28 is a side cross-sectional view illustrating a side structure of the MFMC of FIG. 27.
- FIG. 29 is a side cross-sectional view illustrating another side structure of the MFMC.
- FIG. 30 is a transparent plan view illustrating another planar structure of the MFMC.
- FIG. 31 is a side view illustrating a side structure of the MFMC of FIG.
- FIG. 32 is a side cross-sectional view illustrating still another side structure of the MFMC.
- FIG. 33 is a plan view illustrating still another planar structure of the MFMC.
- FIG. 34 is a side sectional view showing a side structure of the MFMC corresponding to the plane structure of FIG. 33.
- FIG. 35 is a side cross-sectional view illustrating a side structure of still another MFMC.
- FIG. 36 is a side cross-sectional view illustrating a side structure of still another MFMC.
- FIG. 37 is a side sectional view of an MFMC using a dielectric antenna chip.
- Fig. 38 is an external perspective view of the MFMC to which the R SMMC package is applied.
- FIG. 39 shows the outside of the MFMC using the standard MMC package.
- FIG. 40 is a perspective view showing an example in which an internal antenna is provided inside the cap in the standard MMC package structure.
- FIG. 41 is a side sectional view showing the structure of the MFMC incorporated in the cap of FIG.
- FIG. 42 is a side cross-sectional view showing the MFMC assembled with the ferrite plate in the cap of FIG. 40.
- FIG. 43 is a side cross-sectional view illustrating a structure of an MFC M in which a divided ground pattern is formed on a wiring board.
- FIG. 44 is a sectional view showing a side sectional structure of FIG. 43.
- FIG. 45 is a side cross-sectional view illustrating a structure in which an electromagnetic shield is provided by a cap mixed with ferrite particles.
- FIG. 46 is a cross-sectional side view illustrating a structure in which a metal cap performs electromagnetic shielding.
- FIG. 47 is a side cross-sectional view illustrating a structure in which an electromagnetic scenerode is performed with a mold cap containing metal or ferrite.
- FIG. 48 is a side cross-sectional view illustrating a structure for performing electromagnetic shielding by a label.
- FIG. 49 is a cross-sectional side view illustrating another structure for performing electromagnetic shielding by a label.
- FIG. 50 is a side sectional view showing still another structure for performing electromagnetic shielding by a label.
- FIG. 51 is a perspective view showing an MFMC having a standard MMC package structure in which an electromagnetic shield label is attached in the format of FIG. 48.
- FIG. 52 is a perspective view showing an MFMC having an HSMMC package structure to which an electromagnetic shield label is attached in the format of FIG. 50.
- FIG. 53 is a perspective view showing the MFMC of the RSMMC package structure to which the electromagnetic shield label is attached in the format of FIG. 49.
- FIG. 54 is a cross-sectional view showing a vertical cross-sectional structure in which a step portion to be engaged with the elastic claw of the socket is formed in the sealing resin.
- FIG. 55 is a cross-sectional view showing a structure of a comparative example in which no step is provided in the sealing resin.
- FIG. 56 is a perspective view illustrating a structure in which a step portion is not symmetrical.
- FIG. 57 is a perspective view showing a state where the MFMC of FIG. 56 is mounted on a socket.
- FIG. 58 is a side view illustrating a structure in which the external connection terminals of the MFMC are nonlinearly symmetric with respect to the center of the package.
- FIG. 59 is a side view showing a state in which the MFMC is inserted into the socket in the left-right reversed direction in the structure of FIG.
- FIG. 60 is a plan view showing a terminal arrangement corresponding to the terminal configuration of FIG. 3 as a specific example of the terminal arrangement shifted left and right.
- FIG. 61 is a plan view showing a terminal arrangement in which external connection terminals are arranged in a plurality of rows as a terminal arrangement for preventing reverse insertion, and the plurality of rows are mutually biased in the parallel direction.
- FIG. 62 is a plan view showing a terminal arrangement employing both the deviation with respect to the step portion and the deviation in the arrangement direction of the terminal arrangement.
- FIG. 63 is a plan view showing a configuration in which the terminals are shifted entirely in one direction in the terminal arrangement direction with respect to the sealing resin to cause a bias.
- FIG. 64 is a perspective view showing another example of an unbalanced shape with respect to a step portion for preventing reverse insertion.
- FIG. 65 is a perspective view illustrating still another unbalanced shape with respect to a step portion for preventing reverse insertion.
- FIG. 66 is an explanatory diagram exemplifying an arrangement state of test terminals in the MFMC.
- FIG. 67 is a front view of a wiring board used for manufacturing an MFMC having a microphone opening MMC package structure having a step by batch molding.
- FIG. 68 is a front view showing a state in which chips are stacked on the wiring board shown in FIG. 67 and wire-bonded.
- FIG. 69 is a front sectional view showing a state in which a wiring board in which chips are stacked in a mold cavity is arranged.
- FIG. 70 is a front sectional view showing a state in which a sealing resin is injected into the cavity of FIG. 69.
- FIG. 71 is a front sectional view showing a state in which the sealing resin and the wiring substrate are diced.
- FIG. 72 is a front sectional view showing an individualized MFMC.
- FIG. 73 is a circuit diagram illustrating a case where the NVCBT structure of FIG. 22 is employed as a nonvolatile switch for path switching.
- FIG. 1 schematically shows a communication portable terminal device such as a portable telephone to which a multifunction memory card according to an example of the present invention is applied.
- Communication The mobile terminal 1 includes, for example, a microprocessor (MPU) 2 that controls the entire system, a baseband processing unit (BB) 3 that performs baseband processing such as modulation and demodulation for mobile communication, It has a high-frequency unit (RF c 1) 4 for transmitting and receiving by high frequency, and a multi-function memory card (MFMC) 5.
- the MFMC 5 is detachable from a card slot (not shown) of the communication portable terminal device 1.
- MPU 2 is MFMC 5 Is regarded as a card host.
- the MFM 5 has, for example, a storage function for memory storage, a multi-memory interface function for memory storage, security processing functions such as encryption / decryption processing of content data and user authentication, and a contactless interface function.
- a storage function for memory storage for example, a storage function for memory storage, a multi-memory interface function for memory storage, security processing functions such as encryption / decryption processing of content data and user authentication, and a contactless interface function.
- FIG. 2 shows an example of the configuration of the MFM 5.
- a plurality of semiconductor chips are mounted on a wiring board on which a plurality of external connection terminals 13A and 13B are formed, and one semiconductor chip is connected to the external connection terminals 13A.
- the other semiconductor chips constitute one or a plurality of memories 12 connected to the interface controller 10 described above.
- an IC card microcomputer 11 as a security controller composed of the interface controller 10 and another semiconductor chip.
- the IC card microcomputer 1 is connected to the interface controller 10 and an external connection terminal 13B.
- the IC card microcomputer 11 may be formed of the same semiconductor chip as the interface controller 10.
- the interface controller 10 has a plurality of interface control modes, and controls an external interface operation and a memory interface operation for the memory 2 in a control mode according to an external instruction.
- the interface control mode of the MFMC 5 is not particularly limited, each mode is an MMC, HS-MMC, SD card, or memory stick interface mode.
- Each memory card interface mode conforms to the interface specifications of each single memory card.
- the interface controller 10 uses the interface specifications of those memory cards.
- the functions of the supported memo card controller are realized by program control (partly by hard-wired logic, writing to ROM memory, etc.). Therefore, if you do not want to support a specific memory card interface specification, you do not need to have a control program for it.
- the operation may be disabled by a nonvolatile control bit or the like. It is also possible to later support the required memory card interface specifications by adding a control program to the interface controller 10 by downloading via a network or the like. If the execution of a predetermined control program is prohibited by the license information obtained via the network, the predetermined memory card interface specification can be disabled later.
- the function of the interface controller 10 is to exchange commands via the external connection terminal with the outside, recognize the memory card interface control mode corresponding to the bus state, and switch the bus width according to the recognized memory card interface control mode. , Data format conversion according to the recognized memory card interface control mode, power-on reset function, IC power-interface control with microcomputer 11, interface control with memory 12, and power supply voltage conversion Etc.
- the external connection terminal 13 B is a dedicated terminal for the IC card microcomputer 11. I.
- the card microcomputer 11 performs security processing according to the signal state of the external terminal 13B or an operation command given from the interface controller 10. Further, the IC card microcomputer 11 can perform security processing through a non-contact interface function such as a transformer connection.
- the external terminals, signal protocols, commands, and the like of the IC card microcomputer 11 conform to, for example, the ISII / IEC 7816 standard.
- FIG. 3 shows an example of the external terminals 13 A and 13 B of the MFMC 5. It has external connection terminals # 1 to # 20 as external terminals 13A and 13B.
- DAT A 2 is a data terminal
- CD / DAT 3 is a card detector data terminal
- CMD is a command input terminal
- V cc is a power supply terminal
- CLK is a clock input terminal
- DAT 0 is a data terminal
- V ss is a circuit ground terminal.
- IZ ⁇ — ic is the I / O terminal dedicated to the IC card microcomputer
- LA and LB are external antenna connection terminals
- DAT 4 ZD 3—ms is the data terminal
- INS—ms is the disconnection detection terminal
- DAT 5 / D 2- ms is the data terminal
- DAT 6 / SDIO / D 0 is the data terminal
- DAT 7 / D 1—ms is the data terminal
- BS—ms is the bus status terminal
- Vcc—ic is the IC card microcomputer dedicated power supply terminal
- Ic is a dedicated input terminal for IC card microcomputer.
- the suffix 1 ic added to the terminal name means that it is a terminal for IC card microcomputer
- the suffix 1 ms means that it is a terminal for Memory Stick.
- FIG. 4 shows an example of the external connection terminals and the corresponding SD card terminals that are enabled when the SD card or MMC interface function is realized by the MFMC 5.
- SD mode data input / output is performed at 1-bit data terminal DAT0 or 4-bit data terminal DAT0 to DAT3, and command input is performed at command terminal.
- CMD performs with CMD.
- MMC mode data input / output is performed by one bit of the data terminal DAT0, command input is performed by the command terminal CMD, and terminal CD / DAT3 is non-connected.
- FIG. 5 shows an example of an external connection terminal that is enabled when the HSMMC interface function is realized in the MFMC 5, and a corresponding terminal of the HSMMC card.
- Data input / output is performed at the 1-bit data terminal DAT0 or 4-bit data terminal DAT0 to DAT3, or the 8-bit data terminal DAT0 to DAT7, and command input is performed at the command terminal CMD.
- HSMMC is positioned as an extension of the MMC mode by increasing the number of parallel data input / output bits.
- the data bus of the SD card, MMC and HSMMC is a bull-up bus such as an open drain bus.
- FIG. 6 exemplifies the external connection terminals which are enabled when the interface function of the memory stick Pro is realized by the MFMC 5, and the terminals of the memory stick Pro corresponding thereto.
- Data input / output and command input are performed at the 4-bit data terminals D 0 -ms to D 3 ms.
- the bus of the memory stick Pro is a pull-down bus.
- the data terminals DAT 4ZD3_ms, DAT5 / D2-ms, DAT6 / SD IO / D0-ms, and DAT7 / Dl-ms are connected to the 3-state output buffer. Since they are connected, as shown in Figs. 5 and 6, these terminals can support both bull-up bus specifications and pull-down bus specifications.
- the terminals can be shared for the implementation of the memory stick interface mechanism that is a 1-bit bus specification.
- FIG. 7 shows an example of the external connection terminals that are enabled when the contact interface function of the IC card microcomputer is realized and the corresponding terminals of the IC card microcomputer. Except for the circuit ground terminal V ss, the IC card microcomputer dedicated terminal is used.
- the IC card microcomputer has a power-on reset and a system reset. The former is instructed by turning on the power to the power supply terminal Vcc-ic, and the latter is instructed by the low level of the reset signal / RES.
- the former is I Data may be held in some registers of the C card microcomputer. For example, a power-on reset is required to perform a complete initialization in order to realize a forced reset for no response or hang-up of the system. Input and output of data and commands are performed using the 1-bit data terminal IZO.
- Fig. 8 illustrates the external connection terminals that are enabled when implementing the contact interface and non-contact interface functions of the IC card microcomputer, and the corresponding IC card microcomputer terminals.
- the antenna terminals LA and LB are increasing. External antennas are selectively connected to antenna terminals LA and LB.
- the other terminals are the same as in FIG.
- the external connection terminal 13A is classified into an individual terminal which is individualized for each interface control mode of the MFMC 5, and a common-terminal which is commonized for each interface control mode. Is done.
- the common terminal includes a quick input terminal C LKZS C LK-ms, a power supply terminal V cc and a ground terminal V ss.
- the individual terminals for example, data terminals D1-ms, DO-ms, D2-ms, D3_ms for a memory stick, bus status BS-ms, and data terminals DAT0-D for MMCZS D card. There are AT3 and command terminal CMD.
- the terminals I / 0-ic, CLK-ic, RES-ic, Vcc-ic, LA, and LB for the IC card microcomputer are completely connected to other terminals. Be individualized. For security processing, it is possible to guarantee that the IC card microcomputer 11 performs the interface alone. Furthermore, the signal status of the dedicated terminal for the IC card microcomputer 11 depends on the signal status. As a result, the MPU 2 as an external card host can independently recognize the IC card microcomputer 11.
- the MPU 2 as a card host recognizes and initializes the memory card according to the specifications of the memory card it supports, and attempts to access the memory card using commands in the system according to the specification.
- the MF MC 5 must recognize which memory card interface specification should be used for interface operation in response to an instruction from the MPU 2.
- FIG. 9 illustrates a recognition sequence of the interface control mode.
- the external terminals 13 A and 13 B of the MFMC 5 are set to the input terminals or input / output terminals, for example, the minimum necessary terminals for the system can be input, and the output from the MPU 2 is output. And make it possible to determine the request. Specifically, first, it waits for the input of an IC card command to the input / output terminal I / IIc assigned to the direct interface of the IC card microcomputer 11. Second, it waits for an input of an initialization command for the range of the data terminals DAT0 to DAT7 allocated to the interface of the SD card and the memory card system of the MMC. Third, wait for the supply of the ground potential to the terminal INS-nis assigned to the memory stick removal detection of the memory stick.
- the terminal INS-ms on the Memory Stick is internally connected to the ground terminal of the circuit, and the card host side bulls up the connection path of the terminal INS-ms and detects a drop in the level of the path to detect the memory stick. Detect import. MFMC 5 detects external current flowing to the bull-up resistor at terminal INS-ms Thus, it is determined that the interface control mode of the Memory Stick is required.
- step S4 the MFMC 5 decodes the commands sequentially supplied as the initialization command, and sends a response to the decoding result to the MPU 2
- the MPU 2 recognizes whether the type of memory card required by the MPU 2 is an SD card, MMC, or HSMMC, and returns the recognition result to the MPU 2.
- memory card initialization processing such as address assignment according to MMC mode, SD mode, SPI mode, etc. is performed.
- the MFMC 5 is enabled to execute the control program for realizing the interface control mode of the SD card, MMC, or HSMMC, and in response to the subsequent access command, the interface operation and the memory operation. I do.
- the MFMC 5 upon detecting a current supply to the terminal INS-ms, the MFMC 5 is enabled to execute a control program for realizing the interface control mode of the memory stick, and performs interface operation and memory operation in response to a subsequent access command. I do.
- terminal I / O—ic to ic terminal I / O—ic to ic.
- the IC card microcomputer executes security processing etc. in response to the command.
- MFMC 5 is compatible with IC card microcomputers.
- the connection between the IC card microcomputer 11 and the interface controller 10 is disconnected.
- the connection between the external connection terminal 13 A and the interface controller 10 is disconnected.
- This separation control takes into account the security of security processing, and is performed by the IC card microcomputer 11, and the separation state can be eliminated by an IC card command.
- the former should be recognized in the same way as the specifications of various memory cards.
- the MPU 2 as the card host controls the state of the card detect terminal CD so that the MFMC 5 can recognize the necessary interface specifications.
- yo By using the ⁇ detection terminal INS- m S in the case of a memory stick.
- the IC card command sent via the non-contact interface as well as the terminal I / O-ic may be handled in the same manner as described above.
- the IC card microcomputer can set one of the interface functions to disable operation by the predetermined IC card command ⁇ and operation priority determination. Is done.
- FIG. 10 illustrates details of the interface controller 10.
- the memory 12 is constituted by, for example, a flash memory which is a nonvolatile memory which can be electrically erased and written.
- the memory 12 has electrically erasable and writable nonvolatile memory cell transistors (also referred to as flash memory cells).
- the flash memory cell has a so-called stacked gate structure having a floating gate or an ON-type (N-type). Oxide) It has a so-called split gate structure consisting of a memory transistor section provided with a gut insulating film and a select transistor section.
- the threshold voltage of the flash memory cell increases when electrons are injected into the floating gate or the like, and decreases when electrons are extracted from the floating gate or the like.
- the flash memory cell stores information according to the level of the threshold voltage with respect to the read line voltage for reading data.
- a state where the threshold voltage of the memory cell transistor is low is referred to as an erased state
- a state where the threshold voltage is high is referred to as a written state.
- the interface controller 10 includes a host interface circuit 20, a microcomputer 21, a flash controller 22, a buffer controller 23, a buffer memory 24, and an IC card interface circuit 25.
- the buffer memory 24 includes a dynamic random access memory (DRAM) or a static random access memory (SRAM).
- the IC card microcomputer 11 is connected to the interface circuit 25 for the IC card.
- the microcomputer 21 is a CPU (Central Processing Unit) 27, a program memory (PGM) 28 holding the operation program of the CPU 27, and a work memory (WR AM) 29 used for the work area of the CPU 27 It is composed of The control program of the interface control mode corresponding to the SD card, MMC, HSMMC, and memory stick is held by PGM28.
- the host interface circuit 10 When the host interface circuit 10 detects the issuance of the memory card initialization command described in FIG. 9 or the detection of the current supply to the terminal INS-ms, the host interface circuit 10 controls the interface control mode corresponding to the microcomputer 21 by an interrupt. Make the program executable.
- the microcomputer 21 executes the control program to host the microcomputer.
- the interface circuit 10 controls the external interface operation
- the flash controller 22 controls access to the memory 12 (write, erase, and read operations) and data management
- the buffer controller 23 controls the memory card. It controls the format conversion between this data format 1 and the common data format for memory.
- the buffer memory 24 temporarily holds data read from the memory 12 or data to be written to the memory 12.
- the flash controller 22 operates the memory 12 as a hard disk compatible file memory, and manages data in sector units.
- the IC card interface circuit 25 When the interface controller 10 is controlled in a required memory card interface control mode, the IC card interface circuit 25 operates the microcomputer 11 according to the IC card command from the MUP 2. The necessary data and control signals are converted.
- the flash controller 22 includes an ECC circuit (not shown), adds an ECC code when storing data in memory, and performs a selection error detection and correction process on the read data using the ECC code.
- FIG. 11 illustrates details of the IC card microcomputer 11.
- the IC card microcomputer 11 has a CPU 32, RAM as work RAM (random 'access' memory) 34, a timer 35, EEP ROM (electrical flash memory) and 'programmable read' only. Memory) 36, coprocessor unit 37, mask ROM (read only, memory) 40, system controller one-way logic 41, input / output port (I / ⁇ port 1,) 42, data bus 43 ,, Address bus 44 and RF section 45.
- the mask ROM 40 stores an operation program (encryption program, decryption program, interface control program, etc.) of the CPU 32 and data Used to store.
- the RAM 34 is used as a work area or a temporary data storage area of the CPU 32, and includes, for example, SRAM (static random access memory) or DRAM (dynamic random-access memory).
- SRAM static random access memory
- DRAM dynamic random-access memory
- the coprocessor unit 37 performs, for example, the RSA and the remainder calculation processing in the elliptic curve symbol calculation under the control of the CPU 32.
- the I / O port 42 has a 1-bit input / output terminal IZO, which is also used for data input / output and external interrupt signal input.
- the I / ⁇ port 42 is coupled to the data bus 43, and the data bus 43 is connected to the CPU 32, RAM 34, timer 35, EEPROM 36, coprocessor cut 37, etc. .
- the system control logic 31 controls the operation mode of the IC card microcomputer 11 and interrupts, and further includes random number generation logic used for generating an encryption key.
- the IC card microcomputer 11 When the reset operation is instructed by the reset signal / RES, the IC card microcomputer 11 is initialized internally, and the CPU 2 starts executing instructions from the start address of the EEPROM6 program. The IC card microcomputer 11 is operated in synchronization with the mouth signal CL.
- the EEPROM 36 can be electrically erased and written, and is used as an area for storing data such as ID information and an authentication certificate used to identify an individual.
- a flash memory or a ferroelectric memory may be used instead of the EEPR PM 36.
- IC card machine The icon 11 supports both a contact interface using an external connection terminal as an interface with the outside and a non-contact interface using an antenna.
- An RF unit 45 for performing a non-contact interface has antenna terminals TML 1 and TML 2 of the chip.
- the RF unit 45 When power is supplied from the RF unit via the antenna or the non-contact interface is selected via the internal bus by the system control logic 41, the RF unit 45 (For example, an induced electromotive force generated by crossing a high-frequency fluctuating magnetic flux or a microphone mouth wave) outputs a power supply voltage Vcc as an operation power supply, and an internal circuit based on an induced current generated corresponding to the frequency of the predetermined radio wave.
- the CK signal CK, the internal data obtained by separating the data passed over the predetermined radio wave by the RF unit 15 and the reset signal / RES are generated, and the information is input from the antenna without contact. Perform output.
- the RF unit 45 operating via a non-contact interface is a small-scale circuit independent of the IC card operating CPU 32 and the like operating via a contact interface. It is preferable to configure. Circuits necessary for the operation of the contactless card, for example, a processor for the contactless card, a memory used for a control program area and a work area of the processor, and an RF transmission / reception and power supply circuit section are provided therein as the RF section 45. Can be Since the RF unit 45 is composed of independent small-scale circuits such as a processor function and its control program, even in an environment where power cannot be supplied via the contact terminals, for example, The circuit can be easily operated by the induced electromotive force. The RF unit 45 can also input / output data between the contactless card and the contact card via the internal data bus and address bus.
- FIG. 12 shows some of the applications for MFMC5.
- the communication terminal device 1 has a function of accessing a memory card according to a predetermined memory card specification. For example, it is assumed that the communication portable terminal device 1 has obtained a license to use the MMC. Accordingly, the MPU 2 has a function of accessing the MMC according to the specifications of the MMC.
- the MPU 2 issues an MMC-defined initialization command to the M FMC 5, waits for a response to the command, and recognizes the card. Perform initialization.
- the MFMC 5 can execute the control program in the MMC interface control mode in response to the issuance of the MMC initialization command. As a result, the MFMC 5 operates as an MMC, and fetches content data and the like into the memory 12.
- the format of the data stored in the memory 12 is a data format specific to MFMC5.
- the MFMC 5 may be removed and attached to the new model of the communication portable terminal 1.
- the MPU 2 built in the new type of communication portable terminal device 1 outputs a signal for detecting the attachment of the memory stick V to the terminal INS-ms of the card 5 so that the MFMC 5
- a control program in a memory stick interface control mode is made executable, and operates with a memory stick compliant card interface.
- the MFMC 5 can read and use the content data and the like previously stored in the memory by the MMC operation to another terminal device 1 by the memory stick operation and use it.
- the MFMC 5 can be used by changing the card interface with a PCMC IA adapter, a USB adapter, a Bluetooth adapter, or the like. Furthermore, it can be used like a conventional RF-IC card by connecting an external non-contact antenna.
- the secure area of the memory 12 stores user identification information.
- the encrypted license information is downloaded together with the user identification information as a secret key.
- the decryption key for decrypting the content data is included in the license information, and the license information is decrypted using the user identification information as the decryption key. This protects the copyright of the content data.
- Such security processing is performed under program control by the microcomputer 21.
- the security processing by the IC card microcomputer 11 will be described.
- the IC card microcomputer 11 implements a function that has been certified by a certification organization with the evaluation of ISOZOEC 15408, which can be used for electronic payment services and the like.
- a predetermined authentication certificate is stored in the EEPROM 6, and when an authentication request is received from the host, the authentication certificate is sent, and subsequent communication processing is possible provided that the authentication is obtained.
- the operation program for such security processing is stored in the mask ROM 40.
- the authentication process by the IC card microcomputer 11 is performed inside the IC card microcomputer 11
- the IC card microcomputer 11 is used for high-level security processing such as electronic payment, a power-on reset that initializes all internal states for abnormal states of the IC card microcomputer 11 is not possible. It is more likely to be performed more frequently than the interface controller 10 or the like. Considering this, as shown schematically in FIG. 13, since the IC card microcomputer 11 has the dedicated external power supply terminal V cc -ic described in FIGS. 7 and 8, Power-on reset can be freely performed by the IC card microcomputer 5 alone without resetting the entire MFMC.5. As a result, MFMC 5's operability can be improved while ensuring security.
- FIGS. 14 to 16 show some other examples of enabling independent power-on reset for the IC card microcomputer 11.
- the IC card microcomputer 11 and the interface controller 10 have, as external connection terminals, an external power supply terminal V cc common to the IC card microcomputer 11 and the power supply of the IC card microcomputer 11 from the aforementioned common external power supply terminal V cc.
- the power supply path 51 leading to the terminal 50 has a power supply switch 52 that can shut off power supply under the control of the interface controller 10.
- an external power supply terminal V cc common to the IC card microcomputer 11 and the interface controller 10 is provided as the external connection terminal, and the IC card microcomputer 11 is powered on from the interface controller 10. It has an input terminal 53 for a reset signal res for instructing reset. This also enables the power-on reset by the IC card microcomputer alone.
- the interface controller 10 is supplied with operating power from the external power supply terminal Vcc, and the IC card microcomputer 11 converts the operating power through the power supply circuit 54 such as a step-down circuit and a regulator.
- the voltage-changed or bypassed power supply is used as an operation power supply, and the IC card microcomputer 1 has an input terminal 53 for a reset signal res for instructing power-on reset from the interface controller 10. This also enables power-on reset by the IC card microcomputer 11 alone. This is particularly effective when the IC card microcomputer 11 and the interface controller 10 are formed on separate chips and have different operating power supply voltages.
- the input capacitance viewed from the antenna terminals TML 1 and TML 2 of the RF unit 45 of the IC card microcomputer 11 has a maximum manufacturing variation of approximately 20%.
- a tuning capacitor 56 resonating with the built-in antenna 55 built in the MFMC 5 is arranged so as not to cause a variation in the tuning frequency.
- the tuning capacitor 56 may be composed of a chip capacitor, a varicap capacitor, a nonvolatile MOS capacitor, or the like.
- the nonvolatile MOS capacitance for example, an electrically rewritable flash memory cell transistor 58 may be used as illustrated in FIG.
- Flash memory cell transistors 58 A source region SF and a drain region DF are formed in a region WF, and a gate oxide film, a floating gate FG, an insulating film, and a control gut CG are stacked on a channel region CF therebetween.
- a charge trap film such as a silicon nitride film may be used in place of the floating gate FG.
- the non-volatile MOS capacitor has one storage electrode as a control gate CG and the other storage electrode as a cell region.
- the size of the depletion layer formed in the channel differs between the erased state and the written state, which causes a difference in the capacitance value between the two terminals.
- a variable capacitance can be configured with a change in threshold voltage according to the degree of erasing and writing. Since it is a nonvolatile memory cell transistor, the erase-write state set once is maintained independently. By connecting a plurality of nonvolatile memory cell transistors 58 in series, it is possible to ensure the withstand voltage of the nonvolatile MOS capacitance.
- the MFMC'5 functions independently as an operating power source using the induced electromotive force generated by a transformer coupling, similar to a non-contact IC card It is possible to let them. It is meaningful when the MFM C5 is removed from the card host or used when the power of the power host is turned off.
- Fig. 19 shows an example in which the external antenna is connected to be detachable from the internal antenna.
- External antenna connection end instead of the internal antenna 5
- a switch circuit 62 that can selectively connect the slaves LA and LB to the antenna terminals TML 1 and TML 2 of the IC card microcomputer 11 is adopted.
- An external antenna 60 is connected to the connection terminals LA and LB, and a tuning capacitor 61 is further connected.
- By preparing the external antenna 60 it becomes possible to use an antenna that is superior in characteristics such as transmission / reception sensitivity as compared with the internal antenna.
- the external antenna 60 when a high-frequency signal flowing from the external antenna 60 flows to the internal antenna 55, the high-frequency signal is emitted from the built-in antenna 55 inside the device incorporating the MFMC 5.
- the internal antenna 55 may be a source of high-frequency noise for devices equipped with the MFMC 5.
- the internal antenna 55 detachable when the external antenna 60 is used, it is possible to eliminate the possibility that such unwanted high-frequency noise is generated.
- the MFMC 5 when the MFMC 5 was taken out from a device such as the communication portable terminal 1, by switching to a state where the internal antenna 55 was connected to the IC card microcomputer 11, the MFMC 5 became independent as a contactless IC card by itself. Function can be used. Depending on how it is used, it does not require power supply to the card and operates without a battery.
- the switch circuit 62 includes a switch 63 and a control circuit 64 thereof.
- the switch 63 is a non-volatile memory element 65 that is interposed between corresponding connection terminals and can electrically control the cutoff or conduction of the path by electrically changing the threshold voltage. It is constituted by.
- the nonvolatile memory element 65 may be constituted by the flash memory cell transistor 58.
- the control circuit 64 sets the threshold voltage viewed from the selection terminal (gate) of the nonvolatile memory element 65 to a first state, for example, a write state, cuts off the path, and changes the threshold voltage to a second state, for example, an erase state. The above route is conducted. In the second state of the threshold voltage, the selection terminal is connected to circuit ground. Connected to voltage.
- the instruction of the write / erase operation to the control circuit 64 is given by, for example, the interphase controller 10.
- the control circuit 64 controls the operation procedure for the nonvolatile memory element 65 in accordance with the write / erase instruction. ⁇ ⁇ ⁇ Considering the application of a high voltage when changing the threshold voltage of the nonvolatile memory element 65, as illustrated in FIG. 21, a pair of separating elements are connected in series with the nonvolatile memory element 65 interposed therebetween.
- a switch MOS transistor 66 may be provided. The isolation switch MOS transistor 66 is turned on when its selection terminal is connected to the circuit ground voltage Vss.
- the control circuit 64 controls the separation switch MOS transistor 66 to an off state when changing the threshold voltage of the nonvolatile memory element 65. At this time, the gate voltage of the separation switch MOS transistor 66 is set to a negative voltage. By employing the isolation switch MOS transistor 66, it is not necessary to make all the circuits connected to the path where the transistor is interposed have a high breakdown voltage.
- FIG. 22 and 23 show another example of the nonvolatile memory element 65.
- FIG. FIG. 22 shows a circuit configuration
- FIG. 23 shows a longitudinal sectional structure of the transistor.
- the nonvolatile memory element 65 shown in the figure has a high withstand voltage nonvolatile transistor element structure (NVCBT: Non-Voltage Channel Bipolar Transistor), and has a gate T gt, an anode T an and a power source T ca.
- NVCBT Non-Voltage Channel Bipolar Transistor
- the nonvolatile memory element 65 includes a bipolar transistor section 70 and a nonvolatile MOS transistor section 71 having a drain and a source connected between a base and a collector of the bipolar transistor section 70,
- a charge storage region is formed on a channel between a source and a drain via an insulating film, and a threshold voltage is varied according to a charge stored in the charge storage region.
- the charge storage region is formed of, for example, a floating gate, on which a control gate is formed via an insulating film.
- the breakdown voltage of the nonvolatile MOS transistor section 71 can be lower than the breakdown voltage of the bipolar transistor section.
- the nonvolatile memory element 65 having the NVCC structure when no electrons are accumulated in the floating gate, the nonvolatile MS transistor section 71 is set to an erased state, in particular, a depletion state. First, the conduction state will be described.
- the applied voltage Vg of the control gate is higher than the threshold voltage Vth of the nonvolatile MOS transistor section 71, and the nonvolatile MOS transistor section 71
- the control gate voltage should satisfy at least a bias state (the above-described ground voltage application state) to such an extent that the hot electron is not injected into the floating gate.
- the cutoff state will be described. Electrons injected into the floating gate In the written state, the threshold voltage is increased. If the applied voltage Vg of the control gate is lower than the threshold voltage in the write state, no channel inversion layer is formed between the source and the drain, so electrons are not injected into the bipolar transistor section 70 and the base current flows. Since there is no bipolar transistor 70, the node between the positive potential node and the negative potential force node in the bipolar transistor section 70 is cut off. For example, the off state is maintained even if the control gate applied voltage Vg is grounded at the same potential as the force source. The control gate potential only needs to satisfy at least the condition that the accumulated electrons in the floating gate are not pulled out (the above-described ground voltage application state).
- the control gate voltage Vg is set to a sufficiently negative potential with respect to the source, drain, and ⁇ -well region (collector region in FIG. 22) of the MOS transistor section 71, so that the FN (Fowler Nordheim ) The current stored in the floating gate can be pulled out by current and erased. As a result, the MOS transistor 71 can change from the enhancement mode to the depletion mode.
- the switch state of ON in the erase state and OFF state in the write state is changed to the nonvolatile MOS state. Satisfactory maintenance and storage can be facilitated only by the presence / absence of the formation of the channel region of the transistor portion 71 and the necessary writing / erasing.
- the nonvolatile memory element 65 represented by the NVCBT structure can also be used for the path switching circuit described in FIG.
- two switches with two nonvolatile memory elements 65 of NVCBT structure are used like a MOS transfer gate,
- the anode Ta1 of the nonvolatile memory element 6 of one NVCBT structure is connected to the nonvolatile memory element 6 of the other NVCBT structure.
- Composed of 5 force swords connected to Tca One such switch is used for selective connection between terminal LA (LB) and terminal TML 1 (TML 2), and another switch is used for connecting terminal TML 1 (TML 2) to antenna 55. Used for selective connection.
- the program control for the nonvolatile memory element 65 having the NVC BT structure is performed by the control circuit 64 through the gate Tgt.
- the nonvolatile memory element 65 represented by the NVC BT structure can be used not only for an antenna switch but also for a circuit power switch.
- a nonvolatile memory element 65 and a control circuit 64 are arranged on the power supply terminal V cc side of a predetermined circuit 66.
- the anode Ta11 (emitter) of the nonvolatile memory element 65 having the NVC BT structure is connected to the power supply terminal Vcc.
- the control circuit 64 is supplied with an operation enable signal EN and a write / erase instruction signal EW.
- the circuit 66 is, for example, an RF unit 45. When the non-contact interface is not used, the supply of operating power to the RF unit 45 can be completely cut off.
- the switch circuit 63 and the control circuit 64 using the nonvolatile memory element 65 are used to selectively disconnect the IC card microcomputer 11 and the interface controller 10. Is also available. At this time, an operation instruction to the control circuit 64 is issued by either the IC card microcomputer 11 or the interface controller 10. It is assumed that the IC card microcomputer 11 is desirably separated from other circuits when performing authentication processing or the like at a high security level. At this time, the IC card microcomputer 11 is interfaced using the dedicated external terminal 13B. If necessary, the IC card microcomputer 11 can use the memory 12 via the interface controller 10 by connecting the switch circuit 63.
- Non-volatile memory element 65 represented by NVCBT structure
- NVCBT structure By selectively disconnecting the icon, switching between internal and external antennas, and using it as a power switch, it eliminates the need for the steady externally applied voltage 'power required for on-Z-off control as in the conventional MS switch. Therefore, it can contribute to low power consumption.
- FIG. 27 illustrates a planar structure of MFM C.5.
- a wiring coil pattern 81 constituting the internal antenna 55 is formed around the outer periphery thereof, and a number of bonding pads 82 are arranged inside the wiring coil pattern 81.
- a ferrite chip 84 which is an example of a ferrite plate, is arranged inside the bonding pad 82, and, for example, two semiconductor chips 85, 86 are stacked on the ferrite chip 84.
- the bonding pads 82 of the wiring board are connected to the corresponding bonding pads 88 of the semiconductor chips 85 and 86 by bonding wires 90.
- one semiconductor chip 86 realizes the interface controller 10 and the IC microcomputer 11.
- FIG. 28 illustrates a side structure of the MFMC 5 corresponding to the plane structure of FIG.
- the stacked wiring boards 8, 0 and the ferrite chip 84, the ferrite chip 84 and the semiconductor chip 85, and the semiconductor chips 85, 86 are bonded to each other with adhesives 91, 92, respectively.
- the wiring board 80 is, for example, a multilayer A connector terminal (or a solder connection terminal) 93 connected to the bonding pad 82 is formed on the back surface of the wiring substrate.
- the connector terminal 93 is an example of the external connection electrodes 13A and 13B.
- the entire surface of the wiring board 80 is sealed with a resin 95.
- the casing is made of a sealing resin 95 formed by a resin mold.
- ferrite which is a ferromagnetic material
- the magnetic flux tries to take a path along the ferrite chip 84 without penetrating it. Therefore, since the internal antenna 55 composed of the coil pattern 81 is placed around the outer periphery of the ferrite chip 84, a large magnetic flux can be obtained in the vicinity of the antenna 55. 55 Inductance performance, that is, the antenna performance can be improved here.
- the semiconductor chips 85 and 86 are overlaid on the ferrite chip 84, the transmission of magnetic flux to the semiconductor chips 85 and 86 can be alleviated, and the semiconductor chips 85 and 86 cannot be transmitted to the semiconductor chips 85 and 86. It is possible to prevent a possibility that a malfunction may occur due to generation of a desired eddy current or induced electromotive force.
- FIG. 29 illustrates another side structure of the MFMC5.
- ferrite 1 was used in place of the ferrite chip, and an adhesive 96 containing ferrite powder as a plate was used.
- the wiring board 80 and the semiconductor chip 85 are connected using the adhesive 96. This also provides the same effect as the ferrite chip 84.
- the ferrite plate is not limited to the ferrite paste coated with the ferrite chip 84, the ferrite powder-containing adhesive 96, or the like. It may be a ferrite film that has been pasted.
- the ferrite MO - because typified F e 2 0 3 collectively ferromagnetic oxide may be a ferromagnetic oxide other than so-called Blow I and.
- FIG. 30 illustrates another planar structure of the MFMC 5.
- FIG. 31 illustrates a side structure of the MFMC 5 corresponding to the planar structure of FIG.
- the wiring coil pattern 98 constituting the internal antenna 55 is formed using a multilayer wiring pattern in the wiring board 97.
- FIG. 30 is generally larger than that of FIG.
- the package configuration shown in FIGS. 30 and 31 is called an RSMMC package.
- FIG. 38 is a perspective view showing an external appearance of the MFMC 5 to which the R SMMC package is applied.
- FIG. 32 illustrates yet another side structure of the MFMC 5.
- an adhesive 96 containing ferrite powder was used as a ferrite plate.
- the wiring board 97 and the semiconductor chip 102 are bonded using the adhesive 96.
- the semiconductor chips are stacked and arranged on the wiring board 97 of the MFMC 5, it is easy to secure a distance between the wiring coil pattern 98 and each semiconductor chip. If the distance between each semiconductor chip and the wiring coil pattern 98 can be reduced so that the effect of the electromagnetic field on the semiconductor chip can be reduced to a negligible level, the ferromagnetic Each semiconductor chip can be bonded onto the wiring board 97 with a die bonding adhesive or the like that does not contain any material. .
- FIG. 33 illustrates yet another planar structure of the MFMC 5.
- FIG. 34 illustrates a side structure of the MFMC 5 corresponding to the plane structure of FIG. If there is no need to dispose the internal antenna 55 on the outer periphery of the semiconductor chips 100 and 11011 as described above from the viewpoint of space factor, the internal The wiring coil pattern 107 constituting the antenna 55 may be formed, and the semiconductor chips 100 and 110102 may be arranged on the side thereof.
- the casing is constituted by a cap 108 which is larger than the case of FIG. Also in this case, from the viewpoint of improving the antenna performance, it is desirable to dispose the fly chip 110 at the center of the wiring coil pattern 107 constituting the internal antenna 55.
- FIG. 33 and 34 is referred to as a standard MMC package.
- Fig. 39 shows a perspective view of the appearance of MFMC 5 to which the standard MMC package is applied.
- FIG. 35 illustrates another side structure of the MFMC 5. The difference from FIG. 34 is that a ferrite chip 110 that is larger than the outer shape of the wiring coil pattern 107 that forms the internal antenna 55 is provided, and the ferrite chip is as wide as the space allows. The use of 110 contributes to the improvement of antenna efficiency.
- the ferrite chip 110 is not covered with the resin 95 and is fixed to the wiring board 109 with an adhesive 95B.
- the ferrite chip 110 is mounted on the wiring board 109 after the step of forming the resin 95. And it is easier to mount a thicker ferrite chip 11 than when the ferrite chip 110 is sealed inside the resin 95. This can contribute to an improvement in antenna efficiency.
- FIG. 36 illustrates a side structure of still another MFMC 5. From the viewpoint of preventing the semiconductor chips 100, 101, 102 from malfunctioning due to magnetic flux, the semiconductor chips 100, 100 arranged on the side of the wiring coil pattern 107 constituting the internal antenna 55 are described. It is better to further cover 01 and 102 with an inner cap 112 containing metal or ferrite. In FIG. 36, the wiring board 109 and the cap 108 are adhered via an adhesive 95B.
- the inductor of the internal antenna 55 is formed, for example, by coil patterns 81, 98, 107 formed on a wiring board. The inductor may be formed by a wound coil.
- the coil patterns 81, 98, 107 are formed by the same wiring pattern as the bonding pads 82 connected to the semiconductor chips 100, 101, 102 or other wiring.
- the cost can be reduced and the device can be easily made thinner.
- the antenna 55 is made of a dielectric antenna chip made of dielectric ceramics or the like. You can substitute In terms of antenna characteristics, it is desirable that the dielectric antenna chip be stacked on a ferrite plate.
- a ferrite chip 94 is stacked on a dielectric antenna chip 113, and the semiconductor chips 86 and 85 may be stacked on the ferrite chip 94.
- Ferrite Tip 94 is an adhesive or ferrite containing ferrite powder. It can be changed to another ferrite plate such as film.
- the internal antenna 55 is not limited to the structure provided on the wiring board, and may be provided on, for example, the caps 105 and 108.
- a coil 115 constituting the lower antenna 55 is formed inside the cap 108.
- a region of the sealing resin 95 is overlapped on the coil 115 to expose the connector terminal 93 to the outside.
- the cap 105 is made of resin mixed with ferrite powder, the antenna efficiency is improved in the same manner as described above, which also helps to prevent the malfunction of the semiconductor chip. From the viewpoint of improving the antenna efficiency and preventing malfunction of the semiconductor chip, as shown in FIG.
- a ferrite chip, a ferrite finolem or a ferrite finolem is provided between the coil 115 and the sealing resin 95. It is better to insert a ferrite plate 1 1 6 such as a ferrite travel.
- the cap 105 may be a simple resin. 40 to 42 can be applied to other package structures.
- the coil 115 formed on the cap 105 and the antenna terminals TML1 / TML2 of the IC card microcomputer 11 are formed on the wiring board 97. Connected to coil pattern 115 through wiring 97A.
- the wiring 97 A and the coil pattern 115 may be electrically connected through a conductive adhesive 977 B such as an Ag paste, for example.
- the coil 115 By forming the coil 115 on the cap 105, it is easy to secure the distance between the coil 115 and each semiconductor chip. Ensuring the coil 1 1 5 the distance between each semiconductor chip, even in ensuring the characteristics of Koi Honoré 1 1 5 to reduce the eddy current loss, Ku undesired eddy currents if the semiconductor chip is induced electromotive It is also effective in preventing the possibility of malfunction due to power generation. ⁇ Prevention of deterioration of antenna characteristics due to eddy current loss ⁇
- a relatively large ground pattern that is conducted to the ground potential is formed on a multilayer wiring board typified by a composite wiring board.
- the wiring board is divided into a plurality of divided ground patterns 1 18 a to 1 1 8 i.
- the divided ground pattern 118a is connected to the bonding pad Vss receiving the ground voltage, and is connected in series to the other divided ground patterns 118b and 118c.
- the divided ground pattern 118d is connected to the bonding pad Vss receiving the ground voltage, and is connected in series to the other divided land patterns 118e and 118f.
- Divided ground pattern 118 g is connected to bonding pad V ss receiving the ground voltage, and connected in series to other divided ground patterns 118 h and 118 i.
- FIG. 44 shows the side sectional structure of FIG.
- the divided ground patterns 118 a to 118 i are formed on the lower layer side of the multilayer wiring board. As a result, deterioration of antenna characteristics due to eddy current loss generated on the surface of the ground pattern can be reduced.
- the split ground pattern structure is naturally applicable not only to the microphone opening MMC package structure but also to the R SMMC and standard MMC package structures.
- This section describes EMI countermeasures, that is, the suppression of electromagnetic interference to the outside and the suppression of failures caused by external electromagnetic waves.
- These resin caps 108 become electromagnetic shields.
- the connector terminal 93 of the wiring board is exposed at the opening of the cap 108.
- the receiving surface of the antenna faces the opening.
- the magnetic flux shielding structure by the cap can be applied to package structures other than the standard MMC package structure.
- the cap 105 is made of metal and the surface of which is provided with an insulating film may be employed as illustrated in FIG.
- the metal cap 105 serves as an electromagnetic shield.
- the eddy current loss structure by the metal cap 105 can be applied to a package structure other than the R SMM C package structure.
- a mold cap structure containing metal or ferrite is adopted. That is, the cap 105 has metal or ferrite 121 in its core portion, and is molded into a resin 120 to insulate the entire shape and is shaped into a predetermined shape.
- the mold cap 105 serves as an electromagnetic shield.
- This structure can be applied to package structures other than the RSMMC package structure.
- the metal or ferrite 121 does not have to be entirely molded with the resin 120.
- the thickness of the mold cap 105 covering the resin 95 is reduced. can do. If the portion 95 of the mold cap 105 covering the resin is made thinner, the volume of the resin 95 can be increased, which is advantageous in mounting a large-capacity memory.
- FIG. 51 is a perspective view of the MFMC 5 of the standard MMC package structure to which the electromagnetic shield label 122 is attached in the form of FIG. 48.
- FIG. 51 is a perspective view of the MFMC 5 of the standard MMC package structure to which the electromagnetic shield label 122 is attached in the form of FIG. 48.
- FIG. 52 is a perspective view of the MFMC 5 having the HSMMC package structure to which the electromagnetic shield label 122 is attached in the format of FIG. 50.
- FIG. 53 is a perspective view of the MFMC 5 of the R SMMC package structure to which the electromagnetic shield labels 122 are attached in the form of FIG. 49.
- the electromagnetic shield label 122 is, for example, a label on which ferrite particles are applied, printed or adhered, a metal-deposited pine label such as aluminum, aluminum copper, a directional silicon steel sheet, or a ferromagnetic material. Metal plate label.
- the electromagnetic interference using the Cap-label can suppress or reduce the occurrence of electromagnetic interference and external electromagnetic interference.
- Such electromagnetic shielding technology can be applied to memory cards that do not have a contactless IC card function.
- FIG. 56 shows a state before the MFMC 5 is mounted on the socket 130
- FIG. 57 shows a state where the MFMC 5 is mounted on the socket 130
- FIGS. 58 and 59 show cross sections AA ′ of FIG. 56
- FIG. 54 shows cross sections BB ′ of FIG. 57.
- the microphone opening MMC package structure will be described as an example. micro
- the package that is, the sealing resin 95
- the sealing resin 95 is This is formed in a mold or MAP (mold 'array ⁇ package) form.
- the sealing resin 95 has elastic claws 13 1, 13 2 of the socket 130 in the thickness direction.
- Steps 1 33 and 1 34 to be locked to are formed.
- Steps 1 3 3 and 1 34 are formed by forming a projection on the inner surface of the cavity of the sealing mold at the time of collective molding, so that a groove is formed in advance along the cutting and separating position of the sealing resin 95, and then This is achieved by cutting and separating the devices individually along the grooves.
- the steps 13 33 and 134 are formed on the parallel edges of the sealing resin 95.
- the thickness of the sealing resin 95 is defined by the thickness necessary to seal the semiconductor chips 85 and 86 and the bonding wires 90 described in FIG. There is no problem because the steps 1 3 3 and 1 34 are formed at both ends of the sealing resin 95 and are shifted from the stacks of the semiconductor chips 85 and 86. 13 6 and 13 7 are cantilevered elastic terminals that come into contact with the connector terminal 93 of the MFMC 5.
- a wiring board 8 OA is prepared.
- the wiring board 80A prepared here has a plurality of units formed with wiring patterns and pad electrodes necessary for one MFMC 5.
- chips 84, 85, 86 are mounted on the wiring pattern of each unit of 80A on the wiring board, and the pads of chips 84, 85, 86 are mounted. Connect to corresponding bonding pad 82 with bonding wire 90.
- the wiring substrate 80A on which the chips 84, 85, 86 are mounted is placed in the cavity of the sealing die composed of the upper die 150 and the lower die 151 (see FIG. See Fig. 69). Resin 15 2 was injected into the cavity, Thus, a sealing resin is formed (see FIG.
- the sealing resin 152 and the wiring board 80A are cut with a dicing blade 1553, and the MFMC 5 is separated into individual pieces (see Fig. 71). Then, the MFMC 5 in which the steps 13 33 and 134 are formed is completed.
- the elastic claws 13 1 and 13 2 of the socket 13 lock the steps 13 3 and 1 34 which are thinner than the thickness of the sealing resin 95, the thickness HI of the socket 130 is reduced. It is easier to minimize.
- no step is provided in the sealing resin as shown in FIG. 55 as a comparative example, the position of the elastic claw is increased, and the thickness H2 of the socket is increased accordingly.
- the two step portions 133, 134 are asymmetric.
- one step portion 134 is formed uniformly, and the other step portion 133 stops forming a step in the middle.
- the corresponding elastic claw 13 1 is formed with a recess 13 A for locking the projection 13 A.
- MFMC 5 can be mounted only in the orientation shown in FIG. 57.
- FIG. 60 illustrates a terminal arrangement corresponding to the terminal configuration of FIG.
- the external connection terminals 93 may be arranged in plural rows as shown in FIG. 61, and the plural rows may be mutually biased in the parallel direction.
- the bias may be PZ2.
- the width of the terminal 93 itself is smaller than that of FIG.
- both the deviation with respect to the steps 133, 134 and the deviation in the terminal arrangement direction may be adopted.
- the terminals are shifted entirely in one direction in the terminal arrangement direction with respect to the sealing resin 95 so as to be biased.
- the deviation should be half the terminal pitch P. P / 2.
- the shape of the steps 1333 and 134 for preventing reverse insertion may be an unbalanced shape shown in FIG. 64 or FIG.
- the position of the elastic claws 13 1 and 13 2 and the position of the external connection terminal 93 are changed.
- the sockets By designing the sockets so that they are arranged at different positions on the plan view, it becomes easy to simplify the structure of the molding die, and the productivity of the socket can be improved.
- a relatively thick and large semiconductor chip 85 is overlaid, and a relatively thin and small semiconductor chip 86 is overlaid.
- this method makes it easy to make the ferrite plate thicker. Thickening the ferrite plate is effective in reducing magnetic resistance.
- each of the plurality of first external terminals 93 is connected to the plurality of first external terminals 93 and has a pitch and surface area greater than those of the first external terminals 93. It is good to arrange a plurality of test terminals 93 T with a large length.
- the operation of bringing a test probe into contact with a large number of MFMCs 5 in a vertical direction becomes easy.
- the plurality of first external terminals 93 are arranged in a plurality of rows apart from each other, and the plurality of second external terminals 93 It is good to arrange T.
- the multifunction card device may be a device without a security controller, such as an IC card microcomputer.
- the wiring board of the multifunction card device or the semiconductor card device is not limited to the multilayer wiring board, and may be a so-called lead frame.
- antenna characteristics are prevented from deteriorating due to eddy current loss, inductance performance is improved, EMI countermeasures, and semiconductor card devices for sockets are prevented.
- the invention relating to prevention of reverse insertion of a chair, thinning of a socket for a semiconductor card device, and facilitation of a test are not limited to application to a multifunction card device, and other semiconductor card devices such as a modem card and a LAN card. Can also be widely applied. Industrial applicability
- the present invention can be widely applied not only to a multifunction memory card equipped with a card controller, a flash memory, and an IC card microcomputer, but also to other multifunction cards, communication cards, IZ cards, and memory cards. .
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Power Engineering (AREA)
- Computer Security & Cryptography (AREA)
- General Engineering & Computer Science (AREA)
- Credit Cards Or The Like (AREA)
- Storage Device Security (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims
Priority Applications (10)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CNB038267357A CN100390818C (zh) | 2003-07-03 | 2003-07-03 | 多功能卡装置 |
AU2003304308A AU2003304308A1 (en) | 2003-07-03 | 2003-07-03 | Multi-function card device |
KR1020067000155A KR101010789B1 (ko) | 2003-07-03 | 2003-07-03 | 멀티 펑션 카드 디바이스 |
PCT/JP2003/008434 WO2005004047A1 (ja) | 2003-07-03 | 2003-07-03 | マルチファンクションカードデバイス |
JP2005503380A JP4447553B2 (ja) | 2003-07-03 | 2003-07-03 | マルチファンクションカードデバイス |
KR1020107018870A KR20100107057A (ko) | 2003-07-03 | 2003-07-03 | 반도체 카드 디바이스 |
CNA2008100902132A CN101271538A (zh) | 2003-07-03 | 2003-07-03 | 多功能卡装置 |
US10/562,727 US7971791B2 (en) | 2003-07-03 | 2003-07-03 | Multi-function card device |
TW096105780A TW200739429A (en) | 2003-07-03 | 2003-07-21 | Multi-function card device |
US13/153,384 US20110227234A1 (en) | 2003-07-03 | 2011-06-03 | Multi-function card device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2003/008434 WO2005004047A1 (ja) | 2003-07-03 | 2003-07-03 | マルチファンクションカードデバイス |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/153,384 Division US20110227234A1 (en) | 2003-07-03 | 2011-06-03 | Multi-function card device |
Publications (1)
Publication Number | Publication Date |
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WO2005004047A1 true WO2005004047A1 (ja) | 2005-01-13 |
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ID=33562081
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2003/008434 WO2005004047A1 (ja) | 2003-07-03 | 2003-07-03 | マルチファンクションカードデバイス |
Country Status (7)
Country | Link |
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US (2) | US7971791B2 (ja) |
JP (1) | JP4447553B2 (ja) |
KR (2) | KR20100107057A (ja) |
CN (2) | CN101271538A (ja) |
AU (1) | AU2003304308A1 (ja) |
TW (1) | TW200739429A (ja) |
WO (1) | WO2005004047A1 (ja) |
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JP2006221501A (ja) * | 2005-02-14 | 2006-08-24 | Matsushita Electric Ind Co Ltd | アンテナ内蔵半導体メモリモジュール |
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JP2013070454A (ja) * | 2011-09-20 | 2013-04-18 | Toshiba Corp | 磁界共鳴方式受電回路 |
US10897253B2 (en) | 2014-10-28 | 2021-01-19 | SK Hynix Inc. | Calibration circuit and calibration apparatus including the same |
US11082043B2 (en) | 2014-10-28 | 2021-08-03 | SK Hynix Inc. | Memory device |
US11755255B2 (en) | 2014-10-28 | 2023-09-12 | SK Hynix Inc. | Memory device comprising a plurality of memories sharing a resistance for impedance matching |
US10067903B2 (en) | 2015-07-30 | 2018-09-04 | SK Hynix Inc. | Semiconductor device |
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USRE49496E1 (en) | 2015-07-30 | 2023-04-18 | SK Hynix Inc. | Semiconductor device |
US10860258B2 (en) | 2015-12-24 | 2020-12-08 | SK Hynix Inc. | Control circuit, memory device including the same, and method |
US11347444B2 (en) | 2015-12-24 | 2022-05-31 | SK Hynix Inc. | Memory device for controlling operations according to different access units of memory |
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Also Published As
Publication number | Publication date |
---|---|
JPWO2005004047A1 (ja) | 2006-08-17 |
KR20060059252A (ko) | 2006-06-01 |
JP4447553B2 (ja) | 2010-04-07 |
CN101271538A (zh) | 2008-09-24 |
US20110227234A1 (en) | 2011-09-22 |
AU2003304308A1 (en) | 2005-01-21 |
CN1802655A (zh) | 2006-07-12 |
US20060151614A1 (en) | 2006-07-13 |
KR20100107057A (ko) | 2010-10-04 |
TW200739429A (en) | 2007-10-16 |
US7971791B2 (en) | 2011-07-05 |
CN100390818C (zh) | 2008-05-28 |
KR101010789B1 (ko) | 2011-01-25 |
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