WO2004114318A1 - 半導体試験装置及びその制御方法 - Google Patents
半導体試験装置及びその制御方法 Download PDFInfo
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- WO2004114318A1 WO2004114318A1 PCT/JP2004/008361 JP2004008361W WO2004114318A1 WO 2004114318 A1 WO2004114318 A1 WO 2004114318A1 JP 2004008361 W JP2004008361 W JP 2004008361W WO 2004114318 A1 WO2004114318 A1 WO 2004114318A1
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- waveform
- semiconductor memory
- memory devices
- semiconductor
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C29/56004—Pattern generation
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
- G01R31/31928—Formatter
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C2029/5602—Interface to device under test
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C2029/5606—Error catch memory
Definitions
- the present invention relates to a semiconductor test device and a control method therefor.
- the present invention relates to a semiconductor test apparatus for simultaneously testing a plurality of semiconductor devices and a control method thereof.
- This application is related to the following Japanese application. For those designated countries for which incorporation by reference to the literature is permitted, the contents described in the following application are incorporated into this application by reference and become a part of this application.
- a semiconductor test apparatus for performing various tests on a semiconductor device such as a logic IC or a semiconductor memory device before shipment.
- a general semiconductor test apparatus for testing semiconductor memory has a simultaneous measurement function for a large number of semiconductor devices, and the same test data pattern waveform is applied to the same pin of a plurality of semiconductor devices. You can enter and test.
- the multiple simultaneous measurement function it is possible to measure a large number of semiconductor memories with a small resource, so that the device scale does not become extremely large and the cost can be reduced.
- a part of a semiconductor memory device for example, some flash memories
- at least a part of a storage area for example, a block
- a defective storage area is provided with a defective storage area by a manufacturer.
- the defective storage area is masked by writing defective area information for identifying the defective storage area.
- a device that uses the semiconductor memory device does not use the storage area when certain storage area defect area information is read.
- an object of the present invention is to provide a semiconductor test apparatus and a control method thereof that can solve the above-mentioned problems.
- This object is achieved by a combination of features described in the independent claims.
- the dependent claims define further advantageous embodiments of the present invention.
- the first waveform generating means for generating a common pattern waveform corresponding to common information common to each of the plurality of semiconductor devices, and each of the plurality of semiconductor devices has A plurality of second waveform generating means for generating individual pattern waveforms corresponding to a plurality of individually prepared corresponding individual information, and the first waveform generating means for each of the plurality of semiconductor devices.
- a semiconductor test apparatus comprising a switching unit.
- Each of the plurality of semiconductor devices is a semiconductor memory device, and the waveform switching unit applies the common pattern waveform generated by the first waveform generation unit to each of the plurality of semiconductor memory devices.
- An operation of inputting in common and an operation of individually inputting the individual pattern waveform generated by each of the plurality of second waveform generating means as a write address where data is to be written are selectively performed.
- the semiconductor memory corresponds to the common pattern waveform or the individual pattern waveform.
- Pass / fail determination means for performing a pass / fail determination of a test target location in the semiconductor memory device based on an output waveform output from the redevice, and a fail memory for storing a determination result by the pass / fail determination means May be further provided.
- a memory for storing the individual information may be further provided, and the second waveform generating means may read the individual information stored in the memory to generate the individual pattern waveform.
- Each of the plurality of semiconductor memory devices has an interface for inputting a write address and write data in a time-division manner, and the waveform switching means inputs a write address to each of the plurality of semiconductor memory devices.
- each of the plurality of individual pattern waveforms is individually input to each of the plurality of semiconductor memory devices via the interface, and write data is written to each of the plurality of semiconductor memory devices.
- the common pattern waveform generated by the first waveform generating means may be commonly input to each of the plurality of semiconductor memory devices via the interface.
- Each of the interfaces of the plurality of semiconductor memory devices inputs a command, the write address and the write data in a time-division manner, and the waveform switching means outputs the command to each of the plurality of semiconductor memory devices.
- the common pattern waveform generated by the first waveform generating means is commonly input to each of the plurality of semiconductor memory devices via the interface, and
- each of the plurality of individual pattern waveforms is individually input to each of the plurality of semiconductor memory devices via the interface, and
- the timing at which write data should be input to each of the memory devices In grayed, to each of the plurality of semiconductor memory devices, it may be input through the interface of the first of the common pattern waveform generated by the waveform generating means in common.
- the plurality of semiconductor memories correspond to the first common pattern waveform generated by the first waveform generation means or the plurality of individual pattern waveforms generated by the plurality of second waveform generation means.
- a plurality of pass / fail determination means for performing a pass / fail determination of the storage area to be tested in the semiconductor memory device; and a fail memory for storing a plurality of determination results by the plurality of pass / fail determination means.
- a failure storage area selection unit that outputs information identifying a failure storage area for each of the plurality of semiconductor memory devices as each of the plurality of individual information based on the plurality of determination results stored in the fail memory.
- the plurality of second waveform generating means each include a plurality of the individual pattern waveforms respectively identified by the plurality of individual information and indicating an address of the defective storage area in each of the plurality of semiconductor memory devices.
- the first waveform generation means writes the write data for identifying that the storage area is defective.
- Generating the second common pattern waveform indicating the data, and the waveform switching means outputs the individual write command to each of the plurality of semiconductor memory devices as the write address indicating the defective storage area of the semiconductor memory device.
- a pattern waveform is individually input, the second common pattern waveform is commonly input as the write data indicating that the storage area corresponding to the write address is defective, and the write address is written in the write address. Data may be written.
- the defective storage area selecting means outputs information for identifying one or more defective storage areas for each of the plurality of semiconductor memory devices as each of the plurality of individual information, and Each of the waveform generation means generates the individual pattern waveform indicating an address of one or a plurality of the defective storage areas in each of the plurality of semiconductor memory devices identified by each of the plurality of individual information;
- the first waveform generating means generates the second common pattern waveform indicating write data for identifying that the storage area is defective, and the waveform switching means operates the respective ones of the plurality of semiconductor memory devices.
- the individual pattern waveform is individually used as one or more write addresses indicating one or more defective storage areas of the semiconductor memory device.
- the second common pattern waveform is commonly input as the write data indicating that one or a plurality of storage areas corresponding to one or a plurality of the write addresses is defective. Prohibiting writing to the semiconductor memory device that has finished writing the write data to all of the defective storage areas in the semiconductor memory device. In the state where the write data has not been written to all of the defective storage areas of the plurality of semiconductor memory devices, writing to the semiconductor memory device has not been completed. You can write it.
- a method of controlling a semiconductor test apparatus for testing a plurality of semiconductor devices wherein a common pattern waveform corresponding to common information common to each of the plurality of semiconductor devices is generated.
- a first waveform generating step for generating a plurality of individual waveforms corresponding to a plurality of individual information individually prepared for each of the plurality of semiconductor devices.
- a waveform switching step of selectively performing the operation of individually inputting the individual pattern waveforms thus performed.
- a semiconductor test apparatus for testing a plurality of semiconductor memory devices, wherein the plurality of semiconductor memory devices are tested based on test results of the plurality of semiconductor memory devices.
- a defective storage area selecting means for outputting individual information for identifying a defective storage area for each of the plurality of semiconductor memory devices; and a pattern waveform corresponding to a command for writing data in parallel with the plurality of semiconductor memory devices,
- a pattern waveform corresponding to the address of the defective storage area identified by the individual information of each semiconductor memory device is individually input as a write address, and it is determined that the storage area corresponding to the write address is defective.
- Waveform output means for commonly inputting a pattern waveform corresponding to the data to be indicated as write data.
- a method of controlling a semiconductor test apparatus for testing a plurality of semiconductor memory devices wherein the plurality of semiconductor memory devices are tested based on test results of the plurality of semiconductor memory devices.
- the pattern waveform corresponding to the address of the defective storage area is individually input as a write address
- the pattern waveform corresponding to the data indicating that the storage area corresponding to the write address is defective is defined as the write data.
- the present invention provides a control method having a common input waveform output stage.
- the operation of generating and inputting a plurality of individual information items different from each other can be performed in parallel with respect to each of the plurality of semiconductor devices, and separate operation can be performed for each of the plurality of semiconductor memory devices.
- the time required for the test and / or the rescue operation when the input of the address based on the individual information is required can be reduced.
- FIG. 1 shows a configuration of a semiconductor test apparatus according to one embodiment.
- FIG. 2 shows a specific example of a test operation in which an individual write operation is performed as necessary.
- FIG. 3 shows a specific example of a rescue operation in which an individual write operation is performed as needed.
- FIG. 4 shows a configuration of a semiconductor test apparatus according to a modification of the present embodiment.
- FIG. 1 is a diagram showing a configuration of a semiconductor test apparatus of the present embodiment.
- the semiconductor test apparatus shown in FIG. 1 performs tests on a plurality of DUTs (Device Under Tests) 9 in parallel, and also performs relief operations on the plurality of DUTs 9 in parallel.
- the semiconductor test apparatus of the present embodiment includes an ALPG (algorithmic 'pattern. Generator) 1, an AFM (address' fail' memory) 3, a 1-pin processing unit 5, a 1-channel 7, a test control unit. It is composed of ten.
- the DUT 9 has a wide range of semiconductor devices such as semiconductor memory devices and logic ICs. In the following description, semiconductor memory devices are mainly tested.
- the ALPG 1 generates pattern data (PAT) to be input to the 1 ⁇ pin of the DUT 9 for performing a test or a rescue operation.
- the AFM 3 stores fail information, which is a judgment result obtained by a test on the DUT 9, in units of cells of the DUT 9. Specifically, as a result of a pass / fail test of a storage cell corresponding to one of the logical addresses X and Y of the DUT 9, the data is stored in an area specified by the addresses X and Y of the force AFM3.
- the IO pin processing unit 5 generates data to be input to the 1 D pin of the DUT 9 and performs a pass / fail judgment of the data output from these IO pins.
- the “IO pin” is a pattern waveform such as a pin of a semiconductor memory device for inputting a command and / or an address to the semiconductor memory device and a pin for inputting and outputting memory data to and from the semiconductor memory device. This is a pin for input and output.
- the TG / main FC unit 50 performs a function as a timing generator for generating various timing edges included in the basic cycle of the test operation, and based on the timing edges and the pattern data output from the ALPG1, Generates actual data (common pattern waveform) input to DUT9. This data is input to one input terminal of an AND circuit 51 provided at a subsequent stage. To the other input terminal of the AND circuit 51, an individual write mode signal (MODE) is inverted and input. “Individual write mode” is an operation mode in which individual information is written in parallel to each of multiple DUTs 9 to be measured simultaneously. The individual write mode is specified by, for example, setting the individual write mode signal to a high level using the above-described ALPG1.
- this mode signal is a signal that can be controlled by the ALPG1, and by using this mode signal, it is possible to switch between the common pattern waveform and the individual write pattern waveform in real time.
- the memory 54 stores arbitrary pattern data.
- 1 ⁇ pin processing unit 5 1 ⁇ pin processing unit 5
- the sub FC unit 58 generates actual data (individual pattern waveform) to be input to each DUT 9 in the individual write mode based on the data to which the memory 54 is also input.
- the output data of the sub FC unit 58 is input to the other end of the AND circuit 151 having the individual write mode signal (MODE) input to the negative end, and when the individual write mode signal is at the high level, It is input to the OR circuit 52 at the subsequent stage.
- MODE individual write mode signal
- each sub FC unit 58 individually has the function of the timing generator of the TG / main FC unit 50.
- the OR circuit 52 receives data generated by the TG / main FC unit 50 and input via the AND circuit 51 or data generated by the sub FC unit 58 and input via the AND circuit 151. Output.
- the output data of the OR circuit 52 is output to the IO channel 7 through a flip-flop 53 that generates a data pattern to be applied to the IO channel 7.
- the logical comparator 59 compares data output from the 1 ⁇ pin of the DUT 9 with predetermined expected value data, and performs a pass determination if they match and a fail determination if they do not match. This judgment result is stored in AFM3.
- the internal configuration of the 1 ⁇ pin processing unit 5 is such that the TG / main FC unit 50 and AND circuit 51 are provided in common for a plurality of DUTs 9, and the other sub FC unit 58, memory 54, Logical comparators 59 and the like are individually provided corresponding to each of the plurality of DUTs 9. Further, an IO pin processing unit 5 is individually provided for each of the plurality of IO pins of each DUT 9.
- the IO channel 7 generates an actual pattern waveform applied to the pin 1 of the DUT 9, and converts a waveform actually output from the pin 1 into logical data.
- the 1-channel 7 has a driver (DR) 70 and a comparator (CP) 71.
- the dry loop 70 generates a normal waveform based on the data input to the flip-flop 53 in the corresponding 1-pin processing unit 5.
- the comparator 71 determines the value of the logical data by comparing the voltage of the waveform appearing at the IO pin (I / O) of the DUT 9 with a predetermined reference voltage.
- the test control unit 10 is an example of a defective storage area selection unit, and is provided for controlling a test by a semiconductor test device.
- the test control unit 10 based on the determination result stored in the AFM 3, the test control unit 10 generates a plurality of pieces of individual information used for the test operation or the rescue operation of the plurality of DUTs 9, and outputs the individual information to the memory.
- the test control unit 10 includes one or more EWSs (engineering's) to speed up the process of generating individual information from the judgment results. (Workstation).
- the ALPG1, the AFM3, and the IO pin processing unit 5 operate as a waveform output unit that inputs a pattern waveform to a plurality of DUTs 9 in parallel.
- the TG / main FC unit 50 operates as first waveform generation means for generating a common pattern waveform corresponding to common information supplied from the ALPG 1 and common to each of the plurality of DUTs 9.
- the plurality of sub FC sections 58 operate as a plurality of second waveform generating means for generating individual pattern waveforms corresponding to a plurality of individual information individually prepared in the memory 54 corresponding to each of the plurality of DUTs 9. I do.
- the AND circuits 51 and 151 and the OR circuit 52 perform an operation of commonly inputting the common pattern waveform generated by the first waveform generating means to each of the plurality of DUTs 9, and a plurality of second circuits. It operates as waveform switching means for selectively inputting individual pattern waveforms generated by each of the waveform generating means.
- the waveform switching means selects an operation of individually inputting an individual pattern waveform to each of the plurality of DUTs 9. May be performed. More specifically, the waveform switching means may individually input the individual pattern waveform to each of the plurality of DUTs 9 as a write address where data such as defective area information is to be written.
- the logical comparator 59 performs a pass / failure for performing a pass / fail judgment of a test target portion in the DUT 9 based on an output waveform output from the DUT 9 corresponding to the common pattern waveform or the individual pattern waveform. It operates as a determination means.
- the AFM 3 operates as a fail memory for storing the result of the judgment by the pass / fail judgment means.
- the semiconductor test apparatus of the present embodiment has such a configuration, and a test operation and a rescue operation for the DUT 9 will be described.
- the pattern data output from ALPG1 is supplied to the IO pin processing unit 5 corresponding to the IO pin to which the pattern data is to be input.
- the TGZ main FC unit 50 create test data according to the actual input timing.
- the individual write mode signal maintains the low level
- the output data of the TG / main FC unit 50 input to one input terminal is output from the AND circuit 51 as it is.
- An output terminal of the AND circuit 51 is branched and connected to one input terminal of an OR circuit 52 provided corresponding to each of the plurality of DUTs 9. Therefore, common data output from the TG / main FC unit 50 is simultaneously input to the plurality of OR circuits 52 and input to the flip-flop 53.
- the driver 70 In the IO channel 7, the driver 70 generates a normal waveform based on the data input to the flip-flop 53 in the IO pin processing unit 5. This normal waveform is input to the corresponding 1 ⁇ pin (IZO).
- the normal waveform generated by the IO pin processing unit 5 and the IO channel 7 is input to the IO pin.
- the comparator 71 compares the voltage of the waveform output from this IO pin with a predetermined reference voltage to generate logical data. Further, in the IO pin processing unit 5 corresponding to the 1 ⁇ pin, the logical comparator 59 performs pass / fail determination using the data input from the comparator 71 in the IO channel 7. This determination result is stored in AFM3.
- pattern data corresponding to each IO pin of each DUT 9 stored in the memory 54 is read and input to the sub FC unit 58.
- the sub FC unit 58 creates test data corresponding to the individual information for each DUT 9 in accordance with the actual input timing based on the input pattern data.
- a normal waveform is generated based on the data input to the flip-flop 53 via the OR circuit 52.
- the driver 70 In the IO channel 7, the driver 70 generates a normal waveform based on the data input to the flip-flop 53 in the IO pin processing unit 5.
- a different normal waveform is generated for each DUT9 and input to the corresponding DUT9 IO pin (1 ⁇ ).
- FIG. 2 is a timing diagram showing a specific example of a test operation in which an individual write operation is performed as necessary.
- FIG. 2 shows an example of a timing when a plurality of flash memories are tested as a plurality of DUTs 9. ing.
- each of the plurality of DUTs 9 is provided with an interface for inputting a command, a write address, and write data in a time-division manner at the time of a write operation at the 1st pin (1st).
- This data has different contents set for each flash memory. For example, data D, D,... corresponding to DUT #a,
- Data D ', D', ... are set as data D ", D", ... corresponding to DUT #n.
- Input operation of individual information such as 0 0 0 is performed by generating individual data by the sub FC unit 58 in the IO pin processing unit 5 based on the individual information stored in the AFM 3 or the memory 54. Be done.
- the waveform switching unit when performing a test of writing different write data to the same write address of each of the plurality of DUTs 9, the waveform switching unit inputs a command and a common write address to each of the plurality of DUTs 9.
- the common pattern waveform generated by the first waveform generating means is commonly input to each of the plurality of DUTs 9 via the interface of each DUT 9.
- the waveform switching means may output the plurality of individual patterns generated by the second waveform generation means to each of the plurality of DUTs 9 at a timing at which different write data is to be input to each of the plurality of DUTs 9.
- Each of the waveforms is individually input via the respective DUT9 interface.
- the DUT 9 Programming is performed in each of (DUT # a— # n). Then, based on the pattern data stored in ALPG1, a command to output a programming result is input to each of the plurality of DUTs 9 from the IO pin, and the programming result is output in a polling format. The result of this programming is input to the comparator 71 in the IO channel 7 and further passed to the logical comparator 59 in the 1 ⁇ pin processing unit 5 to make a pass / fail determination.
- the semiconductor test apparatus switches the individual write mode signal from the low level to the high level during the test, thereby changing the test operation using the ALPG1 from the test operation using the memory 54 to the individual write mode. It can be changed at any time. Then, by returning the individual write mode signal from the high level to the low level as needed, the test operation using the ALPG1 can be returned.
- the mode is switched to the individual write mode at the timing required in a series of test operations, or conversely, It is possible to return to the mode, and complicated control of switching timing is not required.
- the semiconductor test apparatus supplies a common command, address, and / or data to at least a part of the command, address, and data to be supplied to the plurality of DUTs 9, and supplies the common command, address, and / or data to other parts.
- Individual commands, addresses, and / or data can be provided to them.
- the rescue operation it is necessary to input an address for specifying the defective storage area of each of the plurality of DUTs 9 as individual information to each DUT 9 and to commonly input the defective area information as write data. That is, the operation of inputting the individual information to the specific 1 pin is the same as the operation of the individual write mode in the test operation described above. The operation of inputting common information to the IO pins of each DUT 9 is the same as the operation in the test operation described above except for the individual write mode.
- the setting of each part of the IO pin processing unit 5 at the time of the rescue operation is basically the same as the setting at the time of the individual writing mode in the test operation described above, and the individual indicating the rescue position of each DUT 9 is performed.
- Write address is generated by the sub FC unit 58 in the IO pin processing unit 5. Input from IO channel 7 to the I ⁇ pin of each DUT9.
- FIG. 3 is a timing chart showing a specific example of the rescue operation.
- the semiconductor test equipment To rescue a DUT 9 containing a defective cell, the semiconductor test equipment first performs a test operation and stores individual information for identifying a defective storage area in a memory based on the test result stored in the test result AFM3. Write it in 54.
- the plurality of logical comparators 59 include a first common pattern waveform generated by the first waveform generating means or a plurality of individual patterns generated by the plurality of second waveform generating means. Based on the output waveforms output from each of the plurality of DUTs 9 corresponding to the waveforms, a pass Z fail determination of the storage area to be tested in the DUT 9 is performed.
- the AFM 3 stores the judgment results of the plurality of logical comparators 59 as test results of the plurality of DUTs 9 respectively.
- the test control unit 10 determines the information for identifying the defective storage area for each of the plurality of DUTs 9 and the information for each of the plurality of individual information. Is output to each of the plurality of memories 54 and stored.
- the first waveform generation means generates a common pattern waveform of common data (program) corresponding to the "command".
- the waveform switching means commonly inputs a common pattern waveform corresponding to the command to each of the plurality of DUTs 9 via the interface of the IO pin at a timing when a command is to be input to each of the plurality of DUTs 9.
- each of the plurality of second waveform generation units is identified by each of the plurality of individual information stored in the memory 54 and corresponding to the plurality of DUTs 9, respectively. Then, an individual pattern waveform indicating the address of the defective storage area is generated.
- the waveform switching means inputs each of the plurality of individual pattern waveforms to each of the plurality of DUTs 9 individually via the 1 ⁇ pin interface at the timing when the write address is to be input to each of the plurality of DUTs 9.
- the first waveform generation means generates a common pattern waveform indicating write data for identifying that the storage area is defective.
- the waveform switching means uses the common pin waveform generated by the first waveform generating means to each of the plurality of DUTs 9 at the timing at which the write data is to be input to each of the plurality of DUTs 9, and the I / O pin interface. To enter through.
- the waveform output means inputs a pattern waveform corresponding to a command for writing data in parallel to a plurality of DUTs 9 and identifies them by individual information for each of the plurality of DUTs 9.
- the pattern waveform corresponding to the address of the defective storage area to be written is individually input as a write address, and the pattern waveform corresponding to the data indicating that the storage area corresponding to the write address is defective is used as the write data. Can be entered in common.
- the waveform switching means individually inputs an individual pattern waveform as a write address indicating the defective storage area of the DUT 9 to each of the plurality of DUTs 9, and the storage area corresponding to the write address is A common pattern waveform can be commonly input as write data indicating failure, and write data can be written to a write address.
- the semiconductor test apparatus can write the defective area information in parallel to the defective storage areas of different addresses of the plurality of DUTs 9, and can reduce the time required for the rescue operation.
- the semiconductor test apparatus performs the following rescue operation.
- the test control unit 10 outputs information identifying one or a plurality of defective storage areas for each of the plurality of DUTs 9 as each of a plurality of individual information based on the plurality of determination results stored in the AFM 3, and In each of the memories 54.
- the first waveform generating means generates a common pattern waveform of common data (program) corresponding to “command” corresponding to one or a plurality of defective storage areas in each of the plurality of DUTs 9.
- Each of the plurality of second waveform generation means generates an individual pattern waveform indicating the address of one or a plurality of defective storage areas in each of the plurality of DUTs 9 identified by each of the plurality of individual information stored in the memory 54. Generate sequentially.
- the first waveform generation means generates a common pattern waveform indicating write data for identifying that the storage area is defective, corresponding to each of the one or more defective storage areas.
- the waveform switching means commonly inputs a common pattern waveform of a command to each of the plurality of DUTs 9 corresponding to each of the defective storage areas of the DUT 9.
- one or more documents indicating one or more defective storage areas of the DUT 9 are assigned to each of the plurality of DUTs 9.
- the individual pattern waveform is individually input as the embedded address.
- a common pattern waveform of the generated write data is commonly input as write data indicating that one or more storage areas corresponding to one or more write addresses are defective.
- the plurality of DUTs 9 may each have a different number of defective storage areas.
- the waveform switching means writes the DUT 9 that has finished writing the write data to all the defective storage areas among the plurality of DUTs 9. In the prohibited state, the writing of the write data to all the defective storage areas of the plurality of DUTs 9 which has not been completed is completed, and the write data is written.
- the waveform switching unit writes the DUT 9 to the DUT 9 that has not finished writing the write data to all the defective storage areas.
- the write data is written by enabling the enable signal pin (ZWE).
- the writing of the write data is prohibited by setting the write enable signal pin (/ WE) of the DUT 9 to disabled.
- the waveform switching means enables or disables the chip enable signal pin (/ CE) instead of the write enable signal pin, thereby selecting or deselecting the DUT 9 itself and writing. Data writing may be permitted or prohibited.
- the operations of generating and inputting a plurality of pieces of individual information different from each other can be performed in parallel for each of the plurality of DUTs 9.
- the time required for the test when the input of individual information is required can be reduced.
- the expansion of the device scale can be minimized. Can be suppressed.
- the memory 54 for storing the individual information is provided in the 1 ⁇ pin processing unit 5, the wiring routed outside the ASIC package is not required, and the wiring can be simplified. In addition, since unnecessary wiring is eliminated, timing shifts and the like hardly occur, and reading of individual information is prevented. Extrusion can be performed at high speed.
- a sub FC section 58 in which some of these functions are omitted is provided.
- the same number of TG / main FC units may be provided instead of the sub FC unit 58.
- FIG. 4 is a diagram showing a configuration of a semiconductor test apparatus according to a modification of the present embodiment.
- the semiconductor test apparatus shown in Fig. 4 performs tests on multiple DUTs 9 in parallel, and performs relief operations on these multiple DUTs 9 in parallel.
- the members in FIG. 4 that are denoted by the same reference numerals as those in FIG. 1 have the same functions and configurations as the members denoted by the same reference numerals in FIG.
- the semiconductor test apparatus includes a plurality of test modules 202 provided for each of a plurality of DUTs 9, an IO channel 7, and a test control unit 210.
- the plurality of test modules 202 are an example of waveform output means, and input pattern data generated by the ALPG1 or PG (pattern 'generator) 201 to the DUT9 via the IO channel 7 in parallel with the plurality of DUT9. I do.
- the test module 202 includes an ALPG1, a PG201, one or a plurality of IO pin processing units 205, and an AFM3.
- the PG 201 includes a pattern memory for storing a test pattern to be output to the DUT 9, and sequentially supplies the test patterns stored in the pattern memory to the 1-pin processing unit 205.
- a plurality of IO pin processing units 205 are provided corresponding to the plurality of 1-pins of the DUT 9 to which the test module 202 is connected, respectively, and are provided to the DUT 9 based on the pattern data supplied from the ALPG1 or PG201. Generates input data and performs pass / fail judgment of data output from the corresponding 1 ⁇ pin.
- the IO pin processing unit 205 includes a TG / main FC unit 250, a flip-flop 53, and a logical comparator 59.
- the TG / main FC unit 250 generates a pattern waveform to be input to the DUT 9 to which the test module 202 including the TGZ main FC unit 250 is connected, and supplies the pattern waveform to the flip-flop 53.
- the TG / main FC unit 250 has the same function and configuration as the TGZ main FC unit 50 shown in FIG.
- the test control unit 210 is an example of a defective storage area selection unit, and is provided to control a test using a semiconductor test apparatus.
- the test control unit 210 Based on the judgment results stored in AFM3 as the test results for each of 9
- a plurality of pieces of individual information used for the test operation or the rescue operation of the UT 9 are generated and output to the test control unit 210.
- the multiple ALPGs 1 provided corresponding to the multiple DUTs 9 output the same pattern data based on the same algorithm.
- the pattern data output from ALPG1 is supplied to a 1-pin processing unit 205 corresponding to a 1-pin to which the pattern data is to be input.
- the TGZ main FC unit 50 creates test data according to the actual input timing based on the input pattern data.
- the driver 70 In the IO channel 7, the driver 70 generates a normal waveform based on the data input to the flip-flop 53 in the IO pin processing unit 205. This normal waveform is input to the corresponding IO pin (I / O).
- the normal waveform generated by the IO pin processing unit 205 and the IO channel 7 is input to the 1 ⁇ pin.
- the comparator 71 compares the voltage of the waveform output from the 1 ⁇ pin with a predetermined reference voltage to generate logical data. Further, in the IO pin processing unit 5 corresponding to the IO pin, the logical comparator 59 performs pass / fail determination using the data input from the comparator 71 in the IO channel 7. This determination result is stored in AFM3.
- the test control unit 210 stores different test patterns in the pattern memory provided in the PG 201 in the plurality of test modules 202 in accordance with the individual information.
- the PG 201 reads out individual test patterns and supplies individual pattern data to the TG / main FC unit 250.
- the TGZ main FC section 250 performs actual input based on the input pattern data.
- the flip-flop 53 generates a normal waveform based on the input data.
- the driver 70 generates a normal waveform based on the data input to the flip-flop 53 in the 1 ⁇ pin processing unit 205.
- a different normal waveform is generated for each DUT9 and input to the corresponding 1 ⁇ pin (IO) of the DUT9.
- the timing of the test operation in which the individual write operation is performed is the same as that in FIG. 2, for example, except for the individual write mode signal.
- common pattern data corresponding to “command”, common pattern data corresponding to “address”, and individual pattern data corresponding to “data” are stored in a plurality of PGs 201 corresponding to a plurality of DUTs 9, respectively. Test patterns to be output sequentially are stored.
- the plurality of test modules 202 write different data in parallel to the plurality of DUTs 9 based on the test patterns stored in the PG 201 in the test module 202. More specifically, the 1 ⁇ pin processing unit 205 inputs the write command and the pattern waveform corresponding to the write address, which are stored in common to all PGs 201, to the DUT 9 and individually inputs to each PG 201 By inputting the pattern waveform corresponding to the stored write data to the DUT 9 in common, different write data is written in parallel to the same write address of each of the multiple DUTs 9. In this way, the semiconductor test apparatus according to the present modification supplies the command, the address, and / or the data to be supplied to the plurality of DUTs 9 and the individual command, the address, and / or the other parts. Data can be supplied.
- the rescue operation it is necessary to input an address for specifying the defective storage area of each of the plurality of DUTs 9 as individual information to each DUT 9 and to commonly input the defective area information as write data. That is, the operation of inputting the individual information to the specific 1 pin is the same as the individual writing operation in the test operation described above.
- the operation of inputting common information to the 1 ⁇ pin of each DUT 9 is the same as the operation other than the individual write operation in the test operation described above.
- each unit of the IO pin processing unit 205 during the rescue operation is basically described above. This is the same as the setting in the individual write operation in the test operation.
- the individual write address indicating the rescue location of each DUT 9 is stored as a test pattern in the PG 201 corresponding to the DUT 9 and a pattern waveform is generated by the TG / main FC unit 250 in the IO pin processing unit 205 Then, it is input from IO channel 7 to pin 1 ⁇ of each DUT9.
- the timing of the test operation in which the individual rescue operation is performed is the same as, for example, the one except for the individual write mode signal in FIG.
- the test control unit 210 determines a failure for each of the plurality of DUTs 9 based on a plurality of determination results stored in the AFM 3, which are test results of the plurality of DUTs 9.
- a test pattern including individual information for identifying a region is generated. This test pattern is a pattern for sequentially outputting common pattern data corresponding to “command”, individual pattern data corresponding to “address”, and common pattern data corresponding to “data”.
- the test control unit 210 individually transmits the test pattern generated corresponding to each DUT 9 to each of the plurality of test modules 202 and stores the test pattern in the PG 201.
- the plurality of test modules 202 write defect area information to different defect storage areas in parallel with respect to the plurality of DUTs 9 based on the test pattern stored in the PG 201 in the test module 202. More specifically, based on the test pattern stored in the PG 201, the IO pin processing unit 205 inputs a pattern waveform corresponding to the write command to a plurality of DUTs 9 in common, and A pattern waveform corresponding to the address of the defective storage area identified by the individual information is individually input as a write address to a plurality of DUTs 9 and a pattern corresponding to data indicating that the storage area corresponding to the write address is defective. Input the waveform as write data to multiple DUTs in common.
- the semiconductor test apparatus according to the present modification can write different write data to the same write address of each of the plurality of DUTs 9 in parallel.
- the semiconductor test apparatus according to the present modification can write defective area information in parallel to defective storage areas of different addresses of the plurality of DUTs 9, and can reduce the time required for the rescue operation.
- the present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the present invention.
- a plurality of power logic ICs which have been described mainly with a semiconductor memory as the DUT 9 are simultaneously tested.
- the present invention can be applied when conducting an experiment.
- the operations of generating and inputting a plurality of pieces of individual information different from each other can be performed in parallel for each of a plurality of semiconductor devices.
- the time required for a test and / or a rescue operation can be reduced.
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- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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EP04745915A EP1643509B1 (en) | 2003-06-19 | 2004-06-15 | Semiconductor test device and control method thereof |
DE602004025347T DE602004025347D1 (de) | 2003-06-19 | 2004-06-15 | Halbleiter-prüfeinrichtung und steuerverfahren dafür |
US11/303,191 US7356435B2 (en) | 2003-06-19 | 2005-12-16 | Semiconductor test apparatus and control method therefor |
Applications Claiming Priority (4)
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JP2003174477 | 2003-06-19 | ||
JP2003-174477 | 2003-06-19 | ||
JP2003-185679 | 2003-06-27 | ||
JP2003185679A JP4334285B2 (ja) | 2003-06-19 | 2003-06-27 | 半導体試験装置及びその制御方法 |
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US11/303,191 Continuation US7356435B2 (en) | 2003-06-19 | 2005-12-16 | Semiconductor test apparatus and control method therefor |
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WO2004114318A1 true WO2004114318A1 (ja) | 2004-12-29 |
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PCT/JP2004/008361 WO2004114318A1 (ja) | 2003-06-19 | 2004-06-15 | 半導体試験装置及びその制御方法 |
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Country | Link |
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US (1) | US7356435B2 (ja) |
EP (1) | EP1643509B1 (ja) |
JP (1) | JP4334285B2 (ja) |
KR (1) | KR100733234B1 (ja) |
CN (1) | CN100524536C (ja) |
DE (1) | DE602004025347D1 (ja) |
PT (1) | PT1643509E (ja) |
TW (1) | TWI317430B (ja) |
WO (1) | WO2004114318A1 (ja) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4542852B2 (ja) * | 2004-08-20 | 2010-09-15 | 株式会社アドバンテスト | 試験装置及び試験方法 |
US7913002B2 (en) * | 2004-08-20 | 2011-03-22 | Advantest Corporation | Test apparatus, configuration method, and device interface |
JP2006294104A (ja) * | 2005-04-08 | 2006-10-26 | Yokogawa Electric Corp | デバイス試験装置およびデバイス試験方法 |
KR100753050B1 (ko) | 2005-09-29 | 2007-08-30 | 주식회사 하이닉스반도체 | 테스트장치 |
KR100788913B1 (ko) * | 2005-11-18 | 2007-12-27 | 주식회사디아이 | 반도체 장치의 테스트 시스템을 위한 전치 분기 패턴 발생장치 |
KR100750397B1 (ko) * | 2006-01-24 | 2007-08-17 | 주식회사디아이 | 웨이퍼 검사장치의 멀티 테스트 구현시스템 |
US20070208968A1 (en) * | 2006-03-01 | 2007-09-06 | Anand Krishnamurthy | At-speed multi-port memory array test method and apparatus |
KR100859793B1 (ko) * | 2007-06-25 | 2008-09-23 | 주식회사 메모리앤테스팅 | 반도체 테스트 장치 및 이를 이용한 반도체 테스트 방법 |
US7821284B2 (en) * | 2008-10-24 | 2010-10-26 | It&T | Semiconductor test head apparatus using field programmable gate array |
CN101776731B (zh) * | 2009-01-14 | 2012-06-13 | 南亚科技股份有限公司 | 半导体组件测试装置与方法 |
JP2011007721A (ja) * | 2009-06-29 | 2011-01-13 | Yokogawa Electric Corp | 半導体試験装置、半導体試験方法および半導体試験プログラム |
EP2587489A1 (en) * | 2011-10-27 | 2013-05-01 | Maishi Electronic (Shanghai) Ltd. | Systems and methods for testing memories |
CN103093829A (zh) * | 2011-10-27 | 2013-05-08 | 迈实电子(上海)有限公司 | 存储器测试系统及存储器测试方法 |
US9285828B2 (en) * | 2013-07-11 | 2016-03-15 | Apple Inc. | Memory system with improved bus timing calibration |
US20170045579A1 (en) * | 2015-08-14 | 2017-02-16 | Texas Instruments Incorporated | Cpu bist testing of integrated circuits using serial wire debug |
US10319453B2 (en) * | 2017-03-16 | 2019-06-11 | Intel Corporation | Board level leakage testing for memory interface |
KR20220052780A (ko) * | 2020-10-21 | 2022-04-28 | 에스케이하이닉스 주식회사 | 테스트회로를 포함하는 전자장치 및 그의 동작 방법 |
CN115047307B (zh) * | 2022-08-17 | 2022-11-25 | 浙江杭可仪器有限公司 | 一种半导体器件老化测试箱 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11203893A (ja) * | 1998-01-05 | 1999-07-30 | Fujitsu Ltd | 半導体装置及び半導体装置の試験方法 |
JP2002071766A (ja) * | 2000-08-28 | 2002-03-12 | Advantest Corp | 半導体試験装置 |
JP2002174669A (ja) * | 1999-03-01 | 2002-06-21 | Formfactor Inc | Dut間及びdut内比較を用いる、集積回路デバイスの同時テスト |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR0140176B1 (ko) * | 1994-11-30 | 1998-07-15 | 김광호 | 반도체 메모리장치의 동작모드 제어장치 및 방법 |
US6094733A (en) * | 1996-01-25 | 2000-07-25 | Kabushiki Kaisha Toshiba | Method for testing semiconductor memory devices, and apparatus and system for testing semiconductor memory devices |
JPH09288153A (ja) * | 1996-04-19 | 1997-11-04 | Advantest Corp | 半導体試験装置 |
US5794175A (en) * | 1997-09-09 | 1998-08-11 | Teradyne, Inc. | Low cost, highly parallel memory tester |
WO2001013347A1 (fr) * | 1999-08-17 | 2001-02-22 | Advantest Corporation | Adaptateur de commande d'instrument de mesure, instrument de mesure, systeme de commande d'instrument de mesure, procede d'execution de mesure et support enregistre |
JP3447638B2 (ja) * | 1999-12-24 | 2003-09-16 | 日本電気株式会社 | 半導体装置のテスト方法及びシステム並びに記録媒体 |
JP2002015596A (ja) * | 2000-06-27 | 2002-01-18 | Advantest Corp | 半導体試験装置 |
WO2002103379A1 (fr) * | 2001-06-13 | 2002-12-27 | Advantest Corporation | Instrument destine a tester des dispositifs semi-conducteurs et procede destine a tester des dispositifs semi-conducteurs |
JP4291596B2 (ja) * | 2003-02-26 | 2009-07-08 | 株式会社ルネサステクノロジ | 半導体集積回路の試験装置およびそれを用いた半導体集積回路の製造方法 |
-
2003
- 2003-06-27 JP JP2003185679A patent/JP4334285B2/ja not_active Expired - Fee Related
-
2004
- 2004-06-15 PT PT04745915T patent/PT1643509E/pt unknown
- 2004-06-15 KR KR1020057024360A patent/KR100733234B1/ko not_active IP Right Cessation
- 2004-06-15 CN CNB2004800169762A patent/CN100524536C/zh not_active Expired - Fee Related
- 2004-06-15 WO PCT/JP2004/008361 patent/WO2004114318A1/ja active Application Filing
- 2004-06-15 DE DE602004025347T patent/DE602004025347D1/de not_active Expired - Lifetime
- 2004-06-15 EP EP04745915A patent/EP1643509B1/en not_active Expired - Lifetime
- 2004-06-18 TW TW093117611A patent/TWI317430B/zh not_active IP Right Cessation
-
2005
- 2005-12-16 US US11/303,191 patent/US7356435B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11203893A (ja) * | 1998-01-05 | 1999-07-30 | Fujitsu Ltd | 半導体装置及び半導体装置の試験方法 |
JP2002174669A (ja) * | 1999-03-01 | 2002-06-21 | Formfactor Inc | Dut間及びdut内比較を用いる、集積回路デバイスの同時テスト |
JP2002071766A (ja) * | 2000-08-28 | 2002-03-12 | Advantest Corp | 半導体試験装置 |
Non-Patent Citations (1)
Title |
---|
See also references of EP1643509A4 * |
Also Published As
Publication number | Publication date |
---|---|
CN100524536C (zh) | 2009-08-05 |
EP1643509A4 (en) | 2007-04-04 |
TW200508631A (en) | 2005-03-01 |
US20060092755A1 (en) | 2006-05-04 |
US7356435B2 (en) | 2008-04-08 |
KR20060019607A (ko) | 2006-03-03 |
EP1643509A1 (en) | 2006-04-05 |
TWI317430B (en) | 2009-11-21 |
JP4334285B2 (ja) | 2009-09-30 |
EP1643509B1 (en) | 2010-01-27 |
PT1643509E (pt) | 2010-03-25 |
DE602004025347D1 (de) | 2010-03-18 |
CN1809896A (zh) | 2006-07-26 |
KR100733234B1 (ko) | 2007-06-27 |
JP2005063471A (ja) | 2005-03-10 |
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