WO2004061978A1 - 電界効果トランジスタ - Google Patents
電界効果トランジスタ Download PDFInfo
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- WO2004061978A1 WO2004061978A1 PCT/JP2003/016033 JP0316033W WO2004061978A1 WO 2004061978 A1 WO2004061978 A1 WO 2004061978A1 JP 0316033 W JP0316033 W JP 0316033W WO 2004061978 A1 WO2004061978 A1 WO 2004061978A1
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- electrode
- insulating film
- electric field
- effect transistor
- film
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- 230000005669 field effect Effects 0.000 title claims description 39
- 230000005684 electric field Effects 0.000 claims abstract description 210
- 239000004065 semiconductor Substances 0.000 claims description 98
- 150000004767 nitrides Chemical class 0.000 claims description 45
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 34
- 230000000694 effects Effects 0.000 claims description 31
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- 229910002704 AlGaN Inorganic materials 0.000 abstract description 8
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
Definitions
- the present invention relates to a field effect transistor using a group III nitride semiconductor.
- Group III nitride semiconductors such as GaN have a large band gap, a high breakdown electric field, a high electron saturation drift velocity, and the use of a two-dimensional carrier gas by a heterojunction. It is expected to be a material for realizing electronic devices that excel in high-temperature operation, high-speed switching operation, and high-power operation.
- Non-Patent Document 1 An extremely large sheet electron density is generated. This phenomenon is described in detail in Non-Patent Document 1, for example.
- an electric field is applied to the heterostructure between to form a Omikku electrodes electrodes, 1 X 1 0 13 / " cm 2 current based on the charge transport of the high electron density of the order one flow.
- III-nitride Unlike a GaAs-based semiconductor FET driven by a carrier generated by impurity doping, a semiconductor device operates by a high-concentration carrier generated by both spontaneous polarization and piezo polarization. In a group III nitride semiconductor transistor operated by such a mechanism, it is required to improve the breakdown voltage while improving the gain. Conventionally, the following techniques have been known as methods for improving the withstand voltage.
- Non-Patent Document 2 describes a configuration in which an eave-shaped field plate is provided on the drain side of a gate electrode, and a SIN film is arranged below the field plate.
- FIG. 18 shows a schematic structure of the HJFET.
- the HJFET is formed on the SiC substrate 110.
- a buffer layer 111 composed of a semiconductor layer is formed.
- a GaN channel layer 112 is formed on this puffer layer 111.
- An A 1 GaN electron supply layer 113 is formed on the channel layer.
- On this electron supply layer there are a source electrode 101 and a drain electrode 103 in ohmic contact, between which a field plate 105 and a gate electrode in short shot contact are formed. There are 102.
- the surface of the electron supply layer 113 is covered with a SiN film 121, and the SiN film 121 is disposed immediately below the field plate part 105. According to the document, it is described that the gate withstand voltage is improved by adopting such a configuration.
- Patent Document 1 discloses a technique of providing an electric field control electrode between a gate electrode and a drain electrode in a GaAs semiconductor device. This document describes that the provision of such an electric field control electrode reduces the electric field concentration at the drain-side end of the gate electrode, and improves the device performance.
- Non-Patent Document 1 In a stacked structure of a group III nitride semiconductor including a heterojunction, a large charge is generated in the channel layer due to piezo polarization and the like, while a large charge is generated on the surface of the semiconductor layer such as A 1 GaN. It is known that a negative charge is generated (Non-Patent Document 1). 'These negative charges directly affect the drain current and have a strong effect on device performance. Specifically, when a large negative charge is generated on the surface, the maximum drain current during AC operation is deteriorated as compared with DC. This phenomenon is hereinafter referred to as collabs. Collabs occurred remarkably in devices using Group III nitride semiconductors, and was not apparent in GaAs-based semiconductor devices. This is because the generation of polarized charges is extremely small in the A1GaAsZZGaAs heterojunction.
- FIG. 17 is a cross-sectional view of a conventional heterojunction field effect transistor (HJFET).
- HJFET heterojunction field effect transistor
- a buffer layer 111 made of A 1 N, a GaN channel layer 112 and an A 1 GaN electron supply layer 113 are laminated on a sapphire substrate 109 in this order.
- a source electrode 101 and a drain electrode 103 are formed thereon, and these electrodes are in ohmic contact with the A 1 GaN electron supply layer 113.
- a gate electrode 102 is formed between the source electrode 101 and the drain electrode 103, and the gate electrode is in Schottky contact with the A1GaN electron supply layer 113.
- a SiN film 121 is formed as a surface protective film.
- Non-Patent Document 1 UKMishra, P.Parikh, and Yi-Feng Wu, "AlGaN / GaN HEMTs-An overview of device operator and applicat ions," Proc.IEEE, vol.90, No.6, pp.1022 -1031, 2002.
- Non-Patent Document 2 2001 Electronics Letters (Electronics Letters vol.37 p.196-197), Li, etc.
- Patent Document 1 Japanese Patent Application Laid-Open No. 2000-3919
- FIG. 19 shows the results of a trial production of an HJFET having the structure of FIG. 17 without the electric field control electrode, and evaluating the relationship between the thickness of the surface protective film SIN, the amount of Collabs, and the gate breakdown voltage.
- circles correspond to Collabs
- triangles correspond to gate breakdown voltage.
- the collapse amount can be reduced.
- the amount of Collabs is 60% or more, but when the SiN film thickness is 100 nm, the amount of Collabs is 10%. % Or less.
- the SiN film is made thicker, the surface negative charges are canceled, and The electric field concentration between the drains becomes remarkable, and the gate breakdown voltage decreases. That is, there is a trade-off between Collabs and gate breakdown voltage.
- the reliability of the insulating film immediately below the electric field control electrode deteriorates due to deterioration with time of the film quality. In other words, there is a trade-off in terms of reliability and reliability.
- HJFE composed of I II group nitride semiconductors including GaN
- the present invention has been made in view of the above circumstances, and an object of the present invention is to provide a transistor having excellent Collabs and gate breakdown voltage balance. Another object of the present invention is to provide a transistor having excellent reliability and high-frequency characteristics in addition to the balance between the performance of the Collabs and the gate withstand voltage.
- the negative polarization charge generated on the A 1 GaN surface has a large effect on the FET characteristics due to the electrical properties of the protective film (passivation film) deposited thereon.
- the protective film passivation film
- a large negative fixed charge is present on the surface, a large gate withstand voltage can be obtained, but the maximum drain current during AC operation tends to deteriorate compared to DC operation.
- the amount of negative charge on the surface is small, the gate breakdown voltage is small, but the deterioration of the maximum drain current during AC operation is also small.
- the operation of the FET is governed by this trade-off relationship.However, in the A 1 G a NZG a N hetero structure, a negative charge of the order of 1 ⁇ 10 13 / cm 2 is generated on the surface, so that Depending on the quality of the passivation, the trade-off relationship described above becomes very pronounced. It is not uncommon for the withstand voltage to vary by more than an order of magnitude due to differences in surface passivation conditions. Such a large change is a phenomenon not seen in the GaAs FET. Conversely, GaN-based FETs are devices that are extremely sensitive to surface conditions, and in order to stably obtain high performance in terms of electrical characteristics at high yields, pay close attention to controlling the surface passivation film. Need to pay.
- the present inventor has studied from such a viewpoint, and has made an element electrode structure including an electric field control electrode, and a protective film under the electric field control electrode with a specific material, a specific structure, As a result, it has been found that the balance of performance in the above-mentioned trade-off can be effectively improved by these synergistic effects. Furthermore, it has been found that in the configuration of the present invention, since the electric field control electrode can be independently controlled, it is possible to effectively reduce the Collabs, and furthermore, to realize a very excellent drainage ratio in which the decrease in the gain can be suppressed. The present invention has been made based on such new findings.
- a group III nitride semiconductor layer structure including a heterojunction, a source electrode and a drain electrode separately formed on the semiconductor layer structure, and a source electrode and a drain electrode And a gate electrode disposed between the gate electrode and the drain electrode.
- An electric field control electrode is formed above the group III nitride semiconductor layer structure via an insulating film in a region between the gate electrode and the drain electrode.
- the insulating film is a laminated film including a first insulating film containing silicon and nitrogen as constituent elements, and a second insulating film having a lower dielectric constant than the first insulating film. Field effect transistor is provided.
- an electric field control electrode is provided, and the laminated film having the above structure is formed between the electric field control electrode and the surface of the semiconductor layer structure.
- the present invention provides a second insulating film for reducing the capacitance immediately below the electric field control electrode, while providing the first insulating film for reducing the influence of surface negative charges:
- the effect of the surface negative charge is reduced by the action of the insulating film, but the gate insulating voltage is improved by a second insulating film having a lower relative dielectric constant than the first insulating film, for example, a film containing no nitrogen.
- the deterioration of the insulating film with time and the increase in capacitance in the region under the electric field control electrode can be effectively suppressed, and a transistor having excellent reliability and high-frequency gain can be obtained.
- the first insulating film may be formed in contact with the surface of the group III nitride semiconductor layer structure, and the second insulating film may be stacked on the first insulating film. it can. By doing so, the improvement of Collabs becomes more remarkable.
- the thickness of the first insulating film is preferably 150 nm or less, more preferably 100 nm or less. By doing so, the capacitance below the electric field control electrode can be reliably reduced, and the high-frequency gain is improved.
- the relative dielectric constant of the second insulating film may be set to 3.5 or less. By doing so, the capacitance below the electric field control electrode can be reduced, and the gain can be further improved.
- a structure may be provided in which a third insulating film containing silicon and nitrogen as constituent elements is further provided on the second insulating film.
- a configuration in which the insulating film composed of a laminated film including the first and second insulating films is provided separately from the gate electrode, and the second insulating film is provided in the separated portion It can be. This can significantly improve the performance balance between the Collabs and the gate breakdown voltage.
- a group III nitride semiconductor layer structure including a heterojunction, a source electrode and a drain electrode formed separately on the semiconductor layer structure, and disposed between the source electrode and the drain electrode
- An electric field control electrode is formed above a group III nitride semiconductor layer structure via an insulating film in a region between the gate electrode and the drain electrode;
- a field-effect transistor characterized by containing silicon and nitrogen as constituent elements.
- a Group III nitride semiconductor layer structure including a heterojunction; A source electrode and a drain electrode formed separately on the semiconductor layer structure; and a gate electrode disposed between the source electrode and the drain electrode.
- an electric field control electrode is formed above the group III nitride semiconductor layer structure via an insulating film, and the insulating film is an insulating film containing silicon, oxygen and carbon as constituent elements. Is provided.
- the balance between the collapse and the gate breakdown voltage is significantly improved by the synergistic action of the electric field control electrode and the insulating film thereunder.
- the compound may further contain oxygen, carbon, or the like as a constituent element.
- the material of the insulating film contains oxygen and carbon as constituent elements in addition to silicon and nitrogen, the internal stress in the film is remarkably reduced as compared with SiN or the like. For this reason, it is possible to effectively suppress the deterioration of the film quality of the insulating film located in the region immediately below the electric field control electrode while realizing relatively good Collabs and gate withstand voltage.
- the dielectric constant is lower than that of SiN, the capacitance generated in a region below the electric field control electrode can be reduced. As described above, according to the present invention, a transistor having excellent reliability and high-frequency gain can be obtained.
- a group III nitride semiconductor layer structure including a heterojunction, a source electrode and a drain electrode separately formed on the semiconductor layer structure, and a source electrode and a drain electrode And a gate electrode disposed between the gate electrode and the drain electrode.
- An electric field control electrode is formed above the group III nitride semiconductor layer structure via an insulating film in a region between the gate electrode and the drain electrode.
- the insulating film is characterized in that the gate electrode side is made of an insulating material not containing nitrogen as a constituent element, and the drain electrode side is made of an insulating material containing silicon and nitrogen as constituent elements.
- the insulating material provided on the drain electrode side of the insulating film may have a configuration including oxygen and / or carbon as a constituent element in addition to silicon and nitrogen.
- the insulating film is made of a material having a relatively low dielectric constant that does not contain nitrogen on the gate electrode side, it is made up of an electric field control electrode, a semiconductor layer structure, and an insulating film therebetween. The required capacity can be reduced. As a result, a transistor having an excellent performance balance between the gate breakdown voltage, the reliability, and the high-frequency gain can be obtained.
- a compound containing silicon, nitrogen and oxygen as constituent elements, for example, SiN is formed, so that a decrease in performance due to negative surface charges can be reduced.
- a group III nitride semiconductor layer structure including a heterojunction, a source electrode and a drain electrode formed separately on the semiconductor layer structure, and between the source electrode and the drain electrode
- An electric field control electrode is formed above a group III nitride semiconductor layer structure via an insulating film in a region between the gate electrode and the drain electrode.
- a field effect transistor is provided, wherein the relative permittivity of the insulating film is 3.5 or less.
- an electric field control electrode is provided, and the low dielectric constant film having the above configuration is formed between the electric field control electrode and the surface of the semiconductor layer structure. Since the low dielectric constant film is formed in the region directly below the electric field control electrode, it is possible to avoid applying a high voltage to the insulating film located in this region. As a result, the deterioration with time of the film quality of the insulating film under the electric field control electrode is effectively suppressed, and the reliability of the element is remarkably improved. In addition, by using a low dielectric constant film, the capacitance formed by the electric field control electrode, the semiconductor layer structure, and the insulating film therebetween can be reduced, so that the high frequency gain is also improved.
- the insulating film having a relative dielectric constant of 3.5 or less in the present invention may be a single layer film or a laminated film, and the average value of the relative dielectric constant may be 3.5 or less.
- the group 11 nitride semiconductor layer structure is, for example, In XG a 1-xN (0 ⁇ X ⁇ 1) And a channel layer made of A 1 yG a 1-yN (0 ⁇ y ⁇ 1).
- the stacking order of the channel layer and the electron supply layer is arbitrary.
- An intermediate layer or a cap layer may be appropriately provided on this semiconductor layer structure.
- a contact layer may be provided between the source electrode and the surface of the group III nitride semiconductor layer structure and between the drain electrode and the surface of the group III nitride semiconductor layer structure.
- the structure including the contact layer is called a so-called wide recess structure.
- the electric field concentration at the drain-side end of the gate electrode can be more effectively dispersed and reduced by the synergistic effect of the electric field control electrode and the insulating film structure immediately below the electric field control electrode.
- a recess structure a multi-stage recess may be used.
- the electric field control electrode may be configured to extend to an upper portion of the contact layer. In this way, the electric field concentration on the drain side can be reduced.
- the electric field concentration at the end of the drain electrode due to the overlap with the drain electrode becomes a problem.
- the contact layer is made of an undoped A 1 GN layer, that is, an A 1 GaN layer that is not intentionally doped, the electric field concentration at the end of the drain electrode can be significantly reduced.
- the group III nitride semiconductor layer structure includes a channel layer composed of I nxGal- xN (0 ⁇ x ⁇ 1), an electron supply layer composed of A 1 yGal-yN (0 ⁇ y ⁇ 1), and a G layer.
- the structure may be such that a cap layer made of aN is laminated in this order.
- the effective Schottky height can be increased, and a higher gate breakdown voltage can be realized. That is, a further excellent gate breakdown voltage can be obtained by the synergistic action of the electric field control electrode, the laminated film immediately below the electric field control electrode, and the GaN cap layer according to the present embodiment.
- the distance between the gate electrode and the drain electrode can be longer than the distance between the gate electrode and the source electrode. This is a so-called offset structure, which more effectively distributes the electric field concentration at the drain side edge of the gate electrode. Can be scattered and relaxed. There is also a manufacturing advantage that the electric field control electrode can be easily formed.
- the electric field control electrode can be configured to be independently controllable with respect to the gate electrode. That is, different electric potentials can be applied to the electric field control electrode and the gate electrode. With such a structure, the field-effect transistor can be driven under optimal conditions.
- the field-effect transistor of the present invention can simultaneously suppress Collabs and achieve high gate withstand voltage. This greatly improves the output characteristics during high-voltage large-signal operation.
- FIG. 1 is a diagram illustrating a structure of a transistor according to an example.
- FIG. 2 is a diagram illustrating the structure of the transistor according to the example.
- FIG. 3 is a diagram illustrating the structure of the transistor according to the example.
- FIG. 4 is a diagram illustrating the structure of the transistor according to the example.
- FIG. 5 is a diagram illustrating the structure of the transistor according to the example.
- FIG. 6 is a diagram illustrating the structure of the transistor according to the example.
- FIG. 7 is a diagram illustrating the structure of the transistor according to the example.
- FIG. 8 is a diagram illustrating the structure of the transistor according to the example.
- FIG. 9 is a diagram illustrating the structure of the transistor according to the example.
- FIG. 10 is a diagram illustrating the structure of the transistor according to the example.
- FIG. 11 is a diagram illustrating the structure of the transistor according to the example.
- FIG. 12 is a diagram illustrating the structure of the transistor according to the example.
- FIG. 13 is a diagram illustrating the structure of the transistor according to the example.
- FIG. 14 is a diagram illustrating the structure of the transistor according to the example.
- FIG. 15 is a diagram illustrating the structure of the transistor according to the example.
- FIG. 16 is a diagram illustrating the structure of the transistor according to the example.
- FIG. 17 is a diagram showing a structure of a conventional transistor.
- FIG. 18 is a diagram showing a structure of a conventional transistor.
- FIG. 19 is a diagram for explaining the gate breakdown voltage and the trade-off of Collabs.
- FIG. 20 is a diagram for explaining gate breakdown voltage and trade-off of Collabs.
- FIG. 21 is a diagram illustrating the method of manufacturing the transistor according to the example.
- FIG. 22 is a diagram illustrating the method of manufacturing the transistor according to the example.
- FIG. 23 is a diagram illustrating the method of manufacturing the transistor according to the example.
- FIG. 24 is a diagram illustrating the method of manufacturing the transistor according to the example.
- FIG. 25 is a diagram illustrating the method of manufacturing the transistor according to the example.
- FIG. 26 is a diagram illustrating the method of manufacturing the transistor according to the example.
- FIG. 27 is a diagram illustrating the method of manufacturing the transistor according to the example.
- FIG. 28 is a view for explaining the film thickness that can be formed from SiO 2.
- FIG. 29 is a diagram showing the relationship between the gate breakdown voltage and the change in the Collabs current.
- FIG. 30 is a diagram showing the relationship between the gate breakdown voltage and the change in the Collaves current.
- FIG. 31 is a diagram showing the relationship between the thickness of the insulating film and the gain.
- FIG. 1 shows a cross-sectional structure of the HJFET of this embodiment.
- This HJFET is formed on a substrate 10 such as SiC.
- a buffer layer 11 made of a semiconductor layer is formed.
- G a N channel layer on this buffer layer 1 1 1 2 is formed.
- An A 1 GaN electron supply layer 13 is formed on the channel layer.
- On this electron supply layer there are a source electrode 1 and a drain electrode 3 that have an ohmic contact, and a gate electrode 2 that has an electric field control electrode 5 and has a Schottky contact is provided between them.
- the surface of the electron supply layer 13 is covered with a SiO 2 film 21, and a SiO 2 film 22 is further provided thereon.
- the S i N film 2 1 and S i 0 2 film 2 2 is provided immediately below the field control electrode 5.
- a semiconductor is grown on a substrate 10 made of SiC by, for example, a molecular beam epitaxy (MBE) growth method.
- MBE molecular beam epitaxy
- a buffer layer 11 composed of AND A 1 N, an undoped GaN channel layer 12 (film thickness 2 zm), and an AND A 1 ( ) . 2 G a. . 8 consisting N
- a 1 G aN electron supply layer 1 3 is a semiconductor layer structure formed by stacking is obtained (FIG. 2 1 (a)).
- a part of the epitaxial layer structure is removed by etching until the GaN channel layer 12 is exposed, thereby forming an element isolation mesa (not shown).
- a source electrode 1 and a drain electrode 3 are formed by evaporating a metal such as Ti / A 1 on the A 1 GaN electron supply layer 13, and annealing is performed at 65 ° C. This makes ohmic contact (Fig. 21 (b)).
- a SiN film 21 film thickness 50 nm
- the S i ⁇ 2 film 22 thickness 1 5 0 nm
- the gate electrode 2 and the electric field control Although the example in which the electrodes 5 are formed at the same time has been described, they may be formed in separate steps (a step of forming a resist having an opening and a step of forming an electrode in the opening is performed separately). In this case, the interval between the gate electrode 2 and the electric field control electrode 5 can be formed at a shorter interval.
- the electric field applied to the drain-side end of the gate electrode is reduced by the action of the electric field control electrode, thereby improving the gate breakdown voltage.
- the surface potential can be modulated by the electric field control electrode, so that the response speed of the surface trap is increased to suppress Collabs. That is, the balance between the Collabs, the gate breakdown voltage and the gain can be remarkably improved. Further, even when the surface state fluctuates due to variations in the manufacturing process or the like, such good performance can be stably realized.
- the electric field control electrode in this embodiment can be controlled independently of the gate electrode.
- the response of the surface trap can be suppressed by fixing the surface potential
- the Collabs can be more effectively suppressed than in the case where the electric field control electrode is set to the same potential as the gate electrode and the surface potential is modulated.
- the effect of independently controlling this electric field control electrode is remarkable in a group II nitride semiconductor device in which the influence of surface negative charge is a major problem as in the present invention.
- the effect of suppressing Collabs will be sufficient Yes, preferably 0.5 m or more. Further, it is preferable that the end of the electric field control electrode does not overlap with the drain electrode. The larger the size of the electric field control electrode is, the higher the effect of suppressing the Collabs is, but the end of the electric field control electrode on the drain electrode side is the distance between the gate electrode and the drain electrode. If the distance exceeds 70% of the distance between the gate electrode and the gate electrode, the gate breakdown voltage tends to decrease because the gate breakdown voltage is determined by the concentration of the electric field between the electric field control electrode and the drain electrode. For this reason, the dimension of the electric field control electrode is preferably set to 70% or less of the distance between the gate electrode and the drain electrode.
- an example was shown in which an SiO 2 film was formed as an upper layer of the surface protective film.
- a low dielectric constant film having a relative dielectric constant of 4 or less should be used. Is more preferred.
- Such low dielectric constant materials include S i OC (sometimes called S i ⁇ CH), BCB (benzocyclobutene), FSG (flouroSi 1 icate glass: Si OF), HSQ (hydrogen-Si lsesquioxane), Examples include MSQ (methyl-Silsesquioxane), an organic polymer, and a material obtained by forming a porous material thereof.
- the insulating film formed on the A 1 GaN electron supply layer 13 is replaced with a SiN film 21, 3 10 2 film. It has a three-layer structure in which the 22 ⁇ and SiN films 21 are stacked in this order.
- the layer structure of the semiconductor under the gate electrode is the same as that of the embodiment described above.
- the top layer of the insulating film is not the Si 2 film 22 but the SiN film 21, so that it is easy to stably form the resist in the manufacturing process of this element, and the yield is low. improves.
- the insulating film provided on the uppermost portion of the insulating film is also 150 nm or less, more preferably 100 nm or less, from the viewpoint of film reliability, similarly to the SiN film provided on the lowermost layer. It is more preferable that the film thickness be as thin as possible.
- FIG. 3 shows a cross-sectional structure of the HJFET of this embodiment.
- This HJ FET is It is formed on a substrate 10 such as SiC.
- a buffer layer 11 made of a semiconductor layer is formed.
- the GaN channel layer 12 is formed on the puffer layer 11.
- a 10 & electron supply layer 13 are formed.
- On the electron supply layer there are a source electrode 1 and a drain electrode 3 which are in ohmic contact, between which an electric field control electrode 5 and a gate electrode 2 which is in Schottky contact are provided.
- the surface of the electron supply layer 13 is covered with a SiN film 21, and the SiN film 21 is provided immediately below the electric field control electrode 5.
- the above HJ FET is formed as follows. First, a semiconductor is grown on a substrate 10 made of SiC by, for example, molecular beam epitaxy.
- the semiconductor layer formed in this manner includes, in order from the substrate side, a buffer layer 11 (film thickness 20 nm) made of undoped A 1 N, an undoped GaN channel layer 12 (film thickness 2 m), and an undoped A 1 0. a 2 G a Q. consisting 8 N a 1 G aN electron supply layer 1 3 (film thickness 2 5 nm).
- a part of the epitaxial layer structure is removed by etching until the GaN channel layer 12 is exposed, thereby forming an element isolation mesa.
- a source electrode 1 and a drain electrode 3 are formed by depositing a metal such as Ti / A 1 on the electron supply layer 13 and then annealing at 650 ° C. Make ohmic contact.
- an SiN film 21 (film thickness 150 nm) is formed by a plasma CVD method or the like.
- a metal such as NiZAu is deposited on the A 1 A & 1 ⁇ electron supply layer 13 exposed by etching away a part of the SiN film 21 1 to form a Schottky-contact gate electrode 2.
- an electric field control electrode 5 is formed.
- the HJFET shown in FIG. 3 is manufactured.
- the surface protection film is the SiN film 21. Since the SIN film 21 has a large internal stress, it cannot be formed thick, and the effect of suppressing Collabs decreases as the film thickness decreases.
- the electric field control electrode 5 is provided between the gate electrode 2 and the drain electrode 3, and this electric field control electrode 5 is provided. Because the surface potential can be modulated by 5, collabs can be effectively suppressed. Further, by controlling the electric field control electrode 5 independently of the gate electrode 2, it is possible to more effectively suppress Collabs.
- the electric field control electrode 5 may have the same potential as the source electrode 1, and in this case, the device configuration can be simplified as compared with the case of independent control.
- the configuration in which the electric field control electrode of the present embodiment can be controlled independently enables a transistor having a high gain and excellent high-frequency characteristics even if the thickness of the surface protective film is smaller than that of the field plate electrode described in Non-Patent Document 2. realizable.
- FIG. 29 and FIG. 30 are diagrams comparing the gate breakdown voltage and the performance balance of Collabs between the transistor according to the present embodiment and the conventional transistor.
- the prototype devices of Gr.l to Gr.3 are the same except for the presence or absence of the electric field control electrode and the method of applying the potential to the electric field control electrode.
- Electric field control electrode Yes (electric potential is fixed at 0 V)
- Electric field control electrode dimensions 0.5 m
- Protective film Five points where the thickness of the SiN film was 10, 400, 90, and 120 nm were evaluated.
- Electric field control electrode None Protective film: Five points of the device having a sine film of 10, 40, 60, 90 and 120 nm were evaluated.
- Electric field control electrode Yes (electric potential is fixed at 0 V)
- Electric field control electrode dimensions 0.5 im
- Protective film Five points where the thickness of the SiN film was 10, 40, 60, 90, and 120 nm were evaluated.
- FIG. 29 is a characteristic diagram of the Gr.1 and Gr.2 devices
- FIG. 30 is a characteristic diagram of the Gr.3 and Gr.2 devices.
- the device having the configuration according to the present invention can achieve both high gate breakdown voltage and suppression of Collabs.
- Collabs the larger the size of the electric field control electrode, the greater its suppression effect.
- the dimension of the electric-field control electrode is 0.3 m or more, the effect of suppressing the Collabs is sufficiently obtained, and preferably, it is 0.5 m or more.
- the end of the electric field control electrode is located at a position that does not overlap with the drain electrode. The larger the size of the electric field control electrode, the greater the effect of suppressing the Collabs.
- the end of the electric field control electrode on the drain electrode side is the distance between the gate electrode and the drain electrode (from the end of the gate electrode on the drain electrode side to the gate of the drain electrode). If it exceeds 70% of the distance between the electrodes, the gate breakdown voltage tends to decrease because the gate breakdown voltage is determined by the electric field concentration between the electric field control electrode and the drain electrode. Therefore, preferably, the dimension of the electric field control electrode is set to 70% or less of the distance between the gate electrode and the drain electrode.
- FIG. 31 shows the relationship between the gain and the thickness of the SiN film.
- a transistor having a field plate electrode described in Non-Patent Document 2 (FIG. 18)
- a transistor having a configuration of this embodiment having an electric field control electrode FIG.
- the transistor having the structure of this embodiment can achieve high gate breakdown voltage, suppression of Collabs, and high gain.
- the thickness of the SiN film 21 in the configuration of the present embodiment is preferably 150 nm or less from the viewpoint of film reliability. More preferably, it is 100 nm or less. Further, when the film thickness is smaller than 10 nm, the effect of suppressing Collabs becomes extremely small. Therefore, the film thickness is preferably set to 10 nm or more.
- the dimension of the electric field control electrode 5 (dimension in the direction of the gate drain electrode) is preferably 0.3 m or more. More preferably, it is 0.5 m or more. Further, it is preferable that the end of the electric field control electrode is located at a position that does not overlap with the drain electrode. More preferably, the dimension of the electric field control electrode is set to 70% or less of the distance between the gate electrode and the drain electrode.
- FIG. 4 shows a cross-sectional structure of the HJFET of this embodiment.
- This HJFET is formed on a substrate 10 such as SiC.
- a buffer layer 11 made of a semiconductor layer is formed.
- a GaN channel layer 12 is formed on the buffer layer 11.
- An A 1 GaN electron supply layer 13 is formed on the channel layer.
- On the electron supply layer there are a source electrode 1 and a drain electrode 3 which are in ohmic contact, between which an electric field control electrode 5 and a gate electrode 2 which is in Schottky contact are provided.
- the surface of the electron supply layer 13 is covered with a SiON film 23, and the SiON film 23 is provided directly below the electric field control electrode 5.
- the above HJFET is formed as follows. First, a substrate made of SiC 1
- a semiconductor is grown by, for example, molecular beam epitaxy.
- the semiconductor layer formed in this manner includes, in order from the substrate side, a buffer layer 11 (thickness: 20 nm) made of AND A 1 N and an undoped GaN channel layer 12 (thickness: 2 m), an AND one flop A 1 0. 2 consists G A 1 G a N electron supply layer 1 3 (film thickness 2 5 nm).
- a part of the epitaxial layer structure is removed by etching until the GaN channel layer 12 is exposed, thereby forming an element isolation mesa.
- a source electrode 1 and a drain electrode 3 are formed by evaporating a metal such as TiZA 1 on the A 1 GaN electron supply layer 13, and annealing is performed at 65 0. Make sexual contact.
- a SiON film 23 (film thickness 150 nm) is formed by a plasma CVD method or the like.
- a metal such as NiZAu is deposited on the A1GaN electron supply layer 13 exposed by removing a part of the SiON film 23 by etching to form a Schottky contact gate electrode 2.
- an electric field control electrode is formed.
- the HJFET shown in FIG. 4 is manufactured.
- the surface protection film is a SiON film.
- the internal stress generated in the SiON film is smaller than that of the SiON film.
- FIG. 28 is a diagram showing the results of investigation of the film thickness that can be grown without cracking when a SiON film and a SiN film were formed by the plasma CVD method.
- the oxygen composition ratio of SiO was changed, and the corresponding growthable film thickness was examined. It can be seen that increasing the oxygen composition ratio increases the film thickness that can be grown. That is, according to the present embodiment, the insulating film can be formed thicker than when the SIN film is formed below the electric field control electrode, and the high-frequency gain can be improved by reducing the capacitance below the electric field control electrode. it can.
- the SiON film under the electric field control electrode has a thickness of 200 nm or more. Since the oxygen composition ratio corresponding to a growth thickness of 200 nm is 5% (on a molar basis), it is preferable to use an oxygen composition ratio of 5% or more when a SiON film is used.
- the SiON film of this embodiment preferably has a refractive index in the range of 1.65 or more and 2.05 or less.
- the dimensions of the electric field control electrode are preferably equal to or more than the above. More preferably, it is set to 0.5 tim or more. Further, it is preferable that the end of the electric field control electrode is located at a position not overlapping with the drain electrode. More preferably, the dimension of the electric field control electrode is set to 70% or less of the distance between the gate electrode and the drain electrode.
- the protective film was Si ON, but the present invention is not limited to this, and Si CN, Si OCN, or the like may be used.
- FIG. 5 shows a cross-sectional structure of the HJFET of this embodiment.
- the HJFET is formed on a substrate 10 such as SiC.
- a buffer layer 11 made of a semiconductor layer is formed.
- the GaN channel layer 12 is formed on the buffer layer 11.
- An A 1 GaN electron supply layer 13 is formed on the channel layer.
- this electron supply layer there are a source electrode 1 and a drain electrode 3 which are in ohmic contact, and an electric field control electrode 5 and a gate electrode 2 which is in Schottky contact are provided therebetween.
- the surface of the electron supply layer 13 is covered with a Si OC film 24, and the Si OC film 24 is provided immediately below the electric field control electrode 5.
- the above HJFET is formed as follows. First, a substrate made of SiC 1
- a semiconductor is grown by, for example, molecular beam epitaxy.
- a buffer layer 11 film thickness 20 nm
- an AND GaN channel layer 12 film thickness 2 m
- an AND A 1. 2 G a. . 8 consisting N
- a 1 G a N electron supply layer 1 3 semiconductor layer structure was product layer.
- a part of the epitaxial layer structure is removed by etching until the GaN channel layer 12 is exposed, thereby forming an element isolation mesa.
- a metal such as T i / A 1 is deposited on the A 1 G a N electron supply layer l 3.
- a source electrode 1 and a drain electrode 3 and anneal at 650 ° C. to make ohmic contact.
- an Si OC film 24 (200 nm thick) is formed by a plasma CVD method.
- a metal such as Ni / Au is deposited on the A 1 GaN electron supply layer 13 exposed by etching away a part of the S i OC film 24 to form a gate electrode 2 of Schottky contact.
- an electric field control electrode 5 is formed.
- the HJFET shown in FIG. 5 is manufactured.
- This embodiment has a structure in which a surface protection film is a SiOC film.
- the S i OC film has a smaller stress than the S i N film, and does not affect the piezoelectric polarization of the Al G aN layer even when the film thickness is increased. For this reason, the film does not have the effect of suppressing the Collabs, but the Collabs is suppressed by controlling the surface charge with the electric field control electrode.
- the dimension of the electric field control electrode is preferably 0.3 xm or more, more preferably 0.5 ⁇ m or more. It is preferable that the end of the electric field control electrode does not overlap with the drain electrode. More preferably, the dimension of the electric field control electrode is 70% or less of the distance between the gate electrode and the drain electrode.
- the surface protective film is a SiOC film having a relative dielectric constant of about 2.5
- another low dielectric constant film (with a relative dielectric constant of 3.5 or less)
- the stress (internal stress) generated in the film is small.
- Such materials include Si ⁇ C (sometimes referred to as Si O CH), BCB (benzocyclobutene), FSG (flouroSilicate glass: SiOF), HSQ (hydrogen-Silsesquioxane)> MSQOnethy, Silsesquioxane, and organic Examples thereof include a polymer or a material obtained by making these porous. In addition, alumina or the like may be used.
- a 1 N having a thickness equal to or less than the critical thickness as the surface protective film, an effect of increasing heat radiation from the element surface can be obtained in addition to the effect of the electric field control electrode. Similar effects can be obtained in a multilayer film structure combining these films.
- the structure of the protective film has a single-layer structure in the vicinity of the gate electrode, and has a two-layer structure in a region far from the gate electrode.
- the layer structure of the semiconductor under the gate electrode is the same as that of the embodiment described above, and the description is omitted.
- a gate electrode 2 form a form and separate the S i N film 2 1 and S i 0 2 laminated film, the bottom of the field control electrode 5, S i 0 2 film 22 first monolayer And a second region, which is located on the drain side of this region and on which the SiO 2 film 22 is stacked on the SiO 2 film 21, is formed.
- a SiO 2 film effective for improving the withstand voltage is provided on the gate electrode side, and a SiO 2 film having an effect of suppressing Collabs is provided on the drain electrode side. Therefore, it is possible to realize a field effect transistor in which the gate breakdown voltage is improved and the Collabs is suppressed.
- the electric field control electrode can be controlled independently of the gate electrode, it is possible to make an adjustment so as to further suppress the Collabs. Further, by fixing the electric field control electrode to a predetermined potential (for example, by setting the same potential as the source electrode), a decrease in gain can be suppressed.
- the gate electrode side S i 0 2 film and the drain electrode side shows an example in which a laminated film of S i N film and S i 0 2 film, further Alternatively, a configuration in which a SiN film is provided on these insulating films may be employed.
- a semiconductor is grown on a substrate 10 made of SiC by, for example, a molecular beam epitaxy (MBE) growth method. More, in this order from the substrate side this, the buffer layer 1 1 of undoped A 1 N (thickness 20 nm), G a N-channel layer 1 2 AND Ichipu (thickness 2 rn), an undoped A 1 0. 2 G a. . Consisting 8 N A 1 G aN electron supply layer 1 3 (thickness 2 5 nm) to obtain the the semiconductor layer structure stack (FIG. 24 (a)).
- MBE molecular beam epitaxy
- a part of the epitaxial layer structure is removed by etching until the GaN channel layer 12 is exposed, thereby forming an element isolation mesa (not shown).
- a metal such as T i / A 1 is deposited on the A 1 G aN electron supply layer 13.
- a source electrode 1 and a drain electrode 3 are formed, and an ohmic contact is made by annealing at 65 ° C. (FIG. 24B).
- an SiN film 21 film thickness 50 nm
- FIG. 25 (c) is formed by a plasma CVD method or the like.
- an opening for exposing the A 1 GaN electron supply layer 13 is provided by etching away a part of the SiN film 21 (FIG. 25D).
- an opening for exposing the AlGaN electron supply layer 13 is provided by removing a part of the SiO 2 film 22 by etching (FIG. 26 (f)).
- a gate metal 31 such as NiZAu is deposited on the GaN electron supply layer 13 using a photoresist 30 to form a Schottky contact gate electrode 2 and an electric field control electrode 5 simultaneously.
- the HJFET shown in FIG. 4 is manufactured.
- the transistor shown in Fig. 4 can be manufactured stably.
- a separate process (a photoresist 30 is provided every time each electrode is formed, and each electrode is formed separately) May be formed.
- the gate electrode 2 and the electric field control electrode 5 can be formed with higher controllability, and for example, the interval between both electrodes can be formed very narrow.
- FIG. 7 shows a cross-sectional structure of the HJFET of this embodiment. This H J FET is
- a substrate 10 such as SiC.
- a buffer layer 11 made of a semiconductor layer is formed.
- the GaN channel layer 12 is formed on the puffer layer 11.
- An A 10 & 1 ⁇ electron supply layer 13 is formed on the channel layer.
- On the electron supply layer there are a source electrode 1 and a drain electrode 3 which have an ohmic contact, and a gate electrode 2 which has a Schottky contact with the electron supply layer 13 is provided therebetween.
- an insulating film is provided between the gate electrode 2 and the drain electrode 3, and the electric field control electrode 5 is provided on the insulating film.
- this insulating film has a Si electrode on the gate electrode side. 0 is 2 film, the drain electrode side is composed of S i N film.
- the configuration of the insulating film is a SiO 2 film effective for improving the withstand voltage on the gate electrode side, and a Si N film effective for suppressing Collabs on the drain electrode side.
- the suppression of the Collabs is also possible by the electric field control electrode.
- by controlling the electric field control electrode independently of the gate electrode further suppression of the Collabs can be achieved.
- by fixing the electric field control electrode at a predetermined potential a decrease in gain can be effectively suppressed. Therefore, with the configuration of the present embodiment, it is possible to realize a field effect transistor having a high gate withstand voltage, a low influence of the collapse, and an excellent high frequency characteristic.
- the S I_ ⁇ 2 film for the gate electrode side gate - may be a valid film for improving preparative breakdown voltage, preferably it Re insulating film der containing no N.
- SiN is provided on the drain electrode side, a SiON film or the like may be provided. In this case, the film thickness can be made thicker than that of SiN, which is effective for improving the gain.
- This embodiment is an example of HJFET adopting a wide recess structure. Hereinafter, description will be made with reference to FIG.
- This HJFET is formed on a substrate 10 such as SiC.
- the source electrode 1 and the drain electrode 3 are formed on the GaN contact layer 14, respectively.
- a buffer layer 11 made of a semiconductor layer is formed on a substrate 10 c.
- a GaN channel layer 12 is formed on the buffer layer 11.
- An A 1 GaN electron supply layer 13 is formed on the channel layer.
- a contact layer 14 is provided on the electron supply layer 13, and a source electrode 1 and a drain electrode 3, which are in uniform contact with the contact layer, are provided. A part of the contact layer between the source electrode 1 and the drain electrode 3 is partially removed, and a gate electrode 2 having a Schottky contact is provided in contact with the exposed A 1 GaN electron supply layer 13. I have.
- S i N film 2 Surface of the electron supply layer 1 3 is covered with S i N film 2 1, further on the upper layer thereof is provided with S i 0 2 film 2 2. Furthermore, Its S i 0 2 2 2 film, the electric field control electrode 5 is provided between the gate electrode 2 and the drain electrode 3 ing.
- This embodiment has a configuration in which a contact layer is added to the first embodiment.
- the contact resistance can be further reduced.
- the electric field distribution at the end on the drain side of the gate electrode 2 changes, so that a more excellent electric field relaxation effect can be obtained together with the function of the electric field control electrode 5.
- the dimension of the electric field control electrode is preferably 0.3 m or more. More preferably, it is 0.5 zm or more. Further, it is preferable that the end of the electric field control electrode be located so as not to overlap with the contact layer. More preferably, the dimension of the electric field control electrode is set at a
- the insulating film provided on the electron supply layer 13 is formed of the SiN film 21 and the S
- This embodiment is an example of HJFET adopting a wide recess structure. Hereinafter, description will be made with reference to FIG.
- This HJFET is formed on a substrate 10 such as SiC.
- the source electrode 1 and the drain electrode 3 are formed on the GaN contact layer 14, respectively.
- a buffer layer 11 made of a semiconductor layer is formed on a substrate 10:
- a GaN channel layer 12 is formed on the buffer layer 11.
- An A 1 GaN electron supply layer 13 is formed on the channel layer.
- a contact layer 14 is provided on the electron supply layer 13, and a source electrode 1 and a drain electrode 3 in ohmic contact with the contact layer are provided.
- a part of the contact layer between the source electrode 1 and the drain electrode 3 is partially removed, and a gate electrode 2 with Schottky contact is provided in contact with the exposed A 1 GaN electron supply layer 13. .
- the element surface is covered with a SiO 2 film 23, and this SiO 2 film 2 On 3, an electric field control electrode 5 is provided between the gate electrode 2 and the drain electrode 3.
- This embodiment has a configuration in which a contact layer is added to the fourth embodiment, and in addition to the effects described in the fourth embodiment, the contact resistance can be further reduced.
- the electric field distribution at the end on the drain side of the gate electrode 2 changes, so that a more excellent electric field relaxation effect can be obtained together with the function of the electric field control electrode 5.
- the SiON film of this embodiment preferably has a refractive index in the range from 1.65 to 2.05.
- the dimension of the electric field control electrode is preferably 0.3 m or more. More preferably, it is 0.5 ⁇ m or more. Further, it is preferable that the end of the electric field control electrode is located at a position that does not overlap with the contact layer. More preferably, the dimension of the electric field control electrode is set to 70% or less of the distance between the gate electrode and the contact layer.
- the structure of the insulating film is the SiON film 23.
- the insulating film may be a SiON film.
- the film thickness is preferably set to 150 nm or less.
- the insulating film may have a structure in which the gate electrode side and the drain electrode side have different structures.
- This embodiment has a configuration in which a contact layer 14 is added to the fifth embodiment.
- the contact resistance can be further reduced.
- the electric field distribution at the end on the drain side of the gate electrode 2 changes, so that a more excellent electric field relaxation effect can be obtained together with the function of the electric field control electrode 5.
- the dimension of the electric field control electrode is preferably 0.3 m or more. More preferably, it is above. Also, the end of the electric field control electrode Is preferably a position that does not overlap with the contact layer. More preferably, the dimension of the electric field control electrode is set to 70% or less of the distance between the gate electrode and the contact layer.
- FIG. 11 shows a cross-sectional structure of the HJFET of this embodiment. This H J F E T
- a substrate 10 such as SiC.
- a buffer layer 11 made of a semiconductor layer is formed.
- a GaN channel layer 12 is formed on the buffer layer 11.
- An A 1 GaN electron supply layer 13 is formed on the channel layer, and a GaN cap layer 15 is formed thereon.
- a source electrode 1 and a drain electrode 3 which have ohmic contact, and a gate electrode 2 which has an electric field control electrode 5 and a Schottky contact between them.
- G a N surface of the cap layer 1 5 is covered by S i N film 2 1, further thereon that provided the S i 0 2 film 2 2.
- the SiO 2 film 21 and the SiO 2 film 22 are provided directly below the electric field control electrode 5.
- This embodiment has a configuration in which a GaN cap layer is added to the uppermost portion of the semiconductor in the first embodiment, and a higher gate breakdown voltage can be realized by increasing the effective Schottky height. That is, an excellent gate breakdown voltage can be obtained by the synergistic action of the electric field control electrode, the laminated film immediately below the electric field control electrode, and the GaN cap layer according to the present embodiment.
- the dimension of the electric field control electrode is not less than 0. More preferably, it is 0.5 m or more. Further, it is preferable that the end of the electric field control electrode is located at a position that does not overlap with the drain electrode. More preferably, the dimension of the electric field control electrode is set to 70% or less of the distance between the gate electrode and the drain electrode.
- FIG. 12 shows a cross-sectional structure of the HJFET of this embodiment.
- a GaN cap layer 15 is formed on the A1 GaN electron supply layer l3.
- a source electrode 1 and a drain electrode 3 which have ohmic contact, an electric field control electrode 5 between them, and a gate electrode 2 which has a Schottky contact.
- the surface of the GaN cap layer 15 is covered with a SiON film 23, and the SiON film 23 is provided immediately below the electric field control electrode 5.
- This embodiment has a configuration in which a GaN cap layer is added to the uppermost portion of the semiconductor in the fourth embodiment, and a higher gate breakdown voltage can be realized by increasing the effective Schottky height. That is, an excellent gate breakdown voltage can be obtained by the synergistic action of the electric field control electrode, the laminated film immediately below the electric field control electrode, and the GaN cap layer according to the present embodiment.
- the SiON film of this embodiment preferably has a refractive index in the range of 1.65 or more and 2.05 or less.
- the size of the electric field control electrode is preferably 0.3 / m or more. More preferably, it is 0.5 m or more. Further, it is preferable that the end of the electric field control electrode does not overlap with the drain electrode. More preferably, the dimension of the electric field control electrode is set to 70% or less of the distance between the gate electrode and the drain electrode.
- the configuration of the insulating film is the SiON film 23.
- the insulating film may be a SiN film.
- the effect of providing the cap layer is the same even when the configuration of the insulating film is different between the gate electrode side and the drain electrode side.
- FIG. 13 shows a cross-sectional structure of the HJFET of this embodiment.
- the HJFET is formed on a substrate 10 such as SiC.
- a buffer layer 11 made of a semiconductor layer is formed.
- the GaN channel layer 12 is formed on the buffer layer 11.
- An A 1 GaN electron supply layer 13 is formed on the channel layer, and a GaN cap layer 15 is formed thereon.
- On the GaN cap layer there are a source electrode 1 and a drain electrode 3 which have ohmic contact, and a gate electrode 2 which has an electric field control electrode 5 and a Schottky contact between them. ing.
- the surface of the GaN cap layer 15 is covered with a SiOC film 24, and the SiOC film 24 is provided directly below the electric field control electrode 5.
- This embodiment has a configuration in which a GaN cap layer is added to the uppermost portion of the semiconductor in the fifth embodiment, and a higher gate breakdown voltage can be realized by increasing the effective Schottky height. That is, an excellent gate breakdown voltage can be obtained by the synergistic action of the electric field control electrode, the laminated film immediately below the electric field control electrode, and the GaN cap layer according to the present embodiment.
- the dimension of the electric field control electrode is not less than 0.3 ⁇ 1. More preferably, it is 0.5 m or more. Further, it is preferable that the end of the electric field control electrode does not overlap with the drain electrode. More preferably, the dimension of the electric field control electrode is set to 70% or less of the distance between the gate electrode and the drain electrode.
- FIG. 14 shows a cross-sectional structure of the HJFET of this embodiment.
- This embodiment relates to a structure in which the contact layer of the eighth embodiment is an AND A 1 GaN and the electric field control electrode is overlapped with the contact layer.
- This HJ FET is formed on a substrate 10 such as SiC.
- a buffer layer 11 made of a semiconductor layer is formed on a substrate 10.
- the GaN channel layer 12 is formed on the buffer layer 11.
- a 1 G above the channel layer a N electron supply layer 13 is formed.
- the gate between the source electrode 1 and the drain electrode 3 is partially removed, and the Schottky contact is made in contact with the exposed A 1 GaN electron supply layer l 3.
- a contact electrode 2 is provided.
- the element surface is covered with a SiN film 21, and a Si 2 film 22 is further provided thereon.
- an electric field control electrode 5 is provided on the SiO 2 film. As shown in the figure, the electric field control electrode 5 may be configured to overlap the AND A 1 GaN layer 16.
- the contact layer is an AND A1GaN layer
- the electric field concentration between the electric field control electrode and the contact layer is moderate. Therefore, even if the electric field control electrode overlaps the contact layer, the gate breakdown voltage does not decrease. As a result, the electric field control electrode can control most surface charges on the surface of the A 1 GaN electron supply layer, which has the effect of more effectively suppressing Collabs.
- the AND A 1 GaN layer 16 is used as the contact layer, the effect of suppressing the electric field concentration near the drain electrode can be obtained.
- the electric field control electrode 5 is extended to the drain side, the electric field concentration near the gate electrode 2 is reduced, but the electric field concentration problem near the drain electrode 3 becomes apparent. According to the configuration of this embodiment, the undoped A 1 GaN layer 16 is interposed between the drain electrode 3 and the electron supply layer 13, so that the electric field concentration near the drain electrode 3 can be effectively reduced. Can be eased.
- This embodiment relates to a structure in which the contact layer of the ninth embodiment is an AND A 1 GaN and the electric field control electrode overlaps with the contact layer.
- FIG. 15 shows a cross-sectional structure of the HJFET of this embodiment.
- This HJFET is formed on a substrate 10 such as SiC.
- a substrate made of a semiconductor layer is placed on the substrate 10.
- the buffer layer 11 is formed.
- a GaN channel layer 12 is formed on the buffer layer 11.
- An A 1 GaN electron supply layer 13 is formed on the channel layer.
- a part of the undoped A 1 GaN layer between the source electrode 1 and the drain electrode 3 is partially removed, and the gate electrode 2 is in Schottky contact with the exposed A 1 GaN supply layer 13.
- the element surface is covered with a SiO 2 film 23, and an electric field control electrode 5 is provided between the gate electrode 2 and the drain electrode 3 on the SiO 2 film 23.
- the contact layer is an undoped A1GaN layer
- the electric field concentration between the electric field control electrode and the contact layer is moderate. Therefore, the gate breakdown voltage does not decrease even if the electric field control electrode overlaps the contact layer. Thereby, the electric field control electrode can control most surface charges on the surface of the A 1 GaN electron supply layer, so that the Collabs can be suppressed more effectively.
- the undoped A 1 GaN layer 16 is used as the contact layer, so that the effect of suppressing the electric field concentration near the drain electrode can be obtained.
- the undoped A 1 GaN layer 16 is interposed between the drain electrode 3 and the electron supply layer 13, so that the electric field concentration near the drain electrode 3 can be effectively reduced. Can be eased.
- FIG. 16 shows a cross-sectional structure of the HJFET of this embodiment.
- This HJFET is formed on a substrate 10 such as SiC.
- a buffer layer 11 made of a semiconductor layer is formed.
- a GaN channel layer 12 is formed on the buffer layer 11.
- An A 1 GaN electron supply layer 13 is formed on the channel layer.
- An undoped A 1 GaN layer 16 is provided on the electron supply layer 13, and a source electrode 1 and a drain electrode 3 which are in ohmic contact with the undoped A 1 GaN layer 16 are provided. Have been.
- a part of the undoped A 1 GaN layer between the source electrode 1 and the drain electrode 3 is partially removed, and the gate electrode 2 is in Schottky contact with the exposed A 1 GaN supply layer 13. Is provided.
- the element surface is covered with a Si OC film 24, and an electric field control electrode 5 is provided on the Si OC film.
- the electric field control electrode 5 may be configured to overlap the undoped A 1 GaN layer 16.
- the contact layer is an AND A1GaN layer
- the electric field concentration between the electric field control electrode and the contact layer is moderate. Therefore, even if the electric field control electrode overlaps the contact layer, the gate breakdown voltage does not decrease. Thereby, the electric field control electrode can control most surface charges on the surface of the A 1 GaN electron supply layer, so that the Collabs can be suppressed more effectively.
- the undoped AlGaN layer 16 is used as the contact layer, so that the effect of suppressing the electric field concentration near the drain electrode can be obtained.-
- the electric field control electrode 5 is extended to the drain side, While the electric field concentration near the electrode 2 is reduced, the problem of the electric field concentration near the drain electrode 3 becomes apparent.
- the AND A 1 GaN layer 16 is interposed between the drain electrode 3 and the electron supply layer 13, the electric field concentration near the drain electrode 3 is reduced. Can be moderated.
- the size of the aluminum composition of the undoped A 1 GaN layer 16 and the A 1 GaN electron supply layer 13 is arbitrary. If these aluminum compositions are equal, they will be composed of the same material, Resistance can be obtained. Also, if the undoped A 1 GaN layer 16 has a higher aluminum composition than the underlying A 1 GaN electron supply layer 13, a carrier is generated at the interface between the two due to the piezo effect, thereby reducing the resistance. Can be achieved.
- SiC silicon carbide
- other dissimilar material substrates such as sapphire, and group III nitride semiconductor substrates such as GaN and AlGaN Etc. may be used.
- the structure of the semiconductor layer under the gate is not limited to the illustrated one, and various embodiments are possible.
- the low dielectric constant film is not limited to those exemplified in the embodiments, and various materials can be used.
- a so-called gate recess structure in which a part of the lower portion of the gate electrode 2 is embedded in the AlGaN electron supply layer 13 can be employed. Thereby, excellent gate withstand voltage can be obtained in combination with the function of the electric field control electrode.
Abstract
Description
Claims
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US10/541,583 US7256432B2 (en) | 2003-01-07 | 2003-12-15 | Field-effect transistor |
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JP2003000842A JP4385206B2 (ja) | 2003-01-07 | 2003-01-07 | 電界効果トランジスタ |
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JP (1) | JP4385206B2 (ja) |
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Also Published As
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CN1757120A (zh) | 2006-04-05 |
JP4385206B2 (ja) | 2009-12-16 |
US7256432B2 (en) | 2007-08-14 |
JP2004214471A (ja) | 2004-07-29 |
CN100573919C (zh) | 2009-12-23 |
US20060043415A1 (en) | 2006-03-02 |
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