JP5200399B2 - Mosトランジスタの製造方法 - Google Patents
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- JP5200399B2 JP5200399B2 JP2007080159A JP2007080159A JP5200399B2 JP 5200399 B2 JP5200399 B2 JP 5200399B2 JP 2007080159 A JP2007080159 A JP 2007080159A JP 2007080159 A JP2007080159 A JP 2007080159A JP 5200399 B2 JP5200399 B2 JP 5200399B2
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- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 239000012535 impurity Substances 0.000 claims description 58
- 125000006850 spacer group Chemical group 0.000 claims description 42
- 239000000758 substrate Substances 0.000 claims description 42
- 238000000151 deposition Methods 0.000 claims description 27
- 230000008021 deposition Effects 0.000 claims description 24
- 229910021332 silicide Inorganic materials 0.000 claims description 18
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 17
- 238000009792 diffusion process Methods 0.000 claims description 10
- 238000010438 heat treatment Methods 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 4
- 239000007943 implant Substances 0.000 claims 1
- 238000002513 implantation Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 89
- 230000015556 catabolic process Effects 0.000 description 20
- 230000008569 process Effects 0.000 description 13
- 230000005684 electric field Effects 0.000 description 11
- 229910017052 cobalt Inorganic materials 0.000 description 10
- 239000010941 cobalt Substances 0.000 description 10
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 10
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 9
- 238000002955 isolation Methods 0.000 description 9
- 229910052698 phosphorus Inorganic materials 0.000 description 9
- 239000011574 phosphorus Substances 0.000 description 9
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 230000007704 transition Effects 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000000470 constituent Substances 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
- H01L29/41783—Raised source or drain electrodes self aligned with the gate
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- H—ELECTRICITY
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
前記絶縁膜を異方性エッチングによりエッチングして、前記ゲート電極と前記堆積型ドレイン層の間隙を前記絶縁膜で埋め込む第2側壁スペーサを形成すると共に、前記第2側壁スペーサのある側と反対側の前記ゲート電極の側壁に第1側壁スペーサを形成する工程と、前記ゲート電極、前記堆積型ドレイン層、前記第1側壁スペーサ、及び前記第2側壁スペーサをマスクとして前記基板に第2不純物を注入してソース領域を形成する工程と、
第1熱処理を行い、前記堆積型ドレイン層に注入された前記第1不純物又は前記第2不純物を前記基板中に拡散させ、前記ドレイン領域と接続される不純物拡散層を形成する工程と、前記ソース領域、前記ゲート電極、前記堆積型ドレイン層、前記第1側壁スペーサ、及び前記第2側壁スペーサの上に金属膜を堆積させ、第2熱処理を行なって前記ソース領域、前記ゲート電極、及び前記堆積型ドレイン層の上に金属シリサイド層を形成する工程とを有する。
(実施例1)
本発明の第1の実施例を、n型高耐圧MOSトランジスタ、n型高耐圧MOSトランジスタの製造方法を例に、図1A〜図1Bを用いて詳細に説明する。第1実施例にかかる高耐圧MOSトランジスタ、高耐圧MOSトランジスタの製造方法は、LDD領域がゲート電極及び堆積型ドレイン層に対して自己整合的に形成されることを特徴とするものである。
(実施例2)
本発明の第2実施例に係る高耐圧MOSトランジスタを、図6A〜図6Bを用いて詳細に説明する。第2実施例に係る高耐圧MOSトランジスタは、ゲート電極がドレイン領域を取り囲むようにして形成されている。そのため、ドレイン領域の形成面積が小さくなり、ドレイン領域に寄生する容量を低減することができることを特徴とするものである。
2a p型ウエル領域
3 ゲート絶縁膜
4a ゲート電極
5a n型ドレイン領域
6a 堆積型ドレイン層
6b 不純物拡散層
7a 第1側壁スペーサを構成する絶縁膜
7b 第2側壁スペーサを構成する絶縁膜
8a n型ソース領域
9 コバルト(Co)シリサイド層
12 素子分離領域(STI)
16 ポリシリコン(Si)
17 低濃度導電性不純物領域
20a ソース領域に配線を接続するためのコンタクトプラグ
20b 堆積型ドレイン層に配線を接続するためのコンタクトプラグ
20c ゲート電極に配線を接続するためのコンタクトプラグ
100 高耐圧MOSトランジスタ
110 高耐圧MOSトランジスタ
Claims (5)
- 基板上にゲート絶縁膜を形成する工程と、
前記基板の第1領域における前記ゲート絶縁膜を除去し、前記第1領域の前記基板を露出させる工程と、
前記ゲート絶縁膜上にゲート電極を形成し、前記第1領域に堆積型ドレイン層を離間して形成する工程と、
前記ゲート電極と前記堆積型ドレイン層とをマスクとして、前記基板に第1の不純物を注入して前記ゲート電極と前記堆積型ドレイン層の間隙にドレイン領域を形成する工程と、
前記ゲート電極、前記堆積型ドレイン層、前記ドレイン領域及び前記基板の上に絶縁膜を堆積させる工程と、
前記絶縁膜を異方性エッチングによりエッチングして、前記ゲート電極と前記堆積型ドレイン層の間隙を前記絶縁膜で埋め込む第2側壁スペーサを形成すると共に、前記第2側壁スペーサのある側と反対側の前記ゲート電極の側壁に第1側壁スペーサを形成する工程と、
前記ゲート電極、前記堆積型ドレイン層、前記第1側壁スペーサ、及び前記第2側壁スペーサをマスクとして前記基板に第2不純物を注入してソース領域を形成する工程と、
第1熱処理を行い、前記堆積型ドレイン層に注入された前記第1不純物又は前記第2不純物を前記基板中に拡散させ、前記ドレイン領域と接続される不純物拡散層を形成する工程と、
前記ソース領域、前記ゲート電極、前記堆積型ドレイン層、前記第1側壁スペーサ、及び前記第2側壁スペーサの上に金属膜を堆積させ、第2熱処理を行なって前記ソース領域、前記ゲート電極、及び前記堆積型ドレイン層の上に金属シリサイド層を形成する工程と
を有することを特徴とするMOSトランジスタの製造方法。 - 前記第2不純物を注入する工程は、前記第1不純物よりも深い位置まで前記第2不純物を注入することを特徴とする請求項1に記載のMOSトランジスタの製造方法。
- 前記不純物拡散層は、前記第2不純物の注入深さよりも浅く形成されることを特徴とする請求項1又は2に記載のMOSトランジスタの製造方法。
- 前記ゲート電極及び前記堆積型ドレイン層はポリシリコンからなることを特徴とする請求項1〜3のいずれか1項に記載のMOSトランジスタの製造方法。
- 前記間隙の幅は、0.2μm以上0.3μm以下であることを特徴とする請求項1〜4のいずれか1項に記載のMOSトランジスタの製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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JP2007080159A JP5200399B2 (ja) | 2007-03-26 | 2007-03-26 | Mosトランジスタの製造方法 |
US12/054,684 US7666745B2 (en) | 2007-03-26 | 2008-03-25 | Method of manufacturing a semiconductor device and a semiconductor device |
US12/652,836 US8138550B2 (en) | 2007-03-26 | 2010-01-06 | Method of manufacturing a semiconductor device and a semiconductor device |
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JP2007080159A JP5200399B2 (ja) | 2007-03-26 | 2007-03-26 | Mosトランジスタの製造方法 |
Publications (2)
Publication Number | Publication Date |
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JP2008244008A JP2008244008A (ja) | 2008-10-09 |
JP5200399B2 true JP5200399B2 (ja) | 2013-06-05 |
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JP2007080159A Expired - Fee Related JP5200399B2 (ja) | 2007-03-26 | 2007-03-26 | Mosトランジスタの製造方法 |
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US (2) | US7666745B2 (ja) |
JP (1) | JP5200399B2 (ja) |
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JP5381989B2 (ja) | 2008-08-26 | 2014-01-08 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
CN101789041A (zh) * | 2010-01-28 | 2010-07-28 | 上海宏力半导体制造有限公司 | 一种可提高布图效率和集成度的器件版图 |
CN105514102A (zh) * | 2014-10-17 | 2016-04-20 | 中芯国际集成电路制造(上海)有限公司 | 一种版图结构、半导体器件和电子装置 |
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JPS5966158A (ja) * | 1982-10-08 | 1984-04-14 | Toshiba Corp | 半導体装置 |
JPH0748503B2 (ja) * | 1988-11-29 | 1995-05-24 | 三菱電機株式会社 | 電界効果トランジスタの製造方法 |
JPH0349236A (ja) * | 1989-07-17 | 1991-03-04 | Sony Corp | Mosトランジスタの製造方法 |
JP2771903B2 (ja) * | 1990-03-05 | 1998-07-02 | 富士通株式会社 | 高耐圧mosトランジスタ及びその製造方法、及び半導体装置及びその製造方法 |
JP2786307B2 (ja) * | 1990-04-19 | 1998-08-13 | 三菱電機株式会社 | 電界効果トランジスタ及びその製造方法 |
JPH04245480A (ja) * | 1991-01-30 | 1992-09-02 | Fujitsu Ltd | Mos型半導体装置およびその製造方法 |
JP2690244B2 (ja) * | 1992-08-20 | 1997-12-10 | 松下電子工業株式会社 | Mis型高耐圧トランジスタおよびその製造方法 |
JPH08255907A (ja) * | 1995-01-18 | 1996-10-01 | Canon Inc | 絶縁ゲート型トランジスタ及びその製造方法 |
JPH09186324A (ja) * | 1995-12-21 | 1997-07-15 | Texas Instr Inc <Ti> | ケイ化物化されたゲートおよび接触体を備えた電力用トランジスタ |
US5672531A (en) * | 1996-07-17 | 1997-09-30 | Advanced Micro Devices, Inc. | Method for fabrication of a non-symmetrical transistor |
US5923982A (en) * | 1997-04-21 | 1999-07-13 | Advanced Micro Devices, Inc. | Method of making asymmetrical transistor with lightly and heavily doped drain regions and ultra-heavily doped source region using two source/drain implant steps |
JPH11186402A (ja) * | 1997-12-22 | 1999-07-09 | Matsushita Electron Corp | 半導体装置及び半導体製造方法 |
JP3298483B2 (ja) | 1997-12-24 | 2002-07-02 | 日本電気株式会社 | 高耐圧mosfetの製造方法 |
JP2002270825A (ja) * | 2001-03-08 | 2002-09-20 | Hitachi Ltd | 電界効果トランジスタ及び半導体装置の製造方法 |
US20040031996A1 (en) * | 2002-08-16 | 2004-02-19 | Brian Li Chi Nan | Semiconductor device and method for forming |
JP4385206B2 (ja) * | 2003-01-07 | 2009-12-16 | 日本電気株式会社 | 電界効果トランジスタ |
JP2005223109A (ja) * | 2004-02-05 | 2005-08-18 | Renesas Technology Corp | 半導体装置およびその製造方法 |
-
2007
- 2007-03-26 JP JP2007080159A patent/JP5200399B2/ja not_active Expired - Fee Related
-
2008
- 2008-03-25 US US12/054,684 patent/US7666745B2/en not_active Expired - Fee Related
-
2010
- 2010-01-06 US US12/652,836 patent/US8138550B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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JP2008244008A (ja) | 2008-10-09 |
US20080237739A1 (en) | 2008-10-02 |
US7666745B2 (en) | 2010-02-23 |
US8138550B2 (en) | 2012-03-20 |
US20100109082A1 (en) | 2010-05-06 |
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