WO2004047168A1 - 電子装置 - Google Patents
電子装置 Download PDFInfo
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- WO2004047168A1 WO2004047168A1 PCT/JP2003/007862 JP0307862W WO2004047168A1 WO 2004047168 A1 WO2004047168 A1 WO 2004047168A1 JP 0307862 W JP0307862 W JP 0307862W WO 2004047168 A1 WO2004047168 A1 WO 2004047168A1
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- metal
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- electronic device
- solder
- substrate
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
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- H05K1/0203—Cooling of mounted components
- H05K1/021—Components thermally connected to metal substrates or heat-sinks by insert mounting
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- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
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- H05K1/00—Printed circuits
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- H05K1/0206—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate by printed thermal vias
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- H05K1/00—Printed circuits
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- H05K1/056—Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an organic insulating layer
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- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10734—Ball grid array [BGA]; Bump grid array
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- H05K2203/049—Wire bonding
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- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
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- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
- H05K3/4608—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated comprising an electrically conductive base or core
Definitions
- the present invention relates to a module substrate and a module structure of an electronic device. 2. Description of the Related Art It is necessary for an electronic device equipped with an electronic substrate to prevent failures caused by heat generated by electronic components. For this reason, a thermal cycle test is performed before shipment. In-vehicle electronic control devices, such as ECUs (Engine Control Units), are particularly suitable for use in a wide temperature range, because the temperature inside the vehicle changes greatly due to the engine on / off and changes in the ambient temperature. It is necessary to withstand the heat cycle (normally 140 degrees to 120 degrees: JASODOO 1 for environmental test of automotive electronic equipment). These days, ECUs tend to be located closer to the engine, and the upper limit of this temperature range tends to be higher.
- ECUs Engine Control Units
- the MCM Multi Chip Module
- Such an MCM structure (herein, including a structure having an interposer that does not necessarily have a plurality of LSIs, is simply called an MCM structure) is an LSI. Since the heat generated by the IC is difficult to escape to the electronic board, it is important to be able to efficiently radiate heat when the heat generated by the LSI is large. If this heat dissipation problem can be solved, an on-vehicle electronic control device with an MCM structure can be realized.
- a heat dissipation structure for example, there is a structure in which a heat sink is provided on the top surface of the LSI, but it is difficult to realize this structure if there are restrictions in the thickness direction due to the product structure. is there . In addition, there is the ability to cause problems in reliability.
- a conventional structure for improving the heat dissipation of a semiconductor module using a metal core substrate as an interposer substrate is disclosed in Japanese Patent Application Laid-Open No. Hei 5-17507. It is described in Japanese Patent Application Laid-Open No. 2000-228452.
- Japanese Patent Application Laid-Open No. Hei 5-175407 discloses a metal core substrate used as an interposer substrate.
- the resin layer on one side (front surface) of the metal core substrate is partially removed, and the semiconductor chip is formed in the core metal exposed region formed by the removal. It is bonded.
- the resin layer on the other surface (back surface) side of the metal core substrate is partially removed, and the core metal exposed region formed thereby is air-cooled.
- Japanese Patent Application Laid-Open No. 2000-228452 discloses a semiconductor device having a mounting structure similar to that of Japanese Patent Application Laid-Open No. 5-175407 on one surface (surface). A metal core board on which the chip is mounted is described.
- this metal core board On the other side (back side) of this metal core board, the conductor between the conductor circuit on which the soldering pole for connection to the other board is fixed, and the metal core A thermal via is formed in the substrate.
- This via hole is, for example, provided with metal plating or filled with a metal such as resin and solder. It is stated that by installing such a thermal via, it is possible to efficiently dissipate the heat generated by the electronic components.
- thermal vias are formed from the core metal to the conductor circuit. Costs are strong in the formation of a. In addition, thermal vias, which can be generally formed on a printed wiring board, are inferior in heat radiation because they are thin, hollow plates made of copper. Disclosure of invention SUMMARY OF THE INVENTION An object of the present invention is to provide an electronic device having low cost and excellent heat dissipation while maintaining the connection reliability between an interposer substrate and a motherboard. . The present invention discloses various means for achieving this purpose. The typical means are described below. ⁇
- a metal core substrate with a large heat capacity and high thermal conductivity will be used for both the interposer substrate and the motherboard mounted on the electronic device.
- a metal core substrate with large heat capacity and high thermal conductivity is used for the interposer substrate, and a metal base substrate with large heat capacity and high thermal conductivity is used for the mother port. You For this reason, the electronic device according to the present invention is excellent in heat dissipation.
- a metal core substrate or a metal base substrate having a thermal expansion coefficient close to that of the metal core substrate used for the interposer substrate is used.
- MCM the reliability of the solder connecting the interposer board to the motherboard can be a problem, mainly due to the interposer board and the motherboard.
- a substrate having a similar coefficient of thermal expansion is used for the interposer substrate and the mother board. As a result, the reliability of the solder connecting the interposer substrate and the mother board is improved, and as a result, the heat resistance of the electronic device is improved.
- the metal (base material) of the interposer substrate and the motherboard is exposed, and a pad for direct solder connection is formed on the exposed portion.
- the interposer substrate Solder connection to motherboard.
- the metal (base material) of the motherboard or the interposer substrate is not interposed through an insulating layer having low thermal conductivity.
- the exposed part of the metal (base material) can be formed at the same time as the formation of the via hole, and the pad on the metal base (base material) can be formed as a pad for other electrical connection. The cost is not high because it can be formed at the same time as.
- the core metal or base metal exposed through the partial removal of the resin layer and the heat-sinking solder connection knuckle are applied to the removed volume of the resin layer. If only the size of the solder connection pad is smaller than the solder connection pad for electrical connection on the resin layer, the solder connection pad for heat dissipation and the solder connection pad for electrical connection Both can be connected with the same volume of solder. For this reason, solder balls of the same size are supplied to both the solder connection pad for heat dissipation and the solder connection pad for electrical connection, and the BGA connection is performed efficiently and collectively under the same reflow conditions. It is possible to do it. BRIEF DESCRIPTION OF THE DRAWINGS FIG.
- FIG. 1 is a cross-sectional view showing a mounting structure according to the present invention.
- FIG. 2 is a cross-sectional view showing a mounting structure according to the present invention.
- FIG. 4 is a cross-sectional view showing a mounting structure according to the present invention.
- FIG. 5 is a cross-sectional view showing a mounting structure according to the present invention.
- FIG. 6 is a sectional view showing a mounting structure according to the present invention.
- FIG. 7 is a cross-sectional view illustrating a mounting structure according to the present invention.
- FIG. 8 is a cross-sectional view illustrating a mounting structure according to the present invention.
- FIG. 9 is a cross-sectional view illustrating a mounting structure according to the present invention.
- FIG. 10 is a cross-sectional view showing a mounting structure according to the present invention.
- FIG. 11 is a cross-sectional view showing a method of manufacturing an electronic substrate according to the present invention.
- FIG. 2 is a cross-sectional view illustrating a mounting structure according to the present invention.
- FIG. 3 is a cross-sectional view illustrating a mounting structure according to the present invention.
- FIG. 4 is a cross-sectional view illustrating a mounting structure according to the present invention.
- FIG. 5 is a cross-sectional view showing an actual 5k according to the present invention.
- FIG. 6 is a sectional view showing a mounting structure according to the present invention.
- FIG. 7 is a cross-sectional view illustrating a mounting structure according to the present invention.
- FIG. 8 is a sectional view showing a mounting structure according to the present invention.
- FIG. 9 is a cross-sectional view illustrating a mounting structure according to the present invention.
- FIG. 20 is a cross-sectional view showing a mounting structure according to the present invention.
- FIG. 21 is an eye view of the ECU according to the present invention in a state where an upper housing is opened.
- FIG. 22 is a cross-sectional view illustrating a mounting structure according to the present invention.
- FIG. 23 is a cross-sectional view showing a mounting structure according to the present invention.
- FIG. 24 is a cross-sectional view showing a mounting structure according to the present invention.
- FIG. 25 is a cross-sectional view showing a mounting structure according to the present invention.
- FIG. 21 is a bird's-eye view of the ECU, which is an electronic device according to the present embodiment, with an upper housing opened.
- a connector (not shown) for connecting to an external terminal is molded into a lower housing 41 and a lower housing 41, which are molded on a side wall.
- Module 100 which is fixed and electrically connected to the connector terminal, is fitted into lower housing 41, and module 100 is sealed. And an upper housing (not shown).
- the housing is usually made of light aluminum. However, since the heat dissipation function of the housing does not depend on the material, the material of the housing can be arbitrarily selected.
- the module 100 is composed of an interposer substrate 20 on which an LSI chip 11 as an electronic component is mounted and a motherboard on which an interposer substrate 25 is mounted. 30 and. These substrates 20 and 30 are connected by solder.
- the three heat generating LSI chips 11 are mounted on different interposer boards together with other electronic components. Of these three LSI chips 11, one is a power supply IC chip and two are dry-drive IC chips.
- the LSI chip mounted on the interposer substrate is either a power supply IC chip or a drain IC chip. is there .
- one LSI chip is mounted.
- the module described above is taken as an example, it is not necessary that the number of LSI chips mounted on the interposer substrate be one or more.
- both the power supply IC chip and the driver IC chip may be mounted on the interposer substrate.
- the module shown in Fig. 1 is used as an LSI chip 11, a solder part 19 formed by melting a solder pole, and an interposer substrate 20. It has a metal core substrate 2 OA, a metal base substrate 3 OA used as a mother port 30 and a solder register 29.
- the metal core substrate 2 OA has a metal plate (core metal 13) as a core, and an insulating layer 21 made of a resin formed on both sides of the core metal 13. It is a substrate provided with a wiring layer 15. In addition, 17 is a snowy horror.
- the metal-based substrate 3 OA is based on a metal plate (metal-based base 23), and has an insulating layer 21 made of resin on one surface thereof. This is a substrate in which a wiring layer 15 is formed on the insulating layer 21.
- a portion of the insulating resin is removed from the insulating layer 21 on one side (front surface) of the metal core substrate 2 OA, and an insulating layer is interposed on the core metallization in that area. Instead, the face-up type LSI chip 11 is die-bonded. The LSI chip 11 is wire-bonded to the wiring layer 15 on the mounting surface of the LSI chip.
- the insulating resin is removed by laser at the same time as the via formation.
- lasers such as a carbonate laser and a YAG laser, but any type of laser can be used. However, if a carbon dioxide laser is used, the processing cost is low. Also, mechanically Fat may be removed.
- solder connection pad for electrically connecting to the mother board is formed on the other side (back side) of the metal core board 2OA.
- solder connection nodes those formed in the area opposite to the mounting area of the LSI chip 11 can be used for heat dissipation, power supply, and grounding. It is used for such purposes.
- two insulating layers 21 and two wiring layers 15 are alternately stacked.
- Part of the wiring layer is a pad for solder connection, and is connected to the interposer substrate 20A by solder.
- the insulating resin in the — part is removed to expose the base metal 23, and N i Au plating is applied to form a solder connection pad 31 for heat dissipation.
- the other surface (back surface) of the metal base substrate 30A is bonded to the housing 41 with an adhesive.
- This metal-co-interposer substrate is manufactured by the following process.
- a copper plate of 0.2 mmt x 300 mm x 500 min is prepared as the core metal 13.
- This copper plate is sized so that multiple boards can be cut out and used later.
- the copper plate may be of a size that is easy to handle in substrate manufacturing.
- the type of metal may be aluminum, iron-Ni alloy, or the like, but is preferably copper having good thermal conductivity.
- a hole for forming a hole (0.8 ⁇ ) and a substrate size later The slit along the outer shape of the board piece was formed by etching to make it easier to cut out with the cutting. Note that a solution containing ferric chloride is used as the etching solution.
- a pre-paider 21 epoxy resin containing glass cross-section, thickness 0.1 mm t
- a copper foil 15 thickness: (0.012mmt) is laminated on the front and back of metal 13 and glued by pressing.
- a resin-coated copper foil RCF Resin Coated Copper Foil
- RCF Resin Coated Copper Foil
- the laser may be any one of a carbon dioxide laser, a YAG laser and the like. However, it is preferable to use a carbon dioxide laser because it can be processed at low cost.
- a drill hole was formed for the through hole 17 for electrically connecting the inner and outer layers of the metal core substrate to each other.
- These through holes can also be machined with a laser, but if you use a pre-predder, there is glass crossing, so drilling is suitable.
- copper was applied with a thickness of about 0.015 mm for the inner layer through-holes, inner layer vias, and inner layer wiring.
- the process of forming the insulating layer and the inner wiring layer The surface circuit was formed by repeating the process again. In this case, the via At the same time, the resin in the LSI chip mounting area is removed. Copper plating of the same thickness as above is applied to the wiring and via holes, and electroless nickel plating (0.005 mm thick) is used to prevent wiring corrosion and solder connection. ) And electroless gold plating (thickness: about 0.00L).
- solder resist 29 was formed of a pattern except for a portion that had to be exposed for mounting electronic components.
- the case where the front and back wiring layers of the metal core substrate 2 OA are two layers has been described.
- the present invention does not depend on the number of wiring layers.
- the wiring layers on the front and back sides of the substrate 20A do not need to be two layers, if not necessarily.
- Ag paste is applied to a desired part for mounting components on the surface of A, and electronic components are mounted. Further, the Ag paste is cured under appropriate curing conditions (for example, 150 ° C., lhr), and the electronic components are bonded to the metal core substrate 2OA. If this bonding is performed with solder, the heat dissipation can be further improved.
- the electrodes of the high heat-generating LSI 11 and the electrodes of the metal core interposer substrate 2OA are connected by wire bonding. If necessary, if the component mounting surface of the interposer substrate 20A is molded into a package by molding it with resin, the handleability is improved.
- a Sn3AgO.5Cu solder pole is mounted on the electrode, and the solder is reflowed at a maximum temperature of 240 ° C and a solder melting time of about 20 seconds. As a result, a solder bump is formed. Note that other solders may be used. In such a case, the poles are formed under reflow conditions according to the type of solder.
- the metal base substrate 3OA used as the motherboard 30 is also formed in the same manner as the metal core substrate 30A except for the following points. Since the insulating layer and the wiring layer are formed on one side, a single hole that penetrates the core metal is not required. This allows for a simpler process to manufacture.
- via holes and counterbores for forming solder connection pads on the base metal 23 are formed on the insulating layer by a carbon dioxide laser or the like. Then, the base metal 23 exposed from the counterbore bottom force is subjected to electroless nickel plating and electroless gold plating. As a result, a solder contact pad for heat dissipation is formed.
- the thickness of the electroless nickel plating on the base metal 23 shall be about 0.005 mm, and the thickness of the gold plating shall be about 0.001 mm.
- the base metal 23 is made of copper, the above-mentioned plating is not always necessary, but when the plating is applied, solder connection and connection reliability can be improved.
- solder printing mask with a mask thickness of 0.1 mm on the 30 A solder paste pad of the metal-based substrate, print the solder paste by the printing method.
- the heat capacity of the mother board is large, so that the heat generated by the LSI is not only diffused in the metal-coin interposer substrate, but also vertical through the solder.
- the heat can be efficiently transferred to the motherboard (in the direction of the motherboard), and the heat can be spread even within the motherboard.
- Almost all ordinary printed circuit boards are made of resin with poor thermal conductivity, but metal-based boards are made of metal with good thermal conductivity.
- the insulating resin layer is thin, an efficient heat dissipation structure as described above can be obtained.
- the reliability of the solder connecting the interposer substrate and the motherboard may be a problem. This is due to the difference in the coefficient of thermal expansion between the interposer substrate and the mother board.
- the base metal and the core metal are connected to each other. Since a material having a thermal expansion coefficient close to that of a defect is not used, a difference in thermal expansion coefficient between the interposer substrate and the mother board can be reduced. As a result, the solder connection reliability is improved. This effect can be expected in any of the following embodiments.
- solder bumps 3 3 pads on ordinary insulating resin are connected by solder bumps 19.
- the heat generated by the LSI can be dissipated to the metal base of the motherboard, so that better heat dissipation can be obtained.
- the size of the solder connection pad for heat dissipation on the core meter / layer exposed by partial removal of the resin layer is reduced by the size corresponding to the removed volume of the resin layer. If the size of the solder connection pad for electrical connection on the resin layer is smaller, both the solder connection pad for heat dissipation and the solder connection pad for electrical connection will be used. It can be connected with the same volume of solder.
- FIG. 2 is the same as FIG. 1 except that the motherboard is a metal core substrate 30 B with double-sided wiring.
- Figs. 3 to 5 show the mother board 30 as a part of the insulating resin on the back side (the surface on which the interposer board is not mounted) and the core metal exposed.
- the structure using the double-sided metallographic substrate 30G, 30C, and 3OD is shown below.
- the heat radiation can be further improved.
- an underfill or a gel is inserted between the interposer substrate and the motherboard.
- high heat dissipation can be obtained.
- the chip mounting counterbore does not need to be near the center of the substrate, and
- the heat-dissipating pad formed directly on the tarl does not need to be directly under the chip mounting part. The same applies to the module having the above-described structure and the module having the structure described below.
- FIG. 7 shows a structure in which the module is bonded to a metal (for example, aluminum) housing 41.
- the high heat conductive member 45 is sandwiched between the counterbore portion on the back side of the motherboard and the housing 41, the heat dissipation can be further improved. be able to .
- the high heat conductive member is a member having a higher thermal conductivity than the adhesive bonding the motherboard and the aluminum casing, for example, It is a metal plate such as copper or aluminum, solder, or a resin or adhesive with high thermal conductivity.
- a pad for solder connection may be formed on the case and connected to the case, or solder may be supplied to the core metallization on the mother board and soldered. It can be pressed into the body and connected by contact only. It is not always necessary to form a pad on the housing if only the solder is brought into contact with the housing.
- an adhesive may be applied to both sides of the metal plate for connection, or they may be simply contacted.
- an adhesive 43 such as a normal adhesive or high heat conductive adhesive. Go.
- Figure 8 shows that the LSI chip 11 on the metal core interposer board is face-down, and the pins are flip-chip connected by bumps 51. This is an example.
- An underfill 53 is interposed between the interposer substrate and the LSI chip 11. The use of the underfill 53 improves reliability and heat dissipation.
- FIG. 9 shows an example of a structure in which a semiconductor package 55 is connected by a solder bump 57 on a metal core interposer substrate. Even in such a structure, heat dissipation can be improved.
- FIG 10 shows an example of an interposer structure for obtaining a highly heat dissipating MCM structure.
- the interposer substrate 20B is a metal core substrate having a metal core and an insulating layer 21 and a wiring layer 15 formed on both sides of the core metal 13. It is. On one side of the board, a counterbore is provided in the insulating resin to mount the high heat-generating LSI, and a portion where the core metal 13 is exposed is formed.
- the insulating resin layer on the other side of the substrate 20B has a solder connection node 61 for electrically connecting to the mother board and a counterbore of a desired size. It is formed.
- the pad 63 for the heat-sinking connection is formed directly on the core 13 exposed at the bottom of the counterbore.
- FIG. 11 shows an example of a manufacturing process for obtaining the interposer substrate 20B shown in FIG.
- a copper plate of 0.2mm1: X300mmX500mm is prepared as metal 13 to be the core.
- This copper plate can be cut out and used later for multiple boards. Size.
- the copper plate may be of a size that is easy to handle in substrate manufacturing.
- the type of metal may be aluminum, iron-Ni alloy, or the like, but is preferably copper having good thermal conductivity.
- a hole (0.8 mm square) for forming a through hole and a slit along the outer shape of the board piece to make it easier to cut out later with the board size are used for etching. More formed.
- the etching solution was ferric chloride (Fig. 11_ (a)).
- the insulating resin layer and the inner layer of the pre-predeer 21 (epoxy resin containing glass cross, thickness O.lmmt) and copper foil 15 (thickness 0 012mmt) is laminated on both sides of the metal, and bonded by pressing.
- Resin-coated copper foil RCF Resin Coated Copper Foils
- Fig. 11_ (b) may be used in place of the pre-prepared and copper foil (Fig. 11_ (b)).
- Unnecessary copper foil for wiring was removed by etching. If it is necessary to electrically connect the core metal to the inner layer wiring, use a laser with a diameter of 0.15 mm to expose the core metal to form the inner layer via. Form a boring. Any type of laser, such as a CO2 laser or a YAG laser, can be used, but a CO2 laser can be processed at low cost.
- a through-hole for the through hole 17 for electrically connecting the inner layers on the front and back of the substrate was formed with a drill. This through-hole can also be machined with a laser, but when using a pre-reader, there is a glass cross, so the drilling force B Are suitable .
- copper with a thickness of about 0.015 mm was applied to the inner layer through holes, inner layer vias, and inner layer wiring (Fig. 11- (c)).
- a 0.6 mm ⁇ BGA solder connection pad 61 for electrical connection and a 0.6 mm ⁇ solder connection pad 63 for heat radiation directly above the core metal are formed simultaneously.
- the node pitches were all 1.5 mm.
- the insulating resin has been removed from the counterbore for heat dissipation. Accordingly, the solder connection height is increased by the thickness of the insulating resin (about 0.2 ram). For this reason, with regard to solder connectivity, the diameter of the pad formed directly above the core is BGA for electrical connection. It is desirable that it is not larger than the head and diameter.
- the pad pitch it is better to make the pitch of the solder connection pad for heat dissipation small in order to further improve the heat dissipation.
- c 0 head, pitch is and this is often shall be the Pas-head pitch in consideration of the safety factor of the degree Ru Oh Ni you'll tio over the door to such Rere, heat dissipation solder portion is Even if you do a short shot, there is no problem, so the pitch can be considerably reduced. As a result, it is possible to increase the total area of the connection portion and improve heat radiation.
- solder register was formed with a pattern, leaving the necessary parts for component mounting (Fig. 11- ( ⁇ (e)).
- each wiring layer is provided, but the present invention does not depend on the number of wiring layers. For this reason, the wiring layers on the front and back of the metal core substrate 2 OB do not necessarily have to be two layers. In order to increase the number of wiring layers on the metal core substrate 20B, the steps shown in FIGS. 11 (b;) to (c) may be repeated.
- FIG. 12 shows an example of a structure in which the substrate 2 OB created as described above is connected to the motherboard 30 as an interposer substrate 20.
- the high heat-generating LSI 11 is a high thermal conductive Ag paste and is connected to the core metal exposed portion of the metal core substrate 20B. If this connection is made with solder, the heat dissipation can be further improved. No, on the back of the interposer substrate 20B.
- a Sn3AgO.5Cu solder pole of 0.75 ⁇ ⁇ ⁇ in diameter is mounted on the head, and the solder is reflowed at 240 ° C, which exceeds the solder melting point. As a result, a solder bump is formed.
- the solder bump is aligned with the pad on the motherboard, and the metal core board 20B is mounted on the motherboard 30. After that, the solder was reflowed at 240 ° C and connected. According to such a structure, the heat generated by the LSI can be efficiently released to the motherboard.
- Fig. 13 shows a structure using a single-sided wiring board (metal-based board) 3OA based on a metal plate as the mother board 30 of Fig. 12.
- the metal core board 20B has, like the high heat dissipation board described above, the counterbore of the insulating resin and the bottom force of the counterbore, and the exposed pad on the metal base.
- the power S set only et al is, this path head 6 1 force S, Nono of meta Norebe scan board 3 0 a 0 head 3 1 and that has been solder connection.
- the heat generated by the LSI Can be dissipated to the mother-port metal base, so that better heat dissipation can be obtained.
- FIG. 14 shows a structure in which a metal core substrate 30 B having double-sided wiring is used as the mother port 30 of FIG. 12. This structure is the same as the embodiment described with reference to FIG. 13 except that the metal core substrate 30B of the double-sided wiring is used as a mother board. .
- Figures 13 and 14 show a metal base with a solder connection pad formed on the metal exposed from the resin layer.
- Board 30A and metal core board 3 Although the structure using the OB as the motherboard 30 in FIG. 12 is shown, the motherboard 30 in FIG. 12 is not necessarily required to use such a meta-board.
- the base board 3OA and the metal core board 30B need not be provided.
- a metal base board or a metal core board without a solder connection pad formed directly on the metal may be connected to the mother port 30 of FIG.
- the pad 61 on the lead may be connected with solder.
- Figure 17 shows a metal core interface with LSI 11 mounted.
- a member having high thermal conductivity is a member having a higher thermal conductivity than the adhesive bonding the mother port and the aluminum casing.
- copper, aluminum, or the like is used.
- It is a metal plate such as lime, solder, resin or adhesive with high thermal conductivity.
- solder connection may be made by forming a pad, or the solder may be supplied to the core metal of the motherboard, and the connection may be made only by contact with the housing by pressing it down.
- FIG. 20 shows an example in which a pad for heat radiation solder connection is formed directly on the core metal, and the heat radiation solder connection part is located off the chip. Also, the electrical solder connection may be in the area directly below the chip. As shown in the present embodiment, regardless of the position of the chip on the board, the solder connection portion for heat dissipation and the electrical connection portion are determined by the wiring design and the heat dissipation design. It can be placed freely.
- the method of manufacturing the interposer substrate 20B is omitted because it is shown in FIG.
- the Ag paste is cured and bonded under appropriate curing conditions (for example, 150 ° C, lhr). Connect the electrodes of the high heat-generating LSI to the electrodes of the metal-co-interposer 20B by wire bonding. If the component mounting surface of the metal core board 20B is molded with resin as needed, the handleability is improved.
- solder balls are also mounted on the heat dissipation pad directly above the core metal.
- Sn3Ag0.5Cu solder reflow at a maximum temperature of 240 ° C and a solder melting time of about 20 seconds to form a solder bump.
- Other solders may be used, and in that case, solder bump formation is performed under reflow conditions according to the type of solder.
- solder printing mask with a mask thickness of 0.1 mm and print the solder paste by the printing method.
- An interposer substrate with a solder bump formed thereon is aligned and mounted on the printed paste-like solder. After that, reflow the solder again and make the solder connection. It is not always necessary to print this solder, but doing so can prevent the displacement of the interposer substrate due to the viscosity of the printed solder.
- the motherboard W As shown in Figures 14 to 16, the motherboard W
- the face-to-face LSI chip 11 is mounted on the surface of the metal core substrate 20C.
- the solder connection pad on the insulation layer on the back side of the metal core substrate 20C is soldered to the solder connection pad on the insulation layer of the metal base substrate 30E.
- the pad is connected to the pad.
- the metal base board 30E is used as the mother board 30.
- the metal core board 30F is used as the mother board. It may be used as the board 30.
- the module shown in FIG. 23 is obtained by removing a part of the insulating resin from the insulating layer 21 on the metal core interposer substrate 2 OA and removing the core metal in that region. It has a structure similar to that of the module of FIG. 22 except that the LSI chip 11 is mounted on the upper side without interposing the insulating layer 21.
- the metal base substrate 30E is used as the mother board 30.
- the metal core substrate 3.0E is used.
- F may be used as mother port 30.
- the modules shown in FIGS. 22 to 25 are attached to the lower housing 41 in the same manner as the modules shown in FIGS. 1 and 2 and the like. You can do it.
- the module shown in Fig. 24 has a metal core board 30F (mother one-port) with the lower surface at the bottom. Adhered to housing 4 1 with adhesive 4 3 .
- an electronic device having low cost and excellent heat dissipation while maintaining the connection reliability between an interposer substrate and a mother board.
- Industrial applicability that can be achieved.
- Electronic devices with excellent heat dissipation can be manufactured at low cost while maintaining the connection reliability between the interposer substrate and the motherboard. It can be provided.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Insulated Metal Substrates For Printed Circuits (AREA)
- Combinations Of Printed Boards (AREA)
- Structure Of Printed Boards (AREA)
Abstract
Description
Claims
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/535,857 US7554039B2 (en) | 2002-11-21 | 2003-06-20 | Electronic device |
KR1020057009038A KR100661044B1 (ko) | 2002-11-21 | 2003-06-20 | 전자 장치 |
AU2003244322A AU2003244322A1 (en) | 2002-11-21 | 2003-06-20 | Electronic device |
CNB038253135A CN100378968C (zh) | 2002-11-21 | 2003-06-20 | 电子装置 |
EP03811481.5A EP1571706B1 (en) | 2002-11-21 | 2003-06-20 | Electronic device |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002337365A JP3938017B2 (ja) | 2002-11-21 | 2002-11-21 | 電子装置 |
JP2002-337366 | 2002-11-21 | ||
JP2002-337365 | 2002-11-21 | ||
JP2002337366A JP3988629B2 (ja) | 2002-11-21 | 2002-11-21 | 電子装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2004047168A1 true WO2004047168A1 (ja) | 2004-06-03 |
Family
ID=32328338
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2003/007862 WO2004047168A1 (ja) | 2002-11-21 | 2003-06-20 | 電子装置 |
Country Status (6)
Country | Link |
---|---|
US (1) | US7554039B2 (ja) |
EP (1) | EP1571706B1 (ja) |
KR (1) | KR100661044B1 (ja) |
CN (1) | CN100378968C (ja) |
AU (1) | AU2003244322A1 (ja) |
WO (1) | WO2004047168A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1612860A3 (en) * | 2004-06-30 | 2007-05-30 | Shinko Electric Industries Co., Ltd. | Interposer, method of fabricating the same, and semiconductor device using the same |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070075436A1 (en) * | 2003-10-06 | 2007-04-05 | Nec Corporation | Electronic device and manufacturing method of the same |
JP4600065B2 (ja) * | 2005-02-03 | 2010-12-15 | 富士電機システムズ株式会社 | 半導体装置及びその製造方法 |
JP2007158279A (ja) | 2005-12-09 | 2007-06-21 | Hitachi Ltd | 半導体装置及びそれを用いた電子制御装置 |
US7919714B2 (en) * | 2007-05-09 | 2011-04-05 | General Electric Company | System and a method for controlling flow of solder |
TW200919685A (en) * | 2007-10-17 | 2009-05-01 | Phoenix Prec Technology Corp | Package on package(pop) structure |
US20090115045A1 (en) * | 2007-11-02 | 2009-05-07 | Phoenix Precision Technology Corporation | Stacked package module and method for fabricating the same |
US7939940B2 (en) * | 2007-12-18 | 2011-05-10 | Omnivision Technologies, Inc. | Multilayer chip scale package |
SG158823A1 (en) * | 2008-07-18 | 2010-02-26 | United Test & Assembly Ct Ltd | Packaging structural member |
JP5290215B2 (ja) * | 2010-02-15 | 2013-09-18 | ルネサスエレクトロニクス株式会社 | 半導体装置、半導体パッケージ、インタポーザ、及びインタポーザの製造方法 |
US8772817B2 (en) | 2010-12-22 | 2014-07-08 | Cree, Inc. | Electronic device submounts including substrates with thermally conductive vias |
KR101431918B1 (ko) * | 2012-12-31 | 2014-08-19 | 삼성전기주식회사 | 인쇄회로기판 및 인쇄회로기판의 표면처리방법 |
JP6516011B2 (ja) * | 2015-07-24 | 2019-05-22 | 日本電気株式会社 | 無線機 |
JP2017139316A (ja) * | 2016-02-03 | 2017-08-10 | ソニー株式会社 | 半導体装置および製造方法、並びに電子機器 |
FR3049156B1 (fr) * | 2016-03-15 | 2018-04-13 | Alstom Transport Technologies | Carte electronique comprenant un circuit intercalaire en matrice de billes |
FR3073978B1 (fr) * | 2017-11-17 | 2022-10-28 | Inst Vedecom | Module electronique de puissance et systeme electronique comprenant un tel module electronique |
JP2020009879A (ja) * | 2018-07-06 | 2020-01-16 | 太陽誘電株式会社 | 回路基板および回路モジュール |
CN114449729B (zh) * | 2020-11-06 | 2023-11-10 | 中移物联网有限公司 | 一种主板保护结构及其装配方法 |
TWI806218B (zh) * | 2021-11-03 | 2023-06-21 | 群光電子股份有限公司 | 電子裝置及其電路板模組 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09102683A (ja) * | 1995-10-02 | 1997-04-15 | Nippon Avionics Co Ltd | 高周波用ハイブリッド集積回路の基板の固定方法 |
JP2000012765A (ja) * | 1998-06-17 | 2000-01-14 | Nec Corp | 積層型半導体装置放熱構造 |
JP2000315747A (ja) * | 1999-04-28 | 2000-11-14 | Sumitomo Metal Electronics Devices Inc | 半導体パッケージ |
JP2002270743A (ja) * | 2001-03-13 | 2002-09-20 | Nec Corp | 半導体素子の実装構造 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6097089A (en) * | 1998-01-28 | 2000-08-01 | Mitsubishi Gas Chemical Company, Inc. | Semiconductor plastic package, metal plate for said package, and method of producing copper-clad board for said package |
JPH05175407A (ja) * | 1991-12-25 | 1993-07-13 | Sumitomo Bakelite Co Ltd | 半導体搭載基板 |
US6303878B1 (en) * | 1997-07-24 | 2001-10-16 | Denso Corporation | Mounting structure of electronic component on substrate board |
US6555900B1 (en) * | 1998-10-21 | 2003-04-29 | Matsushita Electric Industrial Co., Ltd. | Package, semiconductor device and method for fabricating the semiconductor device |
TW410446B (en) * | 1999-01-21 | 2000-11-01 | Siliconware Precision Industries Co Ltd | BGA semiconductor package |
JP2000228452A (ja) | 1999-02-05 | 2000-08-15 | Ibiden Co Ltd | 電子部品搭載用基板 |
JP2001110928A (ja) * | 1999-10-04 | 2001-04-20 | Shinko Electric Ind Co Ltd | 半導体パッケージの製造方法 |
JP2001177202A (ja) | 1999-12-14 | 2001-06-29 | Nitto Denko Corp | メタルコア回路基板およびそれを用いたメタルコア多層回路基板 |
TW462121B (en) * | 2000-09-19 | 2001-11-01 | Siliconware Precision Industries Co Ltd | Heat sink type ball grid array package |
US20020189853A1 (en) * | 2001-06-15 | 2002-12-19 | Phoenix Precision Technology Corp. | BGA substrate with direct heat dissipating structure |
-
2003
- 2003-06-20 KR KR1020057009038A patent/KR100661044B1/ko active IP Right Grant
- 2003-06-20 CN CNB038253135A patent/CN100378968C/zh not_active Expired - Fee Related
- 2003-06-20 WO PCT/JP2003/007862 patent/WO2004047168A1/ja active Application Filing
- 2003-06-20 EP EP03811481.5A patent/EP1571706B1/en not_active Expired - Lifetime
- 2003-06-20 AU AU2003244322A patent/AU2003244322A1/en not_active Abandoned
- 2003-06-20 US US10/535,857 patent/US7554039B2/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09102683A (ja) * | 1995-10-02 | 1997-04-15 | Nippon Avionics Co Ltd | 高周波用ハイブリッド集積回路の基板の固定方法 |
JP2000012765A (ja) * | 1998-06-17 | 2000-01-14 | Nec Corp | 積層型半導体装置放熱構造 |
JP2000315747A (ja) * | 1999-04-28 | 2000-11-14 | Sumitomo Metal Electronics Devices Inc | 半導体パッケージ |
JP2002270743A (ja) * | 2001-03-13 | 2002-09-20 | Nec Corp | 半導体素子の実装構造 |
Non-Patent Citations (1)
Title |
---|
See also references of EP1571706A4 * |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1612860A3 (en) * | 2004-06-30 | 2007-05-30 | Shinko Electric Industries Co., Ltd. | Interposer, method of fabricating the same, and semiconductor device using the same |
US7388293B2 (en) | 2004-06-30 | 2008-06-17 | Shinko Electric Industries, Co. | Interposer method of fabricating same, and semiconductor device using the same having two portions with different constructions |
US7415762B2 (en) | 2004-06-30 | 2008-08-26 | Shinko Electric Industries Co., Ltd. | Interposer, method of fabricating the same, and semiconductor device using the same |
Also Published As
Publication number | Publication date |
---|---|
CN100378968C (zh) | 2008-04-02 |
EP1571706B1 (en) | 2018-09-12 |
US20060234420A1 (en) | 2006-10-19 |
EP1571706A4 (en) | 2008-08-06 |
CN1701437A (zh) | 2005-11-23 |
AU2003244322A1 (en) | 2004-06-15 |
KR20050075032A (ko) | 2005-07-19 |
KR100661044B1 (ko) | 2006-12-26 |
EP1571706A1 (en) | 2005-09-07 |
US7554039B2 (en) | 2009-06-30 |
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