Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
  • H10D86/01—Manufacture or treatment
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
  • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI

Definitions

• the present invention relates to the manufacturing of semiconductor devices, and more particularly, to forming silicon on insulator devices having improved characteristics.
• MOS metal-oxide-semiconductor
• a typical MOS device includes a bulk semiconductor substrate on which a gate electrode is disposed.
• the gate electrode which acts as a conductor, receives an input signal to control operation of the device.
• Source and drain regions are typically formed in regions of the substrate adjacent the gate electrodes by doping the regions with a dopant of a desired conductivity. The conductivity of the doped region depends on the type of impurity used to dope the region.
• the typical MOS device is symmetrical, in that the source and drain are interchangeable. Whether a region acts as a source or drain typically depends on the respective applied voltages and the type of device being made.
• the collective term source/drain region is used herein to generally describe an active region used for the formation of either a source or drain.
• the semiconductor layer can be formed on an insulating substrate, or over an insulation layer formed in a semiconductor substrate.
• This technology is referred to as Silicon-on-Insulator (SOI) technology.
• Silicon on insulator materials offer potential advantages over bulk materials for the fabrication of high performance integrated circuits. For example dielectric isolation and reduction of parasitic capacitance improve circuit performance. Compared to bulk circuits, SOI is more resistant to radiation.
• SOS silicon-on-sapphire
• CMOS radiation-hardened complimentary MOS
• Circuit layout in SOI can also be greatly simplified and packing density greatly increased if the devices are made without body contacts in which the body regions of these devices are "floating".
• a disadvantage of many SOI devices is the lack of a bulk silicon or body contact to the MOS transistor. If the channel/body region is left “floating", various hysteresis effects can prevent proper circuit operation. These effects include the so-called “kink” effect and the parasitic lateral bipolar action. Partially-depleted devices are such that the maximum depletion width in the body is smaller than the thickness of the semiconductor Si layer, and a quasi-neutral region results which has a floating potential. These floating body effects may result in undesirable performance in SOI devices.
• MOS devices using SOI structure typically fall in one of two groups depending on the type of dopants used to form the source, drain and channel regions.
• the two groups are often referred to as n-channel and p-channel devices.
• the type of channel is identified based on the conductivity type of the channel which is developed under the transverse electric field.
• NMOS n-channel MOS
• PMOS p-channel MOS
• p-type impurities e.g., boron
• NMOS and PMOS SOI transistors One consideration when manufacturing NMOS and PMOS SOI transistors is maintaining a proper channel length.
• the channel length can be shortened, for example, if the source/drain regions are exposed to excessive temperature and/or time during activation. This causes excess lateral diffusion of the dopants, which causes the channel length to shorten.
• NMOS and PMOS transistors are formed on a single chip and are therefore exposed to the same temperature/time profile during dopant activation. However, because the NMOS and PMOS transistors are formed using different dopants, which likely have different diffusion characteristics, the temperature/time profile for at least one of the NMOS or PMOS transistors will not be optimized.
• inventions of the present invention provide a method of manufacturing a semiconductor device that improves performance, minimizes floating body effects, and allows for separate optimization of separate transistors formed on an SOI structure.
• the method includes providing a silicon semiconductor layer over an insulating layer, and partially removing a first portion of the silicon layer.
• the silicon layer includes the first portion and a second portion, and a thickness of the second portion is greater than a thickness of the first portion. Initially, the first and second portions of the silicon layer can initially have the same thickness.
• the first portion of the silicon layer is partially removed by etching.
• the partial removal of the first portion of the silicon layer can also include depositing a resist over the silicon layer and exposing and developing the resist to expose the first portion of the silicon layer.
• the thickness of the first portion is determined by etching the first portion for a predetermined length of time.
• the first portion of the silicon layer is partially removed by oxidizing the first portion of the silicon layer and removing the oxidized silicon.
• the partial removal of the first portion of the silicon layer can also include depositing a mask layer and a resist over the silicon layer and exposing and developing the resist to expose a portion of the mask layer over the first portion of the silicon layer and removing the mask layer over the first portion of the silicon layer. After partially removing the first portion, the mask layer can then be removed. Isolating features can be formed before or after the first portion of the silicon layer is partially removed. Also, a first transistor can be formed in the first portion and a second transistor can be formed in the second portion.
• the first transistor can be a fully depleted transistor, and the second transistor can be a partially depleted transistor. Also, the first transistor can include source/drain regions formed with a first dopant and the second transistor can include source/drain regions formed with a second dopant, and the diffusivity of the second dopant into silicon is greater than the diffusivity of the first dopant into silicon.
• a semiconductor device in another embodiment, includes an insulating layer and a silicon semiconductor layer over the insulating layer.
• the silicon layer includes a first portion and a second portion, and a thickness of the second portion is greater than a thickness of the first portion.
• FIGS 1A-1D schematically illustrate sequential phases of a SOI fabrication method according to one embodiment of the present invention.
• FIGS. 2A-2D schematically illustrate sequential phases of a SOI fabrication method according to another embodiment of the present invention.
• Figure 3 schematically illustrates a SOI semiconductor device having different portions with silicon layers having different thicknesses.
• Figure 4 illustrates the semiconductor device of Figure 3 after features are formed on the silicon layers having different thicknesses.
• Figure 5 schematically illustrates a SOI semiconductor device in which the isolating regions are removed.
• the present invention improves performance, reduces floating body effects, and allows for separate optimization of separate transistors formed on an SOI structure. This is achieved, in part, by providing a semiconductor device having different portions, with each portion having a silicon semiconductor layer of the SOI structure, and a thickness of one portion of the silicon layer differing from another portion of the silicon layer. In so doing, the thickness of each portion of the silicon layer can be optimized depending upon factors, such as whether a transistor formed on the SOI structure is to be partially or fully depleted and the diffusion characteristics of the dopants used to form the transistors.
• Figs. 1A and 2A illustrate a conventional SOI structure.
• the SOI structure includes a silicon semiconductor layer 14 above an insulator layer 12.
• the SOI structure is then positioned over a substrate 10.
• the invention is not limited as to the manner in which the SOI structure is formed.
• one method of forming an SOI structure involves implanting heavy doses of oxygen into the substrate 10.
• the substrate 10 is then subjected to an annealing process, which forms a silicon oxide insulator layer 12 and the silicon layer 14 above the insulator layer 12.
• Another method of forming an SOI structure includes a technique termed wafer bonding in which the SOI structure is bonded onto a substrate 10.
• the substrate 10 can be formed from any material suitable for use with an SOI structure, for example, metal substrates have been contemplated. However, in one aspect, the substrate 10 is formed from silicon.
• the insulator layer 12 can be formed from any material suitable for use with an SOI structure.
• sapphire and Si 3 N are materials known to be acceptable for use with an SOI structure.
• the insulator layer 12 is formed from Si0 2 . Although not limited in this manner, the insulator layer 12 can have a thickness from about 100 to 500 nanometers.
• the silicon layer 14 is formed above the insulator layer 12, and the silicon layer 14 is not limited as to a particular thickness. However, in a current aspect of the present invention, the thickness of the silicon layer 14 can be optimized for particular individual devices formed on the wafer, h this manner, a semiconductor device can be provided with different portions, each portion having a silicon layer 14 with a thickness that differs from another portion. The invention is also not limited in the manner in which the thickness of the silicon layer 14 of each portion is modified. Two exemplary methods of modifying the thickness of the silicon layer 14 are respectively illustrated in Figs. 1A-D and 2A-D.
• a photoresist 22 is formed over the silicon layer 14, and in Fig. 1C, the photoresist 22 is selectively irradiated using a photolithographic system, such as a step and repeat optical projection system, in which ultraviolet light from a mercury-vapor lamp is projected through a first reticle and a focusing lens to obtain a first image pattern.
• the photoresist 22 is then developed, and the irradiated portions of the photoresist 22 are removed to provide openings in the photoresist 22.
• the openings expose portions of the silicon layer 14, which will thereby define the portions of the silicon layer 14 having a modified thickness.
• An etch typically anisotropic, although not limited in this manner, is then applied to remove a certain thickness of the exposed portions of the silicon layer 14.
• isolation features 18 can be provided in the silicon layer 14.
• the invention is not limited in the manner in which the isolation features 18 are formed.
• a shallow isolation trench can be formed by etching either isotropically with wet techniques or anisotropically with dry etch techniques. An oxide is thereafter deposited within the trench.
• a field oxide can be formed. A field oxide is typically formed via thermal oxidation in an oxygen-steam ambient at temperatures from about 850 to 1050°C.
• a patterned, oxidation-resistant mask can be used to prevent oxidation of non-isolation device regions.
• the mask is removed using known techniques, for example hot phosphoric acid for a silicon nitride mask or buffered hydrofluoric acid for a pad oxide mask.
• the isolation features 18 can be formed before the thickness of certain portions of the silicon layer 14 are modified.
• a hard mask can be formed over the silicon layer 14 to aid in etching of the silicon layer 14.
• the isolation features 18 are formed in the silicon layer 14, and as described above, the invention is not limited in the manner in which the isolation features 18 are formed.
• a mask layer 20 is formed over the silicon layer 14, and the invention is not limited as to a particular mask layer 20.
• the mask layer 20 can be formed from an anti- reflective film, which can be advantageously used during fine line patterning.
• the mask layer 20 is formed from silicon nitride.
• a photoresist 22 is formed over the mask layer 20.
• the photoresist 22 is selectively irradiated using a photolithographic system, such as a step and repeat optical projection system, in which ultraviolet light from a mercury-vapor lamp is projected through a first reticle and a focusing lens to obtain a first image pattern.
• the photoresist 22 is then developed, and the irradiated portions of the photoresist 22 are removed to provide openings in the photoresist 22.
• the openings expose portions of the mask layer 20.
• a portion of the exposed mask layer 20 below the openings in the photoresist 22 is then removed, which exposes portions of the silicon layer 14 to be modified.
• the exposed portions of the silicon layer 14 are partially removed, and the invention is not limited in the manner in which the exposed portions of the silicon layer 14 are partially removed.
• the exposed portions of the silicon layer 14 can be partially removed using an etch, such as an anisotropic etch.
• the amount of the exposed portions of the silicon layer 14 being removed can be determined, for example, by subjecting the exposed portions of the silicon layer 14 to the etch for a given time, as the removal rate of silicon for a given etchant is known.
• Another example of partially removing exposed portions of the silicon layer 14 involves oxidizing the exposed portions of the silicon layer 14 to form silicon oxide. The silicon oxide can then be removed leaving only the silicon layer 14.
• An advantage of using this process is that the consumption of silicon to form silicon oxide can be very closely controlled, and this allows for precise control of the partial removal of the exposed portions of the silicon layer 14.
• a semiconductor device having different portions, with each portion having a silicon layer 14 with a thickness that differs from another portion is provided. Once the thickness of certain portions of the silicon layer 14 has been modified, features, such as transistors although not limited in this manner, can be formed in the silicon layer 14, as illustrated in Fig. 4.
• the features can include a gate dielectric 16 and a gate electrode 24 over the gate dielectric 16.
• Sidewall spacers 36, 38 can be formed on sidewalls 26, 28 of the gate electrode 24, and source/drain extensions 30, 32 can be formed in the silicon layer 14 underneath the sidewall spacers 36, 38.
• source/drain regions 40, 42 can be formed in the silicon layer 14. As shown, the source/drain regions 40a, 42a in a first portion of the semiconductor device can have different depths than the source/drain regions 40b, 42b in a second portion of the semiconductor device.
• the isolation features 18 can be removed, and the mvention is not limited as to the manner in which the isolation features 18 are removed.
• the isolation features 18 can be removed using an etchant having a high selectivity to the material with which the isolation features 18 are formed.
• the silicon layer 14 between the isolation features 18 can be relaxed.
• the silicon layer 14 is stressed, and this stressing of the silicon layer 14 can degrade transistor performance.
• the removal of the relaxing of the silicon layer 14, for example by removing the isolation features between adjacent silicon layers 14, is not limited to semiconductor devices having portions with different depths.
• the relaxing of the silicon layer 14 can occur for semiconductor devices having a silicon layer 14 with a single depth.
• NMOS and PMOS transistors can be optimized. For example, a transistor with a dopant (e.g., boron) that has a greater diffusion rate in silicon can be formed on a portion of the silicon layer having a greater thickness than a portion of the silicon layer upon which another transistor, with a dopant (e.g., arsenic) with a lower diffusion rate, is formed.
• a dopant e.g., arsenic
• Another advantage of providing a semiconductor device having different portions, with each portion having a silicon layer with a thickness that differs from another portion, is that both fully and partially depleted transistors can be easily formed.
• a partially depleted transistor can be formed on a portion of the silicon layer having a greater thickness
• a fully depleted transistor can be formed on a portion of the silicon layer with a lesser thickness.
• floating body effects can be minimized by eliminating the neutral region between the source/drain region and the insulating layer by making all transistors fully depleted.
• the present invention can be practiced by employing conventional materials, methodology and equipment.

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• Thin Film Transistor (AREA)
• Element Separation (AREA)
• Recrystallisation Techniques (AREA)
• Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

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• 2001
  • 2001-12-20 US US10/023,350 patent/US6764917B1/en not_active Expired - Fee Related
• 2002
  • 2002-12-19 KR KR1020047009734A patent/KR100948938B1/ko not_active Expired - Fee Related
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  • 2002-12-19 AU AU2002357367A patent/AU2002357367A1/en not_active Abandoned
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