US8179714B2 - Nonvolatile storage device and method for writing into memory cell of the same - Google Patents

Nonvolatile storage device and method for writing into memory cell of the same Download PDF

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US8179714B2
US8179714B2 US12/865,193 US86519309A US8179714B2 US 8179714 B2 US8179714 B2 US 8179714B2 US 86519309 A US86519309 A US 86519309A US 8179714 B2 US8179714 B2 US 8179714B2
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variable resistance
memory cell
writing
voltage
storage device
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US20110007553A1 (en
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Takeshi Takagi
Shunsaku Muraoka
Mitsuteru Iijima
Ken Kawai
Kazuhiko Shimakawa
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Nuvoton Technology Corp Japan
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Panasonic Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0064—Verifying circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/0083—Write to perform initialising, forming process, electro forming or conditioning
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/009—Write using potential difference applied between cell electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/30—Resistive cell, memory material aspects
    • G11C2213/32—Material having simple binary metal oxide structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/50—Resistive cell structure aspects
    • G11C2213/56—Structure including two electrodes, a memory active layer and a so called passive or source or reservoir layer which is NOT an electrode, wherein the passive or source or reservoir layer is a source of ions which migrate afterwards in the memory active layer to be only trapped there, to form conductive filaments there or to react with the material of the memory active layer in redox way
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/79—Array wherein the access device being a transistor

Definitions

  • the present invention relates to a nonvolatile storage device having memory cells each of which includes a transistor and a variable resistance element whose resistance value reversibly changes based on electrical signals.
  • variable resistance element is an element with a property that its resistance state reversibly changes between a low resistance state and a high resistance state based on electrical signals, and can store information corresponding to the resistance state in a nonvolatile manner.
  • nonvolatile storage device that includes variable resistance elements
  • a nonvolatile storage device which includes memory cells, referred to as 1T1R (1 Transistor 1 Resistor) memory cells, arranged in a matrix at positions at which bit lines intersect with word lines and source lines that are arranged orthogonally to the bit lines.
  • each of the memory cells includes a MOS transistor and a variable resistance element that are connected in series.
  • Patent Literature 1 discloses a nonvolatile storage device including 1T1R memory cells in which oxides having a perovskite-type crystalline structure are used as variable resistance elements.
  • FIG. 18 is a schematic cross-sectional view of a conventional memory cell described in Patent Literature 1.
  • a memory cell 1011 includes: a source region 1002 serving as a first diffusion layer region and a drain region 1003 serving as a second diffusion layer region that are formed on a semiconductor substrate 1001 ; a selection transistor 1006 including a gate electrode 1005 formed on a gate oxide film 1004 ; and a variable resistance element 1010 formed by having, between a lower electrode 1007 and an upper electrode 1009 , a variable resistance material 1008 whose resistance value changes upon voltage application.
  • the drain region 1003 and the lower electrode 1007 that are electronically connected are connected in series via a conductive via.
  • Patent Literature 1 discloses Pr 1-x Ca x MnO 3 (PCMO), La 1-x Sr x MnO 3 (LSMO) and so on as the variable resistance material 1008 .
  • variable resistance elements In order for the nonvolatile storage device including such variable resistance elements to stably operate, it is necessary to surely change a resistance value of each of the variable resistance elements. To surely change the resistance value of each variable resistance element, there is a case where it is necessary to temporarily apply a higher voltage than a voltage used in normal writing to the variable resistance element.
  • the present invention has been devised in view of such a situation, and has a main object to provide a nonvolatile storage device capable of stably operating without increasing the size of the selection transistor included in each of memory cells.
  • a nonvolatile storage device includes: a semiconductor substrate which has a region of a first conductivity type; a memory cell array which includes memory cells each of which includes a variable resistance element and a transistor that are connected in series and formed above the semiconductor substrate; a selection circuit which selects, from among the memory cells included in the memory cell array, at least one memory cell by applying a voltage pulse to a gate of the transistor included in the at least one memory cell; a write circuit which applies a voltage pulse Jar writing to the variable resistance element included in the at least one memory cell selected by the selection circuit, via the transistor included in the at least one memory cell; and a substrate bias circuit which applies a first bias voltage to the semiconductor substrate, wherein the variable resistance element included in each of the memory cells includes: a first electrode; a second electrode; and a variable resistance layer which is interposed between the first and second electrodes and whose resistance state reversibly changes between a low resistance state and a high resistance state based on a voltage
  • a bias voltage is applied, when writing into a memory cell, to a substrate of a selection transistor included in the memory cell in a forward direction with respect to the selection transistor, and thus a substrate bias effect reduces on-resistance of the selection transistor and causes a large voltage corresponding to the reduction to be applied to a variable resistance element accordingly.
  • the present invention can be realized not only as the nonvolatile storage device but also as a method for writing into memory cells in the nonvolatile storage device.
  • the nonvolatile storage device makes it possible for the resistance value of the variable resistance element to surely change without increasing the size of the selection transistor included in the memory cell, and thus can stably operate.
  • FIG. 1 is a cross-sectional view of a configuration of a variable resistance element included in a nonvolatile storage device in Embodiment 1 of the present invention.
  • FIG. 2( a ) to ( c ) is a cross-sectional view of a manufacturing process of a variable resistance element included in a nonvolatile storage device in Embodiment 1 of the present invention.
  • FIG. 3 is a cross-sectional view of a configuration of a nonvolatile storage device according to Embodiment 1 of the present invention.
  • FIG. 4 is a graph showing a relationship between a voltage effectively applied to a variable resistance element (voltage applied to an element) when a predetermined voltage is applied to both ends of a memory cell and a resistance value of the variable resistance element (element resistance value).
  • FIG. 5 is a block diagram showing a configuration of a nonvolatile storage device according to Embodiment 1 of the present invention.
  • FIG. 6 is a cross-sectional view showing a configuration (2-bit configuration) of a part C shown in FIG. 5 .
  • FIG. 7( a ) to ( c ) is a timing diagram showing an operation example of a nonvolatile storage device according to Embodiment 1 of the present invention.
  • FIG. 8 is a flowchart showing an operation example of a nonvolatile storage device according to Embodiment 1 of the present invention.
  • FIGS. 9( a ) and ( b ) is a timing diagram showing an operation example of a nonvolatile storage device according to Embodiment 2 of the present invention.
  • FIG. 10 is a flowchart showing an operation example of a nonvolatile storage device according to Embodiment 3 of the present invention.
  • FIGS. 11( a ) and ( b ) is a graph showing a change of a resistance state of a variable resistance element included in a nonvolatile storage device in Embodiment 3 of the present invention.
  • FIGS. 12( a ) and ( b ) is a graph showing a distribution of resistance values in the case where a variable resistance element is rewritten one hundred times in Embodiment 4 of the present invention.
  • FIG. 13 is a flowchart showing an operation example of a nonvolatile storage device according to Embodiment 4 of the present invention.
  • FIGS. 14( a ) and ( b ) is a timing diagram showing an operation example of a nonvolatile storage device according to Embodiment 4 of the present invention.
  • FIG. 15 is a graph showing a change of a resistance state caused by additional writing into a single variable resistance element in Embodiment 5 of the present invention.
  • FIG. 16( a ) is a flowchart showing an operation example of a nonvolatile storage device according to Embodiment 5 of the present invention
  • FIG. 16( b ) is a flowchart showing a detailed procedure of a writing step (S 41 ) in FIG. 16( a ).
  • FIG. 17 is a flowchart showing an operation example of a nonvolatile storage device according to Embodiment 6 of the present invention.
  • FIG. 18 is a schematic view showing a cross section of a conventional memory cell.
  • a nonvolatile storage device includes: a semiconductor substrate which has a region of a first conductivity type; a memory cell array which includes memory cells each of which includes a variable resistance element and a transistor that are connected in series and formed above the semiconductor substrate; a selection circuit which selects, from among the memory cells included in the memory cell array, at least one memory cell by applying a voltage pulse to a gate of the transistor included in the at least one memory cell; a write circuit which applies a voltage pulse for writing to the variable resistance element included in the at least one memory cell selected by the selection circuit, via the transistor included in the at least one memory cell; and a substrate bias circuit which applies a first bias voltage to the semiconductor substrate, wherein the variable resistance element included in each of the memory cells includes: a first electrode; a second electrode; and a variable resistance layer which is interposed between the first and second electrodes and whose resistance state reversibly changes between a low resistance state and a high resistance state based on a voltage pulse applied between the first and second electrodes
  • a bias voltage is applied, when writing into a memory cell, to a substrate of a selection transistor included in the memory cell in a forward direction with respect to the selection transistor, and thus a substrate bias effect reduces on-resistance of the selection transistor and causes a large voltage corresponding to the reduction to be applied to a variable resistance element.
  • a substrate bias effect reduces on-resistance of the selection transistor and causes a large voltage corresponding to the reduction to be applied to a variable resistance element.
  • writing into a nonvolatile storage device and “writing into a memory cell” or simply the term “writing” strictly means writing into a variable resistance element included in a memory cell (including both a transition from a low resistance state to a high resistance state and a transition from the high resistance state to the low resistance state).
  • a “selection transistor” is simply referred to as a “transistor”.
  • a voltage may be lower than a threshold voltage with which a current flows from a connected P-type semiconductor to an N-type semiconductor.
  • the substrate bias circuit may apply the first bias voltage in the case where a resistance value of the variable resistance layer is an initial resistance value that is a resistance value when a voltage pulse has not yet been applied since the variable resistance element is manufactured, the variable resistance layer being included in the variable resistance element included in the at least one memory cell selected by the selection circuit.
  • the present invention may be limited to a case where a memory cell is initialized, as writing into the memory cell in which a substrate bias voltage is applied. With this, in an initialization process for which a voltage larger than a voltage in normal writing is required, the substrate bias effect reduces the on-resistance of the selection transistor and causes the large voltage corresponding to the reduction to be applied to the variable resistance element, and thus the initialization process is more surely performed.
  • the substrate bias circuit may apply the first bias voltage in the case where the resistance state of the variable resistance layer is changed from the low resistance state to the high resistance state, the variable resistance layer being included in the variable resistance element included in the at least one memory cell selected by the selection circuit.
  • the present invention may be limited to a case where the resistance state of the variable resistance element is changed from the low resistance state to the high resistance state (that is, “high resistance writing”, or “HR writing”, for short), as the writing into the memory cell in which the substrate bias voltage is applied.
  • the substrate bias effect reduces the on-resistance of the selection transistor and causes the large voltage corresponding to the reduction to be applied to the variable resistance element, and thus suppressed is variation in the resistance value of the variable resistance element in the high resistance state that is unstable in comparison to the low resistant state.
  • the substrate bias circuit may apply the first bias voltage in the case where additional writing is performed on the variable resistance element after writing for changing the resistance state of the variable resistance layer is unsuccessful, the variable resistance layer being included in the variable resistance element included in the at least one memory cell selected by the selection circuit.
  • the present invention may be limited to a case where additional writing is performed on the memory cell, as writing into the memory cell in which the substrate bias voltage is applied. With this, in the additional writing for which a voltage larger than the voltage in the normal writing is required, the substrate bias effect reduces the on-resistance of the selection transistor and causes the large voltage corresponding to the reduction to be applied to the variable resistance element, and the additional writing is accomplished more surely (or with a fewer number of times).
  • the substrate bias circuit may apply the first bias voltage in the case where writing has been performed on the variable resistance element a predetermined number of times, the variable resistance element being included in the at least one memory cell selected by the selection circuit.
  • the present invention may be limited to a refresh process, that is, a case where the writing is performed with a larger voltage for writing when the writing has been performed a certain number of times, as the writing into the memory cell in which the substrate bias voltage is applied.
  • the region of the first conductivity type of the semiconductor substrate may be a well of the first conductivity type formed in the semiconductor substrate, and the substrate bias circuit may apply the first bias voltage to the well.
  • the selection transistor included in the memory cell may be formed within the well formed in the semiconductor substrate.
  • the nonvolatile storage device may include a source line bias circuit which applies, to a source of a transistor included in a memory cell not selected by the selection circuit, a second bias voltage for suppressing a current flowing through the transistor.
  • a source line bias circuit which applies, to a source of a transistor included in a memory cell not selected by the selection circuit, a second bias voltage for suppressing a current flowing through the transistor.
  • FIG. 1 is a cross-sectional view of a configuration of a variable resistance element included in a nonvolatile storage device in Embodiment 1 of the present invention.
  • a variable resistance element 100 includes: a substrate 101 ; an oxide layer 102 formed on the substrate 101 ; a lower electrode 103 formed on the oxide layer 102 (an example of a first electrode or a second electrode according to the present invention); a variable resistance layer 104 formed on the lower electrode 103 ; and an upper electrode 105 formed on the variable resistance layer 104 (an example of the second electrode or the first electrode according to the present invention).
  • the lower electrode 103 and the upper electrode 105 are electrically connected to the variable resistance layer 104 .
  • variable resistance element may include at least the lower electrode 103 , the variable resistance layer 104 , and the upper electrode 105 .
  • the substrate 101 may be, for instance, a silicon single crystal substrate or a semiconductor substrate. However, the substrate 101 is not limited to these substrates.
  • the variable resistance layer 104 can be formed at a relatively low substrate temperature and thus can be formed on a resin material and the like.
  • the materials of the lower electrode 103 and the upper electrode 105 are, for example, one or more of Au (gold), Pt (platinum), Ir (iridium), Pd (palladium), Ag (silver), and Cu (copper).
  • the variable resistance layer 104 is a layer including a metal oxide whose resistance state reversibly changes between a low resistance state and a high resistance state based on a voltage pulse applied between the lower electrode 103 and the upper electrode 105 , and has a stacked structure including a first metal oxide layer and a second metal oxide layer whose oxygen content percentage is higher than that of the first metal oxide layer.
  • the variable resistance layer 104 is formed by stacking a first tantalum oxide layer 104 a , an example of the first metal oxide layer, and a second tantalum oxide layer 104 b , an example of the second metal oxide layer.
  • an oxygen content percentage of the second tantalum oxide layer 104 b is higher than that of the first tantalum oxide layer 104 a.
  • variable resistance element 100 configured as described above can be manufactured in the following manner.
  • FIG. 2( a ) to ( c ) is a cross-sectional view of an example of a manufacturing process of the variable resistance element 100 included in the nonvolatile storage device according to Embodiment 1 of the present invention.
  • thermal oxidation produces the oxide layer 102 having a thickness of 200 nm on the substrate 101 made of single-crystal silicon. Then, by sputtering, a Pt thin film having a thickness of 100 nm is formed on the oxide layer 102 as the lower electrode 103 . After that, the first tantalum oxide layer 104 a is formed on the lower electrode 103 by reactive sputtering, with Ta used as a target.
  • deposition of the first tantalum oxide layer 104 a can be performed under the following condition. In other words, after a substrate is placed in a sputtering apparatus, inside the sputtering apparatus is vacuumed to almost 8 ⁇ 10 ⁇ 6 Pa. Then, the sputtering is performed for 20 seconds with tantalum used as the target, power set to 1.6 kW, a flow of an argon gas at 34 sccm, a flow of an oxygen gas at 21 sccm, and the pressure in the sputtering apparatus kept at 0.17 Pa. With this, the first tantalum oxide layer 104 a can be deposited with a thickness of 30 nm, a resistivity of 6 m ⁇ cm, and an oxygen content percentage of about 61 at % (TaO 1.6 )
  • the top surface of the first tantalum oxide layer 104 a is oxidized to modify the surface property.
  • the oxidation treatment forms a second tantalum oxide layer 104 b having an oxygen content percentage higher than that of the first tantalum oxide layer 104 a .
  • the film thickness of the second tantalum oxide layer 104 b is 5 nm.
  • a Pt thin film having a thickness of 150 nm is formed on the second tantalum oxide layer 104 b as the upper electrode 105 .
  • the upper electrode 105 is preferably formed immediately after the deposition of the second tantalum oxide layer 104 b .
  • photolithography processing creates a pattern 106 using a photoresist, and dry etching produces an element region 107 (see FIG. 2( c )).
  • the element region 107 here is assumed to be a rectangle with each side being, for example, 0.5 ⁇ m in length.
  • FIG. 3 is a cross-sectional view of a configuration of one of memory cells 300 each of which includes the variable resistance element manufactured as described above and which constitute a memory cell array included in the nonvolatile storage device according to Embodiment 1 of the present invention. Peripheral components connected to the memory cell 300 are also shown here together. It is to be noted that a memory cell is a storage element including a variable resistance element and a selection transistor that are connected in series in the present embodiment.
  • a semiconductor substrate 301 is, for instance, an N-type silicon substrate, and includes a region of a first conductivity type (P-type well (P-type diffusion layer) 301 a in the present embodiment) for forming a transistor 317 .
  • P-type well P-type diffusion layer
  • the transistor 317 (a first N-type diffusion layer region 302 a , a second N-type diffusion layer region 302 b , a gate insulator film 303 a , and a gate electrode 303 b ), a first via 304 , a first wiring layer 305 , a second via 306 , a second wiring layer 307 , a third via 308 , a variable resistance element 309 , a fourth via 310 , and a third wiring layer 311 are formed above the semiconductor substrate 301 in this order.
  • first N-type diffusion layer region 302 a and the second N-type diffusion layer region 302 b included in the transistor 317 are examples of a first diffusion region of second conductivity type and a second diffusion region of the second conductivity type according to the present invention, respectively.
  • the third wiring layer 311 connected to the fourth via 310 serves as a bit line BL 0
  • the first wiring layer 305 and the second wiring layer 307 which are electrically connected to the first N-type diffusion layer region 302 a of the transistor 317 serve as a source line SL 0 .
  • the transistor 317 is an NMOS transistor formed in the P-type well 301 a formed in the semiconductor substrate 301 .
  • a substrate terminal BB 0 is connected to the P-type well 301 a , and further connected to a substrate bias circuit (not shown).
  • the substrate bias circuit can apply a forward substrate bias voltage (a first bias voltage according to the present invention) to a substrate region of the transistor 317 with respect to diffusion regions (the first N-type diffusion layer region 302 a and the second N-type diffusion layer region 302 b ) of a source and a drain of the transistor 317 , by applying a voltage to the P-type well 301 a via the substrate terminal BB 0 . With this, a substrate potential of the transistor 317 is controlled.
  • the phrase “apply a forward substrate bias voltage” means applying a voltage in a forward direction to (i) a substrate region (or a well) of a first conductivity type in which a transistor is formed and (ii) a diffusion region of a second conductivity type in which the source and drain of the transistor are formed, and specifically means applying a positive voltage to the substrate region of the first conductivity type with reference to the diffusion region of the second conductivity type in the case where the substrate region of the first conductivity type is a P-type semiconductor and the diffusion region of the second conductivity type is an N-type semiconductor and inversely applying a negative voltage to the substrate region of the first conductivity type with reference to the diffusion region of the second conductivity type in the case where the substrate region of the first conductivity type is the N-type semiconductor and the diffusion region of the second conductivity type is the P-type semiconductor.
  • the variable resistance element 309 has a stacked structure in which the lower electrode 309 a , the variable resistance layer 309 b , and the upper electrode 309 c are formed above the third via 308 .
  • the lower electrode 309 a is connected to the third via 308 connected to the second wiring layer 307
  • the upper electrode 309 c is connected to the fourth via 310 connected to the third wiring layer 311 .
  • the lower electrode 309 a and the upper electrode 309 c are made of the same material, which is Pt (platinum), in the present embodiment.
  • the lower electrode 309 a is connected to the second N-type diffusion layer region 302 b of the transistor via the vias and the wiring layers, and the upper electrode 309 c is connected to the third wiring layer 311 (bit line BL 0 ) via the via.
  • the memory cell includes the transistor 317 and the variable resistance element 309 that are connected in series, and more specifically includes the vias and wiring layers connecting those.
  • applying the forward bias voltage to the substrate of the transistor reduces the on-resistance of the transistor and increases a voltage to be applied to the variable resistance element, which surely enables a resistance change to occur. With this, it is possible to realize a good storage device without increasing the gate width W of the transistor. Focusing on the gate width W of the transistor, the following describes the characteristics of the nonvolatile storage device according to the present embodiment.
  • FIG. 4 is a graph showing a relationship between (i) a voltage effectively applied to the variable resistance element (“voltage applied to an element (V)” indicated by the vertical axis) and (ii) a resistance value of the variable resistance element (“element resistance value ( ⁇ )” indicated by the horizontal axis) when respective predetermined voltages are applied to one ends of the source line SL 0 and the bit line BL 0 after the transistor 317 is turned on by applying a voltage sufficiently higher than a threshold voltage of the transistor 317 to the gate electrode 303 b of the transistor 317 of the memory cell which includes the transistor 317 and the variable resistance element 309 that are shown in FIG. 3 and connected in series.
  • a result obtained through a simulation performed by a computer is plotted.
  • a relationship between a voltage applied to an element and an element resistance value when a resistance state of the variable resistance element is changed from a low resistance state to a high resistance state (when a positive voltage is applied) is represented by a graph A 1
  • a relationship between the voltage applied to the element and the element resistance value when the resistance state of the variable resistance element is changed from the high resistance state to the low resistance state (when a negative voltage is applied) is represented by a graph A 2 .
  • the positive voltage is a voltage to be applied to the upper electrode with reference to the lower electrode
  • the negative voltage is a voltage to be applied to the lower electrode with reference to the upper electrode.
  • the substrate bias voltage as described in the present embodiment is not applied in the graphs A 1 and A 2 .
  • the substrate bias voltage as described in the present embodiment is not applied in the graphs B 1 and B 2 .
  • a relationship between the voltage applied to the element and the element resistance value when the resistance state of the variable resistance element is changed from the low resistance state to the high resistance state (when the positive voltage is applied) is represented by a graph C 1
  • a relationship between the voltage applied to the element and the element resistance value when the resistance state of the variable resistance element is changed from the high resistance state to the low resistance state (when the negative voltage is applied) is represented by a graph C 2 .
  • FIG. 4 which shows the result of the simulation performed under the above conditions
  • a comparison of the graphs A 1 and B 1 shows that even when the same voltage is applied to the memory cell, the voltage applied to the element is lower in the case where the gate width W of the transistor is small.
  • a resistance value (on-resistance) in the case where the transistor is in on-state decreases inversely proportional to the gate width W of the transistor and the on-resistance of the transistor increases in the case where W is small, which results in the increase in the voltage applied to the transistor and the decrease in the voltage applied to the variable resistance element.
  • a comparison of the graphs B 1 and C 1 shows that even when the same voltage is applied to the memory cell including the transistor having the same gate width W, the voltage applied to the element can be increased by applying the substrate bias voltage described in the present embodiment. This holds true with a comparison of the graphs B 2 and C 2 . This is because application of a forward substrate bias voltage reduces the threshold voltage of the transistor and the on-resistance, which results in the decrease in the voltage applied to the transistor and the increase in the voltage applied to the variable resistance element.
  • the application of the substrate bias voltage described in the present embodiment allows the increase in the voltage applied to the element without increasing the gate width W of the transistor, which enables the resistance value of the variable resistance element to surely change. Therefore, it is possible to achieve the stable operations of the nonvolatile storage device.
  • the threshold voltage decreases the threshold voltage of the transistor, but an excessive increase in the substrate bias voltage turns on a PN junction diode formed in the P-type well and the N-type diffusion region of the transistor, and a current flows from the P-type well to the variable resistance element. It is necessary to set the threshold voltage to 0.7 V or less, because generally a diffusion potential of the PN diode made of silicon is approximately 0.7 V. More specifically, 0.5 V or less is desirable in order to more surely prevent a phenomenon in which the current flows from the P-type well to the variable resistance element.
  • a P-channel MOS transistor may be certainly used in the present invention.
  • conductivity types of the diffusion regions of the well and the transistor come to have a polarity which is reverse of the polarity of the N-channel MOS, and a polarity of the substrate bias voltage applied to the well becomes a reverse polarity.
  • the following describes a configuration example of the above-described nonvolatile storage device according to the present embodiment with reference to FIG. 5 .
  • FIG. 5 is a block diagram showing a configuration of the nonvolatile storage device according to Embodiment 1 of the present invention.
  • a nonvolatile storage device 200 includes a memory main body 201 on a semiconductor substrate.
  • the memory main body 201 includes: a memory cell array 202 having 1T1R memory cells arranged in a matrix; a row selection circuit 208 ; a row driver 207 including word line drivers WLD and source line drivers SLD; a column selection circuit 203 ; a write circuit 206 for writing information; a sense amplifier 204 which detects an amount of current flowing in a selected bit line and determines whether data indicates “1” or “0”; a data input and output circuit 205 which performs an input and output process of input and output data via a terminal DQ; and a substrate bias circuit 220 for applying a forward bias voltage to a substrate of a selection transistor provided to the memory array 202 .
  • the nonvolatile storage device 200 includes, as a power source for writing 211 , a power source for low resistance (LR) writing 212 and a power source for high resistance (HR) writing 213 .
  • the low resistance (LR) writing means that the resistance state of the variable resistance element is changed from the high resistance state to the low resistance state
  • the high resistance (HR) writing means that the resistance state of the variable resistance element is changed from the low resistance state to the high resistance state.
  • An output V 2 of the power source for LR writing 212 is provided to the row driver 207
  • an output V 1 of the power source for HR writing 213 is provided to the write circuit 206 .
  • the nonvolatile storage device 200 includes: an address input circuit 209 which receives an address signal externally inputted; and a control circuit 210 which controls operations of the memory main body 201 based on a control signal externally inputted.
  • the memory cell array 202 is formed by two-dimensionally arranging the memory cells each of which includes the variable resistance element and the transistor that are connected in series.
  • the memory cell array 202 includes: word lines WL 0 , WL 1 , WL 2 . . . ; bit lines BL 0 , BL 1 , BL 2 . . . ; source lines SL 0 , SL 2 . . . ; NMOS transistors N 11 , N 12 , N 13 , N 21 , N 22 , N 23 , N 31 , N 32 , N 33 . . . (hereinafter, referred to as “transistors N 11 , N 12 . . .
  • variable resistance elements R 11 , R 12 , R 13 , R 21 , R 22 , R 23 , R 31 , R 32 , R 33 . . . (hereinafter, referred to as “variable resistance elements R 11 , R 12 . . . ”).
  • the word lines and the bit lines are formed above the semiconductor substrate and arranged to intersect with each other.
  • the source lines each are provided at between two of the adjacent word lines WL 0 , WL 1 , WL 2 . . . .
  • the transistors N 11 , N 12 . . . are provided at corresponding points where the word lines WL 0 , WL 1 , WL 2 . . .
  • variable resistance elements R 11 , R 12 . . . are connected in series with the transistors N 11 , N 12 . . . on a one-on-one basis.
  • the 1T1R memory cells M 11 , M 12 , M 13 , M 21 , M 22 , M 23 , M 31 , M 32 , M 33 . . . (hereinafter, referred to as “memory cells M 11 , M 12 . . . ”) are arranged in the matrix, and each of the memory cells M 11 , M 12 . . .
  • gates of the transistors N 11 , N 21 , N 31 . . . are connected to the word line WL 0
  • gates of the transistors N 12 , N 22 , N 32 . . . are connected to the word line WL 1
  • gates of the transistors N 13 , N 23 , N 33 . . . are connected to the word line WL 2 , respectively.
  • the transistors N 11 , N 21 , N 31 . . . and the transistors N 12 , N 22 , N 32 . . . are commonly connected to the source line SL 0
  • the transistors N 13 , N 23 , N 33 . . . and the transistors N 14 , N 24 , N 34 . . . are commonly connected to the source line SL 2 .
  • one of terminals of each of the variable resistance elements R 11 , R 12 , R 13 . . . is connected to the bit line BL 0
  • the other terminal of each of the variable resistance elements R 21 , R 22 , R 23 . . . is connected to the bit line BL 1
  • one of terminals of each of the variable resistance elements R 31 , R 32 , R 33 . . . is connected to the bit line BL 2 .
  • variable resistance element is represented by a symbol of variable resistance in FIG. 5 .
  • An arrow direction shown on the symbol of variable resistance indicates that the resistance state of the variable resistance element is changed from the low resistance state to the high resistance state when the positive voltage is applied in the arrow direction (to the head of the arrow with reference to the back end of the arrow).
  • the address input circuit 209 receives an address signal from an external circuit (not shown), and simultaneously outputs a row address signal to the row selection circuit 208 and a column address signal to the column selection circuit 203 based on the address signal.
  • the address signal is a signal indicating an address of a specific memory cell to be selected from among the memory cells M 11 , M 12 . . . .
  • the row address signal is a signal indicating an address of a row which is a part of the address indicated by the address signal
  • the column address signal is similarly a signal indicating an address of a column which is a part of the address indicated by the address signal.
  • the row selection circuit 208 and the column selection circuit 203 are an example of a selection circuit according to the present invention which selects at least one memory cell by applying a voltage pulse to the gate of the transistor N 11 or the like included in the at least one memory cell among the memory cell M 11 and the like included in the memory cell array 202 .
  • control circuit 210 In a data write cycle, the control circuit 210 outputs, to the write circuit 206 , a write command signal instructing application of a voltage for writing, according to input data Din inputted into the data input and output circuit 205 . On the other hand, in a data read cycle, the control circuit 210 outputs, to the sense amplifier 204 , a read command signal instructing a read operation.
  • the row selection circuit 208 receives the row address signal outputted from the address input circuit 209 , and selects one of the word lines WL 0 , WL 1 , WL 2 . . . according to the row address signal.
  • the row driver 207 applies a predetermined voltage to the word line selected by the row selection circuit 208 , based on an output signal of the row selection circuit 208 .
  • the row selection circuit 208 receives the row address signal outputted from the address input circuit 209 , and selects one of the source lines SL 0 , SL 2 . . . according to the row address signal.
  • the row driver 207 applies a predetermined voltage to the source line selected by the row selection circuit 208 , based on the output signal of the row selection circuit 208 .
  • the column selection circuit 203 receives the column address signal outputted from the address input circuit 209 , selects one of the bit lines BL 0 , BL 1 , BL 2 . . . according to the column address signal, and applies a voltage for writing or a voltage for reading to the selected bit line.
  • the write circuit 206 is a circuit which applies a voltage pulse for writing to the variable resistance element included in the memory cell selected by the selection circuit according to the present invention via the transistor included in the memory cell.
  • the write circuit 206 outputs, to the column selection circuit 203 , a signal instructing the application of the voltage for writing to the selected bit line in the case where the write circuit 206 has received the write command signal outputted from the control circuit 210 .
  • the term “writing” involves the low resistance (LR) writing (writing “0”) which changes the resistance state of the variable resistance element from the high resistance state to the low resistance state and the high resistance (HR) writing (writing “1”) which inversely changes the resistance state of the variable resistance element from the low resistance state to the high resistance state.
  • the sense amplifier 204 detects an amount of a current flowing in the selected bit line to be read, and determines whether data indicates “1” or “0”.
  • the resultant output data DO is outputted to the external circuit via the data input output circuit 205 .
  • the substrate bias circuit 220 can apply substrate bias voltages to the transistors N 11 , N 12 . . . provided to the memory cell array 202 by controlling the potential of the P-type well 301 a where the memory cell array 202 is formed. The details of the above operation are to be described later.
  • FIG. 6 is a cross-sectional view showing a configuration (2-bit configuration) of a part C shown in FIG. 5 .
  • the transistor 317 and the variable resistance element 309 in FIG. 6 correspond to the transistors N 11 , N 12 . . . and the variable resistance elements R 11 , R 12 . . . in FIG. 5 , respectively.
  • the transistor 317 (the first N-type diffusion layer region 302 a , the second N-type diffusion layer region 302 b , the gate insulator film 303 a , and the gate electrode 303 b ), the first via 304 , the first wiring layer 305 , the second via 306 , the second wiring layer 307 , the third via 308 , the variable resistance element 309 , the fourth via 310 , and the third wiring layer 311 are formed above the semiconductor substrate (N-type silicon substrate) 301 in this order.
  • the third wiring layer 311 connected to the fourth via 310 corresponds to the bit line BL 0 in FIG. 5
  • the first wiring layer 305 and the second wiring layer 307 electrically connected to the first N-type diffusion layer region 302 a of the transistor 317 correspond to the source line SL 0 in FIG. 5 .
  • the transistor 317 is formed in the P-type well 301 a (the region of the first conductivity type according to the present invention, more specifically, a well of the first conductivity type) formed in the semiconductor substrate 301 .
  • the substrate terminal BB 0 is connected to the P-type well 301 a , and further connected to a substrate bias circuit 220 .
  • the substrate bias circuit 220 can apply a forward substrate bias voltage to the transistor 317 by applying a voltage to the P-type well 301 a via the substrate terminal BB 0 . With this, the substrate potential of the transistor 317 is controlled.
  • the selection transistors included in the memory cell array are formed in the same P-type well 301 a , and the substrate potentials of the selection transistors can be controlled using one of the substrate terminals BB 0 .
  • the substrate potentials of the selection transistors can be controlled using one of the substrate terminals BB 0 .
  • the variable resistance element 309 has a stacked structure in which the lower electrode 309 a , the variable resistance layer 309 b , and the upper electrode 309 c are formed above the third via 308 .
  • the lower electrode 309 a is connected to the third via 308 connected to the second wiring layer 307
  • the upper electrode 309 c is connected to the fourth via 310 connected to the third wiring layer 311 .
  • the variable resistance layer 309 b has the stacked structure of the tantalum oxide layers.
  • the lower electrode 309 a and the upper electrode 309 c are made of the same material, which is Pt (platinum), in the present embodiment.
  • the lower electrode 309 a is connected to the second N-type diffusion layer region 302 b of the transistor via the vias, and the upper electrode 309 c is connected to the third wiring layer 311 (bit line BL 0 ) via the via.
  • the following describes operations of the nonvolatile storage device 200 thus configured, in a write cycle to write data and a read cycle to read data.
  • FIG. 7( a ) to ( c ) is a timing diagram showing an operation example of the nonvolatile storage device 200 according to Embodiment 1 of the present invention. It is to be noted that, here, the operation example is described with an assumption that data “1” corresponds to a case where a variable resistance layer is in a high resistance state and data “0” corresponds to a case where a variable resistance layer is in a low resistance state. Furthermore, in the following description, the memory cell M 11 in FIG. 5 is selected, and only cases of writing and reading data for the selected memory cell M 11 are described.
  • V 1 and V 2 indicate voltages generated by the power source for HR writing 213 and the power source for LR writing 212 , respectively, Vread indicates a voltage for reading generated by the sense amplifier 204 , and VDD indicates a power supply voltage supplied to the nonvolatile storage device 200 . Further, VB indicates a bias voltage generated by the substrate bias circuit 220 .
  • the column selection circuit 203 and the row selection circuit 208 set the selected bit line BL 0 and the source line SL 0 to a voltage V 2 (e.g., 2.2 V), respectively (the row selection circuit 208 does this via the row driver 207 ).
  • the row selection circuit 208 sets a word line WL 0 to be selected to the voltage VDD (e.g., 2.2 V) to turn on the NMOS transistor N 11 of the selected memory cell M 11 .
  • the substrate bias circuit 220 sets the substrate terminal BB 0 of the NMOS transistor N 11 to the bias voltage VB (e.g., 0.3 V).
  • the write circuit 206 sets, via the column selection circuit 203 , the selected bit line BL 0 to the voltage 0 V only for a predetermined time period, and subsequently outputs a voltage pulse for writing by setting the selected bit line BL 0 to the voltage V 2 again.
  • the voltage for writing is applied between the lower electrode 309 a and the upper electrode 309 c , and the resistance state of the variable resistance element 309 (R 11 ) is changed from the high resistance state to the low resistance state.
  • the row selection circuit 208 sets, via the row driver 207 , the word line WL 0 to the voltage 0 V to turn off the transistor 317 (NMOS transistor N 11 ), and the writing of the data “0” is completed.
  • the substrate bias circuit 220 applies the forward bias voltage to the substrate of the NMOS transistor N 11 , so that the threshold voltage of the NMOS transistor N 11 can be reduced. This makes it possible to increase the voltage applied to the variable resistance element R 11 . As a result, it is possible to surely change the resistance state of the variable resistance element R 11 from the high resistance state to the low resistance state.
  • the column selection circuit 203 and the row selection circuit 208 set the selected bit line BL 0 and the source line SL 0 to the voltage 0 V, respectively (the row selection circuit 208 does this via the row driver 207 ).
  • the row selection circuit 208 sets a word line WL 0 to be selected to the voltage VDD (e.g., 2.2 V) to turn on the NMOS transistor N 11 of the selected memory cell M 11 .
  • the substrate bias circuit 220 sets the substrate terminal BB 0 of the NMOS transistor N 11 to the bias voltage VB (e.g., 0.3 V).
  • the write circuit 206 sets, via the column selection circuit 203 , the selected bit line BL 0 to the voltage V 1 (e.g., 2.2 V) only for a predetermined time period, and sets the selected bit line BL 0 to the voltage 0 V again.
  • V 1 e.g., 2.2 V
  • the voltage for writing is applied between the lower electrode 309 a and the upper electrode 309 c , and the resistance state of the variable resistance element 309 (R 11 ) is changed from the low resistance state to the high resistance state.
  • the row selection circuit 208 sets, via the row driver 207 , the word line WL 0 to the voltage 0 V to turn off the transistor 317 (NMOS transistor N 11 ), and the writing of the data “1” is completed.
  • the substrate bias circuit 220 applies the forward bias voltage to the substrate of the NMOS transistor N 11 , so that the threshold voltage of the NMOS transistor N 11 can be reduced. This makes it possible to increase the voltage applied to the variable resistance element R 11 . Consequently, it is possible to surely change the resistance state of the variable resistance element R 11 from the low resistance state to the high resistance state.
  • the column selection circuit 203 and the row selection circuit 208 set the selected bit line BL 0 and the source line SL 0 to the voltage 0 V, respectively (the row selection circuit 208 does this via the row driver 207 ).
  • the row selection circuit 208 sets, via the row driver 207 , a word line WL 0 to be selected to the voltage VDD to turn on the NMOS transistor N 11 of the selected memory cell M 11 .
  • the sense amplifier 204 determines whether the data indicates “0” or “1” by setting, via the column selection circuit 203 , the selected bit line BL 0 to the voltage for reading Vread only for a predetermined time period and detecting a value of a current flowing in the selected memory cell M 11 .
  • the row selection circuit 208 sets, via the row driver 207 , the word line WL 0 to the voltage 0 V to turn off the transistor 317 (NMOS transistor N 11 ), and the reading of the data is completed.
  • FIG. 8 is a flowchart showing a procedure of application of a substrate bias voltage which is a characteristic operation of the nonvolatile storage device 200 according to the present embodiment. Described here is a procedure of a method for writing performed by the nonvolatile storage device according to the present invention.
  • a selection circuit (the row selection circuit 208 and the column selection circuit 203 ) selects at least one memory cell from the memory cell array 202 (S 10 ). Then, the control circuit 210 determines whether the write cycle or the read cycle is performed on the selected memory cell (S 11 ). In the case where the write cycle is performed (Yes in S 11 ), the control circuit 210 first instructs the substrate bias circuit 220 to apply a substrate bias voltage (S 12 ), and then causes the write circuit 206 to perform the write cycle (application of a voltage pulse for writing) (S 13 ). On the other hand, in the case where the read cycle is performed (No in S 11 ), the control circuit 210 causes the sense amplifier 204 to perform the read cycle without causing the substrate bias circuit 220 to operate (S 13 ).
  • a forward bias voltage (e.g., 0.3 V) is applied to a semiconductor substrate (the P-type well 301 a in the present embodiment) in which a transistor included in the memory cell is formed, which reduces on-resistance of the transistor. As a result, a higher voltage is applied to the variable resistance element.
  • the application of the forward bias voltage to the semiconductor substrate (well) in which the transistor included in the memory cell is formed allows the application of the higher voltage to the variable resistance element.
  • more stable writing is performed, and it is possible to cause the nonvolatile storage device to stably operate without increasing the gate width of the transistor.
  • the substrate bias circuit applies the forward bias voltage to the substrate of the transistor with respect to the diffusion region of the source or the drain, so that the voltage applied to the variable resistance element is increased, thereby surely changing the resistance state of the variable resistance element.
  • application of the substrate bias voltage causes application of the bias voltage to transistors of memory cells connected to the same bit line as the selected memory cell, and thus threshold voltages of the transistors may be reduced and a leak current may occur.
  • the nonvolatile storage device according to Embodiment 2 can address the above problem.
  • a basic configuration of the nonvolatile storage device according to Embodiment 2 is the same as in the case of Embodiment 1 shown in FIG. 5 , and thus the basic configuration is not described.
  • the nonvolatile storage device according to Embodiment 2 performs a unique operation on non-selected memory cells in the write cycle, in addition to the operations of the nonvolatile storage device according to Embodiment 1. The following describes the above with reference to FIG. 5 as required.
  • FIGS. 9( a ) and ( b ) is a timing diagram showing an operation example of the nonvolatile storage device according to Embodiment 2 of the present invention.
  • described is an operation example of a non-selected memory cell M 13 connected to the same bit line BL 0 as the memory cell M 11 in the case of writing the data “0” or “1” into the memory cell M 11 shown in FIG. 5 .
  • the operations of the selected memory cell M 11 are the same as in the case of Embodiment 1.
  • the column selection circuit 203 sets the selected bit line BL 0 to the voltage V 2 (e.g., 2.2 V). It is to be noted that the voltage VDD (e.g., 2.2 V) is not applied to a word line WL 2 because the memory cell M 13 is not selected, and thus an NMOS transistor N 13 of the memory cell M 13 remains in off-state.
  • the substrate bias circuit 220 sets the substrate terminal BB 0 of the NMOS transistor N 13 to the bias voltage VB (e.g., 0.3 V).
  • the row selection circuit 208 sets, via the row driver 207 (source line driver SLD (source line bias circuit)), the bias voltage VB to the source line SL 2 .
  • the row driver 207 source line driver SLD (source line bias circuit)
  • the bias voltage VB to the source line SL 2 .
  • the source line SL 2 is a signal line connected to the drain of the NMOS transistor N 13
  • application of a positive voltage (here bias voltage VB) to the source line SL 2 increases the source potential of the NMOS transistor N 13 , reduces the potential difference between the substrate (P-type well 301 a ) of the NMOS transistor N 13 and the source of the same, and suppresses the leak current of the NMOS transistor N 13 .
  • the bias voltage VB applied to the source line SL 2 corresponds to a second bias voltage according to the present invention which is applied to the source of a transistor included in a non-selected memory cell so that a current flowing in the transistor is suppressed.
  • the column selection circuit 203 sets the selected bit line BL 0 to the voltage 0 V. In this case also, the memory cell M 13 is not selected, and thus the NMOS transistor N 13 remains in off-state.
  • the substrate bias circuit 220 sets the substrate terminal BB 0 of the NMOS transistor N 11 to the bias voltage VB (e.g., 0.3 V).
  • the row selection circuit 208 sets, via the row driver 207 (source line driver SLD (source line bias circuit)), the bias voltage VB to the source line SL 2 .
  • the occurrence of the leak current can be prevented, because the potential difference between the substrate terminal of the NMOS transistor N 13 and the source line SL 2 (that is, the source of the NMOS transistor N 13 ) disappears. Consequently, it is possible to avoid the erroneous writing.
  • the bias voltage VB applied to the source line SL 2 corresponds to the second bias voltage according to the present invention which is applied to the source of the transistor included in the non-selected memory cell so that the current flowing in the transistor is suppressed.
  • the occurrence of the leak current can be prevented by applying the bias voltage to the source line.
  • bias voltages are applied to substrates of transistors in a memory cell array, it is possible to prevent the erroneous writing from occurring to any non-selected memory cell.
  • a resistance value of a variable resistance element is an initial resistance value (resistance value at a time when a voltage is applied for the first time after the variable resistance element is manufactured, that is, resistance value at a time when a voltage pulse has not yet been applied since the manufacture of the variable resistance element)
  • an initial resistance value resistance value at a time when a voltage is applied for the first time after the variable resistance element is manufactured, that is, resistance value at a time when a voltage pulse has not yet been applied since the manufacture of the variable resistance element
  • initialization process a process for applying a voltage higher than a voltage applied during normal writing
  • a basic configuration of the nonvolatile storage device according to Embodiment 3 is the same as in the case of Embodiment 1 shown in FIG. 5 , and thus the basic configuration is not described.
  • the nonvolatile storage device according to Embodiment 3 applies the substrate bias voltage only in the initialization process. The following describes the above with reference to FIG. 5 as required.
  • the nonvolatile storage device causes the substrate bias circuit 220 to apply the substrate bias voltage in the initialization process.
  • the write process in Embodiment 1 described with reference to FIG. 5 is performed in the initialization process.
  • FIG. 10 is a flowchart showing a procedure of application of a substrate bias voltage which is a characteristic operation of the nonvolatile storage device according to the present embodiment. Described here is the procedure in the write cycle performed by the nonvolatile storage device according to the present invention.
  • a selection circuit (the row selection circuit 208 and the column selection circuit 203 ) selects at least one memory cell into which data is to be written from the memory cell array 202 (S 20 ). Then, the control circuit 210 determines whether or not first writing (that is, the initialization process) is performed after the manufacture (S 21 ). In the case where it is determined that the initialization process is performed (Yes in S 21 ), the control circuit 210 first instructs the substrate bias circuit 220 to apply a substrate bias voltage (S 22 ), and then causes the write circuit 206 to perform the write cycle (application of a voltage pulse for writing) (S 23 ).
  • the control circuit 210 simply causes the write circuit 206 to perform the read cycle (the application of the voltage pulse for writing) without causing the substrate bias circuit 220 to operate (S 23 ). With this, it is possible to increase a voltage applied to an element in the initialization process more than a voltage applied to an element during normal writing, and thus stabilization of subsequent resistance change can be achieved.
  • FIGS. 11( a ) and ( b ) is a graph showing a change of a resistance state of a variable resistance element included in a nonvolatile storage device. More specifically, FIG. 11( a ) shows a change of a resistance state of the nonvolatile storage device according to Embodiment 3 of the present invention, whereas FIG. 11( b ) shows a resistance change of a variable resistance element in the case where the initialization process is not performed.
  • LR writing is performed by applying, as a stimulus pulse, a voltage of ⁇ 1.5 V to the variable resistance element only in the initialization process, and +1.5 V as a voltage for HR writing and ⁇ 1.0 V as a voltage for LR writing are alternately and repeatedly applied in subsequent write processes.
  • the stimulus pulse is applied with the substrate bias circuit 220 applying the forward substrate bias voltage.
  • a resistance value of the variable resistance element is stable in either a high resistance state or a low resistance state from when the initialization process is performed.
  • FIG. 11( b ) it is necessary to repeatedly apply a voltage pulse 20 to 30 times until the resistance value is stabilized in either the high resistance state or the low resistance state.
  • the application of the forward substrate bias voltage using the substrate bias circuit 220 in the initialization process makes it possible to immediately stabilize the resistance change of the variable resistance element. With this, it is possible to realize the nonvolatile storage device which can operate stably.
  • the nonvolatile storage device applies the substrate bias voltage only in the initialization process, as with Embodiment 1, the substrate bias voltage may be applied also in the normal write cycle, in addition to the initialization process. At that time, it is preferable to perform treatment in Embodiment 2 (that is, the application of the bias voltage to the source of the transistor included in the non-selected memory cell) on the non-selected memory cell.
  • the nonvolatile storage device causes the substrate bias circuit 220 to apply a forward substrate bias voltage when a resistance state of a resistance variable element is changed from a low resistance state to a high resistance state.
  • a basic configuration of the nonvolatile storage device according to Embodiment 4 is the same as in the case of Embodiment 1 shown in FIG. 5 , and thus the basic configuration is not described.
  • the nonvolatile storage device according to Embodiment 4 applies a forward bias voltage only in the HR writing. The following describes the above with reference to FIG. 5 as required.
  • FIGS. 12( a ) and ( b ) is a graph showing a distribution of resistance values in the case where a variable resistance element is rewritten 100 times.
  • FIG. 12( a ) shows the distribution of the resistance values in the case where +1.4 V and ⁇ 1.3 V are applied as a voltage for HR writing and a voltage for LR writing, respectively
  • FIG. 12( b ) shows the distribution of the resistance values in the case where +1.8 V and ⁇ 1.3 V are applied as the voltage for HR writing and the voltage for LR writing, respectively.
  • the voltage for LR writing is the same but only the voltage for HR writing is different, and the voltage for HR writing in FIG. 12( b ) is higher than the voltage for HR writing in FIG. 12( a ).
  • any resistance value in the low resistance state is relatively stable.
  • resistance values in the high resistance state differ between FIGS. 12( a ) and ( b ). While the resistance values vary and are unstable in FIG. 12( a ), the resistance values shown in FIG. 12( b ) are stable in the same manner as in the case of the low resistance state. From this, it is clear that a case where a value of “voltage for HR writing/voltage for LR writing (voltage ratio)” is higher makes it possible to stabilize the resistance value in the high resistance state.
  • the nonvolatile storage device when applying the voltage for HR writing, causes the substrate bias circuit 220 to apply the forward substrate bias voltage to increase the value of “voltage for HR writing/voltage for LR writing”, and thus stabilizes the resistance value in the high resistance state.
  • FIG. 13 is a flowchart showing a procedure of application of a substrate bias voltage which is a characteristic operation of the nonvolatile storage device according to the present embodiment. Described here is the procedure in the write cycle performed by the nonvolatile storage device according to the present invention.
  • a selection circuit (the row selection circuit 208 and the column selection circuit 203 ) selects at least one memory cell into which data is to be written from the memory cell array 202 (S 30 ). Then, the control circuit 210 determines whether or not the writing to be performed is the HR writing (writing “1”) (S 31 ). In the case where it is determined that the writing to be performed is the HR writing (Yes in S 31 ), the control unit 210 first instructs the substrate bias circuit 220 to apply a substrate bias voltage (S 32 ), and then causes the write circuit 206 to perform the HR writing in the write cycle (application of a voltage pulse for writing) (S 33 ).
  • the control circuit 210 simply causes the write circuit 206 to perform the LR writing in the write cycle (the application of the voltage pulse for writing) without causing the substrate bias circuit 220 to operate (S 33 ).
  • FIGS. 14( a ) and ( b ) is a timing diagram showing an operation example of the nonvolatile storage device according to Embodiment 4 of the present invention. Described here is the operation example in the case where the data “0” (in the case of the LR writing; FIG. 14( a )) or the data “1” (in the case of the HR writing; FIG. 14( b )) is written into the memory cell M 11 .
  • the operation in the case of the data “1” writing is the same as the operation described above in Embodiment 1 with reference to FIG. 7( b ).
  • the bias voltage VB is not applied to a transistor, unlike FIG. 7( a ). In other words, in the case of the LR writing, the same operation as the conventional operation is performed.
  • Embodiment 2 that is, the application of the bias voltage to the source of the transistor included in the non-selected memory cell
  • the substrate bias voltage may be applied in the initialization process described in Embodiment 3.
  • a change of a resistance state of a variable resistance element is stabilized by causing the substrate bias circuit 220 to apply a bias voltage to a substrate of a transistor in the additional write process.
  • FIG. 15 shows an example of write characteristics of a single variable resistance element.
  • the LR writing and the HR writing are repeated with alternate pluses of ⁇ 1.5 V and +2.3 V, but the HR writing is unsuccessful along the way as shown by spots where the low resistance state continues.
  • the LR state remains when +2.3 V normally used for the HR writing is applied two times and when +2.4 V is applied, but application of +2.5 V performs the HR writing in the same manner as the normal operation.
  • the resistance change occurs with the usual alternate pulses of ⁇ 1.5 V and +2.3 V. It is possible to stabilize the resistance change by performing additional writing with a voltage to be applied that is little higher than a normal voltage, in the case where the resistance change is unsuccessful as stated above.
  • Embodiment 5 a voltage higher than a voltage to be applied in normal writing is applied by causing the substrate bias circuit 220 to apply the forward substrate bias voltage only when the additional write process is performed, and thus the change of the resistance state of the variable resistance element is stabilized.
  • a basic configuration of the nonvolatile storage device according to Embodiment 5 is the same as in the case of Embodiment 1 shown in FIG. 5 , and thus the basic configuration is not described.
  • the nonvolatile storage device according to Embodiment 5 applies the substrate bias voltage only in the case of the additional writing. The following describes the above with reference to FIG. 5 as required.
  • the nonvolatile storage device causes the substrate bias circuit 220 to apply the substrate bias voltage in the additional write process to be performed after the writing is unsuccessful.
  • the write process in Embodiment 1 described with reference to FIGS. 7( a ) and ( b ) is performed in the additional write process.
  • FIG. 16( a ) is a flowchart showing a procedure of application of a substrate bias voltage which is a characteristic operation of the nonvolatile storage device according to the present embodiment. Described here is a procedure of a method for writing performed by the nonvolatile storage device according to the present invention.
  • a selection circuit (the row selection circuit 208 and the column selection circuit 203 ) selects at least one memory cell into which data is to be written from the memory cell array 202 (S 40 ). Then, under control of the control circuit 210 , the write circuit 206 provides a voltage pulse for writing data (e.g., “1”) to the variable resistance element included in the memory cell selected by the selection circuit (the row selection circuit 208 and the column selection circuit 203 ) (S 41 ). Next, the control circuit 210 causes the sense amplifier 204 to read the data stored in the memory cell, and determines (that is, verifies) whether or not the read data corresponds to most recently written data (S 42 ).
  • a voltage pulse for writing data e.g., “1”
  • the write circuit 206 performs the writing using a voltage for writing again (S 41 ) after making preparation for increasing the voltage for writing by a predetermined voltage (e.g., 0.1 V) so that the voltage for writing is higher than a recently applied voltage for writing (S 43 ). Subsequently, the process for increasing the voltage for writing (S 43 ) and the writing again (S 41 ) are repeated until the writing succeeds (the verification is passed).
  • a voltage for writing again S 41
  • FIG. 16( b ) is a flowchart showing a detailed procedure of the writing step (S 41 ) shown in FIG. 16( a ).
  • the control circuit 210 determines whether or not writing is additional writing (S 41 a ). In the case where the writing is the additional writing (Yes in S 41 a ), the control circuit 210 first instructs the substrate bias circuit 220 to apply a substrate bias voltage (S 41 b ), and then causes the write circuit 206 to perform the write cycle (the application of the voltage pulse for writing) (S 41 c ).
  • the control circuit 210 simply causes the write circuit 206 to perform the write cycle (the application of the voltage pulse for writing) without causing the substrate bias circuit 220 to operate (S 41 c ).
  • the forward bias voltage is applied to the semiconductor substrate (well) in which the transistor included in the memory cell is formed.
  • the substrate bias voltage When the substrate bias voltage is applied in the additional writing, it is possible to increase an effective voltage to be applied to the variable resistance element as shown in FIG. 4 . To put it differently, it is possible to produce the same effect as in the case where the voltage to be applied at the time of the additional writing is increased as shown in FIG. 15 .
  • an additional writing pulse obtained through the application of the bias voltage performed by the substrate bias circuit is applied to the variable resistance element, and thus it is possible to stabilize the subsequent change of the resistance state of the variable resistance element. As a result, it is possible to realize the nonvolatile storage device which can operate stably.
  • nonvolatile storage device according to the present embodiment applies the substrate bias voltage only in the additional writing, as in Embodiment 3, the nonvolatile storage device according to the present embodiment may apply the substrate bias voltage in the initialization process as well.
  • the treatment in Embodiment 2 (that is, the application of the bias voltage to the source of the transistor included in the non-selected memory cell) may be performed on the non-selected memory cell.
  • the nonvolatile storage device including variable resistance elements
  • a write process when a write process is repeatedly performed, there is a chance that the resistance of the variable resistance elements does not change after a certain number of times the write process is performed.
  • the nonvolatile storage device performs the refresh process by causing the substrate bias circuit 220 to apply a forward substrate bias voltage.
  • a basic configuration of the nonvolatile storage device according to Embodiment 6 is the same as in the case of Embodiment 1 shown in FIG. 5 , and thus the basic configuration is not described. Unlike the nonvolatile storage device according to Embodiment 1 which applies the substrate bias voltage in all the write cycles, the nonvolatile storage device according to Embodiment 6 applies the substrate bias voltage only in the refresh process. The following describes the above with reference to FIG. 5 as required.
  • the nonvolatile storage device causes the substrate bias circuit 220 to apply the forward substrate bias voltage in the refresh process.
  • the write process in Embodiment 1 described with reference to FIG. 5 is performed in the refresh process.
  • Such a refresh process is performed in the case where writing is performed a predetermined number of times such as 1 million times.
  • FIG. 17 is a flowchart showing a procedure of application of a substrate bias voltage which is a characteristic operation of the nonvolatile storage device according to the present embodiment. Described here is a procedure of a method for writing performed by the nonvolatile storage device according to the present invention.
  • a selection circuit (the row selection circuit 208 and the column selection circuit 203 ) selects at least one memory cell into which data is to be written from the memory cell array 202 (S 50 ). Then, the control circuit 210 determines whether or not the write process had been performed has been performed a predetermined number of times (e.g., 1 million times), using a counter included in the control circuit 210 (S 51 ).
  • the control circuit 210 instructs the substrate bias circuit 220 to apply a substrate bias voltage (part of the refresh process) (S 52 ), and then causes the write circuit 206 to perform the write cycle (application of a voltage pulse for writing) (S 53 ).
  • the control circuit 210 simply causes the write circuit 206 to perform the write cycle (the application of the voltage pulse for writing) without causing the substrate bias circuit 220 to operate (S 53 ). It is to be noted that after performing the refresh process (the application of the substrate bias voltage and the writing), the control circuit 210 resets the counter to zero, and performs the same processing (S 51 to S 53 ).
  • nonvolatile storage device applies the substrate bias voltage only in the refresh process, as in Embodiment 3, the nonvolatile storage device according to the present embodiment may apply the substrate bias voltage in the initialization process as well.
  • the refresh process may be performed only on a memory cell in which the number of times the writing has been performed reaches a predetermined value, or the number of times the writing has been performed on the entire memory cell array 202 is counted and held, and the refresh process may be performed on all of the memory cells included in the memory cell array 202 when the number of times the writing has been performed reaches the predetermined value.
  • the refresh process is performed for each memory cell, it is preferable to perform, in the refresh process, the treatment in Embodiment 2 (that is, the application of the bias voltage to the source of the transistor included in the non-selected memory cell) on the non-selected memory cell.
  • variable resistance layer 104 has the stacked structure of the tantalum oxide layers
  • present invention is not limited to the stacked structure of the tantalum oxide layers.
  • the variable resistance layer 104 may be a layer which shows a resistance change caused by application of a voltage between the upper electrode 105 and the lower electrode 103 .
  • the variable resistance layer 104 may have a structure of a single tantalum oxide layer or may be not the tantalum oxide layer but another metal oxide layer such as a hafnium oxide layer and a zirconium oxide layer.
  • Embodiments 3 and 6 may be combined, so that the substrate bias circuit 220 applies the bias voltage in both the initialization process and the refresh process, and so on. With this, it is possible to realize a nonvolatile storage device which can maintain stable operations for a longer period of time.
  • a nonvolatile storage device is useful as a storage device or the like used for various electronic devices such as a personal computer and a mobile phone, and especially as a nonvolatile memory with a large storage capacity.

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